mirror of
https://github.com/holub/mame
synced 2025-04-22 16:31:49 +03:00
aic6250: new device (nw)
Very WIP status and some obvious issues, but working well enough to load RISC/os.
This commit is contained in:
Patrick Mackinlay
parent
71bf6a65d9
commit
a3244603db
@ -3808,7 +3808,6 @@ if (MACHINES["Z8038"]~=null) then
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}
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end
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---------------------------------------------------
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--
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--@src/devices/machine/scc2698b.h,MACHINES["SCC2698B"] = true
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@ -3821,3 +3820,14 @@ if (MACHINES["SCC2698B"]~=null) then
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}
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end
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---------------------------------------------------
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--
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--@src/devices/machine/aic6250.h,MACHINES["AIC6250"] = true
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---------------------------------------------------
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if (MACHINES["AIC6250"]~=null) then
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files {
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MAME_DIR .. "src/devices/machine/aic6250.cpp",
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MAME_DIR .. "src/devices/machine/aic6250.h",
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}
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end
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@ -673,6 +673,7 @@ MACHINES["IOPINTC"] = true
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MACHINES["IOPSIO2"] = true
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MACHINES["IOPTIMER"] = true
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MACHINES["Z8038"] = true
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MACHINES["AIC6250"] = true
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--------------------------------------------------
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-- specify available bus cores
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1019
src/devices/machine/aic6250.cpp
Normal file
1019
src/devices/machine/aic6250.cpp
Normal file
File diff suppressed because it is too large
Load Diff
280
src/devices/machine/aic6250.h
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280
src/devices/machine/aic6250.h
Normal file
@ -0,0 +1,280 @@
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// license:BSD-3-Clause
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// copyright-holders:Patrick Mackinlay
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#ifndef MAME_MACHINE_AIC6250_H
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#define MAME_MACHINE_AIC6250_H
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#pragma once
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#include "machine/nscsi_bus.h"
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class aic6250_device : public nscsi_device
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{
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public:
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aic6250_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
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void map(address_map &map);
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auto int_cb() { return m_int_cb.bind(); }
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auto breq_cb() { return m_breq_cb.bind(); }
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auto port_a_r_cb() { return m_port_a_r_cb.bind(); }
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auto port_a_w_cb() { return m_port_a_w_cb.bind(); }
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auto port_b_r_cb() { return m_port_b_r_cb.bind(); }
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auto port_b_w_cb() { return m_port_b_w_cb.bind(); }
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DECLARE_WRITE_LINE_MEMBER(back_w);
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DECLARE_READ8_MEMBER(read);
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DECLARE_WRITE8_MEMBER(write);
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u8 dma_r();
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void dma_w(u8 data);
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protected:
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// standard device_interface overrides
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virtual void device_start() override;
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virtual void device_reset() override;
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// ncsci_device overrides
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virtual void scsi_ctrl_changed() override;
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void scsi_reset();
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u8 dma_count_l_r() { return m_dma_count >> 0; }
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u8 dma_count_m_r() { return m_dma_count >> 8; }
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u8 dma_count_h_r() { return m_dma_count >> 16; }
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u8 fifo_status_r();
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u8 rev_cntrl_r() { return m_rev_cntrl; }
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u8 status_reg_0_r();
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u8 status_reg_1_r();
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u8 scsi_signal_reg_r();
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u8 scsi_id_data_r();
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u8 source_dest_id_r() { logerror("source_dest_id_r\n"); return m_source_dest_id; }
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u8 memory_data_r();
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u8 port_a_r();
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u8 port_b_r();
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u8 scsi_latch_data_r() { logerror("scsi_latch_data_r 0x%02x\n", m_scsi_latch_data); return m_scsi_latch_data; }
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void dma_count_l_w(u8 data) { m_dma_count &= ~0x0000ff; m_dma_count |= (data << 0); }
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void dma_count_m_w(u8 data) { m_dma_count &= ~0x00ff00; m_dma_count |= (data << 8); }
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void dma_count_h_w(u8 data) { m_dma_count &= ~0xff0000; m_dma_count |= (data << 16); }
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void int_msk_reg_0_w(u8 data);
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void offset_cntrl_w(u8 data);
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void dma_cntrl_w(u8 data);
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void int_msk_reg_1_w(u8 data);
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void control_reg_0_w(u8 data);
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void control_reg_1_w(u8 data);
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void scsi_signal_reg_w(u8 data);
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void scsi_id_data_w(u8 data);
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void memory_data_w(u8 data);
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void port_a_w(u8 data);
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void port_b_w(u8 data);
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void scsi_bsy_rst_w(u8 data) { /* TODO: target mode, reset /BSY out and enter bus free */ }
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private:
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TIMER_CALLBACK_MEMBER(state_loop);
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int state_step();
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bool int_check();
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void set_int_state(bool asserted);
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bool phase_match(u8 aic6250_phase, u32 nscsi_phase)
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{
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return (bool(aic6250_phase & R09W_SCSI_CD_OUT) == bool(nscsi_phase & S_CTL))
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&& (bool(aic6250_phase & R09W_SCSI_IO_OUT) == bool(nscsi_phase & S_INP))
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&& (bool(aic6250_phase & R09W_SCSI_MSG_OUT) == bool(nscsi_phase & S_MSG));
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}
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enum int_msk_reg_0_mask : u8
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{
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R03W_EN_SELECT_INT = 0x01,
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R03W_EN_RESEL_INT = 0x02,
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R03W_EN_SEL_OUT_INT = 0x04,
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R03W_EN_CMD_DONE_INT = 0x08,
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R03W_EN_ERROR_INT = 0x10,
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R03W_EN_AUTO_ATN = 0x20,
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R03W_ARB_SEL_START = 0x40,
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R03W_RESERVED = 0x80,
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R03W_INT_MASK = 0x0f
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};
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enum offset_cntrl_mask : u8
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{
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R04W_OFFSET = 0x0f,
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R04W_SYNC_XFER_RATE = 0x70,
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R04W_RESERVED = 0x80
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};
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enum fifo_status_mask : u8
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{
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R05R_FIFO_COUNTER = 0x07,
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R05R_FIFO_FULL = 0x08,
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R05R_FIFO_EMPTY = 0x10,
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R05R_OFFSET_COUNT_ZERO = 0x20,
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R05R_TEST_SIGNAL = 0xc0
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};
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enum dma_cntrl_mask : u8
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{
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R05W_DMA_XFER_EN = 0x01,
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R05W_TRANSFER_DIR = 0x02,
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R05W_ODD_XFER_START = 0x04,
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R05W_RESERVED = 0xf8
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};
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enum rev_cntrl_mask : u8
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{
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R06R_REVISION = 0x03,
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R06R_RESERVED = 0xfc
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};
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enum int_msk_reg_1_mask : u8
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{
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R06W_EN_ATN_ON_INT_TGT = 0x01,
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R06W_EN_PHASE_CHANGE_INT_INIT = 0x01,
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R06W_EN_SCSI_PARITY_ERR_INT = 0x02,
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R06W_EN_BUS_FREE_DETECT_INT = 0x04,
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R06W_EN_PHASE_MISMATCH_INT = 0x08,
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R06W_EN_MEM_PARITY_ERROR_INT = 0x10,
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R06W_EN_SCSI_RST_INT = 0x20,
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R06W_EN_SCSI_REQ_ON_INT = 0x40,
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R06W_RESERVED = 0x80,
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R06W_ERROR_INT_MASK = 0x3f
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};
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enum status_reg_0_mask : u8
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{
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R07R_DMA_BYTE_CNT_ZERO = 0x01,
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R07R_SCSI_PHASE_CHG_ATN = 0x02,
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R07R_SCSI_REQ_ON = 0x04,
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R07R_SCSI_PARITY_ERR = 0x08,
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R07R_BUS_FREE_DETECT = 0x10,
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R07R_PHASE_MISMATCH_ERR = 0x20,
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R07R_MEMORY_PARITY_ERR = 0x40,
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R07R_SCSI_RST_OCCURRED = 0x80,
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R07R_ERROR_MASK = 0xfa
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};
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enum control_reg_0_mask : u8
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{
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R07W_SCSI_ID = 0x07,
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R07W_SCSI_INTERFACE_MODE = 0x08,
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R07W_EN_PORT_A_INP_OR_OUT = 0x10,
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R07W_TARGET_MODE = 0x20,
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R07W_P_MEM_RW = 0x40,
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R07W_P_MEM_CYCLE_REQ = 0x80
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};
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enum status_reg_1_mask : u8
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{
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R08R_SELECTED = 0x01,
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R08R_RESELECTED = 0x02,
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R08R_SEL_OUT = 0x04,
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R08R_CMD_DONE = 0x08,
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R08R_ERROR = 0x10,
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R08R_SCSI_RST_IN = 0x20,
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R08R_RESERVED = 0x40,
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R08R_MEM_CYCLE_CMPL = 0x80
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};
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enum control_reg_1_mask : u8
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{
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R08W_CHIP_SW_RESET = 0x01,
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R08W_SCSI_RST_OUT = 0x02,
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R08W_CLK_FREQ_MODE = 0x04,
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R08W_PHASE_CHANGE_MODE = 0x08,
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R08W_EN_PORT_B_INP_OR_OUT = 0x10,
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R08W_RESERVED = 0x20,
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R08W_EN_16_BIT_MEM_BUS = 0x40,
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R08W_AUTO_SCSI_PIO_REQ = 0x80
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};
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enum scsi_signal_reg_mask : u8
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{
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R09R_SCSI_ACK_IN = 0x01,
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R09R_SCSI_REQ_IN = 0x02,
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R09R_SCSI_BSY_IN = 0x04,
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R09R_SCSI_SEL_IN = 0x08,
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R09R_SCSI_ATN_IN = 0x10,
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R09R_SCSI_MSG_IN = 0x20,
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R09R_SCSI_IO_IN = 0x40,
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R09R_SCSI_CD_IN = 0x80,
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R09W_RESERVED = 0x01,
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R09W_SCSI_REQ_OUT = 0x02, // target mode
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R09W_SCSI_ACK_OUT = 0x02, // initiator mode
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R09W_SCSI_BSY_OUT = 0x04,
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R09W_SCSI_SEL_OUT = 0x08,
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R09W_SCSI_ATN_OUT = 0x10,
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R09W_SCSI_MSG_OUT = 0x20,
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R09W_SCSI_IO_OUT = 0x40,
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R09W_SCSI_CD_OUT = 0x80,
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R09R_PHASE_MASK = 0xe0
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};
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devcb_write_line m_int_cb;
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devcb_write_line m_breq_cb;
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devcb_read8 m_port_a_r_cb;
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devcb_write8 m_port_a_w_cb;
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devcb_read8 m_port_b_r_cb;
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devcb_write8 m_port_b_w_cb;
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enum state_t
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{
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IDLE,
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ARB_BUS_FREE,
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ARB_START,
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ARB_EVALUATE,
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SEL_START,
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SEL_DELAY,
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SEL_WAIT_BSY,
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SEL_COMPLETE,
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DMA_IN,
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DMA_IN_NEXT,
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DMA_IN_REQ,
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DMA_IN_DRAIN,
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DMA_IN_DONE,
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DMA_OUT,
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DMA_OUT_NEXT,
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DMA_OUT_REQ,
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DMA_OUT_DONE,
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AUTO_PIO,
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AUTO_PIO_IN,
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AUTO_PIO_OUT,
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AUTO_PIO_DONE,
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};
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// internal state
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emu_timer *m_state_timer;
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state_t m_state;
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bool m_int_asserted;
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u32 m_scsi_ctrl_state;
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u8 m_address_reg;
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// registers
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u32 m_dma_count;
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bool m_offset_count_zero;
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u8 m_rev_cntrl;
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u8 m_status_reg_0;
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u8 m_status_reg_1;
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u8 m_scsi_signal_reg;
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u8 m_scsi_id_data;
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u8 m_source_dest_id;
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u8 m_memory_data;
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u8 m_port_a_latch;
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u8 m_port_b_latch;
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u8 m_scsi_latch_data;
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u8 m_int_msk_reg_0;
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u8 m_offset_cntrl;
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u8 m_dma_cntrl;
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u8 m_int_msk_reg_1;
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u8 m_control_reg_0;
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u8 m_control_reg_1;
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util::fifo <u8, 8> m_fifo;
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};
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DECLARE_DEVICE_TYPE(AIC6250, aic6250_device)
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#endif // MAME_MACHINE_AIC6250_H
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