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-bus/coco/coco_ram.cpp: fix a rather obvious bug in shift/mask
-misc. formatting consistency
This commit is contained in:
parent
731fbe1975
commit
a335166ec2
@ -12,7 +12,7 @@
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#include "emu.h"
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#include "emu.h"
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#include "coco_ram.h"
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#include "coco_ram.h"
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#include "cococart.h"
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#include "machine/ram.h"
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#include "machine/ram.h"
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#define STATICRAM_TAG "static_ram"
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#define STATICRAM_TAG "static_ram"
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@ -53,7 +53,7 @@ namespace
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private:
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private:
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required_device<ram_device> m_staticram;
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required_device<ram_device> m_staticram;
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int m_offset;
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u32 m_offset;
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};
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};
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};
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};
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@ -126,19 +126,19 @@ void coco_pak_ram_device::scs_write(offs_t offset, u8 data)
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{
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{
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// int idata = data;
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// int idata = data;
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switch(offset)
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switch (offset)
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{
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{
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case 0:
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case 0:
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m_offset = ((m_offset & 0xffff00) + data);
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m_offset = (m_offset & 0xffff00) | u32(data);
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break;
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break;
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case 1:
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case 1:
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m_offset = ((m_offset & 0xff00ff) + (data << 8));
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m_offset = (m_offset & 0xff00ff) | (u32(data) << 8);
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break;
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break;
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case 2:
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case 2:
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m_offset = ((m_offset & 0x00ffff) + (data << 16));
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m_offset = (m_offset & 0x00ffff) | (u32(data) << 16);
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break;
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break;
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case 3:
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case 3:
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if( m_offset < BUFFER_SIZE )
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if (m_offset < BUFFER_SIZE)
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{
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{
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m_staticram->write(m_offset, data);
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m_staticram->write(m_offset, data);
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}
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}
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@ -161,20 +161,19 @@ u8 coco_pak_ram_device::scs_read(offs_t offset)
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switch (offset)
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switch (offset)
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{
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{
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case 0:
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case 0:
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data = (m_offset) & 0xff;
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data = u8(m_offset & 0x00ff);
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break;
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break;
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case 1:
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case 1:
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data = (m_offset & 0xff00ff) >> 8;
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data = u8((m_offset >> 8) & 0x00ff);
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break;
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break;
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case 2:
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case 2:
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data = (m_offset & 0xff0000) >> 16;
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data = u8((m_offset >> 16) & 0x00ff);
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break;
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break;
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case 3:
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case 3:
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if( m_offset < BUFFER_SIZE )
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if (m_offset < BUFFER_SIZE)
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{
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{
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data = m_staticram->read(m_offset);
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data = m_staticram->read(m_offset);
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}
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}
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break;
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break;
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}
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}
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@ -107,7 +107,7 @@ void i960_cpu_device::send_iac(uint32_t adr)
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logerror("I960: %x: IAC %08x %08x %08x %08x (invalidate internal instruction cache)\n", m_PIP, iac[0], iac[1], iac[2], iac[3]);
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logerror("I960: %x: IAC %08x %08x %08x %08x (invalidate internal instruction cache)\n", m_PIP, iac[0], iac[1], iac[2], iac[3]);
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// we do not emulate the instruction cache, so this is safe to ignore
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// we do not emulate the instruction cache, so this is safe to ignore
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break;
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break;
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case 0x8F: // enable/disable breakpoints
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case 0x8f: // enable/disable breakpoints
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logerror("I960: %x: IAC %08x %08x %08x %08x (enable/disable breakpoints)\n", m_PIP, iac[0], iac[1], iac[2], iac[3]);
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logerror("I960: %x: IAC %08x %08x %08x %08x (enable/disable breakpoints)\n", m_PIP, iac[0], iac[1], iac[2], iac[3]);
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// processor breakpoints are not emulated, safe to ignore
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// processor breakpoints are not emulated, safe to ignore
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break;
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break;
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@ -881,7 +881,7 @@ const natural_keyboard::keycode_map_entry *natural_keyboard::find_code(char32_t
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{
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{
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keycode_map::const_iterator const found(m_keycode_map.find(ch));
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keycode_map::const_iterator const found(m_keycode_map.find(ch));
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if (m_keycode_map.end() == found) return nullptr;
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if (m_keycode_map.end() == found) return nullptr;
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for(const keycode_map_entry &entry : found->second)
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for (keycode_map_entry const &entry : found->second)
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{
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{
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if (entry.condition.eval())
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if (entry.condition.eval())
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return &entry;
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return &entry;
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@ -81,39 +81,35 @@ void gscpm_state::cflash_w(offs_t offset, uint8_t data)
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uint8_t gscpm_state::sio_r(offs_t offset)
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uint8_t gscpm_state::sio_r(offs_t offset)
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{
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{
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switch(offset & 3)
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switch (offset & 3)
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{
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{
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case 0x00:
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case 0x00:
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return m_sio->da_r();
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return m_sio->da_r();
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break;
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case 0x01:
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case 0x01:
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return m_sio->db_r();
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return m_sio->db_r();
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case 0x02:
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break;
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return m_sio->ca_r();
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case 0x02:
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case 0x03:
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return m_sio->ca_r();
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return m_sio->cb_r();
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break;
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case 0x03:
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return m_sio->cb_r();
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break;
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}
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}
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return 0x00; // can't happen
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return 0x00; // can't happen
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}
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}
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void gscpm_state::sio_w(offs_t offset, uint8_t data)
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void gscpm_state::sio_w(offs_t offset, uint8_t data)
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{
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{
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switch(offset & 3)
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switch (offset & 3)
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{
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{
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case 0x00:
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case 0x00:
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m_sio->da_w(data);
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m_sio->da_w(data);
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break;
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break;
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case 0x01:
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case 0x01:
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m_sio->db_w(data);
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m_sio->db_w(data);
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break;
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break;
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case 0x02:
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case 0x02:
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m_sio->ca_w(data);
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m_sio->ca_w(data);
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break;
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break;
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case 0x03:
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case 0x03:
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m_sio->cb_w(data);
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m_sio->cb_w(data);
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break;
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break;
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}
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}
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}
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}
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