From a35ef58b54fdead56bf3c21f898fce33d18687a1 Mon Sep 17 00:00:00 2001 From: Wilbert Pol Date: Wed, 25 Mar 2009 19:39:41 +0000 Subject: [PATCH] CPU cores are now enabled on a per cpu core family basis instead of per cpu core variant. As a result CPUDEFS is no longer needed in the makefile. --- makefile | 2 +- src/emu/cpu/alph8201/alph8201.c | 12 - src/emu/cpu/cpu.mak | 392 ++++---------------------------- src/emu/cpu/e132xs/e132xs.c | 72 ------ src/emu/cpu/e132xs/e132xs.h | 28 --- src/emu/cpu/i386/i386.c | 6 - src/emu/cpu/i86/i86.c | 10 - src/emu/cpu/i86/i86mem.c | 2 - src/emu/cpu/m6502/6502dasm.c | 24 -- src/emu/cpu/m6502/m6502.c | 46 ---- src/emu/cpu/m6502/m6502.h | 26 --- src/emu/cpu/m6800/6800ops.c | 4 - src/emu/cpu/m6800/6800tbl.c | 10 - src/emu/cpu/m6800/m6800.c | 32 --- src/emu/cpu/m6800/m6800.h | 28 --- src/emu/cpu/m6805/m6805.c | 19 -- src/emu/cpu/m6805/m6805.h | 4 - src/emu/cpu/mips/mips3.c | 12 - src/emu/cpu/mips/mips3.h | 14 -- src/emu/cpu/mips/mips3drc.c | 14 -- src/emu/cpu/mips/psx.c | 2 - src/emu/cpu/nec/nec.c | 20 -- src/emu/cpu/pic16c5x/pic16c5x.c | 10 - src/emu/cpu/pic16c5x/pic16c5x.h | 12 - src/emu/cpu/sharc/sharc.c | 4 - src/emu/cpu/sharc/sharc.h | 2 - src/emu/cpu/ssp1601/ssp1601.c | 2 - src/emu/cpu/ssp1601/ssp1601.h | 2 - src/emu/cpu/tms32025/tms32025.c | 4 - src/emu/cpu/tms32051/tms32051.c | 2 - src/emu/cpu/tms32051/tms32051.h | 2 - src/emu/cpu/tms9900/tms9900.h | 20 -- src/emu/cpu/v60/v60.h | 4 - src/mame/mame.mak | 107 +-------- src/mame/tiny.mak | 6 +- 35 files changed, 49 insertions(+), 907 deletions(-) diff --git a/makefile b/makefile index 4827e37e89e..9da042bcc53 100644 --- a/makefile +++ b/makefile @@ -492,7 +492,7 @@ include $(SRC)/build/build.mak include $(SRC)/tools/tools.mak # combine the various definitions to one -CDEFS = $(DEFS) $(COREDEFS) $(CPUDEFS) $(SOUNDDEFS) +CDEFS = $(DEFS) $(COREDEFS) $(SOUNDDEFS) diff --git a/src/emu/cpu/alph8201/alph8201.c b/src/emu/cpu/alph8201/alph8201.c index 91ae22253c4..cd74578c534 100644 --- a/src/emu/cpu/alph8201/alph8201.c +++ b/src/emu/cpu/alph8201/alph8201.c @@ -525,7 +525,6 @@ static void jz(alpha8201_state *cpustate) { UINT8 i=M_RDMEM_OPCODE(cpustate); if static void jc(alpha8201_state *cpustate) { UINT8 i=M_RDMEM_OPCODE(cpustate); if ( cpustate->cf) M_JMP(cpustate, i);} static void jmp(alpha8201_state *cpustate) { M_JMP(cpustate, M_RDMEM_OPCODE(cpustate) ); } -#if (HAS_ALPHA8201) static const s_opcode opcode_8201[256]= { {C1, nop },{C1,rora },{C1, rola },{C1,inc_b },{C1,dec_b },{C1, inc_a },{C1, dec_a },{C1, cpl }, @@ -566,9 +565,7 @@ static const s_opcode opcode_8201[256]= {C1, undefined },{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined}, {C1, undefined },{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined } }; -#endif -#if (HAS_ALPHA8301) /* ALPHA 8301 : added instruction */ static void exg_a_ix0(alpha8201_state *cpustate) { UINT8 t=cpustate->A; cpustate->A = cpustate->IX0; cpustate->IX0 = t; } @@ -663,7 +660,6 @@ static const s_opcode opcode_8301[256]= {C1,exg_ix0_ix1},{C1,exg_ix0_ix2},{C1,op_rep_ld_ix2_b},{C1, op_rep_ld_b_ix0},{C1, save_zc},{C1, rest_zc},{C1, ld_rxb_a },{C1, ld_a_rxb }, {C1, cmp_a_rxb },{C1, xor_a_rxb},{C1, add_a_cf },{C1, sub_a_cf },{C1, tst_a },{C1, clr_a },{C1, ld_a_ix0_a},{C1, ret } }; -#endif /**************************************************************************** * Initialize emulation @@ -814,13 +810,9 @@ mame_printf_debug("alpha8201: cpustate->PC = %03x, opcode = %02x\n", cpustate- return cycles - cpustate->icount; } -#if (HAS_ALPHA8201) static CPU_EXECUTE( alpha8201 ) { return alpha8xxx_execute(device,opcode_8201,cycles); } -#endif -#if (HAS_ALPHA8301) static CPU_EXECUTE( ALPHA8301 ) { return alpha8xxx_execute(device,opcode_8301,cycles); } -#endif /**************************************************************************** * Set IRQ line state @@ -980,7 +972,6 @@ static CPU_GET_INFO( alpha8xxx ) case CPUINFO_STR_REGISTER + ALPHA8201_R7: sprintf(info->s, "R7:%02X", RD_REG(7)); break; } } -#if (HAS_ALPHA8201) CPU_GET_INFO( alpha8201 ) { switch (state) @@ -992,9 +983,7 @@ CPU_GET_INFO( alpha8201 ) CPU_GET_INFO_CALL(alpha8xxx); } } -#endif -#if (HAS_ALPHA8301) CPU_GET_INFO( alpha8301 ) { switch (state) @@ -1006,4 +995,3 @@ CPU_GET_INFO( alpha8301 ) CPU_GET_INFO_CALL(alpha8xxx); } } -#endif diff --git a/src/emu/cpu/cpu.mak b/src/emu/cpu/cpu.mak index 287c95233fb..2b01e1432b0 100644 --- a/src/emu/cpu/cpu.mak +++ b/src/emu/cpu/cpu.mak @@ -78,9 +78,6 @@ $(DRCOBJ): $(DRCDEPS) # Acorn ARM series #------------------------------------------------- -CPUDEFS += -DHAS_ARM=$(if $(filter ARM,$(CPUS)),1,0) -CPUDEFS += -DHAS_ARM7=$(if $(filter ARM7,$(CPUS)),1,0) - ifneq ($(filter ARM,$(CPUS)),) OBJDIRS += $(CPUOBJ)/arm CPUOBJS += $(CPUOBJ)/arm/arm.o @@ -107,8 +104,6 @@ $(CPUOBJ)/arm7/arm7.o: $(CPUSRC)/arm7/arm7.c \ # Advanced Digital Chips SE3208 #------------------------------------------------- -CPUDEFS += -DHAS_SE3208=$(if $(filter SE3208,$(CPUS)),1,0) - ifneq ($(filter SE3208,$(CPUS)),) OBJDIRS += $(CPUOBJ)/se3208 CPUOBJS += $(CPUOBJ)/se3208/se3208.o @@ -124,10 +119,7 @@ $(CPUOBJ)/se3208/se3208.o: $(CPUSRC)/se3208/se3208.c \ # Alpha 8201 #------------------------------------------------- -CPUDEFS += -DHAS_ALPHA8201=$(if $(filter ALPHA8201,$(CPUS)),1,0) -CPUDEFS += -DHAS_ALPHA8301=$(if $(filter ALPHA8301,$(CPUS)),1,0) - -ifneq ($(filter ALPHA8201 ALPHA8301,$(CPUS)),) +ifneq ($(filter ALPHA8201,$(CPUS)),) OBJDIRS += $(CPUOBJ)/alph8201 CPUOBJS += $(CPUOBJ)/alph8201/alph8201.o DBGOBJS += $(CPUOBJ)/alph8201/8201dasm.o @@ -142,8 +134,6 @@ $(CPUOBJ)/alph8201/alph8201.o: $(CPUSRC)/alph8201/alph8201.c \ # Analog Devices ADSP21xx series #------------------------------------------------- -CPUDEFS += -DHAS_ADSP21XX=$(if $(filter ADSP21XX,$(CPUS)),1,0) - ifneq ($(filter ADSP21XX,$(CPUS)),) OBJDIRS += $(CPUOBJ)/adsp2100 CPUOBJS += $(CPUOBJ)/adsp2100/adsp2100.o @@ -160,8 +150,6 @@ $(CPUOBJ)/adsp2100/adsp2100.o: $(CPUSRC)/adsp2100/adsp2100.c \ # Analog Devices "Sharc" ADSP21062 #------------------------------------------------- -CPUDEFS += -DHAS_ADSP21062=$(if $(filter ADSP21062,$(CPUS)),1,0) - ifneq ($(filter ADSP21062,$(CPUS)),) OBJDIRS += $(CPUOBJ)/sharc CPUOBJS += $(CPUOBJ)/sharc/sharc.o @@ -184,8 +172,6 @@ $(CPUOBJ)/sharc/sharc.o: $(CPUSRC)/sharc/sharc.c \ # APEXC #------------------------------------------------- -CPUDEFS += -DHAS_APEXC=$(if $(filter APEXC,$(CPUS)),1,0) - ifneq ($(filter APEXC,$(CPUS)),) OBJDIRS += $(CPUOBJ)/apexc CPUOBJS += $(CPUOBJ)/apexc/apexc.o @@ -201,8 +187,6 @@ $(CPUOBJ)/apexc/apexc.o: $(CPUSRC)/apexc/apexc.c \ # AT&T DSP32C #------------------------------------------------- -CPUDEFS += -DHAS_DSP32C=$(if $(filter DSP32C,$(CPUS)),1,0) - ifneq ($(filter DSP32C,$(CPUS)),) OBJDIRS += $(CPUOBJ)/dsp32 CPUOBJS += $(CPUOBJ)/dsp32/dsp32.o @@ -218,8 +202,6 @@ $(CPUOBJ)/dsp32/dsp32.o: $(CPUSRC)/dsp32/dsp32.c \ # Atari custom RISC processor #------------------------------------------------- -CPUDEFS += -DHAS_ASAP=$(if $(filter ASAP,$(CPUS)),1,0) - ifneq ($(filter ASAP,$(CPUS)),) OBJDIRS += $(CPUOBJ)/asap CPUOBJS += $(CPUOBJ)/asap/asap.o @@ -235,8 +217,6 @@ $(CPUOBJ)/asap/asap.o: $(CPUSRC)/asap/asap.c \ # Atari Jaguar custom DSPs #------------------------------------------------- -CPUDEFS += -DHAS_JAGUAR=$(if $(filter JAGUAR,$(CPUS)),1,0) - ifneq ($(filter JAGUAR,$(CPUS)),) OBJDIRS += $(CPUOBJ)/jaguar CPUOBJS += $(CPUOBJ)/jaguar/jaguar.o @@ -252,8 +232,6 @@ $(CPUOBJ)/jaguar/jaguar.o: $(CPUSRC)/jaguar/jaguar.c \ # Simutrek Cube Quest bit-sliced CPUs #------------------------------------------------- -CPUDEFS += -DHAS_CUBEQCPU=$(if $(filter CUBEQCPU,$(CPUS)),1,0) - ifneq ($(filter CUBEQCPU,$(CPUS)),) OBJDIRS += $(CPUOBJ)/cubeqcpu CPUOBJS += $(CPUOBJ)/cubeqcpu/cubeqcpu.o @@ -269,8 +247,6 @@ $(CPUOBJ)/cubeqcpu/cubeqcpu.o: $(CPUSRC)/cubeqcpu/cubeqcpu.c \ # Entertainment Sciences AM29116-based RIP #------------------------------------------------- -CPUDEFS += -DHAS_ESRIP=$(if $(filter ESRIP,$(CPUS)),1,0) - ifneq ($(filter ESRIP,$(CPUS)),) OBJDIRS += $(CPUOBJ)/esrip CPUOBJS += $(CPUOBJ)/esrip/esrip.o @@ -286,8 +262,6 @@ $(CPUOBJ)/esrip/esrip.o: $(CPUSRC)/esrip/esrip.c \ # RCA CDP1802 #------------------------------------------------- -CPUDEFS += -DHAS_CDP1802=$(if $(filter CDP1802,$(CPUS)),1,0) - ifneq ($(filter CDP1802,$(CPUS)),) OBJDIRS += $(CPUOBJ)/cdp1802 CPUOBJS += $(CPUOBJ)/cdp1802/cdp1802.o @@ -303,8 +277,6 @@ $(CPUOBJ)/cdp1802/cdp1802.o: $(CPUSRC)/cdp1802/cdp1802.c \ # National Semiconductor COP400 family #------------------------------------------------- -CPUDEFS += -DHAS_COP400=$(if $(filter COP400,$(CPUS)),1,0) - ifneq ($(filter COP400,$(CPUS)),) OBJDIRS += $(CPUOBJ)/cop400 CPUOBJS += $(CPUOBJ)/cop400/cop400.o @@ -323,8 +295,6 @@ $(CPUOBJ)/cop400/cop400.o: $(CPUSRC)/cop400/cop400.c \ # CP1610 #------------------------------------------------- -CPUDEFS += -DHAS_CP1610=$(if $(filter CP1610,$(CPUS)),1,0) - ifneq ($(filter CP1610,$(CPUS)),) OBJDIRS += $(CPUOBJ)/cp1610 CPUOBJS += $(CPUOBJ)/cp1610/cp1610.o @@ -340,8 +310,6 @@ $(CPUOBJ)/cp1610/cp1610.o: $(CPUSRC)/cp1610/cp1610.c \ # Cinematronics vector "CPU" #------------------------------------------------- -CPUDEFS += -DHAS_CCPU=$(if $(filter CCPU,$(CPUS)),1,0) - ifneq ($(filter CCPU,$(CPUS)),) OBJDIRS += $(CPUOBJ)/ccpu CPUOBJS += $(CPUOBJ)/ccpu/ccpu.o @@ -357,8 +325,6 @@ $(CPUOBJ)/ccpu/ccpu.o: $(CPUSRC)/ccpu/ccpu.c \ # DEC T-11 #------------------------------------------------- -CPUDEFS += -DHAS_T11=$(if $(filter T11,$(CPUS)),1,0) - ifneq ($(filter T11,$(CPUS)),) OBJDIRS += $(CPUOBJ)/t11 CPUOBJS += $(CPUOBJ)/t11/t11.o @@ -376,8 +342,6 @@ $(CPUOBJ)/t11/t11.o: $(CPUSRC)/t11/t11.c \ # F8 #------------------------------------------------- -CPUDEFS += -DHAS_F8=$(if $(filter F8,$(CPUS)),1,0) - ifneq ($(filter F8,$(CPUS)),) OBJDIRS += $(CPUOBJ)/f8 CPUOBJS += $(CPUOBJ)/f8/f8.o @@ -393,8 +357,6 @@ $(CPUOBJ)/f8/f8.o: $(CPUSRC)/f8/f8.c \ # G65816 #------------------------------------------------- -CPUDEFS += -DHAS_G65816=$(if $(filter G65816,$(CPUS)),1,0) - ifneq ($(filter G65816,$(CPUS)),) OBJDIRS += $(CPUOBJ)/g65816 CPUOBJS += \ @@ -436,8 +398,6 @@ $(CPUOBJ)/g65816/g65816o4.o: $(CPUSRC)/g65816/g65816o4.c \ # Hitachi 6309 #------------------------------------------------- -CPUDEFS += -DHAS_HD6309=$(if $(filter HD6309,$(CPUS)),1,0) - ifneq ($(filter HD6309,$(CPUS)),) OBJDIRS += $(CPUOBJ)/hd6309 CPUOBJS += $(CPUOBJ)/hd6309/hd6309.o @@ -454,8 +414,6 @@ $(CPUOBJ)/hd6309/hd6309.o: $(CPUSRC)/hd6309/hd6309.c \ # Hitachi H8/30xx (16/32-bit H8/3xx series) #------------------------------------------------- -CPUDEFS += -DHAS_H83002=$(if $(filter H83002,$(CPUS)),1,0) - ifneq ($(filter H83002,$(CPUS)),) OBJDIRS += $(CPUOBJ)/h83002 CPUOBJS += $(CPUOBJ)/h83002/h8_16.o $(CPUOBJ)/h83002/h8periph.o @@ -477,8 +435,6 @@ $(CPUOBJ)/h83002/h8periph.o: $(CPUSRC)/h83002/h8periph.c \ # Hitachi H8/3334 (8/16-bit H8/3xx series) #------------------------------------------------- -CPUDEFS += -DHAS_H83334=$(if $(filter H83334,$(CPUS)),1,0) - ifneq ($(filter H83334,$(CPUS)),) OBJDIRS += $(CPUOBJ)/h83002 CPUOBJS += $(CPUOBJ)/h83002/h8_8.o $(CPUOBJ)/h83002/h8periph.o @@ -499,16 +455,6 @@ $(CPUOBJ)/h83002/h8periph.o: $(CPUSRC)/h83002/h8periph.c \ # Hitachi SH1/SH2 #------------------------------------------------- -CPUDEFS += -DHAS_SH1=$(if $(filter SH1,$(CPUS)),1,0) - -ifneq ($(filter SH1,$(CPUS)),) -OBJDIRS += $(CPUOBJ)/sh2 -CPUOBJS += $(CPUOBJ)/sh2/sh2.o $(CPUOBJ)/sh2/sh2comn.o $(CPUOBJ)/sh2/sh2drc.o $(CPUOBJ)/sh2/sh2fe.o $(DRCOBJ) -DBGOBJS += $(CPUOBJ)/sh2/sh2dasm.o -endif - -CPUDEFS += -DHAS_SH2=$(if $(filter SH2,$(CPUS)),1,0) - ifneq ($(filter SH2,$(CPUS)),) OBJDIRS += $(CPUOBJ)/sh2 CPUOBJS += $(CPUOBJ)/sh2/sh2.o $(CPUOBJ)/sh2/sh2comn.o $(CPUOBJ)/sh2/sh2drc.o $(CPUOBJ)/sh2/sh2fe.o $(DRCOBJ) @@ -535,8 +481,6 @@ $(CPUOBJ)/sh2/sh2fe.o: $(CPUSRC)/sh2/sh2fe.c \ # Hitachi SH4 #------------------------------------------------- -CPUDEFS += -DHAS_SH4=$(if $(filter SH4,$(CPUS)),1,0) - ifneq ($(filter SH4,$(CPUS)),) OBJDIRS += $(CPUOBJ)/sh4 CPUOBJS += $(CPUOBJ)/sh4/sh4.o $(CPUOBJ)/sh4/sh4comn.o @@ -557,8 +501,6 @@ $(CPUOBJ)/sh4/sh4comn.o: $(CPUSRC)/sh4/sh4comn.c \ # Hudsonsoft 6280 #------------------------------------------------- -CPUDEFS += -DHAS_H6280=$(if $(filter H6280,$(CPUS)),1,0) - ifneq ($(filter H6280,$(CPUS)),) OBJDIRS += $(CPUOBJ)/h6280 CPUOBJS += $(CPUOBJ)/h6280/h6280.o @@ -576,22 +518,7 @@ $(CPUOBJ)/h6280/h6280.o: $(CPUSRC)/h6280/h6280.c \ # Hyperstone E1 series #------------------------------------------------- -CPUDEFS += -DHAS_E116T=$(if $(filter E116T,$(CPUS)),1,0) -CPUDEFS += -DHAS_E116XT=$(if $(filter E116XT,$(CPUS)),1,0) -CPUDEFS += -DHAS_E116XS=$(if $(filter E116XS,$(CPUS)),1,0) -CPUDEFS += -DHAS_E116XSR=$(if $(filter E116XSR,$(CPUS)),1,0) -CPUDEFS += -DHAS_E132N=$(if $(filter E132N,$(CPUS)),1,0) -CPUDEFS += -DHAS_E132T=$(if $(filter E132T,$(CPUS)),1,0) -CPUDEFS += -DHAS_E132XN=$(if $(filter E132XN,$(CPUS)),1,0) -CPUDEFS += -DHAS_E132XT=$(if $(filter E132XT,$(CPUS)),1,0) -CPUDEFS += -DHAS_E132XS=$(if $(filter E132XS,$(CPUS)),1,0) -CPUDEFS += -DHAS_E132XSR=$(if $(filter E132XSR,$(CPUS)),1,0) -CPUDEFS += -DHAS_GMS30C2116=$(if $(filter GMS30C2116,$(CPUS)),1,0) -CPUDEFS += -DHAS_GMS30C2132=$(if $(filter GMS30C2132,$(CPUS)),1,0) -CPUDEFS += -DHAS_GMS30C2216=$(if $(filter GMS30C2216,$(CPUS)),1,0) -CPUDEFS += -DHAS_GMS30C2232=$(if $(filter GMS30C2232,$(CPUS)),1,0) - -ifneq ($(filter E116T E116XT E116XS E116XSR E132N E132T E132XN E132XT E132XS E132XSR GMS30C2116 GMS30C2132 GMS30C2216 GMS30C2232,$(CPUS)),) +ifneq ($(filter E1,$(CPUS)),) OBJDIRS += $(CPUOBJ)/e132xs CPUOBJS += $(CPUOBJ)/e132xs/e132xs.o DBGOBJS += $(CPUOBJ)/e132xs/32xsdasm.o @@ -607,8 +534,6 @@ $(CPUOBJ)/e132xs/e132xs.o: $(CPUSRC)/e132xs/e132xs.c \ # Intel 8080/8085A #------------------------------------------------- -CPUDEFS += -DHAS_I8085=$(if $(filter I8085,$(CPUS)),1,0) - ifneq ($(filter I8085,$(CPUS)),) OBJDIRS += $(CPUOBJ)/i8085 CPUOBJS += $(CPUOBJ)/i8085/i8085.o @@ -626,8 +551,6 @@ $(CPUOBJ)/i8085/i8085.o: $(CPUSRC)/i8085/i8085.c \ # Intel MCS-48 (8039 and derivatives) #------------------------------------------------- -CPUDEFS += -DHAS_MCS48=$(if $(filter MCS48,$(CPUS)),1,0) - ifneq ($(filter MCS48,$(CPUS)),) OBJDIRS += $(CPUOBJ)/mcs48 CPUOBJS += $(CPUOBJ)/mcs48/mcs48.o @@ -643,22 +566,7 @@ $(CPUOBJ)/mcs48/mcs48.o: $(CPUSRC)/mcs48/mcs48.c \ # Intel 8051 and derivatives #------------------------------------------------- -CPUDEFS += -DHAS_I8031=$(if $(filter I8031,$(CPUS)),1,0) -CPUDEFS += -DHAS_I8032=$(if $(filter I8032,$(CPUS)),1,0) -CPUDEFS += -DHAS_I8051=$(if $(filter I8051,$(CPUS)),1,0) -CPUDEFS += -DHAS_I8052=$(if $(filter I8052,$(CPUS)),1,0) -CPUDEFS += -DHAS_I8751=$(if $(filter I8751,$(CPUS)),1,0) -CPUDEFS += -DHAS_I8752=$(if $(filter I8752,$(CPUS)),1,0) -CPUDEFS += -DHAS_I80C31=$(if $(filter I80C31,$(CPUS)),1,0) -CPUDEFS += -DHAS_I80C32=$(if $(filter I80C32,$(CPUS)),1,0) -CPUDEFS += -DHAS_I80C51=$(if $(filter I80C51,$(CPUS)),1,0) -CPUDEFS += -DHAS_I80C52=$(if $(filter I80C52,$(CPUS)),1,0) -CPUDEFS += -DHAS_I87C51=$(if $(filter I87C51,$(CPUS)),1,0) -CPUDEFS += -DHAS_I87C52=$(if $(filter I87C52,$(CPUS)),1,0) -CPUDEFS += -DHAS_AT89C4051=$(if $(filter AT89C4051,$(CPUS)),1,0) -CPUDEFS += -DHAS_DS5002FP=$(if $(filter DS5002FP,$(CPUS)),1,0) - -ifneq ($(filter DS5002FP I8031 I8032 I8051 I8052 I8751 I8752 I80C31 I80C32 I80C51 I80C52 I87C51 I87C52 AT89C4051,$(CPUS)),) +ifneq ($(filter MCS51,$(CPUS)),) OBJDIRS += $(CPUOBJ)/mcs51 CPUOBJS += $(CPUOBJ)/mcs51/mcs51.o DBGOBJS += $(CPUOBJ)/mcs51/mcs51dasm.o @@ -672,31 +580,14 @@ $(CPUOBJ)/mcs51/mcs51.o: $(CPUSRC)/mcs51/mcs51.c \ # Intel 80x86 series #------------------------------------------------- -CPUDEFS += -DHAS_I8086=$(if $(filter I8086,$(CPUS)),1,0) -CPUDEFS += -DHAS_I8088=$(if $(filter I8088,$(CPUS)),1,0) -CPUDEFS += -DHAS_I80186=$(if $(filter I80186,$(CPUS)),1,0) -CPUDEFS += -DHAS_I80188=$(if $(filter I80188,$(CPUS)),1,0) -CPUDEFS += -DHAS_I80286=$(if $(filter I80286,$(CPUS)),1,0) -CPUDEFS += -DHAS_I386=$(if $(filter I386,$(CPUS)),1,0) -CPUDEFS += -DHAS_I486=$(if $(filter I486,$(CPUS)),1,0) -CPUDEFS += -DHAS_PENTIUM=$(if $(filter PENTIUM,$(CPUS)),1,0) -CPUDEFS += -DHAS_MEDIAGX=$(if $(filter MEDIAGX,$(CPUS)),1,0) - -ifneq ($(filter I8086 I8088 I80186 I80188,$(CPUS)),) +ifneq ($(filter I86,$(CPUS)),) OBJDIRS += $(CPUOBJ)/i86 $(CPUOBJ)/i386 CPUOBJS += $(CPUOBJ)/i86/i86.o -DBGOBJS += $(CPUOBJ)/i386/i386dasm.o -endif - - -ifneq ($(filter I80286,$(CPUS)),) -OBJDIRS += $(CPUOBJ)/i86 $(CPUOBJ)/i386 CPUOBJS += $(CPUOBJ)/i86/i286.o DBGOBJS += $(CPUOBJ)/i386/i386dasm.o endif - -ifneq ($(filter I386 I486 PENTIUM MEDIAGX,$(CPUS)),) +ifneq ($(filter I386,$(CPUS)),) OBJDIRS += $(CPUOBJ)/i386 CPUOBJS += $(CPUOBJ)/i386/i386.o DBGOBJS += $(CPUOBJ)/i386/i386dasm.o @@ -739,8 +630,6 @@ $(CPUOBJ)/i386/i386.o: $(CPUSRC)/i386/i386.c \ # Intel i860 #------------------------------------------------- -CPUDEFS += -DHAS_I860=$(if $(filter I860,$(CPUS)),1,0) - ifneq ($(filter I860,$(CPUS)),) OBJDIRS += $(CPUOBJ)/i860 CPUOBJS += $(CPUOBJ)/i860/i860.o @@ -755,8 +644,6 @@ $(CPUOBJ)/i860/i860.o: $(CPUSRC)/i860/i860.c \ # Intel i960 #------------------------------------------------- -CPUDEFS += -DHAS_I960=$(if $(filter I960,$(CPUS)),1,0) - ifneq ($(filter I960,$(CPUS)),) OBJDIRS += $(CPUOBJ)/i960 CPUOBJS += $(CPUOBJ)/i960/i960.o @@ -772,8 +659,6 @@ $(CPUOBJ)/i960/i960.o: $(CPUSRC)/i960/i960.c \ # Konami custom CPU (6809-based) #------------------------------------------------- -CPUDEFS += -DHAS_KONAMI=$(if $(filter KONAMI,$(CPUS)),1,0) - ifneq ($(filter KONAMI,$(CPUS)),) OBJDIRS += $(CPUOBJ)/konami CPUOBJS += $(CPUOBJ)/konami/konami.o @@ -791,8 +676,6 @@ $(CPUOBJ)/konami/konami.o: $(CPUSRC)/konami/konami.c \ # LH5801 #------------------------------------------------- -CPUDEFS += -DHAS_LH5801=$(if $(filter LH5801,$(CPUS)),1,0) - ifneq ($(filter LH5801,$(CPUS)),) OBJDIRS += $(CPUOBJ)/lh5801 CPUOBJS += $(CPUOBJ)/lh5801/lh5801.o @@ -809,12 +692,7 @@ $(CPUOBJ)/lh5801/lh5801.o: $(CPUSRC)/lh5801/lh5801.c \ # Fujitsu MB88xx #------------------------------------------------- -CPUDEFS += -DHAS_MB8841=$(if $(filter MB8841,$(CPUS)),1,0) -CPUDEFS += -DHAS_MB8842=$(if $(filter MB8842,$(CPUS)),1,0) -CPUDEFS += -DHAS_MB8843=$(if $(filter MB8843,$(CPUS)),1,0) -CPUDEFS += -DHAS_MB8844=$(if $(filter MB8844,$(CPUS)),1,0) - -ifneq ($(filter MB8841 MB8842 MB8843 MB8844,$(CPUS)),) +ifneq ($(filter MB88XX,$(CPUS)),) OBJDIRS += $(CPUOBJ)/mb88xx CPUOBJS += $(CPUOBJ)/mb88xx/mb88xx.o DBGOBJS += $(CPUOBJ)/mb88xx/mb88dasm.o @@ -829,8 +707,6 @@ $(CPUOBJ)/mb88xx/mb88xx.o: $(CPUSRC)/mb88xx/mb88xx.c \ # Fujitsu MB86233 #------------------------------------------------- -CPUDEFS += -DHAS_MB86233=$(if $(filter MB86233,$(CPUS)),1,0) - ifneq ($(filter MB86233,$(CPUS)),) OBJDIRS += $(CPUOBJ)/mb86233 CPUOBJS += $(CPUOBJ)/mb86233/mb86233.o @@ -846,13 +722,7 @@ $(CPUOBJ)/mb86233/mb86233.o: $(CPUSRC)/mb86233/mb86233.c \ # Microchip PIC16C5x #------------------------------------------------- -CPUDEFS += -DHAS_PIC16C54=$(if $(filter PIC16C54,$(CPUS)),1,0) -CPUDEFS += -DHAS_PIC16C55=$(if $(filter PIC16C55,$(CPUS)),1,0) -CPUDEFS += -DHAS_PIC16C56=$(if $(filter PIC16C56,$(CPUS)),1,0) -CPUDEFS += -DHAS_PIC16C57=$(if $(filter PIC16C57,$(CPUS)),1,0) -CPUDEFS += -DHAS_PIC16C58=$(if $(filter PIC16C58,$(CPUS)),1,0) - -ifneq ($(filter PIC16C54 PIC16C55 PIC16C56 PIC16C57 PIC16C58,$(CPUS)),) +ifneq ($(filter PIC16C5X,$(CPUS)),) OBJDIRS += $(CPUOBJ)/pic16c5x CPUOBJS += $(CPUOBJ)/pic16c5x/pic16c5x.o DBGOBJS += $(CPUOBJ)/pic16c5x/16c5xdsm.o @@ -865,40 +735,23 @@ $(CPUOBJ)/pic16c5x/pic16c5x.o: $(CPUSRC)/pic16c5x/pic16c5x.c \ #------------------------------------------------- # MIPS R3000 (MIPS I/II) series +# MIPS R4000 (MIPS III/IV) series +# Sony PlayStation CPU (R3000-based + GTE) #------------------------------------------------- -CPUDEFS += -DHAS_R3000=$(if $(filter R3000,$(CPUS)),1,0) -CPUDEFS += -DHAS_R3041=$(if $(filter R3041,$(CPUS)),1,0) - -ifneq ($(filter R3000 R3041,$(CPUS)),) +ifneq ($(filter MIPS,$(CPUS)),) OBJDIRS += $(CPUOBJ)/mips CPUOBJS += $(CPUOBJ)/mips/r3000.o +CPUOBJS += $(CPUOBJ)/mips/mips3com.o $(CPUOBJ)/mips/mips3fe.o $(CPUOBJ)/mips/mips3drc.o $(DRCOBJ) +CPUOBJS += $(CPUOBJ)/mips/psx.o DBGOBJS += $(CPUOBJ)/mips/r3kdasm.o +DBGOBJS += $(CPUOBJ)/mips/mips3dsm.o +DBGOBJS += $(CPUOBJ)/mips/psxdasm.o endif $(CPUOBJ)/mips/r3000.o: $(CPUSRC)/mips/r3000.c \ $(CPUSRC)/mips/r3000.h - - -#------------------------------------------------- -# MIPS R4000 (MIPS III/IV) series -#------------------------------------------------- - -CPUDEFS += -DHAS_VR4300=$(if $(filter VR4300,$(CPUS)),1,0) -CPUDEFS += -DHAS_R4600=$(if $(filter R4600,$(CPUS)),1,0) -CPUDEFS += -DHAS_R4650=$(if $(filter R4650,$(CPUS)),1,0) -CPUDEFS += -DHAS_R4700=$(if $(filter R4700,$(CPUS)),1,0) -CPUDEFS += -DHAS_R5000=$(if $(filter R5000,$(CPUS)),1,0) -CPUDEFS += -DHAS_QED5271=$(if $(filter QED5271,$(CPUS)),1,0) -CPUDEFS += -DHAS_RM7000=$(if $(filter RM7000,$(CPUS)),1,0) - -ifneq ($(filter VR4300 R4600 R4650 R4700 R5000 QED5271 RM7000,$(CPUS)),) -OBJDIRS += $(CPUOBJ)/mips -CPUOBJS += $(CPUOBJ)/mips/mips3com.o $(CPUOBJ)/mips/mips3fe.o $(CPUOBJ)/mips/mips3drc.o $(DRCOBJ) -DBGOBJS += $(CPUOBJ)/mips/mips3dsm.o -endif - $(CPUOBJ)/mips/mips3com.o: $(CPUSRC)/mips/mips3.h \ $(CPUSRC)/mips/mips3com.h @@ -912,16 +765,16 @@ $(CPUOBJ)/mips/mips3drc.o: $(CPUSRC)/mips/mips3drc.c \ $(CPUSRC)/mips/mips3fe.h \ $(DRCDEPS) +$(CPUOBJ)/mips/psx.o: $(CPUSRC)/mips/psx.c \ + $(CPUSRC)/mips/psx.h + #------------------------------------------------- # Mitsubishi M37702 and M37710 (based on 65C816) #------------------------------------------------- -CPUDEFS += -DHAS_M37702=$(if $(filter M37702,$(CPUS)),1,0) -CPUDEFS += -DHAS_M37710=$(if $(filter M37710,$(CPUS)),1,0) - -ifneq ($(filter M37702 M37710,$(CPUS)),) +ifneq ($(filter M37710,$(CPUS)),) OBJDIRS += $(CPUOBJ)/m37710 CPUOBJS += \ $(CPUOBJ)/m37710/m37710.o \ @@ -961,39 +814,11 @@ $(CPUOBJ)/m37710/m7700ds.o: $(CPUSRC)/m37710/m7700ds.c \ # Mostek 6502 and its many derivatives #------------------------------------------------- -CPUDEFS += -DHAS_M6502=$(if $(filter M6502,$(CPUS)),1,0) -CPUDEFS += -DHAS_M65C02=$(if $(filter M65C02,$(CPUS)),1,0) -CPUDEFS += -DHAS_M65SC02=$(if $(filter M65SC02,$(CPUS)),1,0) -CPUDEFS += -DHAS_M65CE02=$(if $(filter M65CE02,$(CPUS)),1,0) -CPUDEFS += -DHAS_M6509=$(if $(filter M6509,$(CPUS)),1,0) -CPUDEFS += -DHAS_M6510=$(if $(filter M6510 M6510T M7501 M8502,$(CPUS)),1,0) -CPUDEFS += -DHAS_M6510T=$(if $(filter M6510T,$(CPUS)),1,0) -CPUDEFS += -DHAS_M7501=$(if $(filter M7501,$(CPUS)),1,0) -CPUDEFS += -DHAS_M8502=$(if $(filter M8502,$(CPUS)),1,0) -CPUDEFS += -DHAS_N2A03=$(if $(filter N2A03,$(CPUS)),1,0) -CPUDEFS += -DHAS_DECO16=$(if $(filter DECO16,$(CPUS)),1,0) -CPUDEFS += -DHAS_M4510=$(if $(filter M4510,$(CPUS)),1,0) - -ifneq ($(filter M6502 M65C02 M65SC02 M6510 M6510T M7501 M8502 N2A03 DECO16,$(CPUS)),) +ifneq ($(filter M6502,$(CPUS)),) OBJDIRS += $(CPUOBJ)/m6502 CPUOBJS += $(CPUOBJ)/m6502/m6502.o -DBGOBJS += $(CPUOBJ)/m6502/6502dasm.o -endif - -ifneq ($(filter M65CE02,$(CPUS)),) -OBJDIRS += $(CPUOBJ)/m6502 -CPUOBJS += $(CPUOBJ)/m6502/m65ce02.o -DBGOBJS += $(CPUOBJ)/m6502/6502dasm.o -endif - -ifneq ($(filter M6509,$(CPUS)),) -OBJDIRS += $(CPUOBJ)/m6502 CPUOBJS += $(CPUOBJ)/m6502/m6509.o -DBGOBJS += $(CPUOBJ)/m6502/6502dasm.o -endif - -ifneq ($(filter M4510,$(CPUS)),) -OBJDIRS += $(CPUOBJ)/m6502 +CPUOBJS += $(CPUOBJ)/m6502/m65ce02.o CPUOBJS += $(CPUOBJ)/m6502/m4510.o DBGOBJS += $(CPUOBJ)/m6502/6502dasm.o endif @@ -1023,15 +848,7 @@ $(CPUOBJ)/m6502/m6509.o: $(CPUSRC)/m6502/m6509.c \ # Motorola 680x #------------------------------------------------- -CPUDEFS += -DHAS_M6800=$(if $(filter M6800,$(CPUS)),1,0) -CPUDEFS += -DHAS_M6801=$(if $(filter M6801,$(CPUS)),1,0) -CPUDEFS += -DHAS_M6802=$(if $(filter M6802,$(CPUS)),1,0) -CPUDEFS += -DHAS_M6803=$(if $(filter M6803,$(CPUS)),1,0) -CPUDEFS += -DHAS_M6808=$(if $(filter M6808,$(CPUS)),1,0) -CPUDEFS += -DHAS_HD63701=$(if $(filter HD63701,$(CPUS)),1,0) -CPUDEFS += -DHAS_NSC8105=$(if $(filter NSC8105,$(CPUS)),1,0) - -ifneq ($(filter M6800 M6801 M6802 M6803 M6808 HD63701 NSC8105,$(CPUS)),) +ifneq ($(filter M6800,$(CPUS)),) OBJDIRS += $(CPUOBJ)/m6800 CPUOBJS += $(CPUOBJ)/m6800/m6800.o DBGOBJS += $(CPUOBJ)/m6800/6800dasm.o @@ -1048,11 +865,7 @@ $(CPUOBJ)/m6800/m6800.o: $(CPUSRC)/m6800/m6800.c \ # Motorola 6805 #------------------------------------------------- -CPUDEFS += -DHAS_M6805=$(if $(filter M6805,$(CPUS)),1,0) -CPUDEFS += -DHAS_M68705=$(if $(filter M68705,$(CPUS)),1,0) -CPUDEFS += -DHAS_HD63705=$(if $(filter HD63705,$(CPUS)),1,0) - -ifneq ($(filter M6805 M68705 HD63705,$(CPUS)),) +ifneq ($(filter M6805,$(CPUS)),) OBJDIRS += $(CPUOBJ)/m6805 CPUOBJS += $(CPUOBJ)/m6805/m6805.o DBGOBJS += $(CPUOBJ)/m6805/6805dasm.o @@ -1068,10 +881,7 @@ $(CPUOBJ)/m6805/m6805.o: $(CPUSRC)/m6805/m6805.c \ # Motorola 6809 #------------------------------------------------- -CPUDEFS += -DHAS_M6809=$(if $(filter M6809,$(CPUS)),1,0) -CPUDEFS += -DHAS_M6809E=$(if $(filter M6809E,$(CPUS)),1,0) - -ifneq ($(filter M6809 M6809E,$(CPUS)),) +ifneq ($(filter M6809,$(CPUS)),) OBJDIRS += $(CPUOBJ)/m6809 CPUOBJS += $(CPUOBJ)/m6809/m6809.o DBGOBJS += $(CPUOBJ)/m6809/6809dasm.o @@ -1088,8 +898,6 @@ $(CPUOBJ)/m6809/m6809.o: $(CPUSRC)/m6809/m6809.c \ # Motorola 68HC11 #------------------------------------------------- -CPUDEFS += -DHAS_MC68HC11=$(if $(filter MC68HC11,$(CPUS)),1,0) - ifneq ($(filter MC68HC11,$(CPUS)),) OBJDIRS += $(CPUOBJ)/mc68hc11 CPUOBJS += $(CPUOBJ)/mc68hc11/mc68hc11.o @@ -1105,8 +913,6 @@ $(CPUOBJ)/mc68hc11/mc68hc11.o: $(CPUSRC)/mc68hc11/mc68hc11.c \ # Motorola 68000 series #------------------------------------------------- -CPUDEFS += -DHAS_M680X0=$(if $(filter M680X0,$(CPUS)),1,0) - ifneq ($(filter M680X0,$(CPUS)),) OBJDIRS += $(CPUOBJ)/m68000 CPUOBJS += $(CPUOBJ)/m68000/m68kcpu.o $(CPUOBJ)/m68000/m68kops.o @@ -1149,8 +955,6 @@ $(CPUOBJ)/m68000/m68kcpu.o: $(CPUOBJ)/m68000/m68kops.c \ # Motorola/Freescale dsp56k #------------------------------------------------- -CPUDEFS += -DHAS_DSP56156=$(if $(filter DSP56156,$(CPUS)),1,0) - ifneq ($(filter DSP56156,$(CPUS)),) OBJDIRS += $(CPUOBJ)/dsp56k CPUOBJS += $(CPUOBJ)/dsp56k/dsp56k.o @@ -1165,27 +969,31 @@ $(CPUOBJ)/dsp56k/dsp56k.o: $(CPUSRC)/dsp56k/dsp56k.c \ #------------------------------------------------- # PDP-1 +# TX0 #------------------------------------------------- -CPUDEFS += -DHAS_PDP1=$(if $(filter PDP1,$(CPUS)),1,0) - ifneq ($(filter PDP1,$(CPUS)),) OBJDIRS += $(CPUOBJ)/pdp1 CPUOBJS += $(CPUOBJ)/pdp1/pdp1.o +CPUOBJS += $(CPUOBJ)/pdp1/tx0.o DBGOBJS += $(CPUOBJ)/pdp1/pdp1dasm.o +DBGOBJS += $(CPUOBJ)/pdp1/tx0dasm.o endif $(CPUOBJ)/pdp1/pdp1.o: $(CPUSRC)/pdp1/pdp1.c \ $(CPUSRC)/pdp1/pdp1.h +$(CPUOBJ)/pdp1/tx0.o: $(CPUSRC)/pdp1/tx0.h \ + $(CPUSRC)/pdp1/tx0.c + +$(CPUOBJ)/pdp1/tx0dasm.o: $(CPUSRC)/pdp1/tx0.h \ + $(CPUSRC)/pdp1/tx0dasm.c #------------------------------------------------- # Motorola PowerPC series #------------------------------------------------- -CPUDEFS += -DHAS_POWERPC=$(if $(filter POWERPC,$(CPUS)),1,0) - ifneq ($(filter POWERPC,$(CPUS)),) OBJDIRS += $(CPUOBJ)/powerpc CPUOBJS += $(CPUOBJ)/powerpc/ppccom.o $(CPUOBJ)/powerpc/ppcfe.o $(CPUOBJ)/powerpc/ppcdrc.o $(DRCOBJ) @@ -1211,14 +1019,7 @@ $(CPUOBJ)/powerpc/ppcdrc.o: $(CPUSRC)/powerpc/ppcdrc.c \ # NEC V-series Intel-compatible #------------------------------------------------- -CPUDEFS += -DHAS_V20=$(if $(filter V20,$(CPUS)),1,0) -CPUDEFS += -DHAS_V25=$(if $(filter V25,$(CPUS)),1,0) -CPUDEFS += -DHAS_V30=$(if $(filter V30,$(CPUS)),1,0) -CPUDEFS += -DHAS_V30MZ=$(if $(filter V30MZ,$(CPUS)),1,0) -CPUDEFS += -DHAS_V33=$(if $(filter V33,$(CPUS)),1,0) -CPUDEFS += -DHAS_V35=$(if $(filter V35,$(CPUS)),1,0) - -ifneq ($(filter V20 V25 V30 V33 V35,$(CPUS)),) +ifneq ($(filter NEC,$(CPUS)),) OBJDIRS += $(CPUOBJ)/nec CPUOBJS += $(CPUOBJ)/nec/nec.o DBGOBJS += $(CPUOBJ)/nec/necdasm.o @@ -1252,10 +1053,7 @@ $(CPUOBJ)/v30mz/v30mz.o: $(CPUSRC)/v30mz/v30mz.c \ # NEC V60/V70 #------------------------------------------------- -CPUDEFS += -DHAS_V60=$(if $(filter V60,$(CPUS)),1,0) -CPUDEFS += -DHAS_V70=$(if $(filter V70,$(CPUS)),1,0) - -ifneq ($(filter V60 V70,$(CPUS)),) +ifneq ($(filter V60,$(CPUS)),) OBJDIRS += $(CPUOBJ)/v60 CPUOBJS += $(CPUOBJ)/v60/v60.o DBGOBJS += $(CPUOBJ)/v60/v60d.o @@ -1283,8 +1081,6 @@ $(CPUOBJ)/v60/v60.o: $(CPUSRC)/v60/am.c \ # NEC V810 (uPD70732) #------------------------------------------------- -CPUDEFS += -DHAS_V810=$(if $(filter V810,$(CPUS)),1,0) - ifneq ($(filter V810,$(CPUS)),) OBJDIRS += $(CPUOBJ)/v810 CPUOBJS += $(CPUOBJ)/v810/v810.o @@ -1300,11 +1096,7 @@ $(CPUOBJ)/v810/v810.o: $(CPUSRC)/v810/v810.c \ # NEC uPD7810 series #------------------------------------------------- -CPUDEFS += -DHAS_UPD7810=$(if $(filter UPD7810,$(CPUS)),1,0) -CPUDEFS += -DHAS_UPD7807=$(if $(filter UPD7807,$(CPUS)),1,0) -CPUDEFS += -DHAS_UPD7801=$(if $(filter UPD7801,$(CPUS)),1,0) - -ifneq ($(filter UPD7810 UPD7807 UPD7801,$(CPUS)),) +ifneq ($(filter UPD7810,$(CPUS)),) OBJDIRS += $(CPUOBJ)/upd7810 CPUOBJS += $(CPUOBJ)/upd7810/upd7810.o DBGOBJS += $(CPUOBJ)/upd7810/7810dasm.o @@ -1321,8 +1113,6 @@ $(CPUOBJ)/upd7810/upd7810.o: $(CPUSRC)/upd7810/upd7810.c \ # Nintendo Minx #------------------------------------------------- -CPUDEFS += -DHAS_MINX=$(if $(filter MINX,$(CPUS)),1,0) - ifneq ($(filter MINX,$(CPUS)),) OBJDIRS += $(CPUOBJ)/minx CPUOBJS += $(CPUOBJ)/minx/minx.o @@ -1343,8 +1133,6 @@ $(CPUOBJ)/minx/minx.o: $(CPUSRC)/minx/minx.c \ # Nintendo/SGI RSP (R3000-based + vector processing) #------------------------------------------------- -CPUDEFS += -DHAS_RSP=$(if $(filter RSP,$(CPUS)),1,0) - ifneq ($(filter RSP,$(CPUS)),) OBJDIRS += $(CPUOBJ)/rsp CPUOBJS += $(CPUOBJ)/rsp/rsp.o @@ -1360,8 +1148,6 @@ $(CPUOBJ)/rsp/rsp.o: $(CPUSRC)/rsp/rsp.c \ # Saturn #------------------------------------------------- -CPUDEFS += -DHAS_SATURN=$(if $(filter SATURN,$(CPUS)),1,0) - ifneq ($(filter SATURN,$(CPUS)),) OBJDIRS += $(CPUOBJ)/saturn CPUOBJS += $(CPUOBJ)/saturn/saturn.o @@ -1379,8 +1165,6 @@ $(CPUOBJ)/saturn/saturn.o: $(CPUSRC)/saturn/saturn.c \ # Signetics 2650 #------------------------------------------------- -CPUDEFS += -DHAS_S2650=$(if $(filter S2650,$(CPUS)),1,0) - ifneq ($(filter S2650,$(CPUS)),) OBJDIRS += $(CPUOBJ)/s2650 CPUOBJS += $(CPUOBJ)/s2650/s2650.o @@ -1397,8 +1181,6 @@ $(CPUOBJ)/s2650/s2650.o: $(CPUSRC)/s2650/s2650.c \ # SC61860 #------------------------------------------------- -CPUDEFS += -DHAS_SC61860=$(if $(filter SC61860,$(CPUS)),1,0) - ifneq ($(filter SC61860,$(CPUS)),) OBJDIRS += $(CPUOBJ)/sc61860 CPUOBJS += $(CPUOBJ)/sc61860/sc61860.o @@ -1416,8 +1198,6 @@ $(CPUOBJ)/sc61860/sc61860.o: $(CPUSRC)/sc61860/sc61860.h \ # SM8500 #------------------------------------------------- -CPUDEFS += -DHAS_SM8500=$(if $(filter SM8500,$(CPUS)),1,0) - ifneq ($(filter SM8500,$(CPUS)),) OBJDIRS += $(CPUOBJ)/sm8500 CPUOBJS += $(CPUOBJ)/sm8500/sm8500.o @@ -1434,8 +1214,6 @@ $(CPUOBJ)/sm8500/sm8500.o: $(CPUSRC)/sm8500/sm8500.c \ # Sony/Nintendo SPC700 #------------------------------------------------- -CPUDEFS += -DHAS_SPC700=$(if $(filter SPC700,$(CPUS)),1,0) - ifneq ($(filter SPC700,$(CPUS)),) SPCD = cpu/spc700 OBJDIRS += $(CPUOBJ)/spc700 @@ -1448,30 +1226,10 @@ $(CPUOBJ)/spc700/spc700.o: $(CPUSRC)/spc700/spc700.c \ -#------------------------------------------------- -# Sony PlayStation CPU (R3000-based + GTE) -#------------------------------------------------- - -CPUDEFS += -DHAS_PSXCPU=$(if $(filter PSXCPU,$(CPUS)),1,0) -CPUDEFS += -DHAS_CXD8661R=$(if $(filter CXD8661R,$(CPUS)),1,0) - -ifneq ($(filter PSXCPU CXD8661R,$(CPUS)),) -OBJDIRS += $(CPUOBJ)/mips -CPUOBJS += $(CPUOBJ)/mips/psx.o -DBGOBJS += $(CPUOBJ)/mips/psxdasm.o -endif - -$(CPUOBJ)/mips/psx.o: $(CPUSRC)/mips/psx.c \ - $(CPUSRC)/mips/psx.h - - - #------------------------------------------------- # SSP1601 #------------------------------------------------- -CPUDEFS += -DHAS_SSP1601=$(if $(filter SSP1601,$(CPUS)),1,0) - ifneq ($(filter SSP1601,$(CPUS)),) OBJDIRS += $(CPUOBJ)/ssp1601 CPUOBJS += $(CPUOBJ)/ssp1601/ssp1601.o @@ -1487,10 +1245,7 @@ $(CPUOBJ)/ssp1610/ssp1601.o: $(CPUSRC)/ssp1601/ssp1601.c \ # Texas Instruments TMS7000 series #------------------------------------------------- -CPUDEFS += -DHAS_TMS7000=$(if $(filter TMS7000,$(CPUS)),1,0) -CPUDEFS += -DHAS_TMS7000_EXL=$(if $(filter TMS7000_EXL,$(CPUS)),1,0) - -ifneq ($(filter TMS7000 TMS7000_EXL,$(CPUS)),) +ifneq ($(filter TMS7000,$(CPUS)),) OBJDIRS += $(CPUOBJ)/tms7000 CPUOBJS += $(CPUOBJ)/tms7000/tms7000.o DBGOBJS += $(CPUOBJ)/tms7000/7000dasm.o @@ -1508,37 +1263,11 @@ $(CPUOBJ)/tms7000/7000dasm.o: $(CPUSRC)/tms7000/tms7000.h \ # Texas Instruments TMS99xx series #------------------------------------------------- -CPUDEFS += -DHAS_TMS9900=$(if $(filter TMS9900,$(CPUS)),1,0) -CPUDEFS += -DHAS_TMS9940=$(if $(filter TMS9940,$(CPUS)),1,0) -CPUDEFS += -DHAS_TMS9980=$(if $(filter TMS9980,$(CPUS)),1,0) -CPUDEFS += -DHAS_TMS9985=$(if $(filter TMS9985,$(CPUS)),1,0) -CPUDEFS += -DHAS_TMS9989=$(if $(filter TMS9989,$(CPUS)),1,0) -CPUDEFS += -DHAS_TMS9995=$(if $(filter TMS9995,$(CPUS)),1,0) -CPUDEFS += -DHAS_TMS99105A=$(if $(filter TMS99105A,$(CPUS)),1,0) -CPUDEFS += -DHAS_TMS99110A=$(if $(filter TMS99110A,$(CPUS)),1,0) -CPUDEFS += -DHAS_TMS99000=$(if $(filter TMS99000,$(CPUS)),1,0) -CPUDEFS += -DHAS_TI990_10=$(if $(filter TMS99010,$(CPUS)),1,0) - -ifneq ($(filter TMS9900 TMS9940 TMS99000,$(CPUS)),) +ifneq ($(filter TMS9900,$(CPUS)),) OBJDIRS += $(CPUOBJ)/tms9900 CPUOBJS += $(CPUOBJ)/tms9900/tms9900.o -DBGOBJS += $(CPUOBJ)/tms9900/9900dasm.o -endif - -ifneq ($(filter TMS9980 TMS9985 TMS9989,$(CPUS)),) -OBJDIRS += $(CPUOBJ)/tms9900 CPUOBJS += $(CPUOBJ)/tms9900/tms9980a.o -DBGOBJS += $(CPUOBJ)/tms9900/9900dasm.o -endif - -ifneq ($(filter TMS9995 TMS99105A TMS99110A,$(CPUS)),) -OBJDIRS += $(CPUOBJ)/tms9900 CPUOBJS += $(CPUOBJ)/tms9900/tms9995.o -DBGOBJS += $(CPUOBJ)/tms9900/9900dasm.o -endif - -ifneq ($(filter TMS99010,$(CPUS)),) -OBJDIRS += $(CPUOBJ)/tms9900 CPUOBJS += $(CPUOBJ)/tms9900/ti990_10.o DBGOBJS += $(CPUOBJ)/tms9900/9900dasm.o endif @@ -1569,8 +1298,6 @@ $(CPUOBJ)/tms9900/ti990_10.o: $(CPUSRC)/tms9900/ti990_10.c \ # Texas Instruments TMS340x0 graphics controllers #------------------------------------------------- -CPUDEFS += -DHAS_TMS340X0=$(if $(filter TMS340X0,$(CPUS)),1,0) - ifneq ($(filter TMS340X0,$(CPUS)),) OBJDIRS += $(CPUOBJ)/tms34010 CPUOBJS += $(CPUOBJ)/tms34010/tms34010.o @@ -1590,8 +1317,6 @@ $(CPUOBJ)/tms34010/tms34010.o: $(CPUSRC)/tms34010/tms34010.c \ # Texas Instruments TMS3201x DSP #------------------------------------------------- -CPUDEFS += -DHAS_TMS32010=$(if $(filter TMS32010,$(CPUS)),1,0) - ifneq ($(filter TMS32010,$(CPUS)),) OBJDIRS += $(CPUOBJ)/tms32010 CPUOBJS += $(CPUOBJ)/tms32010/tms32010.o @@ -1607,10 +1332,7 @@ $(CPUOBJ)/tms32010/tms32010.o: $(CPUSRC)/tms32010/tms32010.c \ # Texas Instruments TMS3202x DSP #------------------------------------------------- -CPUDEFS += -DHAS_TMS32025=$(if $(filter TMS32025,$(CPUS)),1,0) -CPUDEFS += -DHAS_TMS32026=$(if $(filter TMS32026,$(CPUS)),1,0) - -ifneq ($(filter TMS32025 TMS32026,$(CPUS)),) +ifneq ($(filter TMS32025,$(CPUS)),) OBJDIRS += $(CPUOBJ)/tms32025 CPUOBJS += $(CPUOBJ)/tms32025/tms32025.o DBGOBJS += $(CPUOBJ)/tms32025/32025dsm.o @@ -1625,10 +1347,7 @@ $(CPUOBJ)/tms32025/tms32025.o: $(CPUSRC)/tms32025/tms32025.c \ # Texas Instruments TMS3203x DSP #------------------------------------------------- -CPUDEFS += -DHAS_TMS32031=$(if $(filter TMS32031,$(CPUS)),1,0) -CPUDEFS += -DHAS_TMS32032=$(if $(filter TMS32032,$(CPUS)),1,0) - -ifneq ($(filter TMS32031 TMS32032,$(CPUS)),) +ifneq ($(filter TMS32031,$(CPUS)),) OBJDIRS += $(CPUOBJ)/tms32031 CPUOBJS += $(CPUOBJ)/tms32031/tms32031.o DBGOBJS += $(CPUOBJ)/tms32031/dis32031.o @@ -1644,8 +1363,6 @@ $(CPUOBJ)/tms32031/tms32031.o: $(CPUSRC)/tms32031/tms32031.c \ # Texas Instruments TMS3205x DSP #------------------------------------------------- -CPUDEFS += -DHAS_TMS32051=$(if $(filter TMS32051,$(CPUS)),1,0) - ifneq ($(filter TMS32051,$(CPUS)),) OBJDIRS += $(CPUOBJ)/tms32051 CPUOBJS += $(CPUOBJ)/tms32051/tms32051.o @@ -1661,8 +1378,6 @@ $(CPUOBJ)/tms32051/tms32051.o: $(CPUSRC)/tms32051/tms32051.c \ # Texas Instruments TMS57002 DSP #------------------------------------------------- -CPUDEFS += -DHAS_TMS57002=$(if $(filter TMS57002,$(CPUS)),1,0) - ifneq ($(filter TMS57002,$(CPUS)),) OBJDIRS += $(CPUOBJ)/tms57002 CPUOBJS += $(CPUOBJ)/tms57002/tms57002.o @@ -1694,8 +1409,6 @@ endif # Toshiba TLCS-90 Series #------------------------------------------------- -CPUDEFS += -DHAS_TLCS90=$(if $(filter TLCS90,$(CPUS)),1,0) - ifneq ($(filter TLCS90,$(CPUS)),) OBJDIRS += $(CPUOBJ)/tlcs90 CPUOBJS += $(CPUOBJ)/tlcs90/tlcs90.o @@ -1707,33 +1420,10 @@ $(CPUOBJ)/tlcs90/tlcs90.o: $(CPUSRC)/tlcs90/tlcs90.c \ -#------------------------------------------------- -# TX0 -#------------------------------------------------- - -CPUDEFS += -DHAS_TX0_64KW=$(if $(filter TX0,$(CPUS)),1,0) -CPUDEFS += -DHAS_TX0_8KW=$(if $(filter TX0,$(CPUS)),1,0) - -ifneq ($(filter TX0,$(CPUS)),) -OBJDIRS += $(CPUOBJ)/pdp1 -CPUOBJS += $(CPUOBJ)/pdp1/tx0.o -DBGOBJS += $(CPUOBJ)/pdp1/tx0dasm.o -endif - -$(CPUOBJ)/pdp1/tx0.o: $(CPUSRC)/pdp1/tx0.h \ - $(CPUSRC)/pdp1/tx0.c - -$(CPUOBJ)/pdp1/tx0dasm.o: $(CPUSRC)/pdp1/tx0.h \ - $(CPUSRC)/pdp1/tx0dasm.c - - - #------------------------------------------------- # Zilog Z80 #------------------------------------------------- -CPUDEFS += -DHAS_Z80=$(if $(filter Z80,$(CPUS)),1,0) - ifneq ($(filter Z80,$(CPUS)),) OBJDIRS += $(CPUOBJ)/z80 CPUOBJS += $(CPUOBJ)/z80/z80.o $(CPUOBJ)/z80/z80daisy.o @@ -1749,8 +1439,6 @@ $(CPUOBJ)/z80/z80.o: $(CPUSRC)/z80/z80.c \ # Sharp LR35902 (Game Boy CPU) #------------------------------------------------- -CPUDEFS += -DHAS_LR35902=$(if $(filter LR35902,$(CPUS)),1,0) - ifneq ($(filter LR35902,$(CPUS)),) OBJDIRS += $(CPUOBJ)/lr35902 CPUOBJS += $(CPUOBJ)/lr35902/lr35902.o @@ -1768,8 +1456,6 @@ $(CPUOBJ)/lr35902/lr35902.o: $(CPUSRC)/lr35902/lr35902.c \ # Zilog Z180 #------------------------------------------------- -CPUDEFS += -DHAS_Z180=$(if $(filter Z180,$(CPUS)),1,0) - ifneq ($(filter Z180,$(CPUS)),) OBJDIRS += $(CPUOBJ)/z180 $(CPUOBJ)/z80 CPUOBJS += $(CPUOBJ)/z180/z180.o $(CPUOBJ)/z80/z80daisy.o @@ -1794,8 +1480,6 @@ $(CPUOBJ)/z180/z180.o: $(CPUSRC)/z180/z180.c \ # Zilog Z8000 #------------------------------------------------- -CPUDEFS += -DHAS_Z8000=$(if $(filter Z8000,$(CPUS)),1,0) - ifneq ($(filter Z8000,$(CPUS)),) OBJDIRS += $(CPUOBJ)/z8000 CPUOBJS += $(CPUOBJ)/z8000/z8000.o diff --git a/src/emu/cpu/e132xs/e132xs.c b/src/emu/cpu/e132xs/e132xs.c index d8a3ef62ff3..d4ac0f31bdd 100644 --- a/src/emu/cpu/e132xs/e132xs.c +++ b/src/emu/cpu/e132xs/e132xs.c @@ -377,57 +377,45 @@ static void check_interrupts(hyperstone_state *cpustate); #define SAME_SRCF_DST (decode)->same_srcf_dst // 4Kb IRAM (On-Chip Memory) -#if (HAS_E116T || HAS_GMS30C2116) static ADDRESS_MAP_START( e116_4k_iram_map, ADDRESS_SPACE_PROGRAM, 16 ) AM_RANGE(0xc0000000, 0xc0000fff) AM_RAM AM_MIRROR(0x1ffff000) ADDRESS_MAP_END -#endif -#if (HAS_E132N || HAS_E132T || HAS_GMS30C2132) static ADDRESS_MAP_START( e132_4k_iram_map, ADDRESS_SPACE_PROGRAM, 32 ) AM_RANGE(0xc0000000, 0xc0000fff) AM_RAM AM_MIRROR(0x1ffff000) ADDRESS_MAP_END -#endif // 8Kb IRAM (On-Chip Memory) -#if (HAS_E116XT || HAS_GMS30C2216) static ADDRESS_MAP_START( e116_8k_iram_map, ADDRESS_SPACE_PROGRAM, 16 ) AM_RANGE(0xc0000000, 0xc0001fff) AM_RAM AM_MIRROR(0x1fffe000) ADDRESS_MAP_END -#endif -#if (HAS_E132XN || HAS_E132XT || HAS_GMS30C2232) static ADDRESS_MAP_START( e132_8k_iram_map, ADDRESS_SPACE_PROGRAM, 32 ) AM_RANGE(0xc0000000, 0xc0001fff) AM_RAM AM_MIRROR(0x1fffe000) ADDRESS_MAP_END -#endif // 16Kb IRAM (On-Chip Memory) -#if (HAS_E116XS || HAS_E116XSR) static ADDRESS_MAP_START( e116_16k_iram_map, ADDRESS_SPACE_PROGRAM, 16 ) AM_RANGE(0xc0000000, 0xc0003fff) AM_RAM AM_MIRROR(0x1fffc000) ADDRESS_MAP_END -#endif -#if (HAS_E132XS || HAS_E132XSR) static ADDRESS_MAP_START( e132_16k_iram_map, ADDRESS_SPACE_PROGRAM, 32 ) AM_RANGE(0xc0000000, 0xc0003fff) AM_RAM AM_MIRROR(0x1fffc000) ADDRESS_MAP_END -#endif INLINE hyperstone_state *get_safe_token(const device_config *device) { @@ -1565,121 +1553,89 @@ static void hyperstone_init(const device_config *device, cpu_irq_callback irqcal cpustate->clock_scale_mask = scale_mask; } -#if (HAS_E116T || HAS_E116XT || HAS_E116XS || HAS_E116XSR || HAS_GMS30C2116 || HAS_GMS30C2216) static void e116_init(const device_config *device, cpu_irq_callback irqcallback, int scale_mask) { hyperstone_state *cpustate = get_safe_token(device); hyperstone_init(device, irqcallback, scale_mask); cpustate->opcodexor = 0; } -#endif -#if (HAS_E116T) static CPU_INIT( e116t ) { e116_init(device, irqcallback, 0); } -#endif -#if (HAS_E116XT) static CPU_INIT( e116xt ) { e116_init(device, irqcallback, 3); } -#endif -#if (HAS_E116XS) static CPU_INIT( e116xs ) { e116_init(device, irqcallback, 7); } -#endif -#if (HAS_E116XSR) static CPU_INIT( e116xsr ) { e116_init(device, irqcallback, 7); } -#endif -#if (HAS_GMS30C2116) static CPU_INIT( gms30c2116 ) { e116_init(device, irqcallback, 0); } -#endif -#if (HAS_GMS30C2216) static CPU_INIT( gms30c2216 ) { e116_init(device, irqcallback, 0); } -#endif -#if (HAS_E132N || HAS_E132T || HAS_E132XN || HAS_E132XT || HAS_E132XS || HAS_E132XSR || HAS_GMS30C2132 || HAS_GMS30C2232) static void e132_init(const device_config *device, cpu_irq_callback irqcallback, int scale_mask) { hyperstone_state *cpustate = get_safe_token(device); hyperstone_init(device, irqcallback, scale_mask); cpustate->opcodexor = WORD_XOR_BE(0); } -#endif -#if (HAS_E132N) static CPU_INIT( e132n ) { e132_init(device, irqcallback, 0); } -#endif -#if (HAS_E132T) static CPU_INIT( e132t ) { e132_init(device, irqcallback, 0); } -#endif -#if (HAS_E132XN) static CPU_INIT( e132xn ) { e132_init(device, irqcallback, 3); } -#endif -#if (HAS_E132XT) static CPU_INIT( e132xt ) { e132_init(device, irqcallback, 3); } -#endif -#if (HAS_E132XS) static CPU_INIT( e132xs ) { e132_init(device, irqcallback, 7); } -#endif -#if (HAS_E132XSR) static CPU_INIT( e132xsr ) { e132_init(device, irqcallback, 7); } -#endif -#if (HAS_GMS30C2132) static CPU_INIT( gms30c2132 ) { e132_init(device, irqcallback, 0); } -#endif -#if (HAS_GMS30C2232) static CPU_INIT( gms30c2232 ) { e132_init(device, irqcallback, 0); } -#endif static CPU_RESET( hyperstone ) { @@ -5190,7 +5146,6 @@ static CPU_GET_INFO( hyperstone ) } -#if (HAS_E116T) CPU_GET_INFO( e116t ) { switch (state) @@ -5211,9 +5166,7 @@ CPU_GET_INFO( e116t ) CPU_GET_INFO_CALL(hyperstone); } } -#endif -#if (HAS_E116XT) CPU_GET_INFO( e116xt ) { switch (state) @@ -5234,9 +5187,7 @@ CPU_GET_INFO( e116xt ) CPU_GET_INFO_CALL(hyperstone); } } -#endif -#if (HAS_E116XS) CPU_GET_INFO( e116xs ) { switch (state) @@ -5257,9 +5208,7 @@ CPU_GET_INFO( e116xs ) CPU_GET_INFO_CALL(hyperstone); } } -#endif -#if (HAS_E116XSR) CPU_GET_INFO( e116xsr ) { switch (state) @@ -5280,9 +5229,7 @@ CPU_GET_INFO( e116xsr ) CPU_GET_INFO_CALL(hyperstone); } } -#endif -#if (HAS_E132N) CPU_GET_INFO( e132n ) { switch (state) @@ -5303,9 +5250,7 @@ CPU_GET_INFO( e132n ) CPU_GET_INFO_CALL(hyperstone); } } -#endif -#if (HAS_E132T) CPU_GET_INFO( e132t ) { switch (state) @@ -5326,9 +5271,7 @@ CPU_GET_INFO( e132t ) CPU_GET_INFO_CALL(hyperstone); } } -#endif -#if (HAS_E132XN) CPU_GET_INFO( e132xn ) { switch (state) @@ -5349,9 +5292,7 @@ CPU_GET_INFO( e132xn ) CPU_GET_INFO_CALL(hyperstone); } } -#endif -#if (HAS_E132XT) CPU_GET_INFO( e132xt ) { switch (state) @@ -5372,9 +5313,7 @@ CPU_GET_INFO( e132xt ) CPU_GET_INFO_CALL(hyperstone); } } -#endif -#if (HAS_E132XS) CPU_GET_INFO( e132xs ) { switch (state) @@ -5395,9 +5334,7 @@ CPU_GET_INFO( e132xs ) CPU_GET_INFO_CALL(hyperstone); } } -#endif -#if (HAS_E132XSR) CPU_GET_INFO( e132xsr ) { switch (state) @@ -5418,9 +5355,7 @@ CPU_GET_INFO( e132xsr ) CPU_GET_INFO_CALL(hyperstone); } } -#endif -#if (HAS_GMS30C2116) CPU_GET_INFO( gms30c2116 ) { switch (state) @@ -5441,9 +5376,7 @@ CPU_GET_INFO( gms30c2116 ) CPU_GET_INFO_CALL(hyperstone); } } -#endif -#if (HAS_GMS30C2132) CPU_GET_INFO( gms30c2132 ) { switch (state) @@ -5464,9 +5397,7 @@ CPU_GET_INFO( gms30c2132 ) CPU_GET_INFO_CALL(hyperstone); } } -#endif -#if (HAS_GMS30C2216) CPU_GET_INFO( gms30c2216 ) { switch (state) @@ -5487,9 +5418,7 @@ CPU_GET_INFO( gms30c2216 ) CPU_GET_INFO_CALL(hyperstone); } } -#endif -#if (HAS_GMS30C2232) CPU_GET_INFO( gms30c2232 ) { switch (state) @@ -5510,4 +5439,3 @@ CPU_GET_INFO( gms30c2232 ) CPU_GET_INFO_CALL(hyperstone); } } -#endif diff --git a/src/emu/cpu/e132xs/e132xs.h b/src/emu/cpu/e132xs/e132xs.h index 5ce4ade1f2c..300fbec2e2b 100644 --- a/src/emu/cpu/e132xs/e132xs.h +++ b/src/emu/cpu/e132xs/e132xs.h @@ -23,75 +23,47 @@ /* Functions */ -#if (HAS_E116T) CPU_GET_INFO( e116t ); #define CPU_E116T CPU_GET_INFO_NAME( e116t ) -#endif -#if (HAS_E116XT) CPU_GET_INFO( e116xt ); #define CPU_E116XT CPU_GET_INFO_NAME( e116xt ) -#endif -#if (HAS_E116XS) CPU_GET_INFO( e116xs ); #define CPU_E116XS CPU_GET_INFO_NAME( e116xs ) -#endif -#if (HAS_E116XSR) CPU_GET_INFO( e116xsr ); #define CPU_E116XSR CPU_GET_INFO_NAME( e116xsr ) -#endif -#if (HAS_E132N) CPU_GET_INFO( e132n ); #define CPU_E132N CPU_GET_INFO_NAME( e132n ) -#endif -#if (HAS_E132T) CPU_GET_INFO( e132t ); #define CPU_E132T CPU_GET_INFO_NAME( e132t ) -#endif -#if (HAS_E132XN) CPU_GET_INFO( e132xn ); #define CPU_E132XN CPU_GET_INFO_NAME( e132xn ) -#endif -#if (HAS_E132XT) CPU_GET_INFO( e132xt ); #define CPU_E132XT CPU_GET_INFO_NAME( e132xt ) -#endif -#if (HAS_E132XS) CPU_GET_INFO( e132xs ); #define CPU_E132XS CPU_GET_INFO_NAME( e132xs ) -#endif -#if (HAS_E132XSR) CPU_GET_INFO( e132xsr ); #define CPU_E132XSR CPU_GET_INFO_NAME( e132xsr ) -#endif -#if (HAS_GMS30C2116) CPU_GET_INFO( gms30c2116 ); #define CPU_GMS30C2116 CPU_GET_INFO_NAME( gms30c2116 ) -#endif -#if (HAS_GMS30C2132) CPU_GET_INFO( gms30c2132 ); #define CPU_GMS30C2132 CPU_GET_INFO_NAME( gms30c2132 ) -#endif -#if (HAS_GMS30C2216) CPU_GET_INFO( gms30c2216 ); #define CPU_GMS30C2216 CPU_GET_INFO_NAME( gms30c2216 ) -#endif -#if (HAS_GMS30C2232) CPU_GET_INFO( gms30c2232 ); #define CPU_GMS30C2232 CPU_GET_INFO_NAME( gms30c2232 ) -#endif extern unsigned dasm_hyperstone(char *buffer, unsigned pc, const UINT8 *oprom, unsigned h_flag, int private_fp); diff --git a/src/emu/cpu/i386/i386.c b/src/emu/cpu/i386/i386.c index df6229c129a..21a71773cd6 100644 --- a/src/emu/cpu/i386/i386.c +++ b/src/emu/cpu/i386/i386.c @@ -1062,7 +1062,6 @@ CPU_GET_INFO( i386 ) /*****************************************************************************/ /* Intel 486 */ -#if (HAS_I486) static CPU_INIT( i486 ) { @@ -1170,12 +1169,10 @@ CPU_GET_INFO( i486 ) default: CPU_GET_INFO_CALL(i386); break; } } -#endif /*****************************************************************************/ /* Pentium */ -#if (HAS_PENTIUM) static CPU_INIT( pentium ) { @@ -1303,12 +1300,10 @@ CPU_GET_INFO( pentium ) default: CPU_GET_INFO_CALL(i386); break; } } -#endif /*****************************************************************************/ /* Cyrix MediaGX */ -#if (HAS_MEDIAGX) static CPU_INIT( mediagx ) { @@ -1436,4 +1431,3 @@ CPU_GET_INFO( mediagx ) default: CPU_GET_INFO_CALL(i386); break; } } -#endif diff --git a/src/emu/cpu/i86/i86.c b/src/emu/cpu/i86/i86.c index 3b244bd8fc0..2ece38042bf 100644 --- a/src/emu/cpu/i86/i86.c +++ b/src/emu/cpu/i86/i86.c @@ -226,14 +226,12 @@ static CPU_INIT( i8086 ) configure_memory_16bit(cpustate); } -#if (HAS_I8088||HAS_I80188) static CPU_INIT( i8088 ) { i8086_state *cpustate = get_safe_token(device); CPU_INIT_CALL(i8086); configure_memory_8bit(cpustate); } -#endif static CPU_RESET( i8086 ) { @@ -334,7 +332,6 @@ static CPU_DISASSEMBLE( i8086 ) } -#if (HAS_I80186 || HAS_I80188) #include "i86.h" @@ -382,7 +379,6 @@ static CPU_EXECUTE( i80186 ) return cycles - cpustate->icount; } -#endif @@ -593,7 +589,6 @@ CPU_GET_INFO( i8086 ) } -#if (HAS_I8088) /************************************************************************** * CPU-specific get_info/set_info **************************************************************************/ @@ -615,10 +610,8 @@ CPU_GET_INFO( i8088 ) default: CPU_GET_INFO_CALL(i8086); break; } } -#endif -#if (HAS_I80186) /************************************************************************** * CPU-specific get_info/set_info **************************************************************************/ @@ -640,10 +633,8 @@ CPU_GET_INFO( i80186 ) default: CPU_GET_INFO_CALL(i8086); break; } } -#endif -#if (HAS_I80188) /************************************************************************** * CPU-specific get_info/set_info **************************************************************************/ @@ -666,4 +657,3 @@ CPU_GET_INFO( i80188 ) default: CPU_GET_INFO_CALL(i8086); break; } } -#endif diff --git a/src/emu/cpu/i86/i86mem.c b/src/emu/cpu/i86/i86mem.c index 572203b0036..c1954c9cdda 100644 --- a/src/emu/cpu/i86/i86mem.c +++ b/src/emu/cpu/i86/i86mem.c @@ -3,7 +3,6 @@ *****************************************************************************/ #ifdef I8086 -#if (HAS_I8088||HAS_I80188) static void configure_memory_8bit(i8086_state *cpustate) { cpustate->mem.fetch_xor = 0; @@ -14,7 +13,6 @@ static void configure_memory_8bit(i8086_state *cpustate) cpustate->mem.wword = memory_write_word_8le; } #endif -#endif /***************************************************************************** diff --git a/src/emu/cpu/m6502/6502dasm.c b/src/emu/cpu/m6502/6502dasm.c index 8c3c5692983..4e63c11472e 100644 --- a/src/emu/cpu/m6502/6502dasm.c +++ b/src/emu/cpu/m6502/6502dasm.c @@ -29,15 +29,9 @@ #include "debugger.h" #include "m6502.h" -#if (HAS_M65CE02) #include "m65ce02.h" -#endif -#if (HAS_M6509) #include "m6509.h" -#endif -#if (HAS_M4510) #include "m4510.h" -#endif enum addr_mode { non, /* no additional arguments */ @@ -341,7 +335,6 @@ static const struct op6502_info op65sc02[256] = { {ill,non},{sbc,abx},{inc,abx},{bbs,zpb} }; -#if (HAS_M65CE02) static const struct op6502_info op65ce02[256] = { {m6502_brk,imm},{ora,idx},{cle,imp},{see,imp},/* 00 */ {tsb,zpg},{ora,zpg},{asl,zpg},{rmb,zpg}, @@ -408,9 +401,7 @@ static const struct op6502_info op65ce02[256] = { {sed,imp},{sbc,aby},{plx,imp},{plz,imp}, {phw,aba},{sbc,abx},{inc,abx},{bbs,zpb} }; -#endif -#if (HAS_M4510) // only map instead of aug and 20 bit memory management static const struct op6502_info op4510[256] = { {m6502_brk,imm},{ora,idx},{cle,imp},{see,imp},/* 00 */ @@ -478,9 +469,7 @@ static const struct op6502_info op4510[256] = { {sed,imp},{sbc,aby},{plx,imp},{plz,imp}, {phw,aba},{sbc,abx},{inc,abx},{bbs,zpb} }; -#endif -#if (HAS_DECO16) static const struct op6502_info opdeco16[256] = { {m6502_brk,imp},{ora,idx},{ill,non},{ill,non},/* 00 */ @@ -548,7 +537,6 @@ static const struct op6502_info opdeco16[256] = {sed,imp},{sbc,aby},{ill,non},{ill,non}, {ill,non},{sbc,abx},{inc,abx},{ill,non} }; -#endif /***************************************************************************** * Disassemble a single opcode starting at pc @@ -747,44 +735,32 @@ CPU_DISASSEMBLE( m6502 ) return internal_m6502_dasm(op6502, buffer, pc, oprom, opram); } -#if (HAS_M65SC02) CPU_DISASSEMBLE( m65sc02 ) { return internal_m6502_dasm(op65sc02, buffer, pc, oprom, opram); } -#endif -#if (HAS_M65C02||HAS_M65SC02||HAS_DECO16) CPU_DISASSEMBLE( m65c02 ) { return internal_m6502_dasm(op65c02, buffer, pc, oprom, opram); } -#endif -#if (HAS_M65CE02) CPU_DISASSEMBLE( m65ce02 ) { return internal_m6502_dasm(op65ce02, buffer, pc, oprom, opram); } -#endif -#if (HAS_M6510) CPU_DISASSEMBLE( m6510 ) { return internal_m6502_dasm(op6502, buffer, pc, oprom, opram); } -#endif -#if (HAS_DECO16) CPU_DISASSEMBLE( deco16 ) { return internal_m6502_dasm(opdeco16, buffer, pc, oprom, opram); } -#endif -#if (HAS_M4510) CPU_DISASSEMBLE( m4510 ) { return internal_m6502_dasm(op4510, buffer, pc, oprom, opram); } -#endif diff --git a/src/emu/cpu/m6502/m6502.c b/src/emu/cpu/m6502/m6502.c index b5b6a7c4188..4907c8980fa 100644 --- a/src/emu/cpu/m6502/m6502.c +++ b/src/emu/cpu/m6502/m6502.c @@ -24,11 +24,6 @@ /* 10.March 2000 PeT added 6502 set overflow input line */ /* 13.September 2000 PeT N2A03 jmp indirect */ -#if ((HAS_M65SC02 || HAS_DECO16) && !HAS_M65C02) -#undef HAS_M65C02 -#define HAS_M65C02 1 -#endif - #include "debugger.h" #include "m6502.h" #include "ops02.h" @@ -82,13 +77,10 @@ struct _m6502_Regs m6502_read_indexed_func rdmem_id; /* readmem callback for indexed instructions */ m6502_write_indexed_func wrmem_id; /* writemem callback for indexed instructions */ -#if (HAS_M6510) || (HAS_M6510T) || (HAS_M8502) || (HAS_M7501) UINT8 ddr; UINT8 port; m6510_port_read_func port_read; m6510_port_write_func port_write; -#endif - }; INLINE m6502_Regs *get_safe_token(const device_config *device) @@ -116,29 +108,19 @@ static void default_wdmem_id(const address_space *space, offs_t offset, UINT8 da ***************************************************************/ #include "t6502.c" -#if (HAS_M6510) #include "t6510.c" -#endif #include "opsn2a03.h" -#if (HAS_N2A03) #include "tn2a03.c" -#endif #include "opsc02.h" -#if (HAS_M65C02) #include "t65c02.c" -#endif -#if (HAS_M65SC02) #include "t65sc02.c" -#endif -#if (HAS_DECO16) #include "tdeco16.c" -#endif /***************************************************************************** * @@ -170,13 +152,11 @@ static void m6502_common_init(const device_config *device, cpu_irq_callback irqc state_save_register_device_item(device, 0, cpustate->irq_state); state_save_register_device_item(device, 0, cpustate->so_state); -#if (HAS_M6510) || (HAS_M6510T) || (HAS_M8502) || (HAS_M7501) if (subtype == SUBTYPE_6510) { state_save_register_device_item(device, 0, cpustate->port); state_save_register_device_item(device, 0, cpustate->ddr); } -#endif } static CPU_INIT( m6502 ) @@ -325,7 +305,6 @@ static void m6502_set_irq_line(m6502_Regs *cpustate, int irqline, int state) /**************************************************************************** * 2A03 section ****************************************************************************/ -#if (HAS_N2A03) static CPU_INIT( n2a03 ) { @@ -342,13 +321,11 @@ void n2a03_irq(const device_config *device) m6502_take_irq(cpustate); } -#endif /**************************************************************************** * 6510 section ****************************************************************************/ -#if (HAS_M6510) static CPU_INIT( m6510 ) { @@ -410,13 +387,11 @@ static ADDRESS_MAP_START(m6510_mem, ADDRESS_SPACE_PROGRAM, 8) AM_RANGE(0x0000, 0x0001) AM_READWRITE(m6510_read_0000, m6510_write_0000) ADDRESS_MAP_END -#endif /**************************************************************************** * 65C02 section ****************************************************************************/ -#if (HAS_M65C02) static CPU_INIT( m65c02 ) { @@ -518,22 +493,18 @@ static void m65c02_set_irq_line(m6502_Regs *cpustate, int irqline, int state) else m6502_set_irq_line(cpustate, irqline,state); } -#endif /**************************************************************************** * 65SC02 section ****************************************************************************/ -#if (HAS_M65SC02) static CPU_INIT( m65sc02 ) { m6502_common_init(device, irqcallback, SUBTYPE_65SC02, insn65sc02, "m65sc02"); } -#endif /**************************************************************************** * DECO16 section ****************************************************************************/ -#if (HAS_DECO16) static CPU_INIT( deco16 ) { @@ -665,7 +636,6 @@ static CPU_EXECUTE( deco16 ) return cycles - cpustate->icount; } -#endif @@ -796,7 +766,6 @@ CPU_GET_INFO( m6502 ) } -#if (HAS_N2A03) /************************************************************************** * CPU-specific set_info **************************************************************************/ @@ -814,10 +783,8 @@ CPU_GET_INFO( n2a03 ) default: CPU_GET_INFO_CALL(m6502); break; } } -#endif -#if (HAS_M6510) || (HAS_M6510T) || (HAS_M8502) || (HAS_M7501) /************************************************************************** * CPU-specific set_info **************************************************************************/ @@ -860,10 +827,8 @@ CPU_GET_INFO( m6510 ) default: CPU_GET_INFO_CALL(m6502); break; } } -#endif -#if (HAS_M6510T) /************************************************************************** * CPU-specific set_info **************************************************************************/ @@ -878,10 +843,8 @@ CPU_GET_INFO( m6510t ) default: CPU_GET_INFO_CALL(m6510); break; } } -#endif -#if (HAS_M7501) /************************************************************************** * CPU-specific set_info **************************************************************************/ @@ -896,10 +859,8 @@ CPU_GET_INFO( m7501 ) default: CPU_GET_INFO_CALL(m6510); break; } } -#endif -#if (HAS_M8502) /************************************************************************** * CPU-specific set_info **************************************************************************/ @@ -914,10 +875,8 @@ CPU_GET_INFO( m8502 ) default: CPU_GET_INFO_CALL(m6510); break; } } -#endif -#if (HAS_M65C02) /************************************************************************** * CPU-specific set_info **************************************************************************/ @@ -952,10 +911,8 @@ CPU_GET_INFO( m65c02 ) default: CPU_GET_INFO_CALL(m6502); break; } } -#endif -#if (HAS_M65SC02) /************************************************************************** * CPU-specific set_info **************************************************************************/ @@ -978,10 +935,8 @@ CPU_GET_INFO( m65sc02 ) default: CPU_GET_INFO_CALL(m65c02); break; } } -#endif -#if (HAS_DECO16) /************************************************************************** * CPU-specific set_info **************************************************************************/ @@ -1026,4 +981,3 @@ CPU_GET_INFO( deco16 ) default: CPU_GET_INFO_CALL(m6502); break; } } -#endif diff --git a/src/emu/cpu/m6502/m6502.h b/src/emu/cpu/m6502/m6502.h index b6785e86650..ff51211725b 100644 --- a/src/emu/cpu/m6502/m6502.h +++ b/src/emu/cpu/m6502/m6502.h @@ -33,21 +33,11 @@ #define FAST_MEMORY 0 #define SUBTYPE_6502 0 -#if (HAS_M65C02) #define SUBTYPE_65C02 1 -#endif -#if (HAS_M6510) #define SUBTYPE_6510 2 -#endif -#if (HAS_N2A03) #define SUBTYPE_2A03 3 -#endif -#if (HAS_M65SC02) #define SUBTYPE_65SC02 4 -#endif -#if (HAS_DECO16) #define SUBTYPE_DECO16 5 -#endif enum { @@ -86,7 +76,6 @@ extern CPU_DISASSEMBLE( m6502 ); /**************************************************************************** * The 6510 ****************************************************************************/ -#if (HAS_M6510) #define M6510_A M6502_A #define M6510_X M6502_X #define M6510_Y M6502_Y @@ -105,9 +94,7 @@ extern CPU_GET_INFO( m6510 ); extern CPU_DISASSEMBLE( m6510 ); -#endif -#if (HAS_M6510T) #define M6510T_A M6502_A #define M6510T_X M6502_X #define M6510T_Y M6502_Y @@ -124,9 +111,7 @@ extern CPU_DISASSEMBLE( m6510 ); extern CPU_GET_INFO( m6510t ); #define CPU_M6510T CPU_GET_INFO_NAME( m6510t ) -#endif -#if (HAS_M7501) #define M7501_A M6502_A #define M7501_X M6502_X #define M7501_Y M6502_Y @@ -142,9 +127,7 @@ extern CPU_GET_INFO( m6510t ); extern CPU_GET_INFO( m7501 ); #define CPU_M7501 CPU_GET_INFO_NAME( m7501 ) -#endif -#if (HAS_M8502) #define M8502_A M6502_A #define M8502_X M6502_X #define M8502_Y M6502_Y @@ -160,13 +143,11 @@ extern CPU_GET_INFO( m7501 ); extern CPU_GET_INFO( m8502 ); #define CPU_M8502 CPU_GET_INFO_NAME( m8502 ) -#endif /**************************************************************************** * The 2A03 (NES 6502 without decimal mode ADC/SBC) ****************************************************************************/ -#if (HAS_N2A03) #define N2A03_A M6502_A #define N2A03_X M6502_X #define N2A03_Y M6502_Y @@ -190,13 +171,11 @@ extern CPU_GET_INFO( n2a03 ); causes an IRQ to be generated. This function allows the IRQ to be called from the PSG core when such an occasion arises. */ extern void n2a03_irq(const device_config *device); -#endif /**************************************************************************** * The 65C02 ****************************************************************************/ -#if (HAS_M65C02) #define M65C02_A M6502_A #define M65C02_X M6502_X #define M65C02_Y M6502_Y @@ -215,12 +194,10 @@ extern CPU_GET_INFO( m65c02 ); extern CPU_DISASSEMBLE( m65c02 ); -#endif /**************************************************************************** * The 65SC02 ****************************************************************************/ -#if (HAS_M65SC02) #define M65SC02_A M6502_A #define M65SC02_X M6502_X #define M65SC02_Y M6502_Y @@ -238,12 +215,10 @@ extern CPU_GET_INFO( m65sc02 ); #define CPU_M65SC02 CPU_GET_INFO_NAME( m65sc02 ) extern CPU_DISASSEMBLE( m65sc02 ); -#endif /**************************************************************************** * The DECO CPU16 ****************************************************************************/ -#if (HAS_DECO16) #define DECO16_A M6502_A #define DECO16_X M6502_X #define DECO16_Y M6502_Y @@ -259,7 +234,6 @@ extern CPU_DISASSEMBLE( m65sc02 ); extern CPU_GET_INFO( deco16 ); #define CPU_DECO16 CPU_GET_INFO_NAME( deco16 ) -#endif extern CPU_DISASSEMBLE( deco16 ); diff --git a/src/emu/cpu/m6800/6800ops.c b/src/emu/cpu/m6800/6800ops.c index e16ff0af52a..757906f9853 100644 --- a/src/emu/cpu/m6800/6800ops.c +++ b/src/emu/cpu/m6800/6800ops.c @@ -22,14 +22,12 @@ OP_HANDLER( illegal ) } /* HD63701 only */ -#if (HAS_HD63701) //OP_HANDLER( trap ) OP_HANDLER( trap ) { logerror("m6800: illegal opcode: address %04X, op %02X\n",PC,(int) M_RDOP_ARG(PC)&0xFF); TAKE_TRAP; } -#endif /* $00 ILLEGAL */ @@ -201,7 +199,6 @@ OP_HANDLER( daa ) /* $1a ILLEGAL */ -#if (HAS_HD63701) /* $1a SLP */ /* HD63701YO only */ OP_HANDLER( slp ) { @@ -209,7 +206,6 @@ OP_HANDLER( slp ) cpustate->wai_state |= M6800_SLP; EAT_CYCLES; } -#endif /* $1b ABA inherent ***** */ OP_HANDLER( aba ) diff --git a/src/emu/cpu/m6800/6800tbl.c b/src/emu/cpu/m6800/6800tbl.c index c0b9d4dc82e..7cb6bbf74b4 100644 --- a/src/emu/cpu/m6800/6800tbl.c +++ b/src/emu/cpu/m6800/6800tbl.c @@ -188,9 +188,7 @@ INLINE void sbcb_ix(m6800_state *cpustate); INLINE void sec(m6800_state *cpustate); INLINE void sei(m6800_state *cpustate); INLINE void sev(m6800_state *cpustate); -#if (HAS_HD63701) INLINE void slp(m6800_state *cpustate); -#endif INLINE void sta_di(m6800_state *cpustate); INLINE void sta_ex(m6800_state *cpustate); INLINE void sta_im(m6800_state *cpustate); @@ -245,9 +243,7 @@ INLINE void cpx_di(m6800_state *cpustate); INLINE void cpx_ex(m6800_state *cpustate); INLINE void cpx_im(m6800_state *cpustate); INLINE void cpx_ix(m6800_state *cpustate); -#if (HAS_HD63701) INLINE void trap(m6800_state *cpustate); -#endif static void (*const m6800_insn[0x100])(m6800_state *cpustate) = { illegal,nop, illegal,illegal,illegal,illegal,tap, tpa, @@ -284,7 +280,6 @@ subb_ex,cmpb_ex,sbcb_ex,illegal,andb_ex,bitb_ex,ldb_ex, stb_ex, eorb_ex,adcb_ex,orb_ex, addb_ex,illegal,illegal,ldx_ex, stx_ex }; -#if (HAS_M6801||HAS_M6803) static void (*const m6803_insn[0x100])(m6800_state *cpustate) = { illegal,nop, illegal,illegal,lsrd, asld, tap, tpa, inx, dex, clv, sev, clc, sec, cli, sei, @@ -319,9 +314,7 @@ eorb_ix,adcb_ix,orb_ix, addb_ix,ldd_ix, std_ix, ldx_ix, stx_ix, subb_ex,cmpb_ex,sbcb_ex,addd_ex,andb_ex,bitb_ex,ldb_ex, stb_ex, eorb_ex,adcb_ex,orb_ex, addb_ex,ldd_ex, std_ex, ldx_ex, stx_ex }; -#endif -#if (HAS_HD63701) static void (*const hd63701_insn[0x100])(m6800_state *cpustate) = { trap ,nop, trap ,trap ,lsrd, asld, tap, tpa, inx, dex, clv, sev, clc, sec, cli, sei, @@ -356,9 +349,7 @@ eorb_ix,adcb_ix,orb_ix, addb_ix,ldd_ix, std_ix, ldx_ix, stx_ix, subb_ex,cmpb_ex,sbcb_ex,addd_ex,andb_ex,bitb_ex,ldb_ex, stb_ex, eorb_ex,adcb_ex,orb_ex, addb_ex,ldd_ex, std_ex, ldx_ex, stx_ex }; -#endif -#if (HAS_NSC8105) static void (*const nsc8105_insn[0x100])(m6800_state *cpustate) = { illegal,illegal,nop, illegal,illegal,tap, illegal,tpa, inx, clv, dex, sev, clc, cli, sec, sei, @@ -393,4 +384,3 @@ eorb_ix,orb_ix, adcb_ix,addb_ix,adcx_im,ldx_ix, illegal,stx_ix, subb_ex,sbcb_ex,cmpb_ex,illegal,andb_ex,ldb_ex, bitb_ex,stb_ex, eorb_ex,orb_ex, adcb_ex,addb_ex,addx_ex,ldx_ex, illegal,stx_ex }; -#endif diff --git a/src/emu/cpu/m6800/m6800.c b/src/emu/cpu/m6800/m6800.c index 8126ab1a89a..7aad08794e7 100644 --- a/src/emu/cpu/m6800/m6800.c +++ b/src/emu/cpu/m6800/m6800.c @@ -657,7 +657,6 @@ INLINE void increment_counter(m6800_state *cpustate, int amount) /* include the opcode functions */ #include "6800ops.c" -#if (HAS_M6801||HAS_M6803||HAS_HD63701) static void m6800_tx(m6800_state *cpustate, int value) { cpustate->port2_data = (cpustate->port2_data & 0xef) | (value << 4); @@ -844,7 +843,6 @@ static TIMER_CALLBACK(m6800_rx_tick) } } } -#endif /**************************************************************************** * Reset registers to their initial values @@ -1286,7 +1284,6 @@ static CPU_EXECUTE( m6800 ) /**************************************************************************** * M6801 almost (fully?) equal to the M6803 ****************************************************************************/ -#if (HAS_M6801) static CPU_INIT( m6801 ) { m6800_state *cpustate = get_safe_token(device); @@ -1306,12 +1303,10 @@ static CPU_INIT( m6801 ) state_register(cpustate, "m6801"); } -#endif /**************************************************************************** * M6802 almost (fully?) equal to the M6800 ****************************************************************************/ -#if (HAS_M6802) static CPU_INIT( m6802 ) { m6800_state *cpustate = get_safe_token(device); @@ -1327,12 +1322,10 @@ static CPU_INIT( m6802 ) state_register(cpustate, "m6802"); } -#endif /**************************************************************************** * M6803 almost (fully?) equal to the M6801 ****************************************************************************/ -#if (HAS_M6803) static CPU_INIT( m6803 ) { m6800_state *cpustate = get_safe_token(device); @@ -1352,7 +1345,6 @@ static CPU_INIT( m6803 ) state_register(cpustate, "m6803"); } -#endif /**************************************************************************** * Execute one instruction @@ -1624,7 +1616,6 @@ INLINE void m6803_execute_one(m6800_state *cpustate, UINT8 ireg) /**************************************************************************** * Execute cycles CPU cycles. Return number of cycles really executed ****************************************************************************/ -#if (HAS_M6803||HAS_M6801) static CPU_EXECUTE( m6803 ) { m6800_state *cpustate = get_safe_token(device); @@ -1654,9 +1645,7 @@ static CPU_EXECUTE( m6803 ) return cycles - cpustate->icount; } -#endif -#if (HAS_M6803) static READ8_HANDLER( m6803_internal_registers_r ); static WRITE8_HANDLER( m6803_internal_registers_w ); @@ -1667,12 +1656,10 @@ static ADDRESS_MAP_START(m6803_mem, ADDRESS_SPACE_PROGRAM, 8) AM_RANGE(0x0080, 0x00ff) AM_RAM /* 6803 internal RAM */ ADDRESS_MAP_END -#endif /**************************************************************************** * M6808 almost (fully?) equal to the M6800 ****************************************************************************/ -#if (HAS_M6808) static CPU_INIT( m6808 ) { m6800_state *cpustate = get_safe_token(device); @@ -1688,12 +1675,10 @@ static CPU_INIT( m6808 ) state_register(cpustate, "m6808"); } -#endif /**************************************************************************** * HD63701 similiar to the M6800 ****************************************************************************/ -#if (HAS_HD63701) static CPU_INIT( hd63701 ) { @@ -2041,13 +2026,11 @@ WRITE8_HANDLER( hd63701_internal_registers_w ) { m6803_internal_registers_w(space, offset,data); } -#endif /**************************************************************************** * NSC-8105 similiar to the M6800, but the opcodes are scrambled and there * is at least one new opcode ($fc) ****************************************************************************/ -#if (HAS_NSC8105) static CPU_INIT( nsc8105 ) { m6800_state *cpustate = get_safe_token(device); @@ -2362,10 +2345,8 @@ static CPU_EXECUTE( nsc8105 ) return cycles - cpustate->icount; } -#endif -#if (HAS_M6803||HAS_HD63701) static READ8_HANDLER( m6803_internal_registers_r ) { @@ -2654,7 +2635,6 @@ static WRITE8_HANDLER( m6803_internal_registers_w ) break; } } -#endif /************************************************************************** @@ -2772,7 +2752,6 @@ CPU_GET_INFO( m6800 ) } -#if (HAS_M6801) /************************************************************************** * CPU-specific set_info **************************************************************************/ @@ -2797,10 +2776,8 @@ CPU_GET_INFO( m6801 ) default: CPU_GET_INFO_CALL(m6800); break; } } -#endif -#if (HAS_M6802) /************************************************************************** * CPU-specific set_info **************************************************************************/ @@ -2822,10 +2799,8 @@ CPU_GET_INFO( m6802 ) default: CPU_GET_INFO_CALL(m6800); break; } } -#endif -#if (HAS_M6803) /************************************************************************** * CPU-specific set_info **************************************************************************/ @@ -2852,10 +2827,8 @@ CPU_GET_INFO( m6803 ) default: CPU_GET_INFO_CALL(m6800); break; } } -#endif -#if (HAS_M6808) /************************************************************************** * CPU-specific set_info **************************************************************************/ @@ -2877,10 +2850,8 @@ CPU_GET_INFO( m6808 ) default: CPU_GET_INFO_CALL(m6800); break; } } -#endif -#if (HAS_HD63701) /************************************************************************** * CPU-specific set_info **************************************************************************/ @@ -2905,10 +2876,8 @@ CPU_GET_INFO( hd63701 ) default: CPU_GET_INFO_CALL(m6800); break; } } -#endif -#if (HAS_NSC8105) /************************************************************************** * CPU-specific set_info **************************************************************************/ @@ -2931,4 +2900,3 @@ CPU_GET_INFO( nsc8105 ) default: CPU_GET_INFO_CALL(m6800); break; } } -#endif diff --git a/src/emu/cpu/m6800/m6800.h b/src/emu/cpu/m6800/m6800.h index c155f48e740..96d6a4e9cbf 100644 --- a/src/emu/cpu/m6800/m6800.h +++ b/src/emu/cpu/m6800/m6800.h @@ -23,7 +23,6 @@ enum /* it is usuali to use PULSE_LINE state */ }; -#if (HAS_M6801||HAS_M6803||HAS_HD63701) /* By default, on a port write port bits which are not set as output in the DDR */ /* are set to the value returned by a read from the same port. If you need to */ /* know the DDR for e.g. port 1, do m6803_internal_registers_r(M6801_DDR1) */ @@ -43,32 +42,22 @@ enum M6803_PORT3, M6803_PORT4 }; -#endif CPU_GET_INFO( m6800 ); #define CPU_M6800 CPU_GET_INFO_NAME( m6800 ) -#if (HAS_M6801) CPU_GET_INFO( m6801 ); #define CPU_M6801 CPU_GET_INFO_NAME( m6801 ) -#endif -#if (HAS_M6802) CPU_GET_INFO( m6802 ); #define CPU_M6802 CPU_GET_INFO_NAME( m6802 ) -#endif -#if (HAS_M6803) CPU_GET_INFO( m6803 ); #define CPU_M6803 CPU_GET_INFO_NAME( m6803 ) -#endif -#if (HAS_M6808) CPU_GET_INFO( m6808 ); #define CPU_M6808 CPU_GET_INFO_NAME( m6808 ) -#endif -#if (HAS_HD63701) CPU_GET_INFO( hd63701 ); #define CPU_HD63701 CPU_GET_INFO_NAME( hd63701 ) @@ -86,12 +75,9 @@ CPU_GET_INFO( hd63701 ); READ8_HANDLER( hd63701_internal_registers_r ); WRITE8_HANDLER( hd63701_internal_registers_w ); -#endif -#if (HAS_NSC8105) CPU_GET_INFO( nsc8105 ); #define CPU_NSC8105 CPU_GET_INFO_NAME( nsc8105 ) -#endif CPU_DISASSEMBLE( m6800 ); @@ -108,7 +94,6 @@ CPU_DISASSEMBLE( nsc8105 ); /**************************************************************************** * For now make the 6801 using the m6800 variables and functions ****************************************************************************/ -#if (HAS_M6801) #define M6801_A M6800_A #define M6801_B M6800_B #define M6801_PC M6800_PC @@ -123,12 +108,10 @@ CPU_DISASSEMBLE( nsc8105 ); #define M6801_IRQ_LINE M6800_IRQ_LINE extern CPU_GET_INFO( m6801 ); -#endif /**************************************************************************** * For now make the 6802 using the m6800 variables and functions ****************************************************************************/ -#if (HAS_M6802) #define M6802_A M6800_A #define M6802_B M6800_B #define M6802_PC M6800_PC @@ -143,12 +126,10 @@ extern CPU_GET_INFO( m6801 ); #define M6802_IRQ_LINE M6800_IRQ_LINE extern CPU_GET_INFO( m6802 ); -#endif /**************************************************************************** * For now make the 6803 using the m6800 variables and functions ****************************************************************************/ -#if (HAS_M6803) #define M6803_A M6800_A #define M6803_B M6800_B #define M6803_PC M6800_PC @@ -164,9 +145,7 @@ extern CPU_GET_INFO( m6802 ); #define M6803_TIN_LINE M6800_TIN_LINE extern CPU_GET_INFO( m6803 ); -#endif -#if (HAS_M6801||HAS_M6803||HAS_HD63701) /* By default, on a port write port bits which are not set as output in the DDR */ /* are set to the value returned by a read from the same port. If you need to */ /* know the DDR for e.g. port 1, do m6803_internal_registers_r(M6801_DDR1) */ @@ -180,12 +159,10 @@ extern CPU_GET_INFO( m6803 ); #define M6803_PORT2 0x101 #define M6803_PORT3 0x102 #define M6803_PORT4 0x103 -#endif /**************************************************************************** * For now make the 6808 using the m6800 variables and functions ****************************************************************************/ -#if (HAS_M6808) #define M6808_A M6800_A #define M6808_B M6800_B #define M6808_PC M6800_PC @@ -200,12 +177,10 @@ extern CPU_GET_INFO( m6803 ); #define M6808_IRQ_LINE M6800_IRQ_LINE extern CPU_GET_INFO( m6808 ); -#endif /**************************************************************************** * For now make the HD63701 using the m6800 variables and functions ****************************************************************************/ -#if (HAS_HD63701) #define HD63701_A M6800_A #define HD63701_B M6800_B #define HD63701_PC M6800_PC @@ -236,12 +211,10 @@ extern CPU_GET_INFO( hd63701 ); READ8_HANDLER( hd63701_internal_registers_r ); WRITE8_HANDLER( hd63701_internal_registers_w ); -#endif /**************************************************************************** * For now make the NSC8105 using the m6800 variables and functions ****************************************************************************/ -#if (HAS_NSC8105) #define NSC8105_A M6800_A #define NSC8105_B M6800_B #define NSC8105_PC M6800_PC @@ -257,7 +230,6 @@ WRITE8_HANDLER( hd63701_internal_registers_w ); #define NSC8105_TIN_LINE M6800_TIN_LINE extern CPU_GET_INFO( nsc8105 ); -#endif #endif #endif /* __M6800_H__ */ diff --git a/src/emu/cpu/m6805/m6805.c b/src/emu/cpu/m6805/m6805.c index 018db023ce4..2da5823b295 100644 --- a/src/emu/cpu/m6805/m6805.c +++ b/src/emu/cpu/m6805/m6805.c @@ -310,7 +310,6 @@ INLINE void WM16( m6805_Regs *cpustate, UINT32 Addr, PAIR *p ) } #endif -#if (HAS_M68705) /* Generate interrupt - m68705 version */ static void m68705_Interrupt( m6805_Regs *cpustate ) @@ -341,7 +340,6 @@ static void m68705_Interrupt( m6805_Regs *cpustate ) cpustate->iCount -= 11; } } -#endif /* Generate interrupts */ static void Interrupt( m6805_Regs *cpustate ) @@ -350,7 +348,6 @@ static void Interrupt( m6805_Regs *cpustate ) /* pending_interrupts until the interrupt is taken, no matter what the */ /* external IRQ pin does. */ -#if (HAS_HD63705) if( (cpustate->pending_interrupts & (1<pc); @@ -370,10 +367,6 @@ static void Interrupt( m6805_Regs *cpustate ) } else if( (cpustate->pending_interrupts & ((1<pending_interrupts & (1<irq_callback)(cpustate->device, 0); -#if (HAS_HD63705) if(SUBTYPE==SUBTYPE_HD63705) { /* Need to add emulation of other interrupt sources here KW-2/4/99 */ @@ -438,7 +430,6 @@ static void Interrupt( m6805_Regs *cpustate ) } } else -#endif { RM16( cpustate, 0xffff - 5, &pPC ); } @@ -529,13 +520,11 @@ static CPU_EXECUTE( m6805 ) { if (cpustate->pending_interrupts != 0) { -#if (HAS_M68705) if (SUBTYPE==SUBTYPE_M68705) { m68705_Interrupt(cpustate); } else -#endif { Interrupt(cpustate); } @@ -817,7 +806,6 @@ static CPU_EXECUTE( m6805 ) /**************************************************************************** * M68705 section ****************************************************************************/ -#if (HAS_M68705) static CPU_INIT( m68705 ) { m6805_Regs *cpustate = get_safe_token(device); @@ -843,12 +831,10 @@ static void m68705_set_irq_line(m6805_Regs *cpustate, int irqline, int state) if (state != CLEAR_LINE) cpustate->pending_interrupts |= 1<pending_interrupts |= 1<mem.fetch_xor = 0; @@ -1149,14 +1148,12 @@ static void configure_memory_8bit(nec_state_t *nec_state) nec_state->mem.wbyte = memory_write_byte_8le; nec_state->mem.wword = memory_write_word_8le; } -#endif /***************************************************************************** 16-bit memory accessors *****************************************************************************/ -#if (HAS_V30||HAS_V33||HAS_V35) static UINT16 read_word_16le(const address_space *space, offs_t addr) { if (!(addr & 1)) @@ -1188,7 +1185,6 @@ static void configure_memory_16bit(nec_state_t *nec_state) nec_state->mem.wbyte = memory_write_byte_16le; nec_state->mem.wword = write_word_16le; } -#endif static CPU_EXECUTE( necv ) { @@ -1220,7 +1216,6 @@ static CPU_EXECUTE( necv ) } /* Wrappers for the different CPU types */ -#if (HAS_V20||HAS_V25) static CPU_INIT( v20 ) { nec_state_t *nec_state = get_safe_token(device); @@ -1231,9 +1226,7 @@ static CPU_INIT( v20 ) nec_state->prefetch_size = 4; /* 3 words */ nec_state->prefetch_cycles = 4; /* four cycles per byte */ } -#endif -#if (HAS_V30||HAS_V35) static CPU_INIT( v30 ) { nec_state_t *nec_state = get_safe_token(device); @@ -1245,9 +1238,7 @@ static CPU_INIT( v30 ) nec_state->prefetch_cycles = 2; /* two cycles per byte / four per word */ } -#endif -#if (HAS_V33) static CPU_INIT( v33 ) { nec_state_t *nec_state = get_safe_token(device); @@ -1262,7 +1253,6 @@ static CPU_INIT( v33 ) configure_memory_16bit(nec_state); } -#endif @@ -1441,7 +1431,6 @@ static CPU_GET_INFO( nec ) } -#if (HAS_V20) /************************************************************************** * CPU-specific set_info **************************************************************************/ @@ -1463,10 +1452,8 @@ CPU_GET_INFO( v20 ) default: CPU_GET_INFO_CALL(nec); break; } } -#endif -#if (HAS_V25) /************************************************************************** * CPU-specific set_info **************************************************************************/ @@ -1488,10 +1475,8 @@ CPU_GET_INFO( v25 ) default: CPU_GET_INFO_CALL(nec); break; } } -#endif -#if (HAS_V30) /************************************************************************** * CPU-specific set_info **************************************************************************/ @@ -1509,10 +1494,8 @@ CPU_GET_INFO( v30 ) default: CPU_GET_INFO_CALL(nec); break; } } -#endif -#if (HAS_V33) /************************************************************************** * CPU-specific set_info **************************************************************************/ @@ -1530,10 +1513,8 @@ CPU_GET_INFO( v33 ) default: CPU_GET_INFO_CALL(nec); break; } } -#endif -#if (HAS_V35) /************************************************************************** * CPU-specific set_info **************************************************************************/ @@ -1551,4 +1532,3 @@ CPU_GET_INFO( v35 ) default: CPU_GET_INFO_CALL(nec); break; } } -#endif diff --git a/src/emu/cpu/pic16c5x/pic16c5x.c b/src/emu/cpu/pic16c5x/pic16c5x.c index 94f1e156ced..66025023af4 100644 --- a/src/emu/cpu/pic16c5x/pic16c5x.c +++ b/src/emu/cpu/pic16c5x/pic16c5x.c @@ -1110,7 +1110,6 @@ static CPU_GET_INFO( pic16c5x ) -#if (HAS_PIC16C54) /**************************************************************************** * Internal Memory Map ****************************************************************************/ @@ -1161,10 +1160,8 @@ CPU_GET_INFO( pic16c54 ) default: CPU_GET_INFO_CALL(pic16c5x); break; } } -#endif -#if (HAS_PIC16C55) /**************************************************************************** * Internal Memory Map ****************************************************************************/ @@ -1215,10 +1212,8 @@ CPU_GET_INFO( pic16c55 ) default: CPU_GET_INFO_CALL(pic16c5x); break; } } -#endif -#if (HAS_PIC16C56) /**************************************************************************** * Internal Memory Map ****************************************************************************/ @@ -1271,10 +1266,8 @@ CPU_GET_INFO( pic16c56 ) default: CPU_GET_INFO_CALL(pic16c5x); break; } } -#endif -#if (HAS_PIC16C57) /**************************************************************************** * Internal Memory Map ****************************************************************************/ @@ -1331,10 +1324,8 @@ CPU_GET_INFO( pic16c57 ) default: CPU_GET_INFO_CALL(pic16c5x); break; } } -#endif -#if (HAS_PIC16C58) /**************************************************************************** * Internal Memory Map ****************************************************************************/ @@ -1391,4 +1382,3 @@ CPU_GET_INFO( pic16c58 ) default: CPU_GET_INFO_CALL(pic16c5x); break; } } -#endif diff --git a/src/emu/cpu/pic16c5x/pic16c5x.h b/src/emu/cpu/pic16c5x/pic16c5x.h index a561ec89a43..704fd565a17 100644 --- a/src/emu/cpu/pic16c5x/pic16c5x.h +++ b/src/emu/cpu/pic16c5x/pic16c5x.h @@ -48,39 +48,27 @@ void pic16c5x_set_config(const device_config *cpu, int data); -#if (HAS_PIC16C54) CPU_GET_INFO( pic16c54 ); #define CPU_PIC16C54 CPU_GET_INFO_NAME( pic16c54 ) -#endif -#if (HAS_PIC16C55) CPU_GET_INFO( pic16c55 ); #define CPU_PIC16C55 CPU_GET_INFO_NAME( pic16c55 ) -#endif -#if (HAS_PIC16C56) CPU_GET_INFO( pic16c56 ); #define CPU_PIC16C56 CPU_GET_INFO_NAME( pic16c56 ) -#endif -#if (HAS_PIC16C57) CPU_GET_INFO( pic16c57 ); #define CPU_PIC16C57 CPU_GET_INFO_NAME( pic16c57 ) -#endif -#if (HAS_PIC16C58) CPU_GET_INFO( pic16c58 ); #define CPU_PIC16C58 CPU_GET_INFO_NAME( pic16c58 ) -#endif -#if (HAS_PIC16C54) || (HAS_PIC16C55) || (HAS_PIC16C56) || (HAS_PIC16C57) || (HAS_PIC16C58) CPU_DISASSEMBLE( pic16c5x ); -#endif #endif /* __PIC16C5X_H__ */ diff --git a/src/emu/cpu/sharc/sharc.c b/src/emu/cpu/sharc/sharc.c index b53721a0c43..c441c656b19 100644 --- a/src/emu/cpu/sharc/sharc.c +++ b/src/emu/cpu/sharc/sharc.c @@ -958,7 +958,6 @@ static CPU_SET_INFO( sharc ) } } -#if (HAS_ADSP21062) static CPU_SET_INFO( adsp21062 ) { if (state >= CPUINFO_INT_INPUT_STATE && state <= CPUINFO_INT_INPUT_STATE + 2) @@ -976,7 +975,6 @@ static CPU_SET_INFO( adsp21062 ) default: CPU_SET_INFO_CALL(sharc); break; } } -#endif static CPU_READ( sharc ) @@ -1327,7 +1325,6 @@ static CPU_GET_INFO( sharc ) } } -#if (HAS_ADSP21062) CPU_GET_INFO( adsp21062 ) { switch(state) @@ -1341,4 +1338,3 @@ CPU_GET_INFO( adsp21062 ) default: CPU_GET_INFO_CALL(sharc); break; } } -#endif diff --git a/src/emu/cpu/sharc/sharc.h b/src/emu/cpu/sharc/sharc.h index c5b42a898d4..641db6647e0 100644 --- a/src/emu/cpu/sharc/sharc.h +++ b/src/emu/cpu/sharc/sharc.h @@ -27,10 +27,8 @@ extern void sharc_set_flag_input(const device_config *device, int flag_num, int extern void sharc_external_iop_write(const device_config *device, UINT32 address, UINT32 data); extern void sharc_external_dma_write(const device_config *device, UINT32 address, UINT64 data); -#if (HAS_ADSP21062) CPU_GET_INFO( adsp21062 ); #define CPU_ADSP21062 CPU_GET_INFO_NAME( adsp21062 ) -#endif extern UINT32 sharc_dasm_one(char *buffer, offs_t pc, UINT64 opcode); diff --git a/src/emu/cpu/ssp1601/ssp1601.c b/src/emu/cpu/ssp1601/ssp1601.c index fbf8f96e2ca..a239633629d 100644 --- a/src/emu/cpu/ssp1601/ssp1601.c +++ b/src/emu/cpu/ssp1601/ssp1601.c @@ -771,7 +771,6 @@ static CPU_DISASSEMBLE( ssp1601 ) return dasm_ssp1601(buffer, pc, oprom); } -#if (HAS_SSP1601) static CPU_SET_INFO( ssp1601 ) { @@ -919,7 +918,6 @@ CPU_GET_INFO( ssp1601 ) case CPUINFO_STR_REGISTER + SSP_PR7: sprintf(info->s, "R7 :%02X", ssp1601_state->r[7]); break; } } -#endif // vim:ts=4 diff --git a/src/emu/cpu/ssp1601/ssp1601.h b/src/emu/cpu/ssp1601/ssp1601.h index 8df2cf15cbe..f1dca8b270d 100644 --- a/src/emu/cpu/ssp1601/ssp1601.h +++ b/src/emu/cpu/ssp1601/ssp1601.h @@ -16,10 +16,8 @@ enum SSP_PR0, SSP_PR1, SSP_PR2, SSP_PR3, SSP_PR4, SSP_PR5, SSP_PR6, SSP_PR7 }; -#if (HAS_SSP1601) CPU_GET_INFO( ssp1601 ); #define CPU_SSP1601 CPU_GET_INFO_NAME( ssp1601 ) -#endif extern unsigned dasm_ssp1601(char *buffer, unsigned pc, const UINT8 *oprom); diff --git a/src/emu/cpu/tms32025/tms32025.c b/src/emu/cpu/tms32025/tms32025.c index f3756ada905..507c41a7d68 100644 --- a/src/emu/cpu/tms32025/tms32025.c +++ b/src/emu/cpu/tms32025/tms32025.c @@ -1796,7 +1796,6 @@ static CPU_RESET( tms32025 ) cpustate->datamap[7] = &cpustate->intRAM[0x380]; /* B1 */ } -#if (HAS_TMS32026) static CPU_RESET( tms32026 ) { tms32025_state *cpustate = get_safe_token(device); @@ -1821,7 +1820,6 @@ static CPU_RESET( tms32026 ) cpustate->datamap[14] = &cpustate->intRAM[0x700]; /* B3 */ cpustate->datamap[15] = &cpustate->intRAM[0x780]; /* B3 */ } -#endif /**************************************************************************** @@ -2436,7 +2434,6 @@ CPU_GET_INFO( tms32025 ) } -#if (HAS_TMS32026) /************************************************************************** * CPU-specific set_info **************************************************************************/ @@ -2454,4 +2451,3 @@ CPU_GET_INFO( tms32026 ) default: CPU_GET_INFO_CALL(tms32025); break; } } -#endif diff --git a/src/emu/cpu/tms32051/tms32051.c b/src/emu/cpu/tms32051/tms32051.c index 1bb68b8e96d..39b796801d3 100644 --- a/src/emu/cpu/tms32051/tms32051.c +++ b/src/emu/cpu/tms32051/tms32051.c @@ -679,7 +679,6 @@ static CPU_GET_INFO( tms ) } } -#if (HAS_TMS32051) static CPU_SET_INFO( tms32051 ) { tms32051_state *cpustate = get_safe_token(device); @@ -732,4 +731,3 @@ CPU_GET_INFO( tms32051 ) default: CPU_GET_INFO_CALL(tms); break; } } -#endif diff --git a/src/emu/cpu/tms32051/tms32051.h b/src/emu/cpu/tms32051/tms32051.h index 691008723da..3d119e59e6c 100644 --- a/src/emu/cpu/tms32051/tms32051.h +++ b/src/emu/cpu/tms32051/tms32051.h @@ -3,10 +3,8 @@ #ifndef __TMS32051_H__ #define __TMS32051_H__ -#if (HAS_TMS32051) CPU_GET_INFO( tms32051 ); #define CPU_TMS32051 CPU_GET_INFO_NAME( tms32051 ) -#endif CPU_DISASSEMBLE( tms32051 ); diff --git a/src/emu/cpu/tms9900/tms9900.h b/src/emu/cpu/tms9900/tms9900.h index b3c18b7fb6c..6b4f618f5a3 100644 --- a/src/emu/cpu/tms9900/tms9900.h +++ b/src/emu/cpu/tms9900/tms9900.h @@ -52,7 +52,6 @@ typedef void (*ti99xx_lrex_func)(const device_config *device); typedef void (*ti99xx_ckon_ckof_func)(const device_config *device, int state); typedef void (*ti99xx_error_interrupt_func)(const device_config *device, int state); -#if (HAS_TI990_10) extern CPU_GET_INFO( ti990_10 ); #define CPU_TI990_10 CPU_GET_INFO_NAME( ti990_10 ) @@ -80,9 +79,7 @@ extern WRITE8_HANDLER(ti990_10_mapper_cru_w); extern READ8_HANDLER(ti990_10_eir_cru_r); extern WRITE8_HANDLER(ti990_10_eir_cru_w); -#endif -#if (HAS_TMS9900) extern CPU_GET_INFO( tms9900 ); #define CPU_TMS9900 CPU_GET_INFO_NAME( tms9900 ) @@ -95,9 +92,7 @@ typedef struct tms9900reset_param ti99xx_idle_func idle_callback; } tms9900reset_param; -#endif -#if (HAS_TMS9940) extern CPU_GET_INFO( tms9940 ); #define CPU_TMS9940 CPU_GET_INFO_NAME( tms9940 ) @@ -110,9 +105,7 @@ typedef struct tms9940reset_param ti99xx_idle_func idle_callback; } tms9940reset_param; -#endif -#if (HAS_TMS9980) extern CPU_GET_INFO( tms9980a ); #define CPU_TMS9980 CPU_GET_INFO_NAME( tms9980a ) @@ -125,9 +118,7 @@ typedef struct tms9980areset_param ti99xx_idle_func idle_callback; } tms9980areset_param; -#endif -#if (HAS_TMS9985) extern CPU_GET_INFO( tms9985 ); #define CPU_TMS9986 CPU_GET_INFO_NAME( tms9985 ) @@ -140,9 +131,7 @@ typedef struct tms9985reset_param ti99xx_idle_func idle_callback; } tms9985reset_param; -#endif -#if (HAS_TMS9989) extern CPU_GET_INFO( tms9989 ); #define CPU_TMS9989 CPU_GET_INFO_NAME( tms9989 ) @@ -155,9 +144,7 @@ typedef struct tms9989reset_param ti99xx_idle_func idle_callback; } tms9989reset_param; -#endif -#if (HAS_TMS9995) extern CPU_GET_INFO( tms9995 ); #define CPU_TMS9995 CPU_GET_INFO_NAME( tms9995 ) @@ -186,9 +173,7 @@ extern WRITE8_HANDLER(tms9995_internal1_w); extern READ8_HANDLER(tms9995_internal2_r); extern WRITE8_HANDLER(tms9995_internal2_w); -#endif -#if (HAS_TMS99000) extern CPU_GET_INFO( tms99000 ); #define CPU_TMS99000 CPU_GET_INFO_NAME( tms99000 ) @@ -201,9 +186,7 @@ typedef struct tms99000reset_param ti99xx_idle_func idle_callback; } tms99000reset_param; -#endif -#if (HAS_TMS99105A) extern CPU_GET_INFO( tms99105a ); #define CPU_TMS99105A CPU_GET_INFO_NAME( tms99105a ) @@ -216,9 +199,7 @@ typedef struct tms99105areset_param ti99xx_idle_func idle_callback; } tms99105areset_param; -#endif -#if (HAS_TMS99110A) extern CPU_GET_INFO( tms99110a ); #define CPU_TMS99110A CPU_GET_INFO_NAME( tms99110a ) @@ -231,7 +212,6 @@ typedef struct tms99110areset_param ti99xx_idle_func idle_callback; } tms99110areset_param; -#endif unsigned Dasm9900 (char *buffer, unsigned pc, int model_id, const UINT8 *oprom, const UINT8 *opram); diff --git a/src/emu/cpu/v60/v60.h b/src/emu/cpu/v60/v60.h index 77e3c9f611b..c0a1103dc1d 100644 --- a/src/emu/cpu/v60/v60.h +++ b/src/emu/cpu/v60/v60.h @@ -81,14 +81,10 @@ enum extern const char *const v60_reg_names[]; void v60_stall(const device_config *device); -#if HAS_V60 CPU_GET_INFO( v60 ); #define CPU_V60 CPU_GET_INFO_NAME( v60 ) -#endif /* HAS_V60 */ -#if HAS_V70 CPU_GET_INFO( v70 ); #define CPU_V70 CPU_GET_INFO_NAME( v70 ) -#endif /* HAS_V70 */ #endif /* __V60_H__ */ diff --git a/src/mame/mame.mak b/src/mame/mame.mak index f4d3fb71341..ac6586e4ab2 100644 --- a/src/mame/mame.mak +++ b/src/mame/mame.mak @@ -37,139 +37,52 @@ CPUS += Z80 CPUS += Z180 CPUS += I8085 CPUS += M6502 -CPUS += M65C02 -CPUS += M65SC02 -CPUS += M65CE02 -CPUS += M6509 -CPUS += M6510 -CPUS += M6510T -CPUS += M7501 -CPUS += M8502 -CPUS += N2A03 -CPUS += DECO16 -CPUS += M4510 CPUS += H6280 -CPUS += I8086 -CPUS += I8088 -CPUS += I80186 -CPUS += I80188 -CPUS += I80286 +CPUS += I86 CPUS += I386 -CPUS += I486 -CPUS += PENTIUM -CPUS += MEDIAGX -CPUS += V20 -CPUS += V25 -CPUS += V30 +CPUS += NEC CPUS += V30MZ -CPUS += V33 -CPUS += V35 CPUS += V60 -CPUS += V70 CPUS += MCS48 -CPUS += I8031 -CPUS += I8032 -CPUS += I8051 -CPUS += I8052 -CPUS += I8751 -CPUS += I8752 -CPUS += I80C31 -CPUS += I80C32 -CPUS += I80C51 -CPUS += I80C52 -CPUS += I87C51 -CPUS += I87C52 -CPUS += AT89C4051 -CPUS += DS5002FP +CPUS += MCS51 CPUS += M6800 -CPUS += M6801 -CPUS += M6802 -CPUS += M6803 -CPUS += M6808 -CPUS += HD63701 -CPUS += NSC8105 CPUS += M6805 -CPUS += M68705 -CPUS += HD63705 CPUS += HD6309 CPUS += M6809 -CPUS += M6809E CPUS += KONAMI CPUS += M680X0 CPUS += T11 CPUS += S2650 CPUS += TMS340X0 CPUS += TMS9900 -CPUS += TMS9940 -CPUS += TMS9980 -CPUS += TMS9985 -CPUS += TMS9989 -CPUS += TMS9995 -CPUS += TMS99105A -CPUS += TMS99110A -CPUS += TMS99000 -CPUS += TMS99010 CPUS += Z8000 CPUS += TMS32010 CPUS += TMS32025 -CPUS += TMS32026 CPUS += TMS32031 -CPUS += TMS32032 CPUS += TMS32051 CPUS += TMS57002 CPUS += CCPU CPUS += ADSP21XX -CPUS += PSXCPU -CPUS += CXD8661R CPUS += ASAP CPUS += UPD7810 -CPUS += UPD7807 -CPUS += UPD7801 CPUS += ARM CPUS += ARM7 CPUS += JAGUAR CPUS += CUBEQCPU CPUS += ESRIP -CPUS += R3000 -CPUS += R3041 -CPUS += VR4300 -CPUS += R4600 -CPUS += R4650 -CPUS += R4700 -CPUS += R5000 -CPUS += QED5271 -CPUS += RM7000 -CPUS += SH1 +CPUS += MIPS CPUS += SH2 CPUS += SH4 CPUS += DSP32C -CPUS += PIC16C54 -CPUS += PIC16C55 -CPUS += PIC16C56 -CPUS += PIC16C57 -CPUS += PIC16C58 +CPUS += PIC16C5X CPUS += G65816 CPUS += SPC700 -CPUS += E116T -CPUS += E116XT -CPUS += E116XS -CPUS += E116XSR -CPUS += E132N -CPUS += E132T -CPUS += E132XN -CPUS += E132XT -CPUS += E132XS -CPUS += E132XSR -CPUS += GMS30C2116 -CPUS += GMS30C2132 -CPUS += GMS30C2216 -CPUS += GMS30C2232 +CPUS += E1 CPUS += I860 CPUS += I960 CPUS += H83002 CPUS += H83334 CPUS += V810 -CPUS += M37702 CPUS += M37710 CPUS += POWERPC CPUS += SE3208 @@ -178,14 +91,10 @@ CPUS += ADSP21062 CPUS += DSP56156 CPUS += RSP CPUS += ALPHA8201 -CPUS += ALPHA8301 CPUS += CDP1802 CPUS += COP400 CPUS += TLCS90 -CPUS += MB8841 -CPUS += MB8842 -CPUS += MB8843 -CPUS += MB8844 +CPUS += MB88XX CPUS += MB86233 CPUS += SSP1601 CPUS += APEXC @@ -195,10 +104,8 @@ CPUS += LH5801 CPUS += PDP1 CPUS += SATURN CPUS += SC61860 -CPUS += TX0 CPUS += LR35902 CPUS += TMS7000 -CPUS += TMS7000_EXL CPUS += SM8500 CPUS += MINX diff --git a/src/mame/tiny.mak b/src/mame/tiny.mak index 6aa04cc597c..4910f33cd20 100644 --- a/src/mame/tiny.mak +++ b/src/mame/tiny.mak @@ -35,10 +35,10 @@ OBJDIRS += \ CPUS += Z80 CPUS += M6502 -CPUS += M6808 +CPUS += M6800 CPUS += M6809 CPUS += M68000 -CPUS += DS5002FP +CPUS += MCS51 @@ -93,4 +93,4 @@ DRVLIBS = \ $(DRIVERS)/astrocde.o: $(LAYOUT)/gorf.lh \ $(LAYOUT)/tenpindx.lh $(DRIVERS)/circus.o: $(LAYOUT)/circus.lh \ - $(LAYOUT)/crash.lh \ No newline at end of file + $(LAYOUT)/crash.lh