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https://github.com/holub/mame
synced 2025-06-07 13:23:50 +03:00
moved i/o handling to the c file
This commit is contained in:
hap
parent
a953b03b5c
commit
a36a9bef31
@ -280,6 +280,157 @@ void hmcs40_cpu_device::device_reset()
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//-------------------------------------------------
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// i/o handling
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//-------------------------------------------------
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UINT8 hmcs40_cpu_device::read_r(int index)
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{
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index &= 7;
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UINT8 inp = 0xf;
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switch (index)
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{
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case 0: inp = m_read_r0(index, 0xff); break;
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case 1: inp = m_read_r1(index, 0xff); break;
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case 2: inp = m_read_r2(index, 0xff); break;
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case 3: inp = m_read_r3(index, 0xff); break;
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case 4: inp = m_read_r4(index, 0xff); break;
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case 5: inp = m_read_r5(index, 0xff); break;
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case 6: inp = m_read_r6(index, 0xff); break;
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case 7: inp = m_read_r7(index, 0xff); break;
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}
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if (m_is_cmos)
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return (inp & m_r[index]) & 0xf;
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else
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return (inp | m_r[index]) & 0xf;
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}
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void hmcs40_cpu_device::write_r(int index, UINT8 data)
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{
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index &= 7;
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data &= 0xf;
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m_r[index] = data;
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switch (index)
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{
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case 0: m_write_r0(index, m_r[index], 0xff); break;
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case 1: m_write_r1(index, m_r[index], 0xff); break;
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case 2: m_write_r2(index, m_r[index], 0xff); break;
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case 3: m_write_r3(index, m_r[index], 0xff); break;
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case 4: m_write_r4(index, m_r[index], 0xff); break;
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case 5: m_write_r5(index, m_r[index], 0xff); break;
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case 6: m_write_r6(index, m_r[index], 0xff); break;
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case 7: m_write_r7(index, m_r[index], 0xff); break;
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}
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}
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int hmcs40_cpu_device::read_d(int index)
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{
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index &= 15;
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if (m_is_cmos)
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return (m_read_d(index, 0xffff) & m_d) >> index & 1;
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else
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return (m_read_d(index, 0xffff) | m_d) >> index & 1;
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}
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void hmcs40_cpu_device::write_d(int index, int state)
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{
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index &= 15;
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m_d = (m_d & ~(1 << index)) | (((state) ? 1 : 0) << index);
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m_write_d(index, m_d, 0xffff);
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}
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// HMCS43:
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// R0 is input-only, R1 is i/o, R2,R3 are output-only, no R4-R7
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// D0-D3 are i/o, D4-D15 are output-only
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UINT8 hmcs43_cpu_device::read_r(int index)
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{
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index &= 7;
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if (index >= 2)
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logerror("%s read from %s port R%d at $%04X\n", tag(), (index >= 4) ? "unknown" : "output", index, m_prev_pc << 1);
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return hmcs40_cpu_device::read_r(index);
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}
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void hmcs43_cpu_device::write_r(int index, UINT8 data)
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{
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index &= 7;
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if (index != 0 && index < 4)
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hmcs40_cpu_device::write_r(index, data);
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else
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logerror("%s ineffective write to port R%d = $%X at $%04X\n", tag(), index, data & 0xf, m_prev_pc << 1);
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}
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int hmcs43_cpu_device::read_d(int index)
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{
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index &= 15;
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if (index >= 4)
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{
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logerror("%s read from output pin D%d at $%04X\n", tag(), index, m_prev_pc << 1);
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return m_d >> index & 1;
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}
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else
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return hmcs40_cpu_device::read_d(index);
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}
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// HMCS44:
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// R0-R3 are i/o, R4,R5 are extra registers, no R6,R7
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// D0-D15 are i/o
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UINT8 hmcs44_cpu_device::read_r(int index)
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{
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index &= 7;
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if (index >= 6)
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logerror("%s read from unknown port R%d at $%04X\n", tag(), index, m_prev_pc << 1);
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return hmcs40_cpu_device::read_r(index);
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}
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void hmcs44_cpu_device::write_r(int index, UINT8 data)
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{
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index &= 7;
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if (index < 6)
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hmcs40_cpu_device::write_r(index, data);
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else
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logerror("%s ineffective write to port R%d = $%X at $%04X\n", tag(), index, data & 0xf, m_prev_pc << 1);
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}
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// HMCS45:
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// R0-R5 are i/o, R6 is output-only, no R7
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// D0-D15 are i/o
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UINT8 hmcs45_cpu_device::read_r(int index)
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{
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index &= 7;
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if (index >= 6)
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logerror("%s read from %s port R%d at $%04X\n", tag(), (index == 7) ? "unknown" : "output", index, m_prev_pc << 1);
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return hmcs40_cpu_device::read_r(index);
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}
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void hmcs45_cpu_device::write_r(int index, UINT8 data)
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{
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index &= 7;
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if (index != 7)
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hmcs40_cpu_device::write_r(index, data);
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else
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logerror("%s ineffective write to port R%d = $%X at $%04X\n", tag(), index, data & 0xf, m_prev_pc << 1);
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}
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//-------------------------------------------------
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//-------------------------------------------------
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// execute
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// execute
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//-------------------------------------------------
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//-------------------------------------------------
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@ -29,156 +29,6 @@ void hmcs40_cpu_device::push_stack()
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}
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}
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// i/o
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UINT8 hmcs40_cpu_device::read_r(int index)
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{
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index &= 7;
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UINT8 inp = 0xf;
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switch (index)
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{
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case 0: inp = m_read_r0(index, 0xff); break;
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case 1: inp = m_read_r1(index, 0xff); break;
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case 2: inp = m_read_r2(index, 0xff); break;
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case 3: inp = m_read_r3(index, 0xff); break;
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case 4: inp = m_read_r4(index, 0xff); break;
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case 5: inp = m_read_r5(index, 0xff); break;
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case 6: inp = m_read_r6(index, 0xff); break;
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case 7: inp = m_read_r7(index, 0xff); break;
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}
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if (m_is_cmos)
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return (inp & m_r[index]) & 0xf;
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else
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return (inp | m_r[index]) & 0xf;
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}
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void hmcs40_cpu_device::write_r(int index, UINT8 data)
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{
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index &= 7;
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data &= 0xf;
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m_r[index] = data;
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switch (index)
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{
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case 0: m_write_r0(index, m_r[index], 0xff); break;
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case 1: m_write_r1(index, m_r[index], 0xff); break;
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case 2: m_write_r2(index, m_r[index], 0xff); break;
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case 3: m_write_r3(index, m_r[index], 0xff); break;
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case 4: m_write_r4(index, m_r[index], 0xff); break;
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case 5: m_write_r5(index, m_r[index], 0xff); break;
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case 6: m_write_r6(index, m_r[index], 0xff); break;
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case 7: m_write_r7(index, m_r[index], 0xff); break;
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}
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}
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int hmcs40_cpu_device::read_d(int index)
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{
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index &= 15;
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if (m_is_cmos)
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return (m_read_d(index, 0xffff) & m_d) >> index & 1;
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else
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return (m_read_d(index, 0xffff) | m_d) >> index & 1;
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}
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void hmcs40_cpu_device::write_d(int index, int state)
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{
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index &= 15;
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m_d = (m_d & ~(1 << index)) | (((state) ? 1 : 0) << index);
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m_write_d(index, m_d, 0xffff);
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}
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// HMCS43:
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// R0 is input-only, R1 is i/o, R2,R3 are output-only, no R4-R7
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// D0-D3 are i/o, D4-D15 are output-only
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UINT8 hmcs43_cpu_device::read_r(int index)
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{
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index &= 7;
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if (index >= 2)
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logerror("%s read from %s port R%d at $%04X\n", tag(), (index >= 4) ? "unknown" : "output", index, m_prev_pc << 1);
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return hmcs40_cpu_device::read_r(index);
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}
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void hmcs43_cpu_device::write_r(int index, UINT8 data)
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{
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index &= 7;
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if (index != 0 && index < 4)
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hmcs40_cpu_device::write_r(index, data);
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else
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logerror("%s ineffective write to port R%d = $%X at $%04X\n", tag(), index, data & 0xf, m_prev_pc << 1);
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}
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int hmcs43_cpu_device::read_d(int index)
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{
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index &= 15;
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if (index >= 4)
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{
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logerror("%s read from output pin D%d at $%04X\n", tag(), index, m_prev_pc << 1);
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return m_d >> index & 1;
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}
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else
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return hmcs40_cpu_device::read_d(index);
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}
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// HMCS44:
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// R0-R3 are i/o, R4,R5 are extra registers, no R6,R7
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// D0-D15 are i/o
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UINT8 hmcs44_cpu_device::read_r(int index)
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{
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index &= 7;
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if (index >= 6)
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logerror("%s read from unknown port R%d at $%04X\n", tag(), index, m_prev_pc << 1);
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return hmcs40_cpu_device::read_r(index);
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}
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void hmcs44_cpu_device::write_r(int index, UINT8 data)
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{
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index &= 7;
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if (index < 6)
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hmcs40_cpu_device::write_r(index, data);
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else
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logerror("%s ineffective write to port R%d = $%X at $%04X\n", tag(), index, data & 0xf, m_prev_pc << 1);
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}
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// HMCS45:
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// R0-R5 are i/o, R6 is output-only, no R7
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// D0-D15 are i/o
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UINT8 hmcs45_cpu_device::read_r(int index)
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{
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index &= 7;
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if (index >= 6)
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logerror("%s read from %s port R%d at $%04X\n", tag(), (index == 7) ? "unknown" : "output", index, m_prev_pc << 1);
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return hmcs40_cpu_device::read_r(index);
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}
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void hmcs45_cpu_device::write_r(int index, UINT8 data)
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{
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index &= 7;
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if (index != 7)
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hmcs40_cpu_device::write_r(index, data);
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else
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logerror("%s ineffective write to port R%d = $%X at $%04X\n", tag(), index, data & 0xf, m_prev_pc << 1);
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}
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// instruction set
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// instruction set
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