mirror of
https://github.com/holub/mame
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pci/zr36057.cpp: preliminary PostOffice interactions, kick off enough glue logic with a ZR36060 so that DC10+ passes board tests
This commit is contained in:
angelosa
parent
4f8fb4b2af
commit
a3bdebb78f
@ -1697,6 +1697,18 @@ if (VIDEOS["X1_001"]~=null) then
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}
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end
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--------------------------------------------------
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--
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--@src/devices/video/zr36060.h,VIDEOS["ZR36060"] = true
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--------------------------------------------------
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if (VIDEOS["ZR36060"]~=null) then
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files {
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MAME_DIR .. "src/devices/video/zr36060.cpp",
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MAME_DIR .. "src/devices/video/zr36060.h",
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}
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end
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--------------------------------------------------
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--
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--@src/devices/video/zr36110.h,VIDEOS["ZR36110"] = true
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@ -14,12 +14,13 @@ iterations.
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ZR36057 is known to have two HW quirks that are been fixed with ZR36067.
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TODO:
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- Currently at dc10plus HW test "Error at M-JPEG codec", requires ZR36060 to continue;
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- Enough to pass board functions in dc10plus HW test, requires VSYNC signal from ZR36060 to continue;
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- Hookup busmaster;
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- What are i2c 0x8e >> 1 address device checks for?
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\- Can't be adv7175 (0xd4 >> 1) nor adv7176 (0x54 >> 1)
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...
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- Soft Reset & Write lock mechanisms (each register have separate macro-groups);
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- GuestBus slot mechanism (relevant when multiple devices are hooked);
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- eventually decouple AV PCI controller part from the actual client cards;
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Known mix-ins:
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@ -37,13 +38,14 @@ Known mix-ins:
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#include "zr36057.h"
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#define LOG_WARN (1U << 1)
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#define LOG_PO (1U << 2) // PostOffice interactions
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#define VERBOSE (LOG_GENERAL | LOG_WARN)
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#define VERBOSE (LOG_GENERAL | LOG_WARN | LOG_PO)
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//#define LOG_OUTPUT_FUNC osd_printf_info
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#include "logmacro.h"
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#define LOGWARN(...) LOGMASKED(LOG_WARN, __VA_ARGS__)
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#define LOGPO(...) LOGMASKED(LOG_PO, __VA_ARGS__)
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DEFINE_DEVICE_TYPE(ZR36057_PCI, zr36057_device, "zr36057", "Zoran ZR36057-based Enhanced Multimedia Controller")
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//DEFINE_DEVICE_TYPE(ZR36067_PCI, zr36067_device, "zr36067", "Zoran ZR36067-based AV Controller")
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@ -51,6 +53,7 @@ DEFINE_DEVICE_TYPE(ZR36057_PCI, zr36057_device, "zr36057", "Zoran ZR36057-ba
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zr36057_device::zr36057_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
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: pci_card_device(mconfig, type, tag, owner, clock)
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, m_guest(*this, "guest")
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, m_decoder(*this, "decoder")
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{
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// ZR36057PQC Video cutting chipset
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@ -73,11 +76,13 @@ zr36057_device::zr36057_device(const machine_config &mconfig, const char *tag, d
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void zr36057_device::device_add_mconfig(machine_config &config)
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{
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// 27'000'000 xtal near ZR36060
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ZR36060(config, m_guest, XTAL(27'000'000));
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SAA7110A(config, m_decoder, XTAL(26'800'000));
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m_decoder->sda_callback().set([this](int state) { m_decoder_sdao_state = state; });
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//ADV7176(config, m_encoder, XTAL(27'000'000));
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// S-Video input/output
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// composite video input/output
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@ -116,8 +121,11 @@ void zr36057_device::device_reset()
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void zr36057_device::software_reset()
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{
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LOG("SoftReset\n");
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m_video_frontend.horizontal_config = (0 << 30) | (0x001 << 10) | (0x3ff << 0);
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m_video_frontend.vertical_config = (0 << 30) | (0x001 << 10) | (0x3ff << 0);
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m_vfe.hspol = m_vfe.vspol = 0;
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m_vfe.hstart = m_vfe.vstart = 0x001;
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m_vfe.hend = m_vfe.vend = 0x3ff;
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m_vfe.horizontal_config = (m_vfe.hspol << 30) | (m_vfe.hstart << 10) | (m_vfe.hend << 0);
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m_vfe.vertical_config = (m_vfe.vspol << 30) | (m_vfe.vstart << 10) | (m_vfe.vend << 0);
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m_pci_waitstate_control = 0;
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m_gpio_ddr = 0xff; // all inputs
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@ -125,6 +133,15 @@ void zr36057_device::software_reset()
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// m_gpio_data = 0xf0;
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for (int i = 0; i < 4; i++)
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m_guestbus.time[i] = 0;
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m_jpeg_guest_id = 4;
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m_jpeg_guest_reg = 0;
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m_po.pending = false;
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m_po.time_out = false;
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m_po.dir = true;
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m_po.guest_id = 0;
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m_po.guest_reg = 0;
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}
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void zr36057_device::config_map(address_map &map)
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@ -134,33 +151,46 @@ void zr36057_device::config_map(address_map &map)
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map(0x3f, 0x3f).lr8(NAME([] () { return 0x10; }));
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}
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// Application Specific Register
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// Application Specific Register(s)
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void zr36057_device::asr_map(address_map &map)
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{
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map(0x000, 0x003).lrw32(
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NAME([this] (offs_t offset) {
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// NOTE: wants to read-back here, throws "Bus Master ASIC error" otherwise (?)
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LOG("Video Front End Horizontal Configuration R\n");
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return m_video_frontend.horizontal_config;
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return m_vfe.horizontal_config;
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}),
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NAME([this] (offs_t offset, u32 data, u32 mem_mask) {
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COMBINE_DATA(&m_video_frontend.horizontal_config);
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COMBINE_DATA(&m_vfe.horizontal_config);
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LOG("Video Front End Horizontal Configuration W %08x & %08x\n", data, mem_mask);
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m_vfe.hspol = BIT(m_vfe.horizontal_config, 30);
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m_vfe.hstart = (m_vfe.horizontal_config >> 10) & 0x3ff;
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m_vfe.hend = (m_vfe.horizontal_config >> 0) & 0x3ff;
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LOG("\tVSPOL %d VSTART %d VEND %d\n", m_vfe.hspol, m_vfe.hstart, m_vfe.hend);
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})
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);
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map(0x004, 0x007).lrw32(
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NAME([this] (offs_t offset) {
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LOG("Video Front End Vertical Configuration R\n");
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return m_video_frontend.vertical_config;
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return m_vfe.vertical_config;
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}),
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NAME([this] (offs_t offset, u32 data, u32 mem_mask) {
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COMBINE_DATA(&m_video_frontend.vertical_config);
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COMBINE_DATA(&m_vfe.vertical_config);
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LOG("Video Front End Vertical Configuration %08x & %08\n", data, mem_mask);
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m_vfe.vspol = BIT(m_vfe.vertical_config, 30);
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m_vfe.vstart = (m_vfe.vertical_config >> 10) & 0x3ff;
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m_vfe.vend = (m_vfe.vertical_config >> 0) & 0x3ff;
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LOG("\tVSPOL %d VSTART %d VEND %d\n", m_vfe.vspol, m_vfe.vstart, m_vfe.vend);
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})
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);
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// ...
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// map(0x008, 0x00b) VFE Config, Video Scaler and Pixel Format
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// map(0x00c, 0x00f) Video Display Top
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// map(0x010, 0x013) Video Display Bottom
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// map(0x014, 0x017) Video Display Stride, Status and Frame Grab
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// map(0x018, 0x01b) Video Display Configuration
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// map(0x01c, 0x01f) Masking Map Top
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// map(0x020, 0x023) Masking Map Bottom
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// map(0x024, 0x027) Overlay Control
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map(0x028, 0x02b).lrw32(
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NAME([this] (offs_t offset) {
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return (m_softreset << 24) | (m_pci_waitstate_control << 16) | m_gpio_ddr;
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@ -191,6 +221,7 @@ void zr36057_device::asr_map(address_map &map)
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// The doc claims 0xf0 default for GPIO, but win98 driver will throw "subvendor ID failed"
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// while testing various ID combinations here
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// This should come from GDAT pin at strapping time
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return (0x7e << 24) | (m_guestbus.time[3] << 12) | (m_guestbus.time[2] << 8) | (m_guestbus.time[1] << 4) | (m_guestbus.time[0] << 0);
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}),
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NAME([this] (offs_t offset, u32 data, u32 mem_mask) {
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@ -212,7 +243,11 @@ void zr36057_device::asr_map(address_map &map)
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}
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})
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);
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// map(0x030, 0x033) MPEG Code Source Address
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// map(0x034, 0x037) MPEG Code Transfer Control
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// map(0x038, 0x03b) MPEG Code Memory Pointer
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// map(0x03c, 0x03f) Interrupt Status
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// map(0x040, 0x043) Interrupt Control
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map(0x044, 0x047).lrw32(
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NAME([this] (offs_t offset) {
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LOG("I2C R\n");
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@ -229,4 +264,112 @@ void zr36057_device::asr_map(address_map &map)
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}
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})
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);
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// map(0x100, 0x103) JPEG Mode and Control
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// map(0x104, 0x107) JPEG Process Control
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// map(0x108, 0x10b) Vertical Sync Parameters (as sync master)
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// map(0x10c, 0x10f) Horizontal Sync Parameters (as sync master)
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// map(0x110, 0x113) Field Horizontal Active Portion
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// map(0x114, 0x117) Field Vertical Active Portion
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// map(0x118, 0x11b) Field Process Parameters
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// map(0x11c, 0x11f) JPEG Code Base Address
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// map(0x120, 0x123) JPEG Code FIFO Threshold
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map(0x124, 0x124).lrw8(
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NAME([this] (offs_t offset) {
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LOG("JPEG Codec Guest ID R\n");
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return (m_jpeg_guest_id << 4) | (m_jpeg_guest_reg << 0);
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}),
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NAME([this] (offs_t offset, u8 data) {
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m_jpeg_guest_id = (data >> 4) & 7;
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m_jpeg_guest_reg = (data >> 0) & 7;
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LOG("JPEG Codec Guest ID W %02x\n", data);
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})
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);
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map(0x12c, 0x12f).lrw32(
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NAME([this] (offs_t offset) {
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LOG("GuestBus Control (II) R\n");
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return (0 << 16) | (m_guestbus.time[7] << 12) | (m_guestbus.time[6] << 8) | (m_guestbus.time[5] << 4) | (m_guestbus.time[4] << 0);
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}),
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NAME([this] (offs_t offset, u32 data, u32 mem_mask) {
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LOG("GuestBus Control (II) W %08x & %08x\n", data, mem_mask);
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if (ACCESSING_BITS_8_15)
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{
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m_guestbus.time[7] = (data >> 12) & 0xf;
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m_guestbus.time[6] = (data >> 8) & 0xf;
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}
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if (ACCESSING_BITS_0_7)
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{
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m_guestbus.time[5] = (data >> 4) & 0xf;
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m_guestbus.time[4] = (data >> 0) & 0xf;
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}
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})
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);
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map(0x200, 0x2ff).rw(FUNC(zr36057_device::postoffice_r), FUNC(zr36057_device::postoffice_w));
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// map(0x300, 0x303) Still Transfer
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}
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// TODO: PostOffice accesses thru GuestBus are dictated with PCI clock cycles, asynchronous
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// We pretend they are synchronous as a starting point, and one port only (which may matter later
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// with CODE transfers). A time out happens 64 PCI cycles later in ZR36067, '120 halves that threshold.
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// This should eventually be expressed in a osd_work_queue, with guestbus address_space roughly as:
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// for (int i = 0; i < 8; i++)
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// {
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// if (<is_device_installed>)
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// map(0 | (i << 2), 3 | (i << 2)).flags(<fn>).m(m_guest[i], map);
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// else
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// map(0 | (i << 2), 3 | (i << 2)).flags(<abort_fn>);
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// }
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u32 zr36057_device::postoffice_r(offs_t offset)
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{
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//LOGPO("PO R %d %d\n", m_po.guest_id, m_po.guest_reg);
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u8 res = 0;
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if (m_po.guest_id == 0)
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{
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if (m_po.dir == false)
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res = m_guest->read(m_po.guest_reg);
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}
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else if (!machine().side_effects_disabled())
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{
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m_po.time_out = true;
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LOGWARN("Warning: PO access unmapped POGuestID read %d %02x\n", m_po.guest_id, m_po.guest_reg);
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}
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return (m_po.pending << 25)
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| (m_po.time_out << 24)
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| (m_po.dir << 23)
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| (m_po.guest_id << 20)
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| (m_po.guest_reg << 16)
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| res;
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}
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void zr36057_device::postoffice_w(offs_t offset, u32 data, u32 mem_mask)
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{
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// clear a previously set time out flag
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if (BIT(data, 24))
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m_po.time_out = false;
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m_po.dir = !!(BIT(data, 23));
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m_po.guest_id = (data >> 20) & 7;
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m_po.guest_reg = (data >> 16) & 7;
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LOGPO("PO W [%08x] %08x & %08x PODir %s POGuestID %d POGuestReg %d POData %02x\n"
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, offset << 2
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, data
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, mem_mask
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, m_po.dir ? "Write" : "Read"
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, m_po.guest_id
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, m_po.guest_reg
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, data & 0xff
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);
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if (m_po.guest_id == 0)
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{
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if (m_po.dir == true)
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m_guest->write(m_po.guest_reg, data & 0xff);
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}
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else
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{
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m_po.time_out = true;
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LOGWARN("Warning: PO access unmapped POGuestID write %d %02x\n", m_po.guest_id, m_po.guest_reg);
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}
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}
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@ -8,6 +8,7 @@
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#include "pci_slot.h"
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#include "video/saa7110.h"
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#include "video/zr36060.h"
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class zr36057_device : public pci_card_device
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{
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@ -25,29 +26,42 @@ protected:
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// virtual const tiny_rom_entry *device_rom_region() const override ATTR_COLD;
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// virtual void map_extra(uint64_t memory_window_start, uint64_t memory_window_end, uint64_t memory_offset, address_space *memory_space,
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// uint64_t io_window_start, uint64_t io_window_end, uint64_t io_offset, address_space *io_space) override;
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virtual void config_map(address_map &map) override ATTR_COLD;
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private:
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required_device<zr36060_device> m_guest;
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required_device<saa7110a_device> m_decoder;
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void asr_map(address_map &map) ATTR_COLD;
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void software_reset();
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u32 postoffice_r(offs_t offset);
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void postoffice_w(offs_t offset, u32 data, u32 mem_mask);
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// Video Front End
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struct {
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u32 horizontal_config;
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u32 vertical_config;
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} m_video_frontend;
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int hspol, vspol;
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u16 hstart, hend, vstart, vend;
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} m_vfe;
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u8 m_jpeg_guest_id, m_jpeg_guest_reg;
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bool m_softreset;
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u8 m_gpio_ddr, m_pci_waitstate_control;
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struct {
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u8 time[4];
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u8 time[8];
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} m_guestbus;
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struct {
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bool dir; /**< true: Write, false: Read */
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bool time_out;
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bool pending;
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u8 guest_id;
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u8 guest_reg;
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} m_po; /**< PostOffice */
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int m_decoder_sdao_state;
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};
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109
src/devices/video/zr36060.cpp
Normal file
109
src/devices/video/zr36060.cpp
Normal file
@ -0,0 +1,109 @@
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// license:BSD-3-Clause
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// copyright-holders: Angelo Salese
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#include "emu.h"
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#include "zr36060.h"
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#define VERBOSE (LOG_GENERAL)
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#include "logmacro.h"
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DEFINE_DEVICE_TYPE(ZR36060, zr36060_device, "zr36060", "Zoran ZR36060 Integrated JPEG codec")
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zr36060_device::zr36060_device(const machine_config &mconfig, char const *tag, device_t *owner, u32 clock)
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: device_t(mconfig, ZR36060, tag, owner, clock)
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, device_memory_interface(mconfig, *this)
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{
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m_space_config = address_space_config("regs", ENDIANNESS_BIG, 8, 10, 0, address_map_constructor(FUNC(zr36060_device::regs_map), this));
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}
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device_memory_interface::space_config_vector zr36060_device::memory_space_config() const
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{
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return space_config_vector {
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std::make_pair(0, &m_space_config)
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};
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}
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void zr36060_device::device_start()
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{
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}
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void zr36060_device::device_reset()
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{
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}
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void zr36060_device::regs_map(address_map &map)
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{
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// map(0x000, 0x000) LOAD Parameters
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// map(0x001, 0x001) Code FIFO Status (r/o)
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// map(0x002, 0x002) Code Interface
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// map(0x003, 0x003) Codec Mode
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// map(0x005, 0x005) Maximum Block Code
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||||
// map(0x006, 0x006) Markers Enable
|
||||
// map(0x007, 0x007) Interrupt Mask
|
||||
// map(0x008, 0x008) Interrupt Status (r/o)
|
||||
// map(0x009, 0x00c) Target Net Code Volume
|
||||
// map(0x00d, 0x010) Target Data Code Volume
|
||||
// map(0x011, 0x012) Scale Factor
|
||||
// map(0x013, 0x015) Allocation Factor
|
||||
// map(0x016, 0x019) Accumulated Code Volume
|
||||
// map(0x01a, 0x01d) Accumulated Total Activity
|
||||
// map(0x01e, 0x021) Accumulated Truncated Bits
|
||||
map(0x022, 0x022).lr8(NAME([this] (offs_t offset) { LOG("Read Device ID\n"); return 0x33; }));
|
||||
map(0x023, 0x023).lr8(NAME([this] (offs_t offset) { LOG("Read Revision ID\n"); return 0x01; }));
|
||||
// map(0x024, 0x025) Test Control
|
||||
|
||||
// map(0x030, 0x030) Video Control
|
||||
// map(0x031, 0x031) Video Polarity
|
||||
// map(0x032, 0x032) Scaling
|
||||
// map(0x033, 0x035) Background Color
|
||||
// map(0x036, 0x041) Sync Generator
|
||||
// map(0x042, 0x049) Active Area
|
||||
// map(0x04a, 0x051) SUBIMG Window
|
||||
|
||||
map(0x060, 0x3ff).ram(); // JPEG Markers Array
|
||||
}
|
||||
|
||||
/**************************************
|
||||
*
|
||||
* Host I/F
|
||||
*
|
||||
*************************************/
|
||||
|
||||
u8 zr36060_device::read(offs_t offset)
|
||||
{
|
||||
switch(offset & 3)
|
||||
{
|
||||
case 0:
|
||||
LOG("CODE FIFO read\n");
|
||||
return 0;
|
||||
case 1:
|
||||
return (m_address >> 8) & 3;
|
||||
case 2:
|
||||
return m_address & 0xff;
|
||||
case 3:
|
||||
return space(0).read_byte(m_address);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
void zr36060_device::write(offs_t offset, u8 data)
|
||||
{
|
||||
switch(offset & 3)
|
||||
{
|
||||
case 0:
|
||||
LOG("CODE FIFO write %02x\n", data);
|
||||
break;
|
||||
case 1:
|
||||
m_address = (data << 8) | (m_address & 0xff);
|
||||
break;
|
||||
case 2:
|
||||
m_address = (data & 0xff) | (m_address & 0x300);
|
||||
break;
|
||||
case 3:
|
||||
space(0).write_byte(m_address, data);
|
||||
break;
|
||||
}
|
||||
}
|
||||
31
src/devices/video/zr36060.h
Normal file
31
src/devices/video/zr36060.h
Normal file
@ -0,0 +1,31 @@
|
||||
// license:BSD-3-Clause
|
||||
// copyright-holders: Angelo Salese
|
||||
|
||||
#ifndef MAME_VIDEO_ZR36060_H
|
||||
#define MAME_VIDEO_ZR36060_H
|
||||
|
||||
#pragma once
|
||||
|
||||
class zr36060_device : public device_t, public device_memory_interface
|
||||
{
|
||||
public:
|
||||
zr36060_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock);
|
||||
|
||||
u8 read(offs_t offset);
|
||||
void write(offs_t offset, u8 data);
|
||||
|
||||
protected:
|
||||
virtual void device_start() override ATTR_COLD;
|
||||
virtual void device_reset() override ATTR_COLD;
|
||||
|
||||
virtual space_config_vector memory_space_config() const override;
|
||||
private:
|
||||
void regs_map(address_map &map);
|
||||
|
||||
u16 m_address;
|
||||
address_space_config m_space_config;
|
||||
};
|
||||
|
||||
DECLARE_DEVICE_TYPE(ZR36060, zr36060_device)
|
||||
|
||||
#endif // MAME_VIDEO_ZR36060_H
|
||||
@ -501,7 +501,7 @@ uint32_t magictg_state::zr36120_r(offs_t offset)
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Post office */
|
||||
// PostOffice reads
|
||||
res = 0;//mame_rand(machine);//m_zr36120.as_regs[0x48/4];
|
||||
}
|
||||
logerror("PINKEYE_R[%x]\n", offset);
|
||||
@ -529,6 +529,9 @@ void magictg_state::zr36120_w(offs_t offset, uint32_t data)
|
||||
}
|
||||
else
|
||||
{
|
||||
// PostOffice writes
|
||||
// - Takes 32 PCI clocks for time out to happen compared to 64 in ZR36067
|
||||
// - Has 4 guests instead of 8
|
||||
uint32_t guest = (data >> 20) & 3;
|
||||
uint32_t g_data = data & 0xff;
|
||||
uint32_t g_reg = (data >> 16) & 7;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user