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https://github.com/holub/mame
synced 2025-04-23 00:39:36 +03:00
pushman: better understanding of how CPU reads MCU data/status
bballs: simplify protection MCU simulation using pushman hookup as a guide (nw) bballs appears to use a simpler single-word arrangement for messages from CPU to MCU, perhaps so it can use a 28-pin MCU (pushman MCU receives the command byte on port D, which the 28-pin parts lack)
This commit is contained in:
Vas Crabb
parent
408a8fceb4
commit
a3e60b3f3d
@ -87,15 +87,15 @@ ADDRESS_MAP_END
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static ADDRESS_MAP_START( pushman_map, AS_PROGRAM, 16, pushman_state )
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AM_IMPORT_FROM(main_map)
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AM_RANGE(0x060000, 0x060001) AM_READWRITE(mcu_data_r, mcu_data_w)
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AM_RANGE(0x060002, 0x600003) AM_WRITE(mcu_cmd_w)
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AM_RANGE(0x060006, 0x060007) AM_READ(mcu_ack_r)
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AM_RANGE(0x060000, 0x060007) AM_READ(mcu_comm_r)
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AM_RANGE(0x060000, 0x060003) AM_WRITE(mcu_comm_w)
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( bballs_map, AS_PROGRAM, 16, bballs_state )
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ADDRESS_MAP_GLOBAL_MASK(0xfffff)
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AM_RANGE(0x00000, 0x3ffff) AM_ROM
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AM_RANGE(0x60000, 0x60007) AM_READWRITE(bballs_68705_r, bballs_68705_w)
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AM_RANGE(0x60000, 0x60007) AM_READ(bballs_68705_r)
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AM_RANGE(0x60000, 0x60003) AM_WRITE(bballs_68705_w)
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// are these mirror addresses or does this PCB have a different addressing?
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AM_RANGE(0xe0800, 0xe17ff) AM_RAM AM_SHARE("spriteram")
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AM_RANGE(0xe4000, 0xe4001) AM_READ_PORT("P1_P2") AM_WRITE(tigeroad_videoctrl_w)
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@ -685,6 +685,7 @@ MACHINE_CONFIG_END
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void pushman_state::machine_start()
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{
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save_item(NAME(m_host_semaphore));
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save_item(NAME(m_mcu_semaphore));
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save_item(NAME(m_host_latch));
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save_item(NAME(m_mcu_latch));
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@ -705,17 +706,14 @@ MACHINE_CONFIG_END
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MACHINE_RESET_MEMBER(bballs_state, bballs)
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{
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m_new_latch = 0;
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m_latch = 0x400;
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std::fill(std::begin(m_shared_ram), std::end(m_shared_ram), 0);
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m_mcu_semaphore = false;
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m_mcu_latch = 0x0400;
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}
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void bballs_state::machine_start()
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{
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save_item(NAME(m_shared_ram));
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save_item(NAME(m_latch));
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save_item(NAME(m_new_latch));
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save_item(NAME(m_mcu_semaphore));
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save_item(NAME(m_mcu_latch));
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}
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static MACHINE_CONFIG_DERIVED_CLASS(bballs, f1dream_comad, bballs_state)
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@ -72,6 +72,7 @@ public:
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pushman_state(const machine_config &mconfig, device_type type, const char *tag)
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: tigeroad_state(mconfig, type, tag)
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, m_mcu(*this, "mcu")
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, m_host_semaphore(false)
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, m_mcu_semaphore(false)
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, m_host_latch(0xffff)
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, m_mcu_latch(0xffff)
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@ -81,10 +82,8 @@ public:
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m_has_coinlock = false;
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}
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DECLARE_READ16_MEMBER(mcu_data_r);
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DECLARE_READ16_MEMBER(mcu_ack_r);
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DECLARE_WRITE16_MEMBER(mcu_data_w);
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DECLARE_WRITE16_MEMBER(mcu_cmd_w);
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DECLARE_READ16_MEMBER(mcu_comm_r);
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DECLARE_WRITE16_MEMBER(mcu_comm_w);
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DECLARE_WRITE8_MEMBER(mcu_pa_w);
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DECLARE_WRITE8_MEMBER(mcu_pb_w);
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@ -95,7 +94,7 @@ protected:
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required_device<m68705u_device> m_mcu;
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bool m_mcu_semaphore;
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bool m_host_semaphore, m_mcu_semaphore;
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u16 m_host_latch, m_mcu_latch;
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u16 m_mcu_output;
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u8 m_mcu_latch_ctl;
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@ -107,9 +106,8 @@ class bballs_state : public tigeroad_state
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public:
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bballs_state(const machine_config &mconfig, device_type type, const char *tag)
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: tigeroad_state(mconfig, type, tag)
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, m_shared_ram{ 0, 0, 0, 0, 0, 0, 0, 0 }
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, m_latch(0xffff)
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, m_new_latch(0)
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, m_mcu_semaphore(false)
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, m_mcu_latch(0xffff)
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{
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m_has_coinlock = false;
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}
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@ -118,12 +116,10 @@ public:
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DECLARE_WRITE16_MEMBER(bballs_68705_w);
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DECLARE_MACHINE_RESET(bballs);
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DECLARE_DRIVER_INIT(bballs);
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protected:
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virtual void machine_start() override;
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u8 m_shared_ram[8];
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u16 m_latch;
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u16 m_new_latch;
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bool m_mcu_semaphore;
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u16 m_mcu_latch;
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};
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@ -124,35 +124,38 @@ WRITE16_MEMBER(tigeroad_state::f1dream_control_w)
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}
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READ16_MEMBER(pushman_state::mcu_data_r)
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READ16_MEMBER(pushman_state::mcu_comm_r)
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{
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return m_mcu_latch;
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}
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READ16_MEMBER(pushman_state::mcu_ack_r)
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{
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if (m_mcu_semaphore)
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switch (offset & 0x03)
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{
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m_mcu_semaphore = false;
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return 0x0000;
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case 0: // read and acknowledge MCU reply
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if (!space.debugger_access())
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m_mcu_semaphore = false;
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return m_mcu_latch;
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case 2: // expects bit 0 to be high when MCU has accepted command (other bits ignored)
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return m_host_semaphore ? 0x0000 : 0x0001;
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case 3: // expects bit 0 to be low when MCU has sent response (other bits ignored)
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return m_mcu_semaphore ? 0x0000 : 0x0001;
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}
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else
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logerror("unknown MCU read offset %X & %04X\n", offset, mem_mask);
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return 0x0000;
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}
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WRITE16_MEMBER(pushman_state::mcu_comm_w)
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{
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switch (offset & 0x01)
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{
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return 0x00ff;
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case 0:
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COMBINE_DATA(&m_host_latch);
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break;
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case 1:
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m_mcu->pd_w(space, 0, data & 0x00ff);
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m_host_semaphore = true;
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m_mcu->set_input_line(M68705_IRQ_LINE, ASSERT_LINE);
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break;
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}
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}
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WRITE16_MEMBER(pushman_state::mcu_data_w)
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{
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COMBINE_DATA(&m_host_latch);
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}
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WRITE16_MEMBER(pushman_state::mcu_cmd_w)
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{
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m_mcu->pd_w(space, 0, data & 0x00ff);
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m_mcu->set_input_line(M68705_IRQ_LINE, ASSERT_LINE);
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}
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WRITE8_MEMBER(pushman_state::mcu_pa_w)
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{
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m_mcu_output = (m_mcu_output & 0xff00) | (u16(data) & 0x00ff);
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@ -172,6 +175,7 @@ WRITE8_MEMBER(pushman_state::mcu_pc_w)
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}
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else
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{
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m_host_semaphore = false;
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m_mcu->set_input_line(M68705_IRQ_LINE, CLEAR_LINE);
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m_mcu->pa_w(space, 0, (m_host_latch >> 8) & 0x00ff);
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m_mcu->pb_w(space, 0, (m_host_latch >> 0) & 0x00ff);
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@ -190,41 +194,35 @@ WRITE8_MEMBER(pushman_state::mcu_pc_w)
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/* ElSemi - Bouncing balls protection. */
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READ16_MEMBER(bballs_state::bballs_68705_r)
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{
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if (offset == 0)
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return m_latch;
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if (offset == 3 && m_new_latch)
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switch (offset)
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{
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m_new_latch = 0;
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return 0;
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case 0: // read and acknowledge MCU reply
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if (!space.debugger_access())
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m_mcu_semaphore = false;
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return m_mcu_latch;
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case 2: // pretend MCU accepts command instantly
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return 0x0001;
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case 3: // expects bit 0 to be low when MCU has sent response (other bits ignored)
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return m_mcu_semaphore ? 0x0000 : 0x0001;
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}
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if (offset == 3 && !m_new_latch)
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return 0xff;
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return (m_shared_ram[2 * offset + 1] << 8) + m_shared_ram[2 * offset];
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logerror("unknown 68705 read offset %X & %04X\n", offset, mem_mask);
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return 0x0000;
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}
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WRITE16_MEMBER(bballs_state::bballs_68705_w)
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{
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if (ACCESSING_BITS_8_15)
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m_shared_ram[2 * offset] = data >> 8;
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if (ACCESSING_BITS_0_7)
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m_shared_ram[2 * offset + 1] = data & 0xff;
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if (offset == 0)
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m_mcu_latch = 0;
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if ((data >> 8) <= 0x0f)
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{
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m_latch = 0;
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if (m_shared_ram[0] <= 0xf)
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{
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m_latch = m_shared_ram[0] << 2;
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if (m_shared_ram[1])
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m_latch |= 2;
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m_new_latch = 1;
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}
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else if (m_shared_ram[0])
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{
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if (m_shared_ram[1])
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m_latch |= 2;
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m_new_latch = 1;
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}
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m_mcu_latch = (data >> 6) & 0x03fc;
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if (data & 0x00ff)
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m_mcu_latch |= 2;
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m_mcu_semaphore = true;
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}
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else if (data >> 8)
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{
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if (data & 0x00ff)
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m_mcu_latch |= 2;
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m_mcu_semaphore = true;
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}
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}
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