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mips1: missed this (nw)

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Make sure the exception target address isn't incremented.
This commit is contained in:
Patrick Mackinlay 2018-12-18 21:04:07 +07:00
parent a7f0f6e027
commit a3f7b2a415
2 changed files with 9 additions and 4 deletions
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6
src/devices/cpu/mips/mips1.cpp
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@ -284,7 +284,7 @@ void mips1core_device_base::generate_exception(int exception)
m_cpr[0][COP0_EPC] -= 4;
CAUSE |= 0x80000000;
}
m_branch_state = NONE;
m_branch_state = EXCEPTION;
// shift the exception bits
SR = (SR & 0xffffffc0) | ((SR << 2) & 0x3c);
@ -789,6 +789,10 @@ void mips1core_device_base::execute_run()
m_branch_state = DELAY;
m_pc += 4;
break;
case EXCEPTION:
m_branch_state = NONE;
break;
}
});
m_icount--;

7
src/devices/cpu/mips/mips1.h
View File

@ -225,9 +225,10 @@ protected:
int m_icount;
enum branch_state_t : unsigned
{
NONE = 0,
DELAY = 1, // delay slot instruction active
BRANCH = 2, // branch instruction active
NONE = 0,
DELAY = 1, // delay slot instruction active
BRANCH = 2, // branch instruction active
EXCEPTION = 3, // exception triggered
}
m_branch_state;
u32 m_branch_target;