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tms57002: Modernize [O. Galibert]

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This commit is contained in:
Olivier Galibert 2012-03-09 18:50:18 +00:00
parent 3dba40f47a
commit a41b3c3898
10 changed files with 830 additions and 1012 deletions
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1
.gitattributes vendored
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@ -532,7 +532,6 @@ src/emu/cpu/tms57002/57002dsm.c svneol=native#text/plain
src/emu/cpu/tms57002/tms57002.c svneol=native#text/plain src/emu/cpu/tms57002/tms57002.c svneol=native#text/plain
src/emu/cpu/tms57002/tms57002.h svneol=native#text/plain src/emu/cpu/tms57002/tms57002.h svneol=native#text/plain
src/emu/cpu/tms57002/tms57kdec.c svneol=native#text/plain src/emu/cpu/tms57002/tms57kdec.c svneol=native#text/plain
src/emu/cpu/tms57002/tms57kpr.h svneol=native#text/plain
src/emu/cpu/tms57002/tmsinstr.lst svneol=native#text/plain src/emu/cpu/tms57002/tmsinstr.lst svneol=native#text/plain
src/emu/cpu/tms57002/tmsmake.c svneol=native#text/plain src/emu/cpu/tms57002/tmsmake.c svneol=native#text/plain
src/emu/cpu/tms7000/7000dasm.c svneol=native#text/plain src/emu/cpu/tms7000/7000dasm.c svneol=native#text/plain

2
src/emu/cpu/cpu.mak
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@ -1712,12 +1712,10 @@ endif
$(CPUOBJ)/tms57002/tms57002.o: $(CPUSRC)/tms57002/tms57002.c \ $(CPUOBJ)/tms57002/tms57002.o: $(CPUSRC)/tms57002/tms57002.c \
$(CPUSRC)/tms57002/tms57002.h \ $(CPUSRC)/tms57002/tms57002.h \
$(CPUSRC)/tms57002/tms57kpr.h \
$(CPUOBJ)/tms57002/tms57002.inc $(CPUOBJ)/tms57002/tms57002.inc
$(CPUOBJ)/tms57002/tms57kdec.o: $(CPUSRC)/tms57002/tms57kdec.c \ $(CPUOBJ)/tms57002/tms57kdec.o: $(CPUSRC)/tms57002/tms57kdec.c \
$(CPUSRC)/tms57002/tms57002.h \ $(CPUSRC)/tms57002/tms57002.h \
$(CPUSRC)/tms57002/tms57kpr.h \
$(CPUOBJ)/tms57002/tms57002.inc $(CPUOBJ)/tms57002/tms57002.inc
$(CPUOBJ)/tms57002/57002dsm.o: $(CPUSRC)/tms57002/57002dsm.c \ $(CPUOBJ)/tms57002/57002dsm.o: $(CPUSRC)/tms57002/57002dsm.c \

19
src/emu/cpu/tms57002/57002dsm.c
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@ -2,13 +2,7 @@
#include "debugger.h" #include "debugger.h"
#include "tms57002.h" #include "tms57002.h"
#ifdef __GNUC__ const char *tms57002_device::get_memadr(UINT32 opcode, char type)
#define noinline __attribute__((noinline))
#else
#define noinline /* */
#endif
static const char *tms57002_get_memadr(UINT32 opcode, char type)
{ {
static char buff[2][10]; static char buff[2][10];
static int index = 0; static int index = 0;
@ -31,8 +25,17 @@ static const char *tms57002_get_memadr(UINT32 opcode, char type)
return buf; return buf;
} }
UINT32 tms57002_device::disasm_min_opcode_bytes() const
{
return 4;
}
CPU_DISASSEMBLE(tms57002) UINT32 tms57002_device::disasm_max_opcode_bytes() const
{
return 4;
}
offs_t tms57002_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
{ {
UINT32 opcode = opram[0] | (opram[1] << 8) | (opram[2] << 16); UINT32 opcode = opram[0] | (opram[1] << 8) | (opram[2] << 16);
UINT8 fa = opcode >> 18; UINT8 fa = opcode >> 18;

967
src/emu/cpu/tms57002/tms57002.c
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File diff suppressed because it is too large Load Diff

221
src/emu/cpu/tms57002/tms57002.h
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@ -1,24 +1,223 @@
/***************************************************************************
asap.h
TMS57002 "DASP" emulator.
****************************************************************************
Copyright Olivier Galibert
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name 'MAME' nor the names of its contributors may be
used to endorse or promote products derived from this software
without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY AARON GILES ''AS IS'' AND ANY EXPRESS OR
IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL AARON GILES BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
***************************************************************************/
#pragma once #pragma once
#ifndef __TMS57002_H__ #ifndef __TMS57002_H__
#define __TMS57002_H__ #define __TMS57002_H__
class tms57002_device : public cpu_device {
public:
tms57002_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
DECLARE_READ8_MEMBER(data_r);
DECLARE_WRITE8_MEMBER(data_w);
DECLARE_WRITE8_MEMBER(pload_w);
DECLARE_WRITE8_MEMBER(cload_w);
DECLARE_READ8_MEMBER(empty_r);
DECLARE_READ8_MEMBER(dready_r);
void sync();
protected:
virtual void device_start();
virtual void device_reset();
virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const;
virtual UINT32 execute_min_cycles() const;
virtual UINT32 execute_max_cycles() const;
virtual UINT32 execute_input_lines() const;
virtual void execute_run();
virtual UINT32 disasm_min_opcode_bytes() const;
virtual UINT32 disasm_max_opcode_bytes() const;
virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
private:
enum {
IN_PLOAD = 0x00000001,
IN_CLOAD = 0x00000002,
SU_CVAL = 0x00000004,
SU_MASK = 0x00000018, SU_ST0 = 0x00, SU_ST1 = 0x08, SU_PRG = 0x10,
S_IDLE = 0x00000020,
S_READ = 0x00000040,
S_WRITE = 0x00000080,
S_BRANCH = 0x00000100,
S_HOST = 0x00000200
};
enum {
ST0_INCS = 0x000001,
ST0_DIRI = 0x000002,
ST0_FI = 0x000004,
ST0_SIM = 0x000008,
ST0_PLRI = 0x000020,
ST0_PBCI = 0x000040,
ST0_DIRO = 0x000080,
ST0_FO = 0x000100,
ST0_SOM = 0x000600,
ST0_PLRO = 0x000800,
ST0_PBCO = 0x001000,
ST0_CNS = 0x002000,
ST0_WORD = 0x004000,
ST0_SEL = 0x008000,
ST0_M = 0x030000, ST0_M_64K = 0x000000, ST0_M_256K = 0x010000, ST0_M_1M = 0x020000,
ST0_SRAM = 0x200000,
ST1_AOV = 0x000001,
ST1_SFAI = 0x000002,
ST1_SFAO = 0x000004,
ST1_MOVM = 0x000020,
ST1_MOV = 0x000040,
ST1_SFMA = 0x000180, ST1_SFMA_SHIFT = 7,
ST1_SFMO = 0x001800, ST1_SFMO_SHIFT = 11,
ST1_RND = 0x038000, ST1_RND_SHIFT = 15,
ST1_CRM = 0x0C0000, ST1_CRM_SHIFT = 18, ST1_CRM_32 = 0x000000, ST1_CRM_16H = 0x040000, ST1_CRM_16L = 0x080000,
ST1_DBP = 0x100000,
ST1_CAS = 0x200000,
ST1_CACHE = ST1_SFAI|ST1_SFAO|ST1_MOVM|ST1_SFMA|ST1_SFMO|ST1_RND|ST1_CRM|ST1_DBP
};
enum { BR_UB, BR_CB, BR_IDLE };
enum { IBS = 8192, HBS = 4096 };
struct icd {
unsigned short op;
short next;
unsigned char param;
};
struct hcd {
unsigned int st1;
short ipc;
short next;
};
struct cd {
short hashbase[256];
hcd hashnode[HBS];
icd inst[IBS];
int hused, iused;
};
struct cstate {
int branch;
short hnode;
short ipc;
};
INT64 macc;
UINT32 cmem[256];
UINT32 dmem0[256];
UINT32 dmem1[32];
UINT32 si[4], so[4];
UINT32 st0, st1, sti;
UINT32 aacc, xoa, xba, xwr, xrd, creg;
UINT8 pc, ca, id, ba0, ba1, rptc, rptc_next, sa;
UINT32 xm_adr;
UINT8 host[4], hidx, allow_update;
cd cache;
const address_space_config program_config, data_config;
address_space *program, *data;
int icount;
int unsupported_inst_warning;
void decode_error(UINT32 opcode);
void decode_cat1(UINT32 opcode, unsigned short *op, cstate *cs);
void decode_cat2_pre(UINT32 opcode, unsigned short *op, cstate *cs);
void decode_cat3(UINT32 opcode, unsigned short *op, cstate *cs);
void decode_cat2_post(UINT32 opcode, unsigned short *op, cstate *cs);
inline int xmode(UINT32 opcode, char type);
inline int sfao(UINT32 st1);
inline int dbp(UINT32 st1);
inline int crm(UINT32 st1);
inline int sfai(UINT32 st1);
inline int sfmo(UINT32 st1);
inline int rnd(UINT32 st1);
inline int movm(UINT32 st1);
inline int sfma(UINT32 st1);
const char *get_memadr(UINT32 opcode, char type);
void xm_init();
void xm_step_read();
void xm_step_write();
INT64 macc_to_output_0(INT64 rounding, UINT64 rmask);
INT64 macc_to_output_1(INT64 rounding, UINT64 rmask);
INT64 macc_to_output_2(INT64 rounding, UINT64 rmask);
INT64 macc_to_output_3(INT64 rounding, UINT64 rmask);
INT64 macc_to_output_0s(INT64 rounding, UINT64 rmask);
INT64 macc_to_output_1s(INT64 rounding, UINT64 rmask);
INT64 macc_to_output_2s(INT64 rounding, UINT64 rmask);
INT64 macc_to_output_3s(INT64 rounding, UINT64 rmask);
INT64 check_macc_overflow_0();
INT64 check_macc_overflow_1();
INT64 check_macc_overflow_2();
INT64 check_macc_overflow_3();
INT64 check_macc_overflow_0s();
INT64 check_macc_overflow_1s();
INT64 check_macc_overflow_2s();
INT64 check_macc_overflow_3s();
void cache_flush();
void add_one(cstate *cs, unsigned short op, UINT8 param);
void decode_one(UINT32 opcode, cstate *cs, void (tms57002_device::*dec)(UINT32 opcode, unsigned short *op, cstate *cs));
short get_hash(unsigned char adr, UINT32 st1, short *pnode);
short get_hashnode(unsigned char adr, UINT32 st1, short pnode);
int decode_get_pc();
};
enum { enum {
TMS57002_PC=1 TMS57002_PC=1
}; };
DECLARE_LEGACY_CPU_DEVICE(TMS57002, tms57002); extern const device_type TMS57002;
WRITE8_DEVICE_HANDLER(tms57002_data_w);
READ8_DEVICE_HANDLER(tms57002_data_r);
WRITE8_DEVICE_HANDLER(tms57002_pload_w);
WRITE8_DEVICE_HANDLER(tms57002_cload_w);
READ8_DEVICE_HANDLER(tms57002_empty_r);
READ8_DEVICE_HANDLER(tms57002_dready_r);
void tms57002_sync(device_t *cpu);
#endif #endif

123
src/emu/cpu/tms57002/tms57kdec.c
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@ -1,31 +1,118 @@
/***************************************************************************
asap.h
TMS57002 "DASP" emulator.
****************************************************************************
Copyright Olivier Galibert
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name 'MAME' nor the names of its contributors may be
used to endorse or promote products derived from this software
without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY AARON GILES ''AS IS'' AND ANY EXPRESS OR
IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL AARON GILES BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
***************************************************************************/
#include "emu.h" #include "emu.h"
#include "debugger.h" #include "debugger.h"
#include "tms57002.h" #include "tms57002.h"
#include "tms57kpr.h"
#ifdef __GNUC__ inline int tms57002_device::xmode(UINT32 opcode, char type)
#define noinline __attribute__((noinline)) {
#else if(((opcode & 0x400) && (type == 'c')) || (!(opcode & 0x400) && (type == 'd'))) {
#define noinline /* */ if(opcode & 0x100)
#endif return 0;
else if(opcode & 0x80)
return 2;
else
return 1;
} else if(opcode & 0x200)
return 2;
static void tms57002_decode_error(tms57002_t *s, UINT32 opcode) return 1;
}
inline int tms57002_device::sfao(UINT32 st1)
{
return st1 & ST1_SFAO ? 1 : 0;
}
inline int tms57002_device::dbp(UINT32 st1)
{
return st1 & ST1_DBP ? 1 : 0;
}
inline int tms57002_device::crm(UINT32 st1)
{
return (st1 & ST1_CRM) >> ST1_CRM_SHIFT;
}
inline int tms57002_device::sfai(UINT32 st1)
{
return st1 & ST1_SFAI ? 1 : 0;
}
inline int tms57002_device::sfmo(UINT32 st1)
{
return (st1 & ST1_SFMO) >> ST1_SFMO_SHIFT;
}
inline int tms57002_device::rnd(UINT32 st1)
{
return (st1 & ST1_RND) >> ST1_RND_SHIFT;
}
inline int tms57002_device::movm(UINT32 st1)
{
return st1 & ST1_MOVM ? 1 : 0;
}
inline int tms57002_device::sfma(UINT32 st1)
{
return (st1 & ST1_SFMA) >> ST1_SFMA_SHIFT;
}
void tms57002_device::decode_error(UINT32 opcode)
{ {
char buf[256]; char buf[256];
UINT8 opr[3]; UINT8 opr[3];
if(s->unsupported_inst_warning) if(unsupported_inst_warning)
return; return;
s->unsupported_inst_warning = 1; unsupported_inst_warning = 1;
opr[0] = opcode; opr[0] = opcode;
opr[1] = opcode >> 8; opr[1] = opcode >> 8;
opr[2] = opcode >> 16; opr[2] = opcode >> 16;
CPU_DISASSEMBLE_NAME(tms57002)(0, buf, s->pc, opr, opr, 0); // CPU_DECODEEMBLE_NAME(tms57002)(0, buf, s->pc, opr, opr, 0);
popmessage("tms57002: %s - Contact Mamedev", buf); popmessage("tms57002: %s - Contact Mamedev", buf);
} }
void tms57002_decode_cat1(tms57002_t *s, UINT32 opcode, unsigned short *op, cstate *cs) void tms57002_device::decode_cat1(UINT32 opcode, unsigned short *op, cstate *cs)
{ {
switch(opcode >> 18) { switch(opcode >> 18) {
case 0x00: // nop case 0x00: // nop
@ -36,12 +123,12 @@ void tms57002_decode_cat1(tms57002_t *s, UINT32 opcode, unsigned short *op, csta
#undef CDEC1 #undef CDEC1
default: default:
tms57002_decode_error(s, opcode); decode_error(opcode);
break; break;
} }
} }
void tms57002_decode_cat2_pre(tms57002_t *s, UINT32 opcode, unsigned short *op, cstate *cs) void tms57002_device::decode_cat2_pre(UINT32 opcode, unsigned short *op, cstate *cs)
{ {
switch((opcode >> 11) & 0x7f) { switch((opcode >> 11) & 0x7f) {
case 0x00: // nop case 0x00: // nop
@ -52,12 +139,12 @@ void tms57002_decode_cat2_pre(tms57002_t *s, UINT32 opcode, unsigned short *op,
#undef CDEC2A #undef CDEC2A
default: default:
tms57002_decode_error(s, opcode); decode_error(opcode);
break; break;
} }
} }
void tms57002_decode_cat2_post(tms57002_t *s, UINT32 opcode, unsigned short *op, cstate *cs) void tms57002_device::decode_cat2_post(UINT32 opcode, unsigned short *op, cstate *cs)
{ {
switch((opcode >> 11) & 0x7f) { switch((opcode >> 11) & 0x7f) {
case 0x00: // nop case 0x00: // nop
@ -68,12 +155,12 @@ void tms57002_decode_cat2_post(tms57002_t *s, UINT32 opcode, unsigned short *op,
#undef CDEC2B #undef CDEC2B
default: default:
tms57002_decode_error(s, opcode); decode_error(opcode);
break; break;
} }
} }
void tms57002_decode_cat3(tms57002_t *s, UINT32 opcode, unsigned short *op, cstate *cs) void tms57002_device::decode_cat3(UINT32 opcode, unsigned short *op, cstate *cs)
{ {
switch((opcode >> 11) & 0x7f) { switch((opcode >> 11) & 0x7f) {
case 0x00: // nop case 0x00: // nop
@ -84,7 +171,7 @@ void tms57002_decode_cat3(tms57002_t *s, UINT32 opcode, unsigned short *op, csta
#undef CDEC3 #undef CDEC3
default: default:
tms57002_decode_error(s, opcode); decode_error(opcode);
break; break;
} }
} }

171
src/emu/cpu/tms57002/tms57kpr.h
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@ -1,171 +0,0 @@
#ifndef TMS57KPRIVATE_H
#define TMS57KPRIVATE_H
CPU_DISASSEMBLE(tms57002);
#ifdef __GNUC__
#define noinline __attribute__((noinline))
#else
#define noinline /* */
#endif
enum {
IN_PLOAD = 0x00000001,
IN_CLOAD = 0x00000002,
SU_CVAL = 0x00000004,
SU_MASK = 0x00000018, SU_ST0 = 0x00, SU_ST1 = 0x08, SU_PRG = 0x10,
S_IDLE = 0x00000020,
S_READ = 0x00000040,
S_WRITE = 0x00000080,
S_BRANCH = 0x00000100,
S_HOST = 0x00000200
};
enum {
ST0_INCS = 0x000001,
ST0_DIRI = 0x000002,
ST0_FI = 0x000004,
ST0_SIM = 0x000008,
ST0_PLRI = 0x000020,
ST0_PBCI = 0x000040,
ST0_DIRO = 0x000080,
ST0_FO = 0x000100,
ST0_SOM = 0x000600,
ST0_PLRO = 0x000800,
ST0_PBCO = 0x001000,
ST0_CNS = 0x002000,
ST0_WORD = 0x004000,
ST0_SEL = 0x008000,
ST0_M = 0x030000, ST0_M_64K = 0x000000, ST0_M_256K = 0x010000, ST0_M_1M = 0x020000,
ST0_SRAM = 0x200000,
ST1_AOV = 0x000001,
ST1_SFAI = 0x000002,
ST1_SFAO = 0x000004,
ST1_MOVM = 0x000020,
ST1_MOV = 0x000040,
ST1_SFMA = 0x000180, ST1_SFMA_SHIFT = 7,
ST1_SFMO = 0x001800, ST1_SFMO_SHIFT = 11,
ST1_RND = 0x038000, ST1_RND_SHIFT = 15,
ST1_CRM = 0x0C0000, ST1_CRM_SHIFT = 18, ST1_CRM_32 = 0x000000, ST1_CRM_16H = 0x040000, ST1_CRM_16L = 0x080000,
ST1_DBP = 0x100000,
ST1_CAS = 0x200000,
ST1_CACHE = ST1_SFAI|ST1_SFAO|ST1_MOVM|ST1_SFMA|ST1_SFMO|ST1_RND|ST1_CRM|ST1_DBP
};
enum { BR_UB, BR_CB, BR_IDLE };
enum { IBS = 8192, HBS = 4096 };
typedef struct {
unsigned short op;
short next;
unsigned char param;
} icd;
typedef struct {
unsigned int st1;
short ipc;
short next;
} hcd;
typedef struct {
short hashbase[256];
hcd hashnode[HBS];
icd inst[IBS];
int hused, iused;
} cd;
typedef struct {
int branch;
short hnode;
short ipc;
} cstate;
typedef struct {
INT64 macc;
UINT32 cmem[256];
UINT32 dmem0[256];
UINT32 dmem1[32];
UINT32 si[4], so[4];
UINT32 st0, st1, sti;
UINT32 aacc, xoa, xba, xwr, xrd, creg;
UINT8 pc, ca, id, ba0, ba1, rptc, rptc_next, sa;
UINT32 xm_adr;
UINT8 host[4], hidx, allow_update;
cd cache;
address_space *program, *data;
int icount;
int unsupported_inst_warning;
} tms57002_t;
void tms57002_decode_cat1(tms57002_t *s, UINT32 opcode, unsigned short *op, cstate *cs);
void tms57002_decode_cat2_pre(tms57002_t *s, UINT32 opcode, unsigned short *op, cstate *cs);
void tms57002_decode_cat3(tms57002_t *s, UINT32 opcode, unsigned short *op, cstate *cs);
void tms57002_decode_cat2_post(tms57002_t *s, UINT32 opcode, unsigned short *op, cstate *cs);
INLINE int xmode(UINT32 opcode, char type)
{
if(((opcode & 0x400) && (type == 'c')) || (!(opcode & 0x400) && (type == 'd'))) {
if(opcode & 0x100)
return 0;
else if(opcode & 0x80)
return 2;
else
return 1;
} else if(opcode & 0x200)
return 2;
return 1;
}
INLINE int sfao(UINT32 st1)
{
return st1 & ST1_SFAO ? 1 : 0;
}
INLINE int dbp(UINT32 st1)
{
return st1 & ST1_DBP ? 1 : 0;
}
INLINE int crm(UINT32 st1)
{
return (st1 & ST1_CRM) >> ST1_CRM_SHIFT;
}
INLINE int sfai(UINT32 st1)
{
return st1 & ST1_SFAI ? 1 : 0;
}
INLINE int sfmo(UINT32 st1)
{
return (st1 & ST1_SFMO) >> ST1_SFMO_SHIFT;
}
INLINE int rnd(UINT32 st1)
{
return (st1 & ST1_RND) >> ST1_RND_SHIFT;
}
INLINE int movm(UINT32 st1)
{
return st1 & ST1_MOVM ? 1 : 0;
}
INLINE int sfma(UINT32 st1)
{
return (st1 & ST1_SFMA) >> ST1_SFMA_SHIFT;
}
#endif

200
src/emu/cpu/tms57002/tmsinstr.lst
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@ -1,10 +1,10 @@
abs 1 01 1 n abs 1 01 1 n
abs abs
s->aacc = %a; aacc = %a;
if(((INT32)s->aacc) < 0) { if(((INT32)aacc) < 0) {
s->aacc = - s->aacc; aacc = - aacc;
if(((INT32)s->aacc) < 0) if(((INT32)aacc) < 0)
s->st1 |= ST1_AOV; st1 |= ST1_AOV;
} }
add 1 03 1 y add 1 03 1 y
@ -40,16 +40,16 @@ ampy 1 2c 2 y
and 1 14 1 n and 1 14 1 n
and %d,a and %d,a
%sfai(d, %d); %sfai(d, %d);
s->aacc &= d; aacc &= d;
and 1 15 1 n and 1 15 1 n
and %c,a and %c,a
s->aacc &= %c; aacc &= %c;
and 1 16 1 n and 1 16 1 n
and %d,%c and %d,%c
%sfai(d, %d); %sfai(d, %d);
s->aacc = %c & d; aacc = %c & d;
b 3 48 3 n b b 3 48 3 n b
b %i b %i
@ -57,7 +57,7 @@ b 3 48 3 n b
bgz 3 50 3 n cb bgz 3 50 3 n cb
bgz %i bgz %i
if(((INT32)s->aacc) > 0) { if(((INT32)aacc) > 0) {
%b(%i); %b(%i);
} }
@ -66,20 +66,20 @@ bioz 3 70 3 n cb
blz 3 58 3 n cb blz 3 58 3 n cb
blz %i blz %i
if(((INT32)s->aacc) < 0) { if(((INT32)aacc) < 0) {
%b(%i); %b(%i);
} }
bnz 3 60 3 n cb bnz 3 60 3 n cb
bnz %i bnz %i
if(s->aacc) { if(aacc) {
%b(%i); %b(%i);
} }
bv 3 78 3 n cb bv 3 78 3 n cb
bv %i bv %i
if(s->st1 & ST1_AOV) { if(st1 & ST1_AOV) {
s->st1 &= ~ST1_AOV; st1 &= ~ST1_AOV;
%b(%i); %b(%i);
} }
@ -112,35 +112,35 @@ diml 2a 1b 1 n
dis 2a 10 1 n dis 2a 10 1 n
dis si0_l,%d dis si0_l,%d
%wd(s->si[0]); %wd(si[0]);
dis 2a 11 1 n dis 2a 11 1 n
dis si0_r,%d dis si0_r,%d
%wd(s->si[1]); %wd(si[1]);
dis 2a 12 1 n dis 2a 12 1 n
dis si1_l,%d dis si1_l,%d
%wd(s->si[2]); %wd(si[2]);
dis 2a 13 1 n dis 2a 13 1 n
dis si1_r,%d dis si1_r,%d
%wd(s->si[3]); %wd(si[3]);
domh 2a 20 1 n domh 2a 20 1 n
domh so0_l domh so0_l
s->so[0] = (%mo >> 24) & 0xffffff; so[0] = (%mo >> 24) & 0xffffff;
domh 2a 21 1 n domh 2a 21 1 n
domh so0_r domh so0_r
s->so[1] = (%mo >> 24) & 0xffffff; so[1] = (%mo >> 24) & 0xffffff;
domh 2a 22 1 n domh 2a 22 1 n
domh so1_l domh so1_l
s->so[2] = (%mo >> 24) & 0xffffff; so[2] = (%mo >> 24) & 0xffffff;
domh 2a 23 1 n domh 2a 23 1 n
domh so1_r domh so1_r
s->so[3] = (%mo >> 24) & 0xffffff; so[3] = (%mo >> 24) & 0xffffff;
doml 2a 24 1 n doml 2a 24 1 n
doml so0_l doml so0_l
@ -168,78 +168,78 @@ dos 2b 1f 1 n
idle 3 08 1 n i idle 3 08 1 n i
idle idle
s->sti |= S_IDLE; sti |= S_IDLE;
incd 2a 42 1 y incd 2a 42 1 y
incd incd
lacc 1 12 1 n lacc 1 12 1 n
lacc %c lacc %c
s->aacc = %c; aacc = %c;
lacd 1 11 1 n lacd 1 11 1 n
lacd %d lacd %d
%sfai(d, %d); %sfai(d, %d);
s->aacc = d; aacc = d;
lbrk 3 28 1 n lbrk 3 28 1 n
lbrk %i lbrk %i
lcaa 2a 08 1 y lcaa 2a 08 1 y
lcaa lcaa
s->ca = %a >> 24; ca = %a >> 24;
lcac 3 40 1 n lcac 3 40 1 n
lcac %i lcac %i
if(((INT32)s->aacc) >= 0) if(((INT32)aacc) >= 0)
s->ca = %i; ca = %i;
lcak 3 18 1 n lcak 3 18 1 n
lcak %i lcak %i
s->ca = %i; ca = %i;
ldpk 2a 44 1 n f ldpk 2a 44 1 n f
ldpk 0 ldpk 0
s->st1 &= ~ST1_DBP; st1 &= ~ST1_DBP;
ldpk 2a 45 1 n f ldpk 2a 45 1 n f
ldpk 1 ldpk 1
s->st1 |= ST1_DBP; st1 |= ST1_DBP;
ld0t 2b 0c 1 y ld0t 2b 0c 1 y
ld0t %d ld0t %d
lira 2a 09 1 y lira 2a 09 1 y
lira lira
s->id = %a >> 24; id = %a >> 24;
lirk 3 20 1 n lirk 3 20 1 n
lirk %i lirk %i
s->id = %i; id = %i;
lmhc 1 33 1 n lmhc 1 33 1 n
lmhc %c lmhc %c
s->macc = ((INT64)(INT32)%c) << 16; macc = ((INT64)(INT32)%c) << 16;
lmhd 1 31 1 n lmhd 1 31 1 n
lmhd %d lmhd %d
s->macc = ((INT64)(INT32)%d) << 16; macc = ((INT64)(INT32)%d) << 16;
lmld 1 32 1 n lmld 1 32 1 n
lmld %d lmld %d
s->macc = (s->macc & ~0xffffffULL) | %d24; macc = (macc & ~0xffffffULL) | %d24;
lpc 2b 31 1 n lpc 2b 31 1 n
lpc %c lpc %c
if(s->sti & S_HOST) if(sti & S_HOST)
break; break;
c = %c; c = %c;
s->host[0] = c >> 24; host[0] = c >> 24;
s->host[1] = c >> 16; host[1] = c >> 16;
s->host[2] = c >> 8; host[2] = c >> 8;
s->host[3] = c; host[3] = c;
s->hidx = 0; hidx = 0;
s->sti |= S_HOST; sti |= S_HOST;
lpd 2b 30 1 n lpd 2b 30 1 n
lpd %d lpd %d
@ -249,63 +249,63 @@ mac 1 24 1 y
d = %d24; d = %d24;
if(d & 0x00800000) if(d & 0x00800000)
d |= 0xff000000; d |= 0xff000000;
s->creg = c = %c; creg = c = %c;
r = (INT64)(INT32)c * (INT64)(INT32)d; r = (INT64)(INT32)c * (INT64)(INT32)d;
s->macc = %ml + (r >> 7); macc = %ml + (r >> 7);
mac 1 25 1 y mac 1 25 1 y
mac a,%d mac a,%d
mac 1 26 1 y mac 1 26 1 y
mac %c,a mac %c,a
s->creg = c = %c; creg = c = %c;
r = (INT64)(INT32)c * (INT64)(INT32)%a; r = (INT64)(INT32)c * (INT64)(INT32)%a;
s->macc = %ml + (r >> 15); macc = %ml + (r >> 15);
macs 1 2e 1 y macs 1 2e 1 y
macs %c,a macs %c,a
s->creg = c = %c; creg = c = %c;
r = (INT64)(INT32)c * (INT64)(INT32)%a; r = (INT64)(INT32)c * (INT64)(INT32)%a;
s->macc = %ml + (r >> 14); macc = %ml + (r >> 14);
macu 1 29 1 y macu 1 29 1 y
macu %d,%c macu %d,%c
d = %d24; // d is 24bits unsigned d = %d24; // d is 24bits unsigned
s->creg = c = %c; creg = c = %c;
r = (INT64)(INT32)c * (INT64)d; r = (INT64)(INT32)c * (INT64)d;
s->macc = %ml + (r >> 7); macc = %ml + (r >> 7);
macu 1 2a 1 y macu 1 2a 1 y
macu a,%d macu a,%d
d = %d24; // d is 24bits unsigned d = %d24; // d is 24bits unsigned
s->creg = c = %a; creg = c = %a;
r = (INT64)(INT32)c * (INT64)d; r = (INT64)(INT32)c * (INT64)d;
s->macc = %ml + (r >> 7); macc = %ml + (r >> 7);
mpy 1 21 1 y mpy 1 21 1 y
mpy %d,%c mpy %d,%c
d = %d24; d = %d24;
if(d & 0x00800000) if(d & 0x00800000)
d |= 0xff000000; d |= 0xff000000;
s->creg = c = %c; creg = c = %c;
r = (INT64)(INT32)c * (INT64)(INT32)d; r = (INT64)(INT32)c * (INT64)(INT32)d;
s->macc = r >> 7; macc = r >> 7;
mpy 1 22 1 y mpy 1 22 1 y
mpy %c,a mpy %c,a
s->creg = c = %c; creg = c = %c;
r = (INT64)(INT32)c * (INT64)(INT32)%a; r = (INT64)(INT32)c * (INT64)(INT32)%a;
s->macc = r >> 15; macc = r >> 15;
mpy 1 23 1 y mpy 1 23 1 y
mpy creg,%d mpy creg,%d
mpyu 1 28 1 y mpyu 1 28 1 y
mpyu %d,%c mpyu %d,%c
s->creg = c = %c; creg = c = %c;
d = %d24; // d is 24bits unsigned d = %d24; // d is 24bits unsigned
r = (INT64)(INT32)c * (INT64)d; r = (INT64)(INT32)c * (INT64)d;
s->macc = r >> 7; macc = r >> 7;
neg 1 02 1 n neg 1 02 1 n
neg neg
@ -313,27 +313,27 @@ neg 1 02 1 n
or 1 17 1 n or 1 17 1 n
or %d,a or %d,a
%sfai(d, %d); %sfai(d, %d);
s->aacc |= d; aacc |= d;
or 1 18 1 n or 1 18 1 n
or %c,a or %c,a
s->aacc |= %c; aacc |= %c;
or 1 19 1 n or 1 19 1 n
or %d,%c or %d,%c
%sfai(d, %d); %sfai(d, %d);
s->aacc = %c | d; aacc = %c | d;
raov 2a 38 1 n raov 2a 38 1 n
raov raov
rde 1 39 1 n rde 1 39 1 n
rde %c rde %c
if(s->sti & (S_READ|S_WRITE)) if(sti & (S_READ|S_WRITE))
break; break;
s->xoa = %c; xoa = %c;
tms57002_xm_init(s); xm_init();
s->sti |= S_READ; sti |= S_READ;
ref 2a 0e 1 n ref 2a 0e 1 n
ref ref
@ -341,47 +341,47 @@ ref 2a 0e 1 n
rmom 2a 40 1 n f rmom 2a 40 1 n f
rmom rmom
s->st1 &= ~ST1_MOVM; st1 &= ~ST1_MOVM;
rmov 2a 3a 1 n rmov 2a 3a 1 n
rmov rmov
s->st1 &= ~ST1_MOV; st1 &= ~ST1_MOV;
rnd 2a 68 1 n f rnd 2a 68 1 n f
rnd 48 rnd 48
s->st1 = (s->st1 & ~ST1_RND) | (0 << ST1_RND_SHIFT); st1 = (st1 & ~ST1_RND) | (0 << ST1_RND_SHIFT);
rnd 2a 69 1 n f rnd 2a 69 1 n f
rnd 32 rnd 32
s->st1 = (s->st1 & ~ST1_RND) | (1 << ST1_RND_SHIFT); st1 = (st1 & ~ST1_RND) | (1 << ST1_RND_SHIFT);
rnd 2a 6a 1 n f rnd 2a 6a 1 n f
rnd 24 rnd 24
s->st1 = (s->st1 & ~ST1_RND) | (2 << ST1_RND_SHIFT); st1 = (st1 & ~ST1_RND) | (2 << ST1_RND_SHIFT);
rnd 2a 6b 1 n f rnd 2a 6b 1 n f
rnd 20 rnd 20
s->st1 = (s->st1 & ~ST1_RND) | (3 << ST1_RND_SHIFT); st1 = (st1 & ~ST1_RND) | (3 << ST1_RND_SHIFT);
rnd 2a 6c 1 n f rnd 2a 6c 1 n f
rnd 16 rnd 16
s->st1 = (s->st1 & ~ST1_RND) | (4 << ST1_RND_SHIFT); st1 = (st1 & ~ST1_RND) | (4 << ST1_RND_SHIFT);
rnd 2a 6d 1 n f rnd 2a 6d 1 n f
rnd <5> rnd <5>
s->st1 = (s->st1 & ~ST1_RND) | (5 << ST1_RND_SHIFT); st1 = (st1 & ~ST1_RND) | (5 << ST1_RND_SHIFT);
rnd 2a 6e 1 n f rnd 2a 6e 1 n f
rnd <6> rnd <6>
s->st1 = (s->st1 & ~ST1_RND) | (6 << ST1_RND_SHIFT); st1 = (st1 & ~ST1_RND) | (6 << ST1_RND_SHIFT);
rnd 2a 6f 1 n f rnd 2a 6f 1 n f
rnd <7> rnd <7>
s->st1 = (s->st1 & ~ST1_RND) | (7 << ST1_RND_SHIFT); st1 = (st1 & ~ST1_RND) | (7 << ST1_RND_SHIFT);
rptk 3 10 1 n rptk 3 10 1 n
rptk %i rptk %i
s->rptc_next = %i; rptc_next = %i;
sacc 2a 01 1 y sacc 2a 01 1 y
sacc %c sacc %c
@ -393,71 +393,71 @@ sacd 2a 02 1 y
scrm 2a 48 1 n f scrm 2a 48 1 n f
scrm 32 scrm 32
s->st1 = (s->st1 & ~ST1_CRM) | (0 << ST1_CRM_SHIFT); st1 = (st1 & ~ST1_CRM) | (0 << ST1_CRM_SHIFT);
scrm 2a 49 1 n f scrm 2a 49 1 n f
scrm 16h scrm 16h
s->st1 = (s->st1 & ~ST1_CRM) | (1 << ST1_CRM_SHIFT); st1 = (st1 & ~ST1_CRM) | (1 << ST1_CRM_SHIFT);
scrm 2a 4a 1 n f scrm 2a 4a 1 n f
scrm 16l scrm 16l
s->st1 = (s->st1 & ~ST1_CRM) | (2 << ST1_CRM_SHIFT); st1 = (st1 & ~ST1_CRM) | (2 << ST1_CRM_SHIFT);
scrm 2a 4b 1 n f scrm 2a 4b 1 n f
scrm <3> scrm <3>
s->st1 = (s->st1 & ~ST1_CRM) | (3 << ST1_CRM_SHIFT); st1 = (st1 & ~ST1_CRM) | (3 << ST1_CRM_SHIFT);
sfai 2b 54 1 n f sfai 2b 54 1 n f
sfai 0 sfai 0
s->st1 &= ~ST1_SFAI; st1 &= ~ST1_SFAI;
sfai 2b 55 1 n f sfai 2b 55 1 n f
sfai -1 sfai -1
s->st1 |= ST1_SFAI; st1 |= ST1_SFAI;
sfao 2a 50 1 n f sfao 2a 50 1 n f
sfao 0 sfao 0
s->st1 &= ~ST1_SFAO; st1 &= ~ST1_SFAO;
sfao 2a 51 1 n f sfao 2a 51 1 n f
sfao 7 sfao 7
s->st1 |= ST1_SFAI; st1 |= ST1_SFAI;
sfma 2b 58 1 n f sfma 2b 58 1 n f
sfma 0 sfma 0
s->st1 = (s->st1 & ~ST1_SFMA) | (0 << ST1_SFMA_SHIFT); st1 = (st1 & ~ST1_SFMA) | (0 << ST1_SFMA_SHIFT);
sfma 2b 59 1 n f sfma 2b 59 1 n f
sfma 2 sfma 2
s->st1 = (s->st1 & ~ST1_SFMA) | (1 << ST1_SFMA_SHIFT); st1 = (st1 & ~ST1_SFMA) | (1 << ST1_SFMA_SHIFT);
sfma 2b 5a 1 n f sfma 2b 5a 1 n f
sfma 4 sfma 4
s->st1 = (s->st1 & ~ST1_SFMA) | (2 << ST1_SFMA_SHIFT); st1 = (st1 & ~ST1_SFMA) | (2 << ST1_SFMA_SHIFT);
sfma 2b 5b 1 n f sfma 2b 5b 1 n f
sfma -16 sfma -16
s->st1 = (s->st1 & ~ST1_SFMA) | (3 << ST1_SFMA_SHIFT); st1 = (st1 & ~ST1_SFMA) | (3 << ST1_SFMA_SHIFT);
sfml 1 34 1 y sfml 1 34 1 y
sfml sfml
s->macc = (s->macc & 0x8000000000000ULL) | ((s->macc << 1) & 0x7ffffffffffffULL); macc = (macc & 0x8000000000000ULL) | ((macc << 1) & 0x7ffffffffffffULL);
sfmo 2a 60 1 n f sfmo 2a 60 1 n f
sfmo 0 sfmo 0
s->st1 = (s->st1 & ~ST1_SFMO) | (0 << ST1_SFMO_SHIFT); st1 = (st1 & ~ST1_SFMO) | (0 << ST1_SFMO_SHIFT);
sfmo 2a 61 1 n f sfmo 2a 61 1 n f
sfmo 2 sfmo 2
s->st1 = (s->st1 & ~ST1_SFMO) | (1 << ST1_SFMO_SHIFT); st1 = (st1 & ~ST1_SFMO) | (1 << ST1_SFMO_SHIFT);
sfmo 2a 62 1 n f sfmo 2a 62 1 n f
sfmo 4 sfmo 4
s->st1 = (s->st1 & ~ST1_SFMO) | (2 << ST1_SFMO_SHIFT); st1 = (st1 & ~ST1_SFMO) | (2 << ST1_SFMO_SHIFT);
sfmo 2a 63 1 n f sfmo 2a 63 1 n f
sfmo -8 sfmo -8
s->st1 = (s->st1 & ~ST1_SFMO) | (3 << ST1_SFMO_SHIFT); st1 = (st1 & ~ST1_SFMO) | (3 << ST1_SFMO_SHIFT);
sfmr 1 35 1 y sfmr 1 35 1 y
sfmr sfmr
@ -483,11 +483,11 @@ smld 2a 04 1 y
smom 2a 41 1 n f smom 2a 41 1 n f
smom smom
s->st1 |= ST1_MOVM; st1 |= ST1_MOVM;
srbd 2a 0f 1 y srbd 2a 0f 1 y
srbd %d srbd %d
%wd(s->xrd); %wd(xrd);
std1 2a 0d 1 y std1 2a 0d 1 y
std1 %d std1 %d
@ -512,12 +512,12 @@ sub 1 0d 1 y
wre 1 38 1 n wre 1 38 1 n
wre %d,%c wre %d,%c
if(s->sti & (S_READ|S_WRITE)) if(sti & (S_READ|S_WRITE))
break; break;
s->xwr = %d24; xwr = %d24;
s->xoa = %c; xoa = %c;
tms57002_xm_init(s); xm_init();
s->sti |= S_WRITE; sti |= S_WRITE;
xor 1 1a 1 n xor 1 1a 1 n
xor %d,a xor %d,a

124
src/emu/cpu/tms57002/tmsmake.c
View File

@ -86,14 +86,14 @@ enum { IxCMODE, IxDMODE, IxSFAI, IxCRM, IxDBP, IxSFAO, IxSFMO, IxRND, IxMOVM, Ix
static const vinfo vinf[] = { static const vinfo vinf[] = {
{ I_CMODE, 3, "cmode", "xmode(opcode, 'c')" }, { I_CMODE, 3, "cmode", "xmode(opcode, 'c')" },
{ I_DMODE, 3, "dmode", "xmode(opcode, 'd')" }, { I_DMODE, 3, "dmode", "xmode(opcode, 'd')" },
{ I_SFAI, 2, "sfai", "sfai(s->st1)" }, { I_SFAI, 2, "sfai", "sfai(st1)" },
{ I_CRM, 4, "crm", "crm(s->st1)" }, { I_CRM, 4, "crm", "crm(st1)" },
{ I_DBP, 2, "dbp", "dbp(s->st1)" }, { I_DBP, 2, "dbp", "dbp(st1)" },
{ I_SFAO, 2, "sfao", "sfao(s->st1)" }, { I_SFAO, 2, "sfao", "sfao(st1)" },
{ I_SFMO, 4, "sfmo", "sfmo(s->st1)" }, { I_SFMO, 4, "sfmo", "sfmo(st1)" },
{ I_RND, 8, "rnd", "rnd(s->st1)" }, { I_RND, 8, "rnd", "rnd(st1)" },
{ I_MOVM, 2, "movm", "movm(s->st1)" }, { I_MOVM, 2, "movm", "movm(st1)" },
{ I_SFMA, 4, "sfma", "sfma(s->st1)" }, { I_SFMA, 4, "sfma", "sfma(st1)" },
{ 0 } { 0 }
}; };
@ -453,10 +453,10 @@ static void save_dasm_cat(FILE *f, const char *def, instr *il, int count)
for(j=0; j != pc; j++) for(j=0; j != pc; j++)
switch(par[j]) { switch(par[j]) {
case PC: case PC:
fprintf(f, ", tms57002_get_memadr(opcode, 'c')"); fprintf(f, ", get_memadr(opcode, 'c')");
break; break;
case PD: case PD:
fprintf(f, ", tms57002_get_memadr(opcode, 'd')"); fprintf(f, ", get_memadr(opcode, 'd')");
break; break;
case PI: case PI:
fprintf(f, ", opcode & 0xff"); fprintf(f, ", opcode & 0xff");
@ -482,15 +482,15 @@ static void intrp_expand(char **p, int s, int e)
break; break;
case PA: case PA:
scs(p, "tms57002_aacc_to_output(s)"); scs(p, "aacc_to_output()");
break; break;
case PC: case PC:
scs(p, "tms57002_opc_read_c(s, opcode)"); scs(p, "opc_read_c(opcode)");
break; break;
case PD: case PD:
scs(p, "(tms57002_opc_read_d(s, opcode) << 8)"); scs(p, "(opc_read_d(opcode) << 8)");
break; break;
case PI: case PI:
@ -498,26 +498,26 @@ static void intrp_expand(char **p, int s, int e)
break; break;
case PD24: case PD24:
scs(p, "tms57002_opc_read_d(s, opcode)"); scs(p, "opc_read_d(opcode)");
break; break;
case PML: case PML:
scs(p, "tms57002_macc_to_loop(s)"); scs(p, "macc_to_loop()");
break; break;
case PMO: case PMO:
scs(p, "tms57002_macc_to_output(s)"); scs(p, "macc_to_output()");
break; break;
case PMV: case PMV:
scs(p, "tms57002_check_macc_overflow(s)"); scs(p, "check_macc_overflow()");
break; break;
case PB: case PB:
scs(p, "s->pc = "); scs(p, "pc = ");
intrp_expand(p, parse_res[i].ppos[0], parse_res[i].ppos[1]); intrp_expand(p, parse_res[i].ppos[0], parse_res[i].ppos[1]);
scs(p, ";\n"); scs(p, ";\n");
scs(p, " s->sti |= S_BRANCH"); scs(p, " sti |= S_BRANCH");
break; break;
case PWA: case PWA:
@ -525,18 +525,18 @@ static void intrp_expand(char **p, int s, int e)
intrp_expand(p, parse_res[i].ppos[0], parse_res[i].ppos[1]); intrp_expand(p, parse_res[i].ppos[0], parse_res[i].ppos[1]);
scs(p, ";\n"); scs(p, ";\n");
scs(p, " if(r < -0x80000000 || r > 0x7fffffff)\n"); scs(p, " if(r < -0x80000000 || r > 0x7fffffff)\n");
scs(p, " s->st1 |= ST1_AOV;\n"); scs(p, " st1 |= ST1_AOV;\n");
scs(p, " s->aacc = r"); scs(p, " aacc = r");
break; break;
case PWC: case PWC:
scs(p, "tms57002_opc_write_c(s, opcode, "); scs(p, "opc_write_c(opcode, ");
intrp_expand(p, parse_res[i].ppos[0], parse_res[i].ppos[1]); intrp_expand(p, parse_res[i].ppos[0], parse_res[i].ppos[1]);
scs(p, ")"); scs(p, ")");
break; break;
case PWD: case PWD:
scs(p, "tms57002_opc_write_d(s, opcode, "); scs(p, "opc_write_d(opcode, ");
intrp_expand(p, parse_res[i].ppos[0], parse_res[i].ppos[1]); intrp_expand(p, parse_res[i].ppos[0], parse_res[i].ppos[1]);
scs(p, ")"); scs(p, ")");
break; break;
@ -546,7 +546,7 @@ static void intrp_expand(char **p, int s, int e)
scs(p, " = "); scs(p, " = ");
intrp_expand(p, parse_res[i].ppos[1], parse_res[i].ppos[2]); intrp_expand(p, parse_res[i].ppos[1], parse_res[i].ppos[2]);
scs(p, ";\n"); scs(p, ";\n");
scs(p, " if(s->st1 & ST1_SFAI)\n"); scs(p, " if(st1 & ST1_SFAI)\n");
scs(p, " "); scs(p, " ");
intrp_expand(p, parse_res[i].ppos[0], parse_res[i].ppos[1]); intrp_expand(p, parse_res[i].ppos[0], parse_res[i].ppos[1]);
scs(p, " = ((INT32)"); scs(p, " = ((INT32)");
@ -636,19 +636,19 @@ static void cintrp_expand(char **p, int s, int e, const int *cv)
case PA: case PA:
if(cv[IxSFAO]) if(cv[IxSFAO])
scs(p, "(s->aacc << 7)"); scs(p, "(aacc << 7)");
else else
scs(p, "s->aacc"); scs(p, "aacc");
break; break;
case PC: { case PC: {
const char *r = NULL; const char *r = NULL;
if(cv[IxCMODE] == 0) if(cv[IxCMODE] == 0)
r = "s->cmem[i->param]"; r = "cmem[i->param]";
else if(cv[IxCMODE] == 1) else if(cv[IxCMODE] == 1)
r = "s->cmem[s->ca]"; r = "cmem[ca]";
else if(cv[IxCMODE] == 2) else if(cv[IxCMODE] == 2)
r = "s->cmem[s->ca++]"; r = "cmem[ca++]";
else else
abort(); abort();
@ -670,19 +670,19 @@ static void cintrp_expand(char **p, int s, int e, const int *cv)
case PD: case PD:
if(cv[IxDMODE] == 0) if(cv[IxDMODE] == 0)
if(cv[IxDBP]) if(cv[IxDBP])
scs(p, "(s->dmem1[(i->param + s->ba1) & 0x1f] << 8)"); scs(p, "(dmem1[(i->param + ba1) & 0x1f] << 8)");
else else
scs(p, "(s->dmem0[(i->param + s->ba0) & 0xff] << 8)"); scs(p, "(dmem0[(i->param + ba0) & 0xff] << 8)");
else if(cv[IxDMODE] == 1) else if(cv[IxDMODE] == 1)
if(cv[IxDBP]) if(cv[IxDBP])
scs(p, "(s->dmem1[(s->id + s->ba1) & 0x1f] << 8)"); scs(p, "(dmem1[(id + ba1) & 0x1f] << 8)");
else else
scs(p, "(s->dmem0[(s->id + s->ba0) & 0xff] << 8)"); scs(p, "(dmem0[(id + ba0) & 0xff] << 8)");
else if(cv[IxDMODE] == 2) else if(cv[IxDMODE] == 2)
if(cv[IxDBP]) if(cv[IxDBP])
scs(p, "(s->dmem1[((s->id++) + s->ba1) & 0x1f] << 8)"); scs(p, "(dmem1[((id++) + ba1) & 0x1f] << 8)");
else else
scs(p, "(s->dmem0[((s->id++) + s->ba0) & 0xff] << 8)"); scs(p, "(dmem0[((id++) + ba0) & 0xff] << 8)");
else else
abort(); abort();
break; break;
@ -694,32 +694,32 @@ static void cintrp_expand(char **p, int s, int e, const int *cv)
case PD24: case PD24:
if(cv[IxDMODE] == 0) if(cv[IxDMODE] == 0)
if(cv[IxDBP]) if(cv[IxDBP])
scs(p, "s->dmem1[(i->param + s->ba1) & 0x1f]"); scs(p, "dmem1[(i->param + ba1) & 0x1f]");
else else
scs(p, "s->dmem0[(i->param + s->ba0) & 0xff]"); scs(p, "dmem0[(i->param + ba0) & 0xff]");
else if(cv[IxDMODE] == 1) else if(cv[IxDMODE] == 1)
if(cv[IxDBP]) if(cv[IxDBP])
scs(p, "s->dmem1[(s->id + s->ba1) & 0x1f]"); scs(p, "dmem1[(id + ba1) & 0x1f]");
else else
scs(p, "s->dmem0[(s->id + s->ba0) & 0xff]"); scs(p, "dmem0[(id + ba0) & 0xff]");
else if(cv[IxDMODE] == 2) else if(cv[IxDMODE] == 2)
if(cv[IxDBP]) if(cv[IxDBP])
scs(p, "s->dmem1[((s->id++) + s->ba1) & 0x1f]"); scs(p, "dmem1[((id++) + ba1) & 0x1f]");
else else
scs(p, "s->dmem0[((s->id++) + s->ba0) & 0xff]"); scs(p, "dmem0[((id++) + ba0) & 0xff]");
else else
abort(); abort();
break; break;
case PML: case PML:
if(cv[IxSFMA] == 0) if(cv[IxSFMA] == 0)
scs(p, "s->macc"); scs(p, "macc");
else if(cv[IxSFMA] == 1) else if(cv[IxSFMA] == 1)
scs(p, "(s->macc << 2)"); scs(p, "(macc << 2)");
else if(cv[IxSFMA] == 2) else if(cv[IxSFMA] == 2)
scs(p, "(s->macc << 4)"); scs(p, "(macc << 4)");
else if(cv[IxSFMA] == 3) else if(cv[IxSFMA] == 3)
scs(p, "(s->macc >> 16)"); scs(p, "(macc >> 16)");
else else
abort(); abort();
break; break;
@ -743,23 +743,23 @@ static void cintrp_expand(char **p, int s, int e, const int *cv)
}; };
char r[256]; char r[256];
sprintf(r, "tms57002_macc_to_output_%d%s(s, 0x%016" I64FMT "xULL, 0x%016" I64FMT "xULL)", cv[IxSFMO], cv[IxMOVM] ? "s" : "", rounding[cv[IxRND]], rmask[cv[IxRND]]); sprintf(r, "macc_to_output_%d%s(0x%016" I64FMT "xULL, 0x%016" I64FMT "xULL)", cv[IxSFMO], cv[IxMOVM] ? "s" : "", rounding[cv[IxRND]], rmask[cv[IxRND]]);
scs(p, r); scs(p, r);
break; break;
} }
case PMV: { case PMV: {
char r[256]; char r[256];
sprintf(r, "tms57002_check_macc_overflow_%d%s(s)", cv[IxSFMO], cv[IxMOVM] ? "s" : ""); sprintf(r, "check_macc_overflow_%d%s()", cv[IxSFMO], cv[IxMOVM] ? "s" : "");
scs(p, r); scs(p, r);
break; break;
} }
case PB: case PB:
scs(p, "s->pc = "); scs(p, "pc = ");
cintrp_expand(p, parse_res[i].ppos[0], parse_res[i].ppos[1], cv); cintrp_expand(p, parse_res[i].ppos[0], parse_res[i].ppos[1], cv);
scs(p, ";\n"); scs(p, ";\n");
scs(p, " s->sti |= S_BRANCH"); scs(p, " sti |= S_BRANCH");
break; break;
case PWA: case PWA:
@ -767,17 +767,17 @@ static void cintrp_expand(char **p, int s, int e, const int *cv)
cintrp_expand(p, parse_res[i].ppos[0], parse_res[i].ppos[1], cv); cintrp_expand(p, parse_res[i].ppos[0], parse_res[i].ppos[1], cv);
scs(p, ";\n"); scs(p, ";\n");
scs(p, " if(r < -0x80000000 || r > 0x7fffffff)\n"); scs(p, " if(r < -0x80000000 || r > 0x7fffffff)\n");
scs(p, " s->st1 |= ST1_AOV;\n"); scs(p, " st1 |= ST1_AOV;\n");
scs(p, " s->aacc = r"); scs(p, " aacc = r");
break; break;
case PWC: case PWC:
if(cv[IxCMODE] == 0) if(cv[IxCMODE] == 0)
scs(p, "s->cmem[i->param] = "); scs(p, "cmem[i->param] = ");
else if(cv[IxCMODE] == 1) else if(cv[IxCMODE] == 1)
scs(p, "s->cmem[s->ca] = "); scs(p, "cmem[ca] = ");
else if(cv[IxCMODE] == 2) else if(cv[IxCMODE] == 2)
scs(p, "s->cmem[s->ca++] = "); scs(p, "cmem[ca++] = ");
else else
abort(); abort();
@ -787,19 +787,19 @@ static void cintrp_expand(char **p, int s, int e, const int *cv)
case PWD: case PWD:
if(cv[IxDMODE] == 0) if(cv[IxDMODE] == 0)
if(cv[IxDBP]) if(cv[IxDBP])
scs(p, "s->dmem1[(i->param + s->ba1) & 0x1f] = "); scs(p, "dmem1[(i->param + ba1) & 0x1f] = ");
else else
scs(p, "s->dmem0[(i->param + s->ba0) & 0xff] = "); scs(p, "dmem0[(i->param + ba0) & 0xff] = ");
else if(cv[IxDMODE] == 1) else if(cv[IxDMODE] == 1)
if(cv[IxDBP]) if(cv[IxDBP])
scs(p, "s->dmem1[(s->id + s->ba1) & 0x1f] = "); scs(p, "dmem1[(id + ba1) & 0x1f] = ");
else else
scs(p, "s->dmem0[(s->id + s->ba0) & 0xff] = "); scs(p, "dmem0[(id + ba0) & 0xff] = ");
else if(cv[IxDMODE] == 2) else if(cv[IxDMODE] == 2)
if(cv[IxDBP]) if(cv[IxDBP])
scs(p, "s->dmem1[((s->id++) + s->ba1) & 0x1f] = "); scs(p, "dmem1[((id++) + ba1) & 0x1f] = ");
else else
scs(p, "s->dmem0[((s->id++) + s->ba0) & 0xff] = "); scs(p, "dmem0[((id++) + ba0) & 0xff] = ");
else else
abort(); abort();
@ -876,7 +876,7 @@ static void save_dasm(FILE *f)
save_dasm_cat(f, "DASM3", cat3, 0x80); save_dasm_cat(f, "DASM3", cat3, 0x80);
} }
static void save_intrp(FILE *f) void save_intrp(FILE *f)
{ {
save_intrp_cat(f, "INTRP1", cat1, 0x40, 0, 0); save_intrp_cat(f, "INTRP1", cat1, 0x40, 0, 0);
save_intrp_cat(f, "INTRP2A", cat2, 0x80, I_POST, 0); save_intrp_cat(f, "INTRP2A", cat2, 0x80, I_POST, 0);
@ -916,7 +916,7 @@ static void save(const char *fname)
compute_cache_ids(); compute_cache_ids();
save_dasm(f); save_dasm(f);
save_intrp(f); // save_intrp(f);
save_cdec(f); save_cdec(f);
save_cintrp(f); save_cintrp(f);

14
src/mame/drivers/konamigx.c
View File

@ -1257,32 +1257,32 @@ static WRITE16_HANDLER( sndcomm68k_w )
static INTERRUPT_GEN(tms_sync) static INTERRUPT_GEN(tms_sync)
{ {
tms57002_sync(device); downcast<tms57002_device *>(device)->sync();
} }
static READ16_HANDLER(tms57002_data_word_r) static READ16_HANDLER(tms57002_data_word_r)
{ {
return tms57002_data_r(space->machine().device("dasp"), 0); return space->machine().device<tms57002_device>("dasp")->data_r(*space, 0);
} }
static WRITE16_HANDLER(tms57002_data_word_w) static WRITE16_HANDLER(tms57002_data_word_w)
{ {
if (ACCESSING_BITS_0_7) if (ACCESSING_BITS_0_7)
tms57002_data_w(space->machine().device("dasp"), 0, data); space->machine().device<tms57002_device>("dasp")->data_w(*space, 0, data);
} }
static READ16_HANDLER(tms57002_status_word_r) static READ16_HANDLER(tms57002_status_word_r)
{ {
return (tms57002_dready_r(space->machine().device("dasp"), 0) ? 4 : 0) | return (space->machine().device<tms57002_device>("dasp")->dready_r(*space, 0) ? 4 : 0) |
(tms57002_empty_r(space->machine().device("dasp"), 0) ? 1 : 0); (space->machine().device<tms57002_device>("dasp")->empty_r(*space, 0) ? 1 : 0);
} }
static WRITE16_HANDLER(tms57002_control_word_w) static WRITE16_HANDLER(tms57002_control_word_w)
{ {
if (ACCESSING_BITS_0_7) if (ACCESSING_BITS_0_7)
{ {
tms57002_pload_w(space->machine().device("dasp"), 0, data & 4); space->machine().device<tms57002_device>("dasp")->pload_w(*space, 0, data & 4);
tms57002_cload_w(space->machine().device("dasp"), 0, data & 8); space->machine().device<tms57002_device>("dasp")->cload_w(*space, 0, data & 8);
cputag_set_input_line(space->machine(), "dasp", INPUT_LINE_RESET, !(data & 16) ? ASSERT_LINE : CLEAR_LINE); cputag_set_input_line(space->machine(), "dasp", INPUT_LINE_RESET, !(data & 16) ? ASSERT_LINE : CLEAR_LINE);
} }
} }