srcclean in preparation for branching release

This commit is contained in:
Vas Crabb 2021-02-21 16:08:12 +11:00
parent 2441cc0f8d
commit a425bd5d90
32 changed files with 230 additions and 230 deletions

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@ -358,7 +358,7 @@ Basic programs:
</dataarea>
</part>
</software>
<software name="hamurabicn">
<description>Hamurabi (Computerland)</description>
<year>197?</year>
@ -417,7 +417,7 @@ Basic programs:
</dataarea>
</part>
</software>
<software name="nightmare6">
<description>Nightmare #6</description>
<year>197?</year>

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@ -9991,7 +9991,7 @@ has been replaced with an all-zero block. -->
<rom name="Hare Raising Havoc (USA) [Walt Disney] [1991] [3.5DD] [Disk 5 of 5].img" size="737280" crc="84e8dff3" sha1="3bfb15045dea49b4e7074ab4b08e1533430daa03"/>
</dataarea>
</part>
</software>
</software>
<software name="harpoon">
<description>Harpoon</description>

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@ -255486,7 +255486,7 @@ license:CC0
</part>
</software>
<!-- Project 2612 VGM Archives located at http://project2612.org/list.php
Also https://archive.org/details/Project2612CompleteArchive20180623681Sets.7z -->

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@ -345,7 +345,7 @@ offs_t v850es_disassembler::dasm_000011(std::ostream &stream, u16 opcode, offs_t
return 2 | SUPPORTED;
}
else
return v850_disassembler::dasm_000011(stream, opcode, pc, opcodes);
return v850_disassembler::dasm_000011(stream, opcode, pc, opcodes);
}
offs_t v850_disassembler::dasm_0001(std::ostream &stream, u16 opcode, offs_t pc, const v850_disassembler::data_buffer &opcodes)

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@ -155,7 +155,7 @@ void iwm_device::flush_write()
u8 iwm_device::control(int offset, u8 data)
{
sync();
if(offset < 8) {
if(offset & 1)
m_phases |= 1 << (offset >> 1);
@ -190,7 +190,7 @@ u8 iwm_device::control(int offset, u8 data)
m_async_update = 0;
m_data = 0x00;
}
} else {
if(m_rw != MODE_WRITE) {
m_rw = MODE_WRITE;
@ -456,7 +456,7 @@ void iwm_device::sync()
if(m_whd & 0x80) {
logerror("underrun\n");
flush_write();
m_flux_write_start = 0;
m_flux_write_start = 0;
m_whd &= ~0x40;
m_last_sync = next_sync;
} else {

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@ -157,11 +157,11 @@ u8 swim1_device::ism_read(offs_t offset)
{
ism_sync();
// static const char *const names[] = {
// "data", "mark", "crc", "param", "phases", "setup", "status", "handshake"
// };
// static const char *const names[] = {
// "data", "mark", "crc", "param", "phases", "setup", "status", "handshake"
// };
// logerror("read ism %s\n", names[offset & 7]);
// logerror("read ism %s\n", names[offset & 7]);
switch(offset & 7) {
case 0x0: { // data
u16 r = ism_fifo_pop();
@ -438,7 +438,7 @@ u8 swim1_device::iwm_control(int offset, u8 data)
m_iwm_async_update = 0;
m_iwm_data = 0x00;
}
} else {
if(m_iwm_rw != MODE_WRITE) {
m_iwm_rw = MODE_WRITE;
@ -758,7 +758,7 @@ void swim1_device::iwm_sync()
if(m_iwm_whd & 0x80) {
logerror("underrun\n");
flush_write();
m_flux_write_start = 0;
m_flux_write_start = 0;
m_iwm_whd &= ~0x40;
m_last_sync = next_sync;
} else {
@ -1022,7 +1022,7 @@ void swim1_device::ism_sync()
if(sct == 1)
resolved_ls_type[resolved_ls_count++] = sct;
else
resolved_ls_type[resolved_ls_count++] = lct;
resolved_ls_type[resolved_ls_count++] = lct;
}
}
@ -1129,7 +1129,7 @@ void swim1_device::ism_sync()
break;
}
m_ism_csm_pair_side = !m_ism_csm_pair_side;
m_ism_csm_pair_side = !m_ism_csm_pair_side;
}

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@ -1820,7 +1820,7 @@ bool a2_woz_format::save(io_generic *io, const std::vector<uint32_t> &variants,
data[off + (j >> 3)] |= 0x80 >> (j & 7);
tb += (size + 4095) / 4096;
}
w32(data, 8, crc32r(&data[12], data.size() - 12));
io_generic_write(io, data.data(), 0, data.size());
@ -1979,7 +1979,7 @@ std::vector<uint32_t> a2_nib_format::generate_levels_from_nibbles(const std::vec
const auto trailing_padding_size = count_trailing_padding(nibbles);
const auto trailing_FF_count =
count_leading_FFs(nibbles.rbegin() + trailing_padding_size,
nibbles.rend());
nibbles.rend());
const auto wrapped_FF_count = leading_FF_count + trailing_FF_count;
const bool wrapped_FF_are_syncs = wrapped_FF_count >= min_sync_bytes;
@ -2042,11 +2042,11 @@ bool a2_nib_format::load(io_generic *io, uint32_t form_factor, const std::vector
std::vector<uint8_t> nibbles(nibbles_per_track);
for (unsigned track = 0; track < nr_tracks; ++track) {
io_generic_read(io, &nibbles[0],
track * nibbles_per_track, nibbles_per_track);
track * nibbles_per_track, nibbles_per_track);
auto levels = generate_levels_from_nibbles(nibbles);
generate_track_from_levels(track, 0,
levels,
0, image);
levels,
0, image);
}
image->set_form_variant(floppy_image::FF_525, floppy_image::SSSD);

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@ -967,7 +967,7 @@ bool floppy_image::track_is_formatted(int track, int head, int subtrack)
return false;
if(data.size() == 1 && (data[0] & MG_MASK) == MG_N)
return false;
return true;
return true;
}
const char *floppy_image::get_variant_name(uint32_t form_factor, uint32_t variant)

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@ -69,7 +69,7 @@ private:
uint32_t m_compressed_offset; // current offset with the compressed stream
FLAC__byte * m_compressed_start; // start of compressed data
uint32_t m_compressed_length; // length of the compressed stream
// parameters
uint32_t m_sample_rate; // sample rate
uint8_t m_channels; // number of channels

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@ -116,7 +116,7 @@ public:
m_ide(*this, PCI_ID_IDE),
m_rtc(*this, "rtc"),
m_io_analog(*this, "AN.%u", 0)
{
{
std::fill(std::begin(board_ctrl), std::end(board_ctrl), 0);
}

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@ -1010,39 +1010,39 @@ void firebeat_spu_state::rf5c400_map(address_map& map)
IRQ2: Executes one command stored in a different buffer from IRQ1.
The buffer can contain up to 8 commands.
The command index counter increments after each IRQ2 call.
If there is no command in the slot at the current counter then it just increments without executing a command.
The command index counter increments after each IRQ2 call.
If there is no command in the slot at the current counter then it just increments without executing a command.
Timing matters. In particular if the speed of the IRQ 2 calls is too fast then the volume and frequency animations will be wrong.
The most common issue with bad timing is keysounds will be cut off.
pop'n music Animelo 2 also has an issue when playing CHA-LA HEAD CHA-LA where one of the beginning keysounds will stay on a
very high pitched frequency. The lower(?) the IRQ 2 frequency, the longer the keysound stays played it seems.
Timing matters. In particular if the speed of the IRQ 2 calls is too fast then the volume and frequency animations will be wrong.
The most common issue with bad timing is keysounds will be cut off.
pop'n music Animelo 2 also has an issue when playing CHA-LA HEAD CHA-LA where one of the beginning keysounds will stay on a
very high pitched frequency. The lower(?) the IRQ 2 frequency, the longer the keysound stays played it seems.
For beatmania III:
cmd[0] = nop
cmd[1] = 0x91bc -> Send stop command for all rf5c400 channels that are done playing
cmd[2] = 0x310a -> Error checking? Sending some kind of state to main CPU???
cmd[3] = 0x29c6 -> Increment a timer for each running DMA(ATA command?)
Each timer must count up to 0x02e8 (744) before it will move on to the next DMA, which I believe is the time out counter.
For beatmania III:
cmd[0] = nop
cmd[1] = 0x91bc -> Send stop command for all rf5c400 channels that are done playing
cmd[2] = 0x310a -> Error checking? Sending some kind of state to main CPU???
cmd[3] = 0x29c6 -> Increment a timer for each running DMA(ATA command?)
Each timer must count up to 0x02e8 (744) before it will move on to the next DMA, which I believe is the time out counter.
In another part of the program (0x363c for a21jca03.bin) is the following code for determining when to start and stop the DMA:
In another part of the program (0x363c for a21jca03.bin) is the following code for determining when to start and stop the DMA:
start_dma();
while (get_dma_timer() < dma_max_timer) {
if (irq6_called_flag) {
break;
}
}
end_dma();
start_dma();
while (get_dma_timer() < dma_max_timer) {
if (irq6_called_flag) {
break;
}
}
end_dma();
irq6_called_flag is set only when IRQ6 is called.
get_dma_timer is the timer that is incremented by 0x29c6.
cmd[4] = 0x94de -> Animates rf5c400 channel volumes
cmd[5] = 0x7b2c -> Send some kind of buffer status flags to spu_status_led_w. Related to IRQ4 since commands come from PPC to set buffer data
cmd[6] = 0x977e -> Animates rf5c400 channel frequencies
cmd[7] = 0x9204 -> Sends current state of rf5c400 channels as well as a list (bitmask integer) of usable channels up to main CPU memory.
Also sends a flag to to spu_status_led_w that shows if there are available SE slots.
If there are no available SE slots then it will set bit 3 to .
irq6_called_flag is set only when IRQ6 is called.
get_dma_timer is the timer that is incremented by 0x29c6.
cmd[4] = 0x94de -> Animates rf5c400 channel volumes
cmd[5] = 0x7b2c -> Send some kind of buffer status flags to spu_status_led_w. Related to IRQ4 since commands come from PPC to set buffer data
cmd[6] = 0x977e -> Animates rf5c400 channel frequencies
cmd[7] = 0x9204 -> Sends current state of rf5c400 channels as well as a list (bitmask integer) of usable channels up to main CPU memory.
Also sends a flag to to spu_status_led_w that shows if there are available SE slots.
If there are no available SE slots then it will set bit 3 to .
IRQ4: Dual-port RAM mailbox (when PPC writes to 0x3FE)
Handles commands from PPC (bytes 0x00 and 0x01)

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@ -4,12 +4,12 @@
Insight Enterprises Z80 Single Board Computer
Possibly a prototype or part of a larger system. A video with more
info is available at https://www.youtube.com/watch?v=_z1kBb-Zwpg.
Possibly a prototype or part of a larger system. A video with more
info is available at https://www.youtube.com/watch?v=_z1kBb-Zwpg.
TODO:
- Verify device hookup
- Figure out what's at 0x20, 0x21, 0x3c, 0x3d
- Figure out what's at 0x20, 0x21, 0x3c, 0x3d
- Hook up FDC
- Hook up CRT8002 (video attributes)
- Much more
@ -81,15 +81,15 @@ void iez80_state::mem_map(address_map &map)
void iez80_state::io_map(address_map &map)
{
map.global_mask(0xff);
// map(0x20, 0x20).lr8([this]() { return machine().rand(); }, "unk20");
// map(0x21, 0x21).lr8([this]() { return machine().rand(); }, "unk21");
// map(0x20, 0x20).lr8([this]() { return machine().rand(); }, "unk20");
// map(0x21, 0x21).lr8([this]() { return machine().rand(); }, "unk21");
map(0x24, 0x27).rw("pio", FUNC(z80pio_device::read), FUNC(z80pio_device::write));
map(0x28, 0x2b).rw("ctc", FUNC(z80ctc_device::read), FUNC(z80ctc_device::write));
map(0x2c, 0x2f).rw("dart1", FUNC(z80sio_device::ba_cd_r), FUNC(z80sio_device::ba_cd_w));
map(0x32, 0x32).rw("dma", FUNC(z80dma_device::read), FUNC(z80dma_device::write));
map(0x38, 0x3b).rw("dart2", FUNC(z80sio_device::ba_cd_r), FUNC(z80sio_device::ba_cd_w));
// map(0x3c, 0x3c).lr8([this]() { return machine().rand(); }, "unk3c");
// map(0x3d, 0x3d).lr8([this]() { return machine().rand(); }, "unk3d");
// map(0x3c, 0x3c).lr8([this]() { return machine().rand(); }, "unk3c");
// map(0x3d, 0x3d).lr8([this]() { return machine().rand(); }, "unk3d");
map(0x40, 0x4f).rw("crtc", FUNC(crt5037_device::read), FUNC(crt5037_device::write));
}
@ -215,7 +215,7 @@ void iez80_state::iez80(machine_config &config)
ROM_START( iez80 )
ROM_REGION(0x1000, "maincpu", 0)
ROM_LOAD("iez80.bin", 0x0000, 0x1000, CRC(d73137d2) SHA1(a340a47c5f37bbef244d35d581ff0beeeec5d677))
ROM_REGION(0x800, "chargen", 0)
ROM_LOAD("8002.bin", 0x0000, 0x0800, CRC(fdd6eb13) SHA1(a094d416e66bdab916e72238112a6265a75ca690))
ROM_END

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@ -1045,9 +1045,9 @@ void shoottv_state::shoottv_map(address_map &map)
void itech32_state::pubball_map(address_map &map)
{
itech020_map(map);
map(0x300000, 0x300003).w(FUNC(itech32_state::color_w<0>)).umask32(0x00ff00ff);
map(0x380000, 0x380003).w(FUNC(itech32_state::color_w<1>)).umask32(0x00ff00ff);
itech020_map(map);
map(0x300000, 0x300003).w(FUNC(itech32_state::color_w<0>)).umask32(0x00ff00ff);
map(0x380000, 0x380003).w(FUNC(itech32_state::color_w<1>)).umask32(0x00ff00ff);
}
@ -4645,13 +4645,13 @@ ROM_START( gtclasscs ) /* Version 1.00S for the 3 tier type PCB with short ROM
ROM_END
/***************************************************************************
The ROM images for both sets below were found by analyzing the contents
of archived source-code CDs acquired at auction. This is why the ROM
definitions in question are not sized to a power of two, as most ROM
dumps typically are.
However, the provided dump of Power Up Baseball has been proven to
work as-is on a properly-configured itech32 board, and passes all
relevant ROM tests, and so can be considered authoritative.
The ROM images for both sets below were found by analyzing the contents
of archived source-code CDs acquired at auction. This is why the ROM
definitions in question are not sized to a power of two, as most ROM
dumps typically are.
However, the provided dump of Power Up Baseball has been proven to
work as-is on a properly-configured itech32 board, and passes all
relevant ROM tests, and so can be considered authoritative.
****************************************************************************/
ROM_START( shoottv )

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@ -295,7 +295,7 @@ void jpmimpct_state::volume_w(offs_t offset, uint16_t data, uint16_t mem_mask)
int changed = m_volume_latch^(data&0xf0);
m_upd7759->set_rom_bank((data >> 1) & 3);
m_upd7759->reset_w(BIT(data, 0));
if ( changed & 0x10)
{ // digital volume clock line changed
if ( !(data & 0x10) )

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@ -2,28 +2,28 @@
// copyright-holders:Angelo Salese
/******************************************************************************
Jungle (c) 2001 Yonshi
Jungle (c) 2001 Yonshi
TODO:
- with a clean NVRAM MAME needs to be soft reset after init or the game
will trip a '1111 exception' (caused by invalid opcode executed at
0x102, incomplete decryption most likely);
- Likewise anything in the 0x100-0x1f7 range doesn't seem valid at all;
- game sometimes expects 1+ coins even if player has available points
(and freezing with "COIN" text blinking), very unlikely to be intended
behaviour?
- system setting screen shows the following settings that don't seem to be
affected by dips:
* Min. Bet (always 1),
* Credit X Ticket Mode (always Cencel (sic)),
* Max. 10 Mode (always Max. 10);
- sound doesn't seem to work 100% correctly (i.e. coin sound only seems
to work from 3rd coin on, lots of invalid sample msgs in error.log).
fwiw there's no extra OKI bank in the ROM, must be either invalid
decryption or fancy OKI status readback instead.
TODO:
- with a clean NVRAM MAME needs to be soft reset after init or the game
will trip a '1111 exception' (caused by invalid opcode executed at
0x102, incomplete decryption most likely);
- Likewise anything in the 0x100-0x1f7 range doesn't seem valid at all;
- game sometimes expects 1+ coins even if player has available points
(and freezing with "COIN" text blinking), very unlikely to be intended
behaviour?
- system setting screen shows the following settings that don't seem to be
affected by dips:
* Min. Bet (always 1),
* Credit X Ticket Mode (always Cencel (sic)),
* Max. 10 Mode (always Max. 10);
- sound doesn't seem to work 100% correctly (i.e. coin sound only seems
to work from 3rd coin on, lots of invalid sample msgs in error.log).
fwiw there's no extra OKI bank in the ROM, must be either invalid
decryption or fancy OKI status readback instead.
Latter may be confirmed by video display stalling at the end of a
normal round, OSD coin counter gets updated after the BGM completes
playback.
normal round, OSD coin counter gets updated after the BGM completes
playback.
- outputs (lamps & ticket dispenser at very least);
===============================================================================
@ -206,7 +206,7 @@ void jungleyo_state::video_start()
uint32_t jungleyo_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
{
bitmap.fill(m_palette->black_pen(), cliprect);
if (m_layer_enable == 0)
return 0;
@ -217,10 +217,10 @@ uint32_t jungleyo_state::screen_update(screen_device &screen, bitmap_ind16 &bitm
u16 scroll = m_reel_vram[Layer][i*2] >> 8;
m_reel_tilemap[Layer]->set_scrolly(i, scroll);
}
m_reel_tilemap[Layer]->draw(screen, bitmap, cliprect, 0, 0);
}
if ((m_video_priority & 1) == 0)
m_bg_tilemap->draw(screen, bitmap, cliprect, 0, 0);

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@ -85,7 +85,7 @@ private:
};
template <uint8_t Which>
template <uint8_t Which>
TILE_GET_INFO_MEMBER(koftball_state::get_tile_info)
{
int data = m_videoram[Which][tile_index];

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@ -154,7 +154,7 @@ MC6845_UPDATE_ROW( laserbas_state::crtc_update_row )
// layer 2 (fixed)
offs_t offset_p2= ((y * 0x80) | (ra << 7)) + (x << 2) + (i >> 1);
uint8_t p2 = (m_vram[0x8000 + offset_p2] >> ((i & 1) * 4)) & 0x0f;
// priority: p2 > p1 > background
uint8_t p = p2 ? p2 : p1 ? (p1 + 16) : m_bset;

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@ -775,7 +775,7 @@ ROM_START( loopingv )
ROM_LOAD( "i-o.11a", 0x2800, 0x1000, CRC(61c74c79) SHA1(9f34d18a919446dd76857b851cea23fc1526f3c2) ) // speech
ROM_REGION( 0x0400, "mcu", 0 ) // COP420 microcontroller code
ROM_LOAD( "cop.bin", 0x0000, 0x0400, CRC(d47fecec) SHA1(7eeedcb40f4cd50e1e259c6b01744a3fc97b60aa) )
ROM_LOAD( "cop.bin", 0x0000, 0x0400, CRC(d47fecec) SHA1(7eeedcb40f4cd50e1e259c6b01744a3fc97b60aa) )
ROM_REGION( 0x1000, "gfx1", 0 )
ROM_LOAD( "log2.8a", 0x0000, 0x800, CRC(ef3284ac) SHA1(8719c9df8c972a56c306b3c707aaa53092ffa2d6) )
@ -799,7 +799,7 @@ ROM_START( loopingva )
ROM_LOAD( "i-o.11a", 0x2800, 0x1000, CRC(61c74c79) SHA1(9f34d18a919446dd76857b851cea23fc1526f3c2) )
ROM_REGION( 0x0400, "mcu", 0 ) // COP420 microcontroller code
ROM_LOAD( "cop.bin", 0x0000, 0x0400, CRC(d47fecec) SHA1(7eeedcb40f4cd50e1e259c6b01744a3fc97b60aa) )
ROM_LOAD( "cop.bin", 0x0000, 0x0400, CRC(d47fecec) SHA1(7eeedcb40f4cd50e1e259c6b01744a3fc97b60aa) )
ROM_REGION( 0x1000, "gfx1", 0 )
ROM_LOAD( "log2.8a", 0x0000, 0x800, CRC(ef3284ac) SHA1(8719c9df8c972a56c306b3c707aaa53092ffa2d6) )
@ -825,7 +825,7 @@ ROM_START( looping )
ROM_LOAD( "loopa11.bin", 0x2800, 0x1000, CRC(61c74c79) SHA1(9f34d18a919446dd76857b851cea23fc1526f3c2) ) // speech
ROM_REGION( 0x0400, "mcu", 0 ) // COP420 microcontroller code
ROM_LOAD( "cop.bin", 0x0000, 0x0400, CRC(d47fecec) SHA1(7eeedcb40f4cd50e1e259c6b01744a3fc97b60aa) ) // taken from the other sets
ROM_LOAD( "cop.bin", 0x0000, 0x0400, CRC(d47fecec) SHA1(7eeedcb40f4cd50e1e259c6b01744a3fc97b60aa) ) // taken from the other sets
ROM_REGION( 0x1000, "gfx1", 0 )
ROM_LOAD( "loopaa8.bin", 0x0000, 0x800, CRC(ef3284ac) SHA1(8719c9df8c972a56c306b3c707aaa53092ffa2d6) )
@ -848,7 +848,7 @@ ROM_START( skybump )
ROM_LOAD( "snd.11a", 0x2800, 0x1000, CRC(61c74c79) SHA1(9f34d18a919446dd76857b851cea23fc1526f3c2) )
ROM_REGION( 0x0400, "mcu", 0 ) // COP420 microcontroller code
ROM_LOAD( "cop.bin", 0x0000, 0x0400, CRC(d47fecec) SHA1(7eeedcb40f4cd50e1e259c6b01744a3fc97b60aa) )
ROM_LOAD( "cop.bin", 0x0000, 0x0400, CRC(d47fecec) SHA1(7eeedcb40f4cd50e1e259c6b01744a3fc97b60aa) )
ROM_REGION( 0x1000, "gfx1", 0 )
ROM_LOAD( "vid.8a", 0x0000, 0x800, CRC(459ccc55) SHA1(747f6789605b48be9e22f779f9e3f6c98ad4e594) )

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@ -5,37 +5,37 @@
LSI M-THREE
Models:
- M-THREE/100 (SA400, 5.25" single sided)
- M-THREE/110 (SA410, 5.25" single sided)
- M-THREE/150 (SA450, 5.25" double sided)
- M-THREE/160 (SA460, 5.25" double sided)
- M-THREE/200 (SA800, 8" single sided)
- M-THREE/250 (SA850, 8" double sided) [emulated by default]
- M-THREE/320 (SA800, 8" single sided, Winchester 5 MB)
- M-THREE/325 (SA850, 8" double sided, Winchester 5 MB)
- M-THREE/340 (SA800, 8" single sided, Winchester 10 MB)
- M-THREE/345 (SA850, 8" double sided, Winchester 10 MB)
- M-THREE/100 (SA400, 5.25" single sided)
- M-THREE/110 (SA410, 5.25" single sided)
- M-THREE/150 (SA450, 5.25" double sided)
- M-THREE/160 (SA460, 5.25" double sided)
- M-THREE/200 (SA800, 8" single sided)
- M-THREE/250 (SA850, 8" double sided) [emulated by default]
- M-THREE/320 (SA800, 8" single sided, Winchester 5 MB)
- M-THREE/325 (SA850, 8" double sided, Winchester 5 MB)
- M-THREE/340 (SA800, 8" single sided, Winchester 10 MB)
- M-THREE/345 (SA850, 8" double sided, Winchester 10 MB)
Hardware:
- Z80
- 64 KB RAM
- Z80 CTC
- 2x D8255AC PPI
- D8251A
- MC6845P CRTC
- FD1793 FDC
- 64 KB RAM
- Z80 CTC
- 2x D8255AC PPI
- D8251A
- MC6845P CRTC
- FD1793 FDC
TODO:
- Initial PC is currently hacked to f000
- Verify/fix floppy hookup (CPU needs to be overclocked?)
- Printer interface
- Buzzer
- Map the rest of the keys, verify existing keys
- Verify/fix floppy hookup (CPU needs to be overclocked?)
- Printer interface
- Buzzer
- Map the rest of the keys, verify existing keys
Notes:
- No offical software available, but a custom version of CP/M
- Y to boot from floppy, ESC to enter monitor, any other key to
boot from IDE
- Y to boot from floppy, ESC to enter monitor, any other key to
boot from IDE
***************************************************************************/
@ -244,7 +244,7 @@ static INPUT_PORTS_START( m3 )
PORT_START("K06")
PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_COMMA) PORT_CHAR(',') PORT_CHAR('<')
PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_B) PORT_CHAR('b') PORT_CHAR('B')
PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_SPACE) PORT_CHAR(' ')
PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_SPACE) PORT_CHAR(' ')
PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("92")
PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_4_PAD) PORT_CHAR(UCHAR_MAMEKEY(4_PAD))
PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_TAB) PORT_CHAR(9)
@ -374,7 +374,7 @@ void m3_state::kbd_p1_w(uint8_t data)
{
// 765----- row select
m_kbd_row = data >> 5;
m_kbd_row = data >> 5;
}
void m3_state::kbd_p2_w(uint8_t data)
@ -472,7 +472,7 @@ uint8_t m3_state::fdc_data_r(offs_t offset)
// cpu tries to read data without drq, halt it and reset pc
m_maincpu->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
m_maincpu->set_state_int(Z80_PC, m_maincpu->state_int(Z80_PC) - 2);
return 0;
}
@ -486,7 +486,7 @@ void m3_state::fdc_data_w(offs_t offset, uint8_t data)
// cpu tries to write data without drq, halt it and reset pc
m_maincpu->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
m_maincpu->set_state_int(Z80_PC, m_maincpu->state_int(Z80_PC) - 2);
return;
}
@ -646,7 +646,7 @@ void m3_state::m3(machine_config &config)
ROM_START( m3 )
ROM_REGION(0x1000, "maincpu", 0)
ROM_LOAD("bootstrap_prom_034.bin", 0x0000, 0x0800, CRC(7fdb051e) SHA1(7aa24d4f44b6a0c8f7f647667f4997432c186cac))
// Homebrew Monitor ROM, written by Steve Hunt. Uses the socket of the HDD ROM.
ROM_LOAD("monitor_prom_v19_2017-07-05.bin", 0x0800, 0x0800, CRC(0608848f) SHA1(9a82cb49056ff1a1d53ce2bd026537a6914a4847))

View File

@ -7,11 +7,11 @@
This only loads the basic stuff - there needs to be more done to make this run.
There are 3 Mainboards, original M1 uses 2x TMP82C79P's, M1A and M1B use 1x TMP82C79P and 1x 80c51 microcontroller with a 12MHz crystal
There are 4 sound options,
1: AY3-8930 on the mainboard.
2: "Digital Sound Board" sound ROM + NEC D7759 on the romcard.
3: "FM & Digital Sound Board" sound ROM + NEC D7759 & YM2413 (3.579Mhz) on the romcard.
3: "FM & Digital Sound Board" sound ROM + NEC D7759 & YM2413 (3.579Mhz) on the romcard.
4: "E.S.P. Board" sound ROMS + OKI M6376, + NEC C1892
** later ESP boards also have a sub-board marked "RAM Protection Board"

View File

@ -4783,9 +4783,9 @@ ROM_END
/*****************************************************************************
Ms PacMan Twin (SUSILU)
-----------------------
Ms PacMan Twin (SUSILU)
-----------------------
Argentine official hack of Ms. PacMan that allows 2 players simultaneously.
Very rare PCB. Was avoiding us for more of 22 years...
@ -4793,12 +4793,12 @@ ROM_END
(normal in mspacman boards) plugged in the Z80 socket.
Here the specs:
Here the specs:
Mini daughterboard 3" x 5.5" aprox.
Mini daughterboard 3" x 5.5" aprox.
In the upper-left corner is vertically printed "SUSILU" and "NMPT008",
and across: "MOD REG 294535" and "INDUSTRIA ARGENTINA".
and across: "MOD REG 294535" and "INDUSTRIA ARGENTINA".
.----------------------------.
| .----------. |
@ -4830,7 +4830,7 @@ ROM_END
| '--------------' |
'----------------------------'
Viewing from the top you can find: U5 U3 U1 U2 U4
Viewing from the top you can find: U5 U3 U1 U2 U4
U5: 74LS245N (Octal Bus Tranceivers with 3-state outputs, DIP20),
with a decoupling cap soldered from leg 10 to leg 20.
@ -4838,7 +4838,7 @@ ROM_END
U3: Unknown 40 pins IC, scratched to avoid recognition. Could be either
a big PLD/CPLD/EPLD, or a kind of protection device.
U1: 40 pins male connector, to plug the kit into Z80's mainboard socket.
U1: 40 pins male connector, to plug the kit into Z80's mainboard socket.
U2: NEC D780C (Z80).
@ -4879,7 +4879,7 @@ ROM_END
NEC D780C (Z80) @ U2:
NEC D780C (Z80)
.-----------v-----------.
.-----------v-----------.
connector pin 01 (A11) ---|01 (A11) (A10) 40|--- connector pin 40 (A10)
connector pin 02 (A12) ---|02 (A12) (A09) 39|--- connector pin 39 (A09)
connector pin 03 (A13) ---|03 (A13) (A08) 38|--- connector pin 38 (A08)
@ -4911,7 +4911,7 @@ ROM_END
unknown DIL40
.-----v-----.
.-----v-----.
GND -|01 ? 40|- VCC
connector/Z80 pin 21 (/RD) -|02 39|- GND
74LS245 pin 19 (/OE) -|03-. 38|- GND
@ -4920,7 +4920,7 @@ ROM_END
74LS245 pin 19 (/OE) -|06-' 35|- GND
N/C -|07 34|- M27256 pin 20 (/CE)
connector/Z80 pin 03 (A13) -|08 33|- connector/Z80 pin 30 (A0)
74LS245 pin 02 (D4) -|09 32|- Z80 pin 07 (D4)
74LS245 pin 02 (D4) -|09 32|- Z80 pin 07 (D4)
74LS245 pin 03 (D3) -|10 31|- Z80 pin 08 (D3)
74LS245 pin 04 (D5) -|11 30|- Z80 pin 09 (D5)
74LS245 pin 05 (D6) -|12 29|- Z80 pin 10 (D6)
@ -4930,7 +4930,7 @@ ROM_END
74LS245 pin 09 (D1) -|16 25|- Z80 pin 15 (D1)
connector/Z80 pin 04 (A14) -|17 24|- GND
connector/Z80 pin 05 (A15) -|18 23|- GND
GND -|19 22|- GND
GND -|19 22|- GND
GND -|20 21|- GND
'-----------'
@ -4938,7 +4938,7 @@ ROM_END
M27256 @ U4:
M27256
.-------v-------.
.-------v-------.
VCC -|01 VPP VCC 28|- VCC
connector/Z80 pin 02 (A12) -|02 A12 A14 27|- connector/Z80 pin 05 (A15) & unknown DIP40 pin 18
connector/Z80 pin 37 (A07) -|03 A07 A13 26|- connector/Z80 pin 03 (A13)
@ -4946,22 +4946,22 @@ ROM_END
connector/Z80 pin 35 (A05) -|05 A05 A09 24|- connector/Z80 pin 39 (A09)
connector/Z80 pin 34 (A04) -|06 A04 A11 23|- connector/Z80 pin 01 (A11)
connector/Z80 pin 33 (A03) -|07 A03 /OE 22|- connector/Z80 pin 21 (/RD) & unknown DIP40 pin 02
connector/Z80 pin 32 (A02) -|08 A02 A10 21|- connector/Z80 pin 40 (A10)
connector/Z80 pin 32 (A02) -|08 A02 A10 21|- connector/Z80 pin 40 (A10)
connector/Z80 pin 31 (A01) -|09 A01 /CE 20|- unknown DIP40 pin 34
connector/Z80 pin 30 (A00) -|10 A00 O7 19|- 74LS245 pin 07 (D7)
74LS245 pin 08 (D0) -|11 O0 O6 18|- 74LS245 pin 05 (D6)
74LS245 pin 09 (D1) -|12 O1 O5 17|- 74LS245 pin 04 (D5)
74LS245 pin 06 (D2) -|13 O2 O4 16|- 74LS245 pin 02 (D4)
GND -|14 GND O3 15|- 74LS245 pin 03 (D3)
GND -|14 GND O3 15|- 74LS245 pin 03 (D3)
'---------------'
74LS245N @ U5:
74LS245
.-------v-------.
.-------v-------.
GND -|01 DIR VCC 20|- VCC
connector pin 07 (D4) -|02 A1 /OE 19|- unknown DIP40 pins 03 & 06
connector pin 07 (D4) -|02 A1 /OE 19|- unknown DIP40 pins 03 & 06
connector pin 08 (D3) -|03 A2 B1 18|- Z80 pin 07 (D4)
connector pin 09 (D5) -|04 A3 B2 17|- Z80 pin 08 (D3)
connector pin 10 (D6) -|05 A4 B3 16|- Z80 pin 09 (D5)

View File

@ -9,7 +9,7 @@
Unknown RAM size, AMD K6 processor (unknown speed)
PCI Ethernet card (unknown chipset)
The security scheme is quite simple:
The security scheme is quite simple:
Each minigame is a VisualBasic executable that receives three numbers when
invoked, the hard disk serial number (readed through the Windows enumerator
file), the Ethernet MAC address, and a third one, and concatenates them

View File

@ -3689,7 +3689,7 @@
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@ -3698,7 +3698,7 @@
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@ -3707,7 +3707,7 @@
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@ -3716,7 +3716,7 @@
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@ -3725,7 +3725,7 @@
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@ -3734,7 +3734,7 @@
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@ -3743,7 +3743,7 @@
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@ -3752,7 +3752,7 @@
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@ -3761,7 +3761,7 @@
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<image statemask="0x00080">
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@ -3770,7 +3770,7 @@
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<image statemask="0x00100">
<data>
<![CDATA[
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@ -3779,7 +3779,7 @@
</image>
<image statemask="0x00200">
<data>
<![CDATA[
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@ -3788,7 +3788,7 @@
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<image statemask="0x00400">
<data>
<![CDATA[
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@ -3797,7 +3797,7 @@
</image>
<image statemask="0x00800">
<data>
<![CDATA[
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@ -3806,7 +3806,7 @@
</image>
<image statemask="0x01000">
<data>
<![CDATA[
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<svg xmlns="http://www.w3.org/2000/svg" width="50" height="80">
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@ -3815,7 +3815,7 @@
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<image statemask="0x02000">
<data>
<![CDATA[
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<svg xmlns="http://www.w3.org/2000/svg" width="50" height="80">
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@ -3824,7 +3824,7 @@
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<image statemask="0x04000">
<data>
<![CDATA[
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@ -3833,7 +3833,7 @@
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<image statemask="0x08000">
<data>
<![CDATA[
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@ -3842,7 +3842,7 @@
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<image statemask="0x10000">
<data>
<![CDATA[
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@ -3851,7 +3851,7 @@
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<image statemask="0x20000">
<data>
<![CDATA[
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@ -5398,7 +5398,7 @@
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</element>
</repeat>
<element name="label15" ref="label_15">
<bounds x="65" y="371" width="27" height="13">
</bounds>
@ -5460,4 +5460,4 @@
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</element>
</view>
</mamelayout>
</mamelayout>

View File

@ -5699,4 +5699,4 @@
</bounds>
</element>
</view>
</mamelayout>
</mamelayout>

View File

@ -20,7 +20,7 @@ license:CC0
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<image statemask="0x10000">
<data>
<![CDATA[
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@ -29,7 +29,7 @@ license:CC0
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@ -74,7 +74,7 @@ license:CC0
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@ -155,7 +155,7 @@ license:CC0
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@ -164,7 +164,7 @@ license:CC0
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@ -20,7 +20,7 @@ license:CC0
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@ -29,7 +29,7 @@ license:CC0
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@ -38,7 +38,7 @@ license:CC0
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@ -47,7 +47,7 @@ license:CC0
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@ -56,7 +56,7 @@ license:CC0
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@ -65,7 +65,7 @@ license:CC0
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<image statemask="0x00010">
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@ -74,7 +74,7 @@ license:CC0
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@ -83,7 +83,7 @@ license:CC0
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@ -92,7 +92,7 @@ license:CC0
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@ -101,7 +101,7 @@ license:CC0
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@ -110,7 +110,7 @@ license:CC0
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@ -119,7 +119,7 @@ license:CC0
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@ -128,7 +128,7 @@ license:CC0
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@ -137,7 +137,7 @@ license:CC0
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@ -146,7 +146,7 @@ license:CC0
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@ -155,7 +155,7 @@ license:CC0
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@ -164,7 +164,7 @@ license:CC0
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@ -6,8 +6,8 @@
TODO: Implement flashing (our only datasheet has that section
completely illegible)
This is a simulation of code running on an NEC D78042GF-090
This is a simulation of code running on an NEC D78042GF-090
**********************************************************************/
#include "emu.h"

View File

@ -1155,10 +1155,10 @@ WRITE_LINE_MEMBER(macadb_device::adb_linechange_w)
if (m_adb_datasize > 0)
{
LOGMASKED(LOG_LINESTATE, "Device has %d bytes of data:\n", m_adb_datasize);
for (int i = 0; i < m_adb_datasize; i++)
{
LOGMASKED(LOG_LINESTATE, " %02x\n", m_adb_buffer[i]);
}
for (int i = 0; i < m_adb_datasize; i++)
{
LOGMASKED(LOG_LINESTATE, " %02x\n", m_adb_buffer[i]);
}
m_adb_linestate = LST_TSTOPSTART; // T1t
m_adb_timer->adjust(attotime::from_ticks(324/4, adb_timebase));
m_adb_stream_ptr = 0;

View File

@ -769,43 +769,43 @@ void atari_slapstic_device::device_start()
m_space->install_readwrite_tap(0, m_space->addrmask(), 0, "slapstic",
[this](offs_t offset, u8 &, u8) { if(!machine().side_effects_disabled()) m_state->test(offset); },
[this](offs_t offset, u8 &, u8) { if(!machine().side_effects_disabled()) m_state->test(offset); });
checker check(m_start, m_end, m_mirror, m_space->data_width(), m_chipnum == 101 ? 13 : 14);
const auto *info = slapstic_table[m_chipnum - 101];
m_s_idle = std::make_unique<idle>(this, check, info);
if(m_chipnum <= 102) {
m_s_active = std::make_unique<active_101_102>(this, check, info);
m_s_alt_valid = std::make_unique<alt_valid_101_102>(this, check, info);
} else if(m_chipnum <= 110) {
m_s_active = std::make_unique<active_103_110>(this, check, info);
m_s_alt_valid = std::make_unique<alt_valid_103_110>(this, check, info);
} else {
m_s_active = std::make_unique<active_111_118>(this, check, info);
m_s_alt_valid = std::make_unique<alt_valid_111_118>(this, check, info);
}
if(m_chipnum <= 110)
m_s_alt_select = std::make_unique<alt_select_101_110>(this, check, info, m_space->data_width() == 16 ? 1 : 0);
else
m_s_alt_select = std::make_unique<alt_select_111_118>(this, check, info, m_space->data_width() == 16 ? 1 : 0);
m_s_alt_commit = std::make_unique<alt_commit>(this, check, info);
if(m_chipnum <= 110) {
m_s_bit_load = std::make_unique<bit_load>(this, check, info);
m_s_bit_set_odd = std::make_unique<bit_set>(this, check, info, true);
m_s_bit_set_even = std::make_unique<bit_set>(this, check, info, false);
}
if(m_chipnum >= 111) {
m_s_add_load = std::make_unique<add_load>(this, check, info);
m_s_add_set = std::make_unique<add_set> (this, check, info);
}
m_state = m_s_idle.get();
}
@ -917,7 +917,7 @@ void atari_slapstic_device::active_101_102::test(offs_t addr) const
m_sl->m_state = m_sl->m_s_idle.get();
} else if(m_alt(addr)) {
m_sl->logerror("alt start (%s)\n", m_sl->machine().describe_context());
m_sl->m_state = m_sl->m_s_alt_valid.get();
m_sl->m_state = m_sl->m_s_alt_valid.get();
} else if(m_bit(addr)) {
m_sl->logerror("bitwise start (%s)\n", m_sl->machine().describe_context());
m_sl->m_state = m_sl->m_s_bit_load.get();
@ -955,7 +955,7 @@ void atari_slapstic_device::active_103_110::test(offs_t addr) const
m_sl->m_state = m_sl->m_s_idle.get();
} else if(m_alt(addr)) {
m_sl->logerror("alt start (%s)\n", m_sl->machine().describe_context());
m_sl->m_state = m_sl->m_s_alt_valid.get();
m_sl->m_state = m_sl->m_s_alt_valid.get();
} else if(m_bit(addr)) {
m_sl->logerror("bitwise start (%s)\n", m_sl->machine().describe_context());
m_sl->m_state = m_sl->m_s_bit_load.get();
@ -993,7 +993,7 @@ void atari_slapstic_device::active_111_118::test(offs_t addr) const
m_sl->m_state = m_sl->m_s_idle.get();
} else if(m_alt(addr)) {
m_sl->logerror("alt start (%s)\n", m_sl->machine().describe_context());
m_sl->m_state = m_sl->m_s_alt_valid.get();
m_sl->m_state = m_sl->m_s_alt_valid.get();
} else if(m_add(addr)) {
m_sl->logerror("add start (%s)\n", m_sl->machine().describe_context());
m_sl->m_state = m_sl->m_s_add_load.get();
@ -1203,7 +1203,7 @@ void atari_slapstic_device::bit_set::test(offs_t addr) const
m_sl->logerror("bitwise commit %d (%s)\n", m_sl->m_loaded_bank, m_sl->machine().describe_context());
m_sl->commit_bank();
m_sl->m_state = m_sl->m_s_idle.get();
}
}
}

View File

@ -65,13 +65,13 @@ private:
struct slapstic_data {
u8 bankstart;
u16 bank[4];
mask_value alt1;
mask_value alt2;
mask_value alt3;
mask_value alt4;
int altshift;
mask_value bit1;
mask_value bit2;
mask_value bit3c0;
@ -79,7 +79,7 @@ private:
mask_value bit3c1;
mask_value bit3s1;
mask_value bit4;
mask_value add1;
mask_value add2;
mask_value addplus1;
@ -270,7 +270,7 @@ private:
std::unique_ptr<state> m_s_alt_valid;
std::unique_ptr<state> m_s_alt_select;
std::unique_ptr<state> m_s_alt_commit;
std::unique_ptr<state> m_s_bit_load;
std::unique_ptr<state> m_s_bit_set_odd;
std::unique_ptr<state> m_s_bit_set_even;

View File

@ -214,7 +214,7 @@ WRITE_LINE_MEMBER(mspactwin_state::flipscreen_w)
{
m_flipscreen = state;
m_bg_tilemap->set_flip(m_flipscreen * ( TILEMAP_FLIPX + TILEMAP_FLIPY ) );
// logerror("Flip: %02x\n", state);
// logerror("Flip: %02x\n", state);
}

View File

@ -271,7 +271,7 @@ static const gdb_register_map gdb_register_map_m68000 =
{ "A4", "a4", false, TYPE_INT },
{ "A5", "a5", false, TYPE_INT },
{ "A6", "fp", true, TYPE_INT },
{ "A7", "sp", true, TYPE_INT },
{ "A7", "sp", true, TYPE_INT },
{ "SR", "ps", false, TYPE_INT }, // NOTE GDB named it ps, but it's actually sr
{ "PC", "pc", true, TYPE_CODE_POINTER },
//NOTE m68-elf-gdb complains about fpcontrol register not present but 68000 doesn't have floating point so...
@ -341,7 +341,7 @@ static const std::map<std::string, const gdb_register_map &> gdb_register_maps =
{ "r4600", gdb_register_map_r4600 },
{ "ppc601", gdb_register_map_ppc601 },
{ "m68020pmmu", gdb_register_map_m68020pmmu },
{ "m68000", gdb_register_map_m68000 },
{ "m68000", gdb_register_map_m68000 },
{ "z80", gdb_register_map_z80 },
{ "m6502", gdb_register_map_m6502 },
{ "n2a03", gdb_register_map_m6502 },