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mb8421: Convert callbacks to devcb3 and update to recent coding standards (nw)

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This commit is contained in:
AJR 2018-08-02 13:54:55 -04:00
parent cdb956fd34
commit a4d28396bf
7 changed files with 103 additions and 58 deletions
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42
src/devices/machine/mb8421.cpp
View File

@ -23,9 +23,9 @@ DEFINE_DEVICE_TYPE(MB8421_MB8431_16BIT, mb8421_mb8431_16_device, "mb8421_mb8431_
//-------------------------------------------------
mb8421_master_device::mb8421_master_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock)
: device_t(mconfig, type, tag, owner, clock),
m_intl_handler(*this),
m_intr_handler(*this)
: device_t(mconfig, type, tag, owner, clock)
, m_intl_callback(*this)
, m_intr_callback(*this)
{
}
@ -47,21 +47,25 @@ mb8421_mb8431_16_device::mb8421_mb8431_16_device(const machine_config &mconfig,
{
}
//-------------------------------------------------
// device_resolve_objects - resolve objects that
// may be needed for other devices to set
// initial conditions at start time
//-------------------------------------------------
void mb8421_master_device::device_resolve_objects()
{
// resolve callbacks
m_intl_callback.resolve_safe();
m_intr_callback.resolve_safe();
}
//-------------------------------------------------
// device_start - device-specific startup
//-------------------------------------------------
void mb8421_master_device::device_start()
{
// resolve callbacks
m_intl_handler.resolve_safe();
m_intr_handler.resolve_safe();
}
void mb8421_device::device_start()
{
mb8421_master_device::device_start();
m_ram = make_unique_clear<u8[]>(0x800);
// state save
@ -70,8 +74,6 @@ void mb8421_device::device_start()
void mb8421_mb8431_16_device::device_start()
{
mb8421_master_device::device_start();
m_ram = make_unique_clear<u16[]>(0x800);
// state save
@ -84,8 +86,8 @@ void mb8421_mb8431_16_device::device_start()
void mb8421_master_device::device_reset()
{
m_intl_handler(0);
m_intr_handler(0);
m_intl_callback(CLEAR_LINE);
m_intr_callback(CLEAR_LINE);
}
//-------------------------------------------------
@ -100,9 +102,9 @@ void mb8421_master_device::update_intr(offs_t offset)
return;
if (row == read_or_write::WRITE && offset == (is_right ? 0x7fe : 0x7ff))
(is_right ? m_intl_handler : m_intr_handler)(1);
(is_right ? m_intl_callback : m_intr_callback)(ASSERT_LINE);
else if (row == read_or_write::READ && offset == (is_right ? 0x7ff : 0x7fe))
(is_right ? m_intr_handler : m_intl_handler)(0);
(is_right ? m_intr_callback : m_intl_callback)(CLEAR_LINE);
}
//-------------------------------------------------
@ -120,7 +122,7 @@ WRITE8_MEMBER(mb8421_device::left_w)
WRITE16_MEMBER(mb8421_mb8431_16_device::left_w)
{
offset &= 0x7ff;
m_ram[offset] = data;
COMBINE_DATA(&m_ram[offset]);
update_intr<read_or_write::WRITE, false>(offset);
}
@ -158,7 +160,7 @@ WRITE8_MEMBER(mb8421_device::right_w)
WRITE16_MEMBER(mb8421_mb8431_16_device::right_w)
{
offset &= 0x7ff;
m_ram[offset] = data;
COMBINE_DATA(&m_ram[offset]);
update_intr<read_or_write::WRITE, true>(offset);
}

89
src/devices/machine/mb8421.h
View File

@ -5,6 +5,61 @@
Fujitsu MB8421/22/31/32-90/-90L/-90LL/-12/-12L/-12LL
CMOS 16K-bit (2KB) dual-port SRAM
***********************************************************************
_____________
_CS(L) 1 |* \_/ | 52 Vcc
_WE(L) 2 | | 51 _CS(R)
_BUSY(L) 3 | | 50 _WE(R)
_INT(L) 4 | | 49 _BUSY(R)
NC 5 | | 48 _INT(R)
A10(L) 6 | | 47 NC
_OE(L) 7 | | 46 A10(R)
A0(L) 8 | | 45 _OE(R)
A1(L) 9 | | 44 A0(R)
A2(L) 10 | | 43 A1(R)
A3(L) 11 | | 42 A2(R)
A4(L) 12 | | 41 A3(R)
A5(L) 13 | MB8421 | 40 A4(R)
A6(L) 14 | MB8431 | 39 A5(R)
A7(L) 15 | | 38 A6(R)
A8(L) 16 | | 37 A7(R)
A9(L) 17 | | 36 A8(R)
I/O0(L) 18 | | 35 A9(R)
I/O1(L) 19 | | 34 I/O7(R)
I/O2(L) 20 | | 33 I/O6(R)
I/O3(L) 21 | | 32 I/O5(R)
I/O4(L) 22 | | 31 I/O4(R)
I/O5(L) 23 | | 30 I/O3(R)
I/O6(L) 24 | | 29 I/O2(R)
I/O7(L) 25 | | 28 I/O1(R)
Vss 26 |_____________| 27 I/O0(R)
_____________
_CS(L) 1 |* \_/ | 48 Vcc
_WE(L) 2 | | 47 _CS(R)
_BUSY(L) 3 | | 46 _WE(R)
A10(L) 4 | | 45 _BUSY(R)
_OE(L) 5 | | 44 A10(R)
A0(L) 6 | | 43 _OE(R)
A1(L) 7 | | 42 A0(R)
A2(L) 8 | | 41 A1(R)
A3(L) 9 | | 40 A2(R)
A4(L) 10 | | 39 A3(R)
A5(L) 11 | MB8422 | 38 A4(R)
A6(L) 12 | MB8432 | 37 A5(R)
A7(L) 13 | | 36 A6(R)
A8(L) 14 | | 35 A7(R)
A9(L) 15 | | 34 A8(R)
I/O0(L) 16 | | 33 A9(R)
I/O1(L) 17 | | 32 I/O7(R)
I/O2(L) 18 | | 31 I/O6(R)
I/O3(L) 19 | | 30 I/O5(R)
I/O4(L) 20 | | 29 I/O4(R)
I/O5(L) 21 | | 28 I/O3(R)
I/O6(L) 22 | | 27 I/O2(R)
I/O7(L) 23 | | 26 I/O1(R)
Vss 24 |_____________| 25 I/O0(R)
**********************************************************************/
#ifndef MAME_MACHINE_MB8421_H
@ -13,19 +68,6 @@
#pragma once
//**************************************************************************
// INTERFACE CONFIGURATION MACROS
//**************************************************************************
// note: INT pins are only available on MB84x1
// INTL is for the CPU on the left side, INTR for the one on the right
#define MCFG_MB8421_INTL_HANDLER(_devcb) \
downcast<mb8421_master_device &>(*device).set_intl_handler(DEVCB_##_devcb);
#define MCFG_MB8421_INTR_HANDLER(_devcb) \
downcast<mb8421_master_device &>(*device).set_intr_handler(DEVCB_##_devcb);
//**************************************************************************
// TYPE DEFINITIONS
//**************************************************************************
@ -35,9 +77,10 @@
class mb8421_master_device : public device_t
{
public:
// configuration helpers
template <class Object> devcb_base &set_intl_handler(Object &&cb) { return m_intl_handler.set_callback(std::forward<Object>(cb)); }
template <class Object> devcb_base &set_intr_handler(Object &&cb) { return m_intr_handler.set_callback(std::forward<Object>(cb)); }
// note: INT pins are only available on MB84x1
// INTL is for the CPU on the left side, INTR for the one on the right
auto intl_callback() { return m_intl_callback.bind(); }
auto intr_callback() { return m_intr_callback.bind(); }
DECLARE_READ_LINE_MEMBER(busy_r) { return 0; } // _BUSY pin - not emulated
@ -45,15 +88,15 @@ protected:
mb8421_master_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock);
// device-level overrides
virtual void device_start() override;
virtual void device_resolve_objects() override;
virtual void device_reset() override;
// internal helpers
template<read_or_write row, bool is_right> void update_intr(offs_t offset);
private:
devcb_write_line m_intl_handler;
devcb_write_line m_intr_handler;
devcb_write_line m_intl_callback;
devcb_write_line m_intr_callback;
};
// ======================> mb8421_device
@ -61,9 +104,9 @@ private:
class mb8421_device : public mb8421_master_device
{
public:
mb8421_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
mb8421_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock = 0);
u8 peek(offs_t offset) { return m_ram[offset & 0x7ff]; }
u8 peek(offs_t offset) const { return m_ram[offset & 0x7ff]; }
DECLARE_WRITE8_MEMBER(left_w);
DECLARE_READ8_MEMBER(left_r);
@ -83,9 +126,9 @@ private:
class mb8421_mb8431_16_device : public mb8421_master_device
{
public:
mb8421_mb8431_16_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
mb8421_mb8431_16_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock = 0);
u16 peek(offs_t offset) { return m_ram[offset & 0x7ff]; }
u16 peek(offs_t offset) const { return m_ram[offset & 0x7ff]; }
DECLARE_WRITE16_MEMBER(left_w);
DECLARE_READ16_MEMBER(left_r);

6
src/mame/drivers/dassault.cpp
View File

@ -541,9 +541,9 @@ MACHINE_CONFIG_START(dassault_state::dassault)
// MCFG_QUANTUM_TIME(attotime::from_hz(8400)) /* 140 CPU slices per frame */
MCFG_QUANTUM_PERFECT_CPU("maincpu") // I was seeing random lockups.. let's see if this helps
MCFG_DEVICE_ADD("sharedram", MB8421_MB8431_16BIT, 0)
MCFG_MB8421_INTL_HANDLER(INPUTLINE("maincpu", M68K_IRQ_5))
MCFG_MB8421_INTR_HANDLER(INPUTLINE("sub", M68K_IRQ_6))
mb8421_mb8431_16_device &sharedram(MB8421_MB8431_16BIT(config, "sharedram"));
sharedram.intl_callback().set_inputline("maincpu", M68K_IRQ_5);
sharedram.intr_callback().set_inputline("sub", M68K_IRQ_6);
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)

6
src/mame/drivers/pve500.cpp
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@ -440,9 +440,9 @@ MACHINE_CONFIG_START(pve500_state::pve500)
clk1.signal_handler().append(m_subcpu, FUNC(tmpz84c015_device::txcb_w));
/* ICF5: 2kbytes of RAM shared between the two CPUs (dual-port RAM)*/
MCFG_DEVICE_ADD("mb8421", MB8421, 0)
MCFG_MB8421_INTL_HANDLER(WRITELINE(*this, pve500_state, mb8421_intl))
MCFG_MB8421_INTR_HANDLER(WRITELINE(*this, pve500_state, mb8421_intr))
mb8421_device &mb8421(MB8421(config, "mb8421"));
mb8421.intl_callback().set(FUNC(pve500_state::mb8421_intl));
mb8421.intr_callback().set(FUNC(pve500_state::mb8421_intr));
/* video hardware */
config.set_default_layout(layout_pve500);

4
src/mame/drivers/segam1.cpp
View File

@ -375,8 +375,8 @@ MACHINE_CONFIG_START(segam1_state::segam1)
MCFG_DEVICE_ADD("uart", I8251, 4000000) // unknown clock
MCFG_DEVICE_ADD("dpram", MB8421, 0)
MCFG_MB8421_INTL_HANDLER(INPUTLINE("m1comm", 0))
mb8421_device &dpram(MB8421(config, "dpram"));
dpram.intl_callback().set_inputline("m1comm", 0);
MCFG_DEVICE_ADD("tile", S24TILE, 0, 0x3fff)
MCFG_GFX_PALETTE("palette")

6
src/mame/drivers/segaybd.cpp
View File

@ -1363,9 +1363,9 @@ MACHINE_CONFIG_START(segaybd_state::yboard_link)
MCFG_DEVICE_PROGRAM_MAP(link_map)
MCFG_DEVICE_IO_MAP(link_portmap)
MCFG_DEVICE_ADD("mb8421", MB8421, 0)
MCFG_MB8421_INTL_HANDLER(WRITELINE(*this, segaybd_state, mb8421_intl))
MCFG_MB8421_INTR_HANDLER(WRITELINE(*this, segaybd_state, mb8421_intr))
mb8421_device &mb8421(MB8421(config, "mb8421"));
mb8421.intl_callback().set(FUNC(segaybd_state::mb8421_intl));
mb8421.intr_callback().set(FUNC(segaybd_state::mb8421_intr));
MACHINE_CONFIG_END
MACHINE_CONFIG_START(segaybd_state::yboard_deluxe)

8
src/mame/drivers/taito_l.cpp
View File

@ -1582,7 +1582,7 @@ MACHINE_CONFIG_START(taitol_2cpu_state::raimais)
tc0040ioc.write_4_callback().set(FUNC(taitol_state::coin_control_w));
tc0040ioc.read_7_callback().set_ioport("IN2");
MB8421(config, "dpram", 0);
MB8421(config, "dpram");
MCFG_MACHINE_START_OVERRIDE(taitol_state, taito_l)
MCFG_MACHINE_RESET_OVERRIDE(taitol_state, taito_l)
@ -1626,7 +1626,7 @@ MACHINE_CONFIG_START(taitol_2cpu_state::kurikint)
tc0040ioc.write_4_callback().set(FUNC(taitol_state::coin_control_w));
tc0040ioc.read_7_callback().set_ioport("IN2");
MB8421(config, "dpram", 0);
MB8421(config, "dpram");
MCFG_MACHINE_START_OVERRIDE(taitol_state, taito_l)
MCFG_MACHINE_RESET_OVERRIDE(taitol_state, taito_l)
@ -1773,8 +1773,8 @@ MACHINE_CONFIG_START(taitol_2cpu_state::evilston)
tc0510nio.write_4_callback().set(FUNC(taitol_state::coin_control_w));
tc0510nio.read_7_callback().set_ioport("IN2");
MCFG_DEVICE_ADD("dpram", MB8421, 0)
MCFG_MB8421_INTL_HANDLER(INPUTLINE("audiocpu", INPUT_LINE_NMI))
mb8421_device &dpram(MB8421(config, "dpram"));
dpram.intl_callback().set_inputline("audiocpu", INPUT_LINE_NMI);
MCFG_MACHINE_START_OVERRIDE(taitol_state, taito_l)
MCFG_MACHINE_RESET_OVERRIDE(taitol_state, taito_l)