decstation: added LANCE controller, started IRQ handling in gate array. [R. Belmont]

src/mame/drivers/decstation.cpp

@@ -67,6 +67,7 @@
 #include "machine/nscsi_cd.h"
 #include "machine/nscsi_hd.h"
 #include "machine/dec_lk201.h"
+#include "machine/am79c90.h"
 #include "bus/rs232/rs232.h"
 #include "screen.h"
 #include "video/bt459.h"
@@ -85,7 +86,8 @@ public:
 		m_scc1(*this, "scc1"),
 		m_asc(*this, "scsibus:7:asc"),
 		m_vrom(*this, "gfx"),
-		m_bt459(*this, "bt459")
+		m_bt459(*this, "bt459"),
+		m_lance(*this, "am79c90")
 		{ }
 
 	void kn02ba(machine_config &config);
@@ -94,6 +96,7 @@ public:
 
 protected:
 	DECLARE_READ_LINE_MEMBER(brcond0_r) { return ASSERT_LINE; }
+	DECLARE_WRITE_LINE_MEMBER(ioga_irq_w);
 
 	DECLARE_READ32_MEMBER(cfb_r);
 	DECLARE_WRITE32_MEMBER(cfb_w);
@@ -107,7 +110,7 @@ private:
 
 	uint32_t screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
 
-	required_device<cpu_device> m_maincpu;
+	required_device<r3041_device> m_maincpu;
 	required_device<screen_device> m_screen;
 	required_device<lk201_device> m_lk201;
 	required_device<dec_ioga_device> m_ioga;
@@ -116,6 +119,7 @@ private:
 	required_device<ncr53c94_device> m_asc;
 	required_memory_region m_vrom;
 	required_device<bt459_device> m_bt459;
+	required_device<am79c90_device> m_lance;
 
 	void threemin_map(address_map &map);
 
@@ -298,6 +302,12 @@ WRITE32_MEMBER(decstation_state::cfb_w)
     MACHINE FUNCTIONS
 ***************************************************************************/
 
+WRITE_LINE_MEMBER(decstation_state::ioga_irq_w)
+{
+	// not sure this is correct
+	m_maincpu->set_input_line(R3000_IRQ3, state);
+}
+
 void decstation_state::machine_start()
 {
 	m_vrom_ptr = m_vrom->base();
@@ -321,6 +331,7 @@ void decstation_state::threemin_map(address_map &map)
 	map(0x10000000, 0x13ffffff).rw(FUNC(decstation_state::cfb_r), FUNC(decstation_state::cfb_w));
 	map(0x101c0000, 0x101c000f).m("bt459", FUNC(bt459_device::map)).umask32(0x000000ff);
 	map(0x1c000000, 0x1c07ffff).m(m_ioga, FUNC(dec_ioga_device::map));
+	map(0x1c0c0000, 0x1c0c0007).rw(m_lance, FUNC(am79c90_device::regs_r), FUNC(am79c90_device::regs_w)).umask32(0x0000ffff);
 	map(0x1c100000, 0x1c100003).rw(m_scc0, FUNC(z80scc_device::ca_r), FUNC(z80scc_device::ca_w)).umask32(0x0000ff00);
 	map(0x1c100004, 0x1c100007).rw(m_scc0, FUNC(z80scc_device::da_r), FUNC(z80scc_device::da_w)).umask32(0x0000ff00);
 	map(0x1c100008, 0x1c10000b).rw(m_scc0, FUNC(z80scc_device::cb_r), FUNC(z80scc_device::cb_w)).umask32(0x0000ff00);
@@ -364,19 +375,23 @@ MACHINE_CONFIG_START(decstation_state::kn02ba)
 
 	BT459(config, m_bt459, 83'020'800);
 
+	AM79C90(config, m_lance, XTAL(12'500'000));
+	m_lance->irq_out().set("ioga", FUNC(dec_ioga_device::lance_irq_w));
+
 	DECSTATION_IOGA(config, m_ioga, XTAL(12'500'000));
+	m_ioga->irq_out().set(FUNC(decstation_state::ioga_irq_w));
 
 	MC146818(config, m_rtc, XTAL(32'768));
 	m_rtc->irq().set("ioga", FUNC(dec_ioga_device::rtc_irq_w));
 	m_rtc->set_binary(true);
 
 	SCC85C30(config, m_scc0, XTAL(14'745'600)/2);
-	//m_scc0->out_int_callback().set("ioga", FUNC(dec_ioga_device::scc0_irq_w));
+	m_scc0->out_int_callback().set("ioga", FUNC(dec_ioga_device::scc0_irq_w));
 	m_scc0->out_txda_callback().set("rs232a", FUNC(rs232_port_device::write_txd));
 	m_scc0->out_txdb_callback().set("rs232b", FUNC(rs232_port_device::write_txd));
 
 	SCC85C30(config, m_scc1, XTAL(14'745'600)/2);
-	//m_scc1->out_int_callback().set("ioga", FUNC(dec_ioga_device::scc1_irq_w));
+	m_scc1->out_int_callback().set("ioga", FUNC(dec_ioga_device::scc1_irq_w));
 	m_scc1->out_txdb_callback().set("lk201", FUNC(lk201_device::rx_w));
 
 	MCFG_DEVICE_ADD("lk201", LK201, 0)

src/mame/machine/decioga.cpp

@@ -2,7 +2,7 @@
 // copyright-holders:R. Belmont
 /******************************************************************************
 *
-*   MIPS DECstation I/O Gate Array emulation
+*   MIPS DECstation and AlphaStation I/O Gate Array emulation
 *   This IC contains some address decoding, an interrupt controller, and
 *   a multi-channel DMA engine.
 */
@@ -20,12 +20,15 @@ void dec_ioga_device::map(address_map &map)
 }
 
 dec_ioga_device::dec_ioga_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
-	: device_t(mconfig, DECSTATION_IOGA, tag, owner, clock)
+	: device_t(mconfig, DECSTATION_IOGA, tag, owner, clock),
+	m_irq_out_cb(*this)
 {
 }
 
 void dec_ioga_device::device_start()
 {
+	m_irq_out_cb.resolve_safe();
+
 	save_item(NAME(m_csr));
 	save_item(NAME(m_intr));
 	save_item(NAME(m_imsk));
@@ -58,10 +61,21 @@ READ32_MEMBER(dec_ioga_device::intr_r)
 {
 	uint32_t rv = m_intr;
 	m_intr &= ~0x20;        // 5000/133 boot ROM tests that reading clears this bit
-	//printf("m_intr = %08x\n", m_intr);
 	return rv;
 }
 
+void dec_ioga_device::recalc_irq()
+{
+	if ((m_intr & m_imsk) != 0)
+	{
+		m_irq_out_cb(ASSERT_LINE);
+	}
+	else
+	{
+		m_irq_out_cb(CLEAR_LINE);
+	}
+}
+
 WRITE32_MEMBER(dec_ioga_device::intr_w)
 {
 	m_intr &= ~data;    // clear bits on write
@@ -83,4 +97,44 @@ WRITE_LINE_MEMBER(dec_ioga_device::rtc_irq_w)
 	{
 		m_intr |= 0x20; // tested by 5000/133 boot ROM circa BFC027C8
 	}
+	recalc_irq();
+}
+
+WRITE_LINE_MEMBER(dec_ioga_device::lance_irq_w)
+{
+	if (state == ASSERT_LINE)
+	{
+		m_intr |= 0x100;
+	}
+	else
+	{
+		m_intr &= ~0x100;
+	}
+	recalc_irq();
+}
+
+WRITE_LINE_MEMBER(dec_ioga_device::scc0_irq_w)
+{
+	if (state == ASSERT_LINE)
+	{
+		m_intr |= 0x40;
+	}
+	else
+	{
+		m_intr &= ~0x40;
+	}
+	recalc_irq();
+}
+
+WRITE_LINE_MEMBER(dec_ioga_device::scc1_irq_w)
+{
+	if (state == ASSERT_LINE)
+	{
+		m_intr |= 0x80;
+	}
+	else
+	{
+		m_intr &= ~0x80;
+	}
+	recalc_irq();
 }

src/mame/machine/decioga.h

@@ -21,6 +21,12 @@ public:
 
 	// irq inputs
 	DECLARE_WRITE_LINE_MEMBER(rtc_irq_w);
+	DECLARE_WRITE_LINE_MEMBER(lance_irq_w);
+	DECLARE_WRITE_LINE_MEMBER(scc0_irq_w);
+	DECLARE_WRITE_LINE_MEMBER(scc1_irq_w);
+
+	// multiplex irq output
+	auto irq_out() { return m_irq_out_cb.bind(); }
 
 protected:
 	virtual void device_start() override;
@@ -32,8 +38,13 @@ protected:
 	DECLARE_WRITE32_MEMBER(intr_w);
 	DECLARE_READ32_MEMBER(imsk_r);
 	DECLARE_WRITE32_MEMBER(imsk_w);
+
 private:
 	uint32_t m_csr, m_intr, m_imsk;
+
+	devcb_write_line m_irq_out_cb;
+
+	void recalc_irq();
 };
 
 DECLARE_DEVICE_TYPE(DECSTATION_IOGA, dec_ioga_device)