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m37710: Rename some registers to agree with Mitsubishi documentation

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This commit is contained in:
AJR 2020-05-14 22:02:59 -04:00
parent 4b654dc9c0
commit a4fb8f4376
6 changed files with 180 additions and 183 deletions
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110
src/devices/cpu/m37710/m37710.cpp
View File

@ -644,14 +644,14 @@ uint16_t m37710_cpu_device::ad_result_r(offs_t offset)
{ {
uint16_t result = m_ad_result[offset]; uint16_t result = m_ad_result[offset];
LOGMASKED(LOG_AD, "ad_result_r from %02x: A/D %d = %x (PC=%x)\n", (int)(offset * 2) + 0x20, offset, result, REG_PB<<16 | REG_PC); LOGMASKED(LOG_AD, "ad_result_r from %02x: A/D %d = %x (PC=%x)\n", (int)(offset * 2) + 0x20, offset, result, REG_PG | REG_PC);
return result; return result;
} }
uint8_t m37710_cpu_device::uart0_mode_r() uint8_t m37710_cpu_device::uart0_mode_r()
{ {
LOGMASKED(LOG_UART, "uart0_mode_r: UART0 transmit/recv mode = %x (PC=%x)\n", m_uart_mode[0], REG_PB<<16 | REG_PC); LOGMASKED(LOG_UART, "uart0_mode_r: UART0 transmit/recv mode = %x (PC=%x)\n", m_uart_mode[0], REG_PG | REG_PC);
return m_uart_mode[0]; return m_uart_mode[0];
} }
@ -665,7 +665,7 @@ void m37710_cpu_device::uart0_mode_w(uint8_t data)
uint8_t m37710_cpu_device::uart1_mode_r() uint8_t m37710_cpu_device::uart1_mode_r()
{ {
LOGMASKED(LOG_UART, "uart1_mode_r: UART1 transmit/recv mode = %x (PC=%x)\n", m_uart_mode[1], REG_PB<<16 | REG_PC); LOGMASKED(LOG_UART, "uart1_mode_r: UART1 transmit/recv mode = %x (PC=%x)\n", m_uart_mode[1], REG_PG | REG_PC);
return m_uart_mode[1]; return m_uart_mode[1];
} }
@ -703,7 +703,7 @@ void m37710_cpu_device::uart1_tbuf_w(uint16_t data)
uint8_t m37710_cpu_device::uart0_ctrl_reg0_r() uint8_t m37710_cpu_device::uart0_ctrl_reg0_r()
{ {
LOGMASKED(LOG_UART, "uart0_ctrl_reg0_r: UART0 transmit/recv ctrl 0 = %x (PC=%x)\n", m_uart_ctrl_reg0[0], REG_PB<<16 | REG_PC); LOGMASKED(LOG_UART, "uart0_ctrl_reg0_r: UART0 transmit/recv ctrl 0 = %x (PC=%x)\n", m_uart_ctrl_reg0[0], REG_PG | REG_PC);
return m_uart_ctrl_reg0[0]; return m_uart_ctrl_reg0[0];
} }
@ -718,7 +718,7 @@ void m37710_cpu_device::uart0_ctrl_reg0_w(uint8_t data)
uint8_t m37710_cpu_device::uart1_ctrl_reg0_r() uint8_t m37710_cpu_device::uart1_ctrl_reg0_r()
{ {
LOGMASKED(LOG_UART, "uart1_ctrl_reg0_r: UART1 transmit/recv ctrl 0 = %x (PC=%x)\n", m_uart_ctrl_reg0[1], REG_PB<<16 | REG_PC); LOGMASKED(LOG_UART, "uart1_ctrl_reg0_r: UART1 transmit/recv ctrl 0 = %x (PC=%x)\n", m_uart_ctrl_reg0[1], REG_PG | REG_PC);
return m_uart_ctrl_reg0[1]; return m_uart_ctrl_reg0[1];
} }
@ -733,7 +733,7 @@ void m37710_cpu_device::uart1_ctrl_reg0_w(uint8_t data)
uint8_t m37710_cpu_device::uart0_ctrl_reg1_r() uint8_t m37710_cpu_device::uart0_ctrl_reg1_r()
{ {
LOGMASKED(LOG_UART, "uart0_ctrl_reg1_r: UART0 transmit/recv ctrl 1 = %x (PC=%x)\n", m_uart_ctrl_reg1[0], REG_PB<<16 | REG_PC); LOGMASKED(LOG_UART, "uart0_ctrl_reg1_r: UART0 transmit/recv ctrl 1 = %x (PC=%x)\n", m_uart_ctrl_reg1[0], REG_PG | REG_PC);
return m_uart_ctrl_reg1[0]; return m_uart_ctrl_reg1[0];
} }
@ -747,7 +747,7 @@ void m37710_cpu_device::uart0_ctrl_reg1_w(uint8_t data)
uint8_t m37710_cpu_device::uart1_ctrl_reg1_r() uint8_t m37710_cpu_device::uart1_ctrl_reg1_r()
{ {
LOGMASKED(LOG_UART, "uart1_ctrl_reg1_r: UART1 transmit/recv ctrl 1 = %x (PC=%x)\n", m_uart_ctrl_reg1[1], REG_PB<<16 | REG_PC); LOGMASKED(LOG_UART, "uart1_ctrl_reg1_r: UART1 transmit/recv ctrl 1 = %x (PC=%x)\n", m_uart_ctrl_reg1[1], REG_PG | REG_PC);
return m_uart_ctrl_reg1[1]; return m_uart_ctrl_reg1[1];
} }
@ -761,21 +761,21 @@ void m37710_cpu_device::uart1_ctrl_reg1_w(uint8_t data)
uint16_t m37710_cpu_device::uart0_rbuf_r() uint16_t m37710_cpu_device::uart0_rbuf_r()
{ {
LOGMASKED(LOG_UART, "uart0_rbuf_r: UART0 recv buf (PC=%x)\n", REG_PB<<16 | REG_PC); LOGMASKED(LOG_UART, "uart0_rbuf_r: UART0 recv buf (PC=%x)\n", REG_PG | REG_PC);
return 0; return 0;
} }
uint16_t m37710_cpu_device::uart1_rbuf_r() uint16_t m37710_cpu_device::uart1_rbuf_r()
{ {
LOGMASKED(LOG_UART, "uart1_rbuf_r: UART1 recv buf (PC=%x)\n", REG_PB<<16 | REG_PC); LOGMASKED(LOG_UART, "uart1_rbuf_r: UART1 recv buf (PC=%x)\n", REG_PG | REG_PC);
return 0; return 0;
} }
uint8_t m37710_cpu_device::count_start_r() uint8_t m37710_cpu_device::count_start_r()
{ {
LOGMASKED(LOG_TIMER, "count_start_r: Count start = %x (PC=%x)\n", m_count_start, REG_PB<<16 | REG_PC); LOGMASKED(LOG_TIMER, "count_start_r: Count start = %x (PC=%x)\n", m_count_start, REG_PG | REG_PC);
return m_count_start; return m_count_start;
} }
@ -801,7 +801,7 @@ void m37710_cpu_device::one_shot_start_w(uint8_t data)
uint8_t m37710_cpu_device::up_down_r() uint8_t m37710_cpu_device::up_down_r()
{ {
LOGMASKED(LOG_TIMER, "up_down_r: Up-down register = %x (PC=%x)\n", m_up_down_reg, REG_PB<<16 | REG_PC); LOGMASKED(LOG_TIMER, "up_down_r: Up-down register = %x (PC=%x)\n", m_up_down_reg, REG_PG | REG_PC);
// bits 7-5 read back as 0 // bits 7-5 read back as 0
return m_up_down_reg & 0x1f; return m_up_down_reg & 0x1f;
@ -828,7 +828,7 @@ void m37710_cpu_device::timer_reg_w(offs_t offset, uint16_t data, uint16_t mem_m
uint8_t m37710_cpu_device::timer_mode_r(offs_t offset) uint8_t m37710_cpu_device::timer_mode_r(offs_t offset)
{ {
LOGMASKED(LOG_TIMER, "timer_mode_r from %02x: Timer %s mode = %x (PC=%x)\n", (int)offset + 0x56, m37710_tnames[offset], m_timer_mode[offset], REG_PB<<16 | REG_PC); LOGMASKED(LOG_TIMER, "timer_mode_r from %02x: Timer %s mode = %x (PC=%x)\n", (int)offset + 0x56, m37710_tnames[offset], m_timer_mode[offset], REG_PG | REG_PC);
return m_timer_mode[offset]; return m_timer_mode[offset];
} }
@ -842,7 +842,7 @@ void m37710_cpu_device::timer_mode_w(offs_t offset, uint8_t data)
uint8_t m37710_cpu_device::proc_mode_r(offs_t offset) uint8_t m37710_cpu_device::proc_mode_r(offs_t offset)
{ {
LOGMASKED(LOG_GENERAL, "proc_mode_r: Processor mode = %x (PC=%x)\n", m_proc_mode, REG_PB<<16 | REG_PC); LOGMASKED(LOG_GENERAL, "proc_mode_r: Processor mode = %x (PC=%x)\n", m_proc_mode, REG_PG | REG_PC);
return m_proc_mode & 0xf7; return m_proc_mode & 0xf7;
} }
@ -873,7 +873,7 @@ void m37710_cpu_device::watchdog_freq_w(uint8_t data)
uint8_t m37710_cpu_device::waveform_mode_r() uint8_t m37710_cpu_device::waveform_mode_r()
{ {
LOGMASKED(LOG_GENERAL, "waveform_mode_r: Waveform output mode (PC=%x)\n", REG_PB<<16 | REG_PC); LOGMASKED(LOG_GENERAL, "waveform_mode_r: Waveform output mode (PC=%x)\n", REG_PG | REG_PC);
return 0; return 0;
} }
@ -885,7 +885,7 @@ void m37710_cpu_device::waveform_mode_w(uint8_t data)
uint8_t m37710_cpu_device::rto_control_r() uint8_t m37710_cpu_device::rto_control_r()
{ {
LOGMASKED(LOG_GENERAL, "rto_control_r: Real-time output control = %x (PC=%x)\n", m_rto_control, REG_PB<<16 | REG_PC); LOGMASKED(LOG_GENERAL, "rto_control_r: Real-time output control = %x (PC=%x)\n", m_rto_control, REG_PG | REG_PC);
return m_rto_control; return m_rto_control;
} }
@ -899,7 +899,7 @@ void m37710_cpu_device::rto_control_w(uint8_t data)
uint8_t m37710_cpu_device::dram_control_r() uint8_t m37710_cpu_device::dram_control_r()
{ {
LOGMASKED(LOG_GENERAL, "dram_control_r: DRAM control = %x (PC=%x)\n", m_dram_control, REG_PB<<16 | REG_PC); LOGMASKED(LOG_GENERAL, "dram_control_r: DRAM control = %x (PC=%x)\n", m_dram_control, REG_PG | REG_PC);
return m_dram_control; return m_dram_control;
} }
@ -932,7 +932,7 @@ uint8_t m37710_cpu_device::get_int_control(int level)
{ {
assert(level < M37710_MASKABLE_INTERRUPTS); assert(level < M37710_MASKABLE_INTERRUPTS);
//LOGMASKED(LOG_INT, "int_control_r: %s IRQ ctrl = %x (PC=%x)\n", m37710_intnames[level], m_int_control[level], REG_PB<<16 | REG_PC); //LOGMASKED(LOG_INT, "int_control_r: %s IRQ ctrl = %x (PC=%x)\n", m37710_intnames[level], m_int_control[level], REG_PG | REG_PC);
uint8_t result = m_int_control[level]; uint8_t result = m_int_control[level];
@ -1025,7 +1025,7 @@ void m37710_cpu_device::m37710i_update_irqs()
if (!FLAG_I && thispri > curpri && thispri > m_ipl) if (!FLAG_I && thispri > curpri && thispri > m_ipl)
{ {
// mark us as the best candidate // mark us as the best candidate
LOGMASKED(LOG_INT, "%s interrupt active with priority %d (PC=%x)\n", m37710_intnames[curirq], thispri, REG_PB<<16 | REG_PC); LOGMASKED(LOG_INT, "%s interrupt active with priority %d (PC=%x)\n", m37710_intnames[curirq], thispri, REG_PG | REG_PC);
wantedIRQ = curirq; wantedIRQ = curirq;
curpri = thispri; curpri = thispri;
} }
@ -1033,7 +1033,7 @@ void m37710_cpu_device::m37710i_update_irqs()
else else
{ {
// non-maskable // non-maskable
LOGMASKED(LOG_INT, "%s interrupt active (PC=%x)\n", m37710_intnames[curirq], REG_PB<<16 | REG_PC); LOGMASKED(LOG_INT, "%s interrupt active (PC=%x)\n", m37710_intnames[curirq], REG_PG | REG_PC);
wantedIRQ = curirq; wantedIRQ = curirq;
curpri = 7; curpri = 7;
break; // no more processing, NMIs always win break; // no more processing, NMIs always win
@ -1054,16 +1054,16 @@ void m37710_cpu_device::m37710i_update_irqs()
// let's do it... // let's do it...
// push PB, then PC, then status // push PB, then PC, then status
CLK(13); CLK(13);
m37710i_push_8(REG_PB>>16); m37710i_push_8(REG_PG>>16);
m37710i_push_16(REG_PC); m37710i_push_16(REG_PC);
m37710i_push_8(m_ipl); m37710i_push_8(m_ipl);
m37710i_push_8(m37710i_get_reg_p()); m37710i_push_8(m37710i_get_reg_ps());
// set I to 1, set IPL to the interrupt we're taking // set I to 1, set IPL to the interrupt we're taking
FLAG_I = IFLAG_SET; FLAG_I = IFLAG_SET;
m_ipl = curpri; m_ipl = curpri;
// then PB=0, PC=(vector) // then PG=0, PC=(vector)
REG_PB = 0; REG_PG = 0;
REG_PC = m37710_read_16(m37710_irq_vectors[wantedIRQ]); REG_PC = m37710_read_16(m37710_irq_vectors[wantedIRQ]);
} }
} }
@ -1131,9 +1131,9 @@ void m37710_cpu_device::device_reset()
IRQ_DELAY = 0; IRQ_DELAY = 0;
/* 37710 boots in full native mode */ /* 37710 boots in full native mode */
REG_D = 0; REG_DPR = 0;
REG_PB = 0; REG_PG = 0;
REG_DB = 0; REG_DT = 0;
REG_S = (REG_S & 0xff) | 0x100; REG_S = (REG_S & 0xff) | 0x100;
REG_XH = REG_X & 0xff00; REG_X &= 0xff; REG_XH = REG_X & 0xff00; REG_X &= 0xff;
REG_YH = REG_Y & 0xff00; REG_Y &= 0xff; REG_YH = REG_Y & 0xff00; REG_Y &= 0xff;
@ -1268,9 +1268,9 @@ void m37710_cpu_device::device_start()
m_s = 0; m_s = 0;
m_pc = 0; m_pc = 0;
m_ppc = 0; m_ppc = 0;
m_pb = 0; m_pg = 0;
m_db = 0; m_dt = 0;
m_d = 0; m_dpr = 0;
m_flag_e = 0; m_flag_e = 0;
m_flag_m = 0; m_flag_m = 0;
m_flag_x = 0; m_flag_x = 0;
@ -1339,9 +1339,9 @@ void m37710_cpu_device::device_start()
save_item(NAME(m_s)); save_item(NAME(m_s));
save_item(NAME(m_pc)); save_item(NAME(m_pc));
save_item(NAME(m_ppc)); save_item(NAME(m_ppc));
save_item(NAME(m_pb)); save_item(NAME(m_pg));
save_item(NAME(m_db)); save_item(NAME(m_dt));
save_item(NAME(m_d)); save_item(NAME(m_dpr));
save_item(NAME(m_flag_e)); save_item(NAME(m_flag_e));
save_item(NAME(m_flag_m)); save_item(NAME(m_flag_m));
save_item(NAME(m_flag_x)); save_item(NAME(m_flag_x));
@ -1390,11 +1390,11 @@ void m37710_cpu_device::device_start()
machine().save().register_postload(save_prepost_delegate(save_prepost_delegate(FUNC(m37710_cpu_device::m37710_restore_state), this))); machine().save().register_postload(save_prepost_delegate(save_prepost_delegate(FUNC(m37710_cpu_device::m37710_restore_state), this)));
state_add( M37710_PC, "PC", m_pc).formatstr("%04X"); state_add( M37710_PC, "PC", m_pc).formatstr("%04X");
state_add( M37710_PB, "PB", m_debugger_pb).callimport().callexport().formatstr("%02X"); state_add( M37710_PG, "PG", m_debugger_pg).callimport().callexport().formatstr("%02X");
state_add( M37710_DB, "DB", m_debugger_db).callimport().callexport().formatstr("%02X"); state_add( M37710_DT, "DT", m_debugger_dt).callimport().callexport().formatstr("%02X");
state_add( M37710_D, "D", m_d).formatstr("%04X"); state_add( M37710_DPR, "DPR", m_dpr).formatstr("%04X");
state_add( M37710_S, "S", m_s).formatstr("%04X"); state_add( M37710_S, "S", m_s).formatstr("%04X");
state_add( M37710_P, "P", m_debugger_p).callimport().callexport().formatstr("%04X"); state_add( M37710_PS, "PS", m_debugger_ps).callimport().callexport().formatstr("%04X");
state_add( M37710_E, "E", m_flag_e).formatstr("%01X"); state_add( M37710_E, "E", m_flag_e).formatstr("%01X");
state_add( M37710_A, "A", m_debugger_a).callimport().callexport().formatstr("%04X"); state_add( M37710_A, "A", m_debugger_a).callimport().callexport().formatstr("%04X");
state_add( M37710_B, "B", m_debugger_b).callimport().callexport().formatstr("%04X"); state_add( M37710_B, "B", m_debugger_b).callimport().callexport().formatstr("%04X");
@ -1404,7 +1404,7 @@ void m37710_cpu_device::device_start()
state_add( STATE_GENPC, "GENPC", m_debugger_pc ).callimport().callexport().noshow(); state_add( STATE_GENPC, "GENPC", m_debugger_pc ).callimport().callexport().noshow();
state_add( STATE_GENPCBASE, "CURPC", m_debugger_pc ).callimport().callexport().noshow(); state_add( STATE_GENPCBASE, "CURPC", m_debugger_pc ).callimport().callexport().noshow();
state_add( STATE_GENFLAGS, "GENFLAGS", m_debugger_p ).formatstr("%8s").noshow(); state_add( STATE_GENFLAGS, "GENFLAGS", m_debugger_ps ).formatstr("%8s").noshow();
set_icountptr(m_ICount); set_icountptr(m_ICount);
} }
@ -1414,17 +1414,17 @@ void m37710_cpu_device::state_import(const device_state_entry &entry)
{ {
switch (entry.index()) switch (entry.index())
{ {
case M37710_PB: case M37710_PG:
m37710_set_reg(M37710_PB, m_debugger_pb); m37710_set_reg(M37710_PG, m_debugger_pg);
break; break;
case M37710_DB: case M37710_DT:
m37710_set_reg(M37710_DB, m_debugger_db); m37710_set_reg(M37710_DT, m_debugger_dt);
break; break;
case M37710_P: case M37710_PS:
m37710_set_reg(M37710_P, m_debugger_p&0xff); m37710_set_reg(M37710_PS, m_debugger_ps&0xff);
m_ipl = (m_debugger_p>>8)&0xff; m_ipl = (m_debugger_ps>>8)&0xff;
break; break;
case M37710_A: case M37710_A:
@ -1437,7 +1437,7 @@ void m37710_cpu_device::state_import(const device_state_entry &entry)
case STATE_GENPC: case STATE_GENPC:
case STATE_GENPCBASE: case STATE_GENPCBASE:
REG_PB = m_debugger_pc & 0xff0000; REG_PG = m_debugger_pc & 0xff0000;
m37710_set_pc(m_debugger_pc & 0xffff); m37710_set_pc(m_debugger_pc & 0xffff);
break; break;
} }
@ -1448,16 +1448,16 @@ void m37710_cpu_device::state_export(const device_state_entry &entry)
{ {
switch (entry.index()) switch (entry.index())
{ {
case M37710_PB: case M37710_PG:
m_debugger_pb = m_pb >> 16; m_debugger_pg = m_pg >> 16;
break; break;
case M37710_DB: case M37710_DT:
m_debugger_db = m_db >> 16; m_debugger_dt = m_dt >> 16;
break; break;
case M37710_P: case M37710_PS:
m_debugger_p = (m_flag_n&0x80) | ((m_flag_v>>1)&0x40) | m_flag_m | m_flag_x | m_flag_d | m_flag_i | ((!m_flag_z)<<1) | ((m_flag_c>>8)&1) | (m_ipl<<8); m_debugger_ps = (m_flag_n&0x80) | ((m_flag_v>>1)&0x40) | m_flag_m | m_flag_x | m_flag_d | m_flag_i | ((!m_flag_z)<<1) | ((m_flag_c>>8)&1) | (m_ipl<<8);
break; break;
case M37710_A: case M37710_A:
@ -1470,7 +1470,7 @@ void m37710_cpu_device::state_export(const device_state_entry &entry)
case STATE_GENPC: case STATE_GENPC:
case STATE_GENPCBASE: case STATE_GENPCBASE:
m_debugger_pc = (REG_PB | REG_PC); m_debugger_pc = (REG_PG | REG_PC);
break; break;
} }
} }
@ -1549,12 +1549,12 @@ void m37710_cpu_device::m37710i_set_execution_mode(uint32_t mode)
void m37710_cpu_device::m37710i_interrupt_software(uint32_t vector) void m37710_cpu_device::m37710i_interrupt_software(uint32_t vector)
{ {
CLK(13); CLK(13);
m37710i_push_8(REG_PB>>16); m37710i_push_8(REG_PG>>16);
m37710i_push_16(REG_PC); m37710i_push_16(REG_PC);
m37710i_push_8(m_ipl); m37710i_push_8(m_ipl);
m37710i_push_8(m37710i_get_reg_p()); m37710i_push_8(m37710i_get_reg_ps());
FLAG_I = IFLAG_SET; FLAG_I = IFLAG_SET;
REG_PB = 0; REG_PG = 0;
REG_PC = m37710_read_16(vector); REG_PC = m37710_read_16(vector);
} }

31
src/devices/cpu/m37710/m37710.h
View File

@ -83,8 +83,8 @@ enum
/* Registers - used by m37710_set_reg() and m37710_get_reg() */ /* Registers - used by m37710_set_reg() and m37710_get_reg() */
enum enum
{ {
M37710_PC=1, M37710_S, M37710_P, M37710_A, M37710_B, M37710_X, M37710_Y, M37710_PC=1, M37710_S, M37710_PS, M37710_A, M37710_B, M37710_X, M37710_Y,
M37710_PB, M37710_DB, M37710_D, M37710_E, M37710_PG, M37710_DT, M37710_DPR, M37710_E,
M37710_NMI_STATE, M37710_IRQ_STATE M37710_NMI_STATE, M37710_IRQ_STATE
}; };
@ -247,9 +247,9 @@ private:
uint32_t m_s; /* Stack Pointer */ uint32_t m_s; /* Stack Pointer */
uint32_t m_pc; /* Program Counter */ uint32_t m_pc; /* Program Counter */
uint32_t m_ppc; /* Previous Program Counter */ uint32_t m_ppc; /* Previous Program Counter */
uint32_t m_pb; /* Program Bank (shifted left 16) */ uint32_t m_pg; /* Program Bank (shifted left 16) */
uint32_t m_db; /* Data Bank (shifted left 16) */ uint32_t m_dt; /* Data Bank (shifted left 16) */
uint32_t m_d; /* Direct Register */ uint32_t m_dpr; /* Direct Page Register */
uint32_t m_flag_e; /* Emulation Mode Flag */ uint32_t m_flag_e; /* Emulation Mode Flag */
uint32_t m_flag_m; /* Memory/Accumulator Select Flag */ uint32_t m_flag_m; /* Memory/Accumulator Select Flag */
uint32_t m_flag_x; /* Index Select Flag */ uint32_t m_flag_x; /* Index Select Flag */
@ -308,19 +308,16 @@ private:
uint16_t m_dmac_control; uint16_t m_dmac_control;
// DMA // DMA
uint32_t m_dma0_src, m_dma0_dst, m_dma0_cnt, m_dma0_mode; uint32_t m_dma_src[4], m_dma_dst[4], m_dma_cnt[4], m_dma_mode[4];
uint32_t m_dma1_src, m_dma1_dst, m_dma1_cnt, m_dma1_mode;
uint32_t m_dma2_src, m_dma2_dst, m_dma2_cnt, m_dma2_mode;
uint32_t m_dma3_src, m_dma3_dst, m_dma3_cnt, m_dma3_mode;
// interrupt controller // interrupt controller
uint8_t m_int_control[M37710_MASKABLE_INTERRUPTS]; uint8_t m_int_control[M37710_MASKABLE_INTERRUPTS];
// for debugger // for debugger
uint32_t m_debugger_pc; uint32_t m_debugger_pc;
uint32_t m_debugger_pb; uint32_t m_debugger_pg;
uint32_t m_debugger_db; uint32_t m_debugger_dt;
uint32_t m_debugger_p; uint32_t m_debugger_ps;
uint32_t m_debugger_a; uint32_t m_debugger_a;
uint32_t m_debugger_b; uint32_t m_debugger_b;
@ -407,17 +404,17 @@ private:
void m37710i_jump_24(uint32_t address); void m37710i_jump_24(uint32_t address);
void m37710i_branch_8(uint32_t offset); void m37710i_branch_8(uint32_t offset);
void m37710i_branch_16(uint32_t offset); void m37710i_branch_16(uint32_t offset);
uint32_t m37710i_get_reg_p(); uint32_t m37710i_get_reg_ps();
void m37710i_set_reg_ipl(uint32_t value); void m37710i_set_reg_ipl(uint32_t value);
void m37710i_interrupt_software(uint32_t vector); void m37710i_interrupt_software(uint32_t vector);
void m37710i_set_flag_m0x0(uint32_t value); void m37710i_set_flag_m0x0(uint32_t value);
void m37710i_set_flag_m0x1(uint32_t value); void m37710i_set_flag_m0x1(uint32_t value);
void m37710i_set_flag_m1x0(uint32_t value); void m37710i_set_flag_m1x0(uint32_t value);
void m37710i_set_flag_m1x1(uint32_t value); void m37710i_set_flag_m1x1(uint32_t value);
void m37710i_set_reg_p_m0x0(uint32_t value); void m37710i_set_reg_ps_m0x0(uint32_t value);
void m37710i_set_reg_p_m0x1(uint32_t value); void m37710i_set_reg_ps_m0x1(uint32_t value);
void m37710i_set_reg_p_m1x0(uint32_t value); void m37710i_set_reg_ps_m1x0(uint32_t value);
void m37710i_set_reg_p_m1x1(uint32_t value); void m37710i_set_reg_ps_m1x1(uint32_t value);
uint32_t EA_IMM8(); uint32_t EA_IMM8();
uint32_t EA_IMM16(); uint32_t EA_IMM16();
uint32_t EA_IMM24(); uint32_t EA_IMM24();

6
src/devices/cpu/m37710/m37710cm.h
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@ -73,9 +73,9 @@ static inline int MAKE_INT_8(int A) {return (A & 0x80) ? A | ~0xff : A & 0xff;}
#define REG_S m_s /* Stack Pointer */ #define REG_S m_s /* Stack Pointer */
#define REG_PC m_pc /* Program Counter */ #define REG_PC m_pc /* Program Counter */
#define REG_PPC m_ppc /* Previous Program Counter */ #define REG_PPC m_ppc /* Previous Program Counter */
#define REG_PB m_pb /* Program Bank */ #define REG_PG m_pg /* Program Bank */
#define REG_DB m_db /* Data Bank */ #define REG_DT m_dt /* Data Bank */
#define REG_D m_d /* Direct Register */ #define REG_DPR m_dpr /* Direct Page Register */
#define FLAG_M m_flag_m /* Memory/Accumulator Select Flag */ #define FLAG_M m_flag_m /* Memory/Accumulator Select Flag */
#define FLAG_X m_flag_x /* Index Select Flag */ #define FLAG_X m_flag_x /* Index Select Flag */
#define FLAG_N m_flag_n /* Negative Flag */ #define FLAG_N m_flag_n /* Negative Flag */

26
src/devices/cpu/m37710/m37710il.h
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@ -142,7 +142,7 @@ inline void m37710_cpu_device::m37710i_jump_16(uint32_t address)
inline void m37710_cpu_device::m37710i_jump_24(uint32_t address) inline void m37710_cpu_device::m37710i_jump_24(uint32_t address)
{ {
REG_PB = address&0xff0000; REG_PG = address&0xff0000;
REG_PC = MAKE_UINT_16(address); REG_PC = MAKE_UINT_16(address);
} }
@ -161,7 +161,7 @@ inline void m37710_cpu_device::m37710i_branch_16(uint32_t offset)
/* ============================ STATUS REGISTER =========================== */ /* ============================ STATUS REGISTER =========================== */
/* ======================================================================== */ /* ======================================================================== */
inline uint32_t m37710_cpu_device::m37710i_get_reg_p() inline uint32_t m37710_cpu_device::m37710i_get_reg_ps()
{ {
return (FLAG_N&0x80) | return (FLAG_N&0x80) |
((FLAG_V>>1)&0x40) | ((FLAG_V>>1)&0x40) |
@ -183,26 +183,26 @@ inline void m37710_cpu_device::m37710i_set_reg_ipl(uint32_t value)
/* ============================= ADDRESS MODES ============================ */ /* ============================= ADDRESS MODES ============================ */
/* ======================================================================== */ /* ======================================================================== */
inline uint32_t m37710_cpu_device::EA_IMM8() {REG_PC += 1; return REG_PB | MAKE_UINT_16(REG_PC-1);} inline uint32_t m37710_cpu_device::EA_IMM8() {REG_PC += 1; return REG_PG | MAKE_UINT_16(REG_PC-1);}
inline uint32_t m37710_cpu_device::EA_IMM16() {REG_PC += 2; return REG_PB | MAKE_UINT_16(REG_PC-2);} inline uint32_t m37710_cpu_device::EA_IMM16() {REG_PC += 2; return REG_PG | MAKE_UINT_16(REG_PC-2);}
inline uint32_t m37710_cpu_device::EA_IMM24() {REG_PC += 3; return REG_PB | MAKE_UINT_16(REG_PC-3);} inline uint32_t m37710_cpu_device::EA_IMM24() {REG_PC += 3; return REG_PG | MAKE_UINT_16(REG_PC-3);}
inline uint32_t m37710_cpu_device::EA_D() {if(MAKE_UINT_8(REG_D)) CLK(1); return MAKE_UINT_16(REG_D + OPER_8_IMM());} inline uint32_t m37710_cpu_device::EA_D() {if(MAKE_UINT_8(REG_DPR)) CLK(1); return MAKE_UINT_16(REG_DPR + OPER_8_IMM());}
inline uint32_t m37710_cpu_device::EA_A() {return REG_DB | OPER_16_IMM();} inline uint32_t m37710_cpu_device::EA_A() {return REG_DT | OPER_16_IMM();}
inline uint32_t m37710_cpu_device::EA_AL() {return OPER_24_IMM();} inline uint32_t m37710_cpu_device::EA_AL() {return OPER_24_IMM();}
inline uint32_t m37710_cpu_device::EA_DX() {return MAKE_UINT_16(REG_D + OPER_8_IMM() + REG_X);} inline uint32_t m37710_cpu_device::EA_DX() {return MAKE_UINT_16(REG_DPR + OPER_8_IMM() + REG_X);}
inline uint32_t m37710_cpu_device::EA_DY() {return MAKE_UINT_16(REG_D + OPER_8_IMM() + REG_Y);} inline uint32_t m37710_cpu_device::EA_DY() {return MAKE_UINT_16(REG_DPR + OPER_8_IMM() + REG_Y);}
inline uint32_t m37710_cpu_device::EA_AX() {uint32_t tmp = EA_A(); if((tmp^(tmp+REG_X))&0xff00) CLK(1); return tmp + REG_X;} inline uint32_t m37710_cpu_device::EA_AX() {uint32_t tmp = EA_A(); if((tmp^(tmp+REG_X))&0xff00) CLK(1); return tmp + REG_X;}
inline uint32_t m37710_cpu_device::EA_ALX() {return EA_AL() + REG_X;} inline uint32_t m37710_cpu_device::EA_ALX() {return EA_AL() + REG_X;}
inline uint32_t m37710_cpu_device::EA_AY() {uint32_t tmp = EA_A(); if((tmp^(tmp+REG_X))&0xff00) CLK(1); return tmp + REG_Y;} inline uint32_t m37710_cpu_device::EA_AY() {uint32_t tmp = EA_A(); if((tmp^(tmp+REG_X))&0xff00) CLK(1); return tmp + REG_Y;}
inline uint32_t m37710_cpu_device::EA_DI() {return REG_DB | OPER_16_D();} inline uint32_t m37710_cpu_device::EA_DI() {return REG_DT | OPER_16_D();}
inline uint32_t m37710_cpu_device::EA_DLI() {return OPER_24_D();} inline uint32_t m37710_cpu_device::EA_DLI() {return OPER_24_D();}
inline uint32_t m37710_cpu_device::EA_AI() {return read_16_A(OPER_16_IMM());} inline uint32_t m37710_cpu_device::EA_AI() {return read_16_A(OPER_16_IMM());}
inline uint32_t m37710_cpu_device::EA_ALI() {return OPER_24_A();} inline uint32_t m37710_cpu_device::EA_ALI() {return OPER_24_A();}
inline uint32_t m37710_cpu_device::EA_DXI() {return REG_DB | OPER_16_DX();} inline uint32_t m37710_cpu_device::EA_DXI() {return REG_DT | OPER_16_DX();}
inline uint32_t m37710_cpu_device::EA_DIY() {uint32_t tmp = REG_DB | OPER_16_D(); if((tmp^(tmp+REG_X))&0xff00) CLK(1); return tmp + REG_Y;} inline uint32_t m37710_cpu_device::EA_DIY() {uint32_t tmp = REG_DT | OPER_16_D(); if((tmp^(tmp+REG_X))&0xff00) CLK(1); return tmp + REG_Y;}
inline uint32_t m37710_cpu_device::EA_DLIY() {return OPER_24_D() + REG_Y;} inline uint32_t m37710_cpu_device::EA_DLIY() {return OPER_24_D() + REG_Y;}
inline uint32_t m37710_cpu_device::EA_AXI() {return read_16_AXI(MAKE_UINT_16(OPER_16_IMM() + REG_X));} inline uint32_t m37710_cpu_device::EA_AXI() {return read_16_AXI(MAKE_UINT_16(OPER_16_IMM() + REG_X));}
inline uint32_t m37710_cpu_device::EA_S() {return MAKE_UINT_16(REG_S + OPER_8_IMM());} inline uint32_t m37710_cpu_device::EA_S() {return MAKE_UINT_16(REG_S + OPER_8_IMM());}
inline uint32_t m37710_cpu_device::EA_SIY() {return MAKE_UINT_16(read_16_SIY(REG_S + OPER_8_IMM()) + REG_Y) | REG_DB;} inline uint32_t m37710_cpu_device::EA_SIY() {return MAKE_UINT_16(read_16_SIY(REG_S + OPER_8_IMM()) + REG_Y) | REG_DT;}
#endif /* __M37710IL_H__ */ #endif /* __M37710IL_H__ */

174
src/devices/cpu/m37710/m37710op.h
View File

@ -7,28 +7,28 @@
#undef FLAG_SET_M #undef FLAG_SET_M
#undef FLAG_SET_X #undef FLAG_SET_X
#undef m37710i_set_flag_mx #undef m37710i_set_flag_mx
#undef m37710i_set_reg_p #undef m37710i_set_reg_ps
#if EXECUTION_MODE == EXECUTION_MODE_M0X0 #if EXECUTION_MODE == EXECUTION_MODE_M0X0
#define FLAG_SET_M 0 #define FLAG_SET_M 0
#define FLAG_SET_X 0 #define FLAG_SET_X 0
#define m37710i_set_flag_mx m37710i_set_flag_m0x0 #define m37710i_set_flag_mx m37710i_set_flag_m0x0
#define m37710i_set_reg_p m37710i_set_reg_p_m0x0 #define m37710i_set_reg_ps m37710i_set_reg_ps_m0x0
#elif EXECUTION_MODE == EXECUTION_MODE_M0X1 #elif EXECUTION_MODE == EXECUTION_MODE_M0X1
#define FLAG_SET_M 0 #define FLAG_SET_M 0
#define FLAG_SET_X 1 #define FLAG_SET_X 1
#define m37710i_set_flag_mx m37710i_set_flag_m0x1 #define m37710i_set_flag_mx m37710i_set_flag_m0x1
#define m37710i_set_reg_p m37710i_set_reg_p_m0x1 #define m37710i_set_reg_ps m37710i_set_reg_ps_m0x1
#elif EXECUTION_MODE == EXECUTION_MODE_M1X0 #elif EXECUTION_MODE == EXECUTION_MODE_M1X0
#define FLAG_SET_M 1 #define FLAG_SET_M 1
#define FLAG_SET_X 0 #define FLAG_SET_X 0
#define m37710i_set_flag_mx m37710i_set_flag_m1x0 #define m37710i_set_flag_mx m37710i_set_flag_m1x0
#define m37710i_set_reg_p m37710i_set_reg_p_m1x0 #define m37710i_set_reg_ps m37710i_set_reg_ps_m1x0
#elif EXECUTION_MODE == EXECUTION_MODE_M1X1 #elif EXECUTION_MODE == EXECUTION_MODE_M1X1
#define FLAG_SET_M 1 #define FLAG_SET_M 1
#define FLAG_SET_X 1 #define FLAG_SET_X 1
#define m37710i_set_flag_mx m37710i_set_flag_m1x1 #define m37710i_set_flag_mx m37710i_set_flag_m1x1
#define m37710i_set_reg_p m37710i_set_reg_p_m1x1 #define m37710i_set_reg_ps m37710i_set_reg_ps_m1x1
#endif #endif
/* ======================================================================== */ /* ======================================================================== */
@ -82,7 +82,7 @@ void m37710_cpu_device::m37710i_set_flag_mx(uint32_t value)
} }
void m37710_cpu_device::m37710i_set_reg_p(uint32_t value) void m37710_cpu_device::m37710i_set_reg_ps(uint32_t value)
{ {
FLAG_N = value; FLAG_N = value;
FLAG_V = value << 1; FLAG_V = value << 1;
@ -115,13 +115,13 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
if (SRC&0x8) \ if (SRC&0x8) \
{ m37710i_push_8(REG_Y); CLK(2); } \ { m37710i_push_8(REG_Y); CLK(2); } \
if (SRC&0x10) \ if (SRC&0x10) \
{ m37710i_push_16(REG_D); CLK(2); } \ { m37710i_push_16(REG_DPR); CLK(2); } \
if (SRC&0x20) \ if (SRC&0x20) \
{ m37710i_push_8(REG_DB>>16); CLK(1); } \ { m37710i_push_8(REG_DT>>16); CLK(1); } \
if (SRC&0x40) \ if (SRC&0x40) \
{ m37710i_push_8(REG_PB>>16); CLK(1); } \ { m37710i_push_8(REG_PG>>16); CLK(1); } \
if (SRC&0x80) \ if (SRC&0x80) \
{ m37710i_push_8(m_ipl); m37710i_push_8(m37710i_get_reg_p()); CLK(2); } { m37710i_push_8(m_ipl); m37710i_push_8(m37710i_get_reg_ps()); CLK(2); }
#else // FLAG_SET_X #else // FLAG_SET_X
#define OP_PSH(MODE) \ #define OP_PSH(MODE) \
SRC = OPER_8_##MODE(); \ SRC = OPER_8_##MODE(); \
@ -135,13 +135,13 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
if (SRC&0x8) \ if (SRC&0x8) \
{ m37710i_push_16(REG_Y); CLK(2); } \ { m37710i_push_16(REG_Y); CLK(2); } \
if (SRC&0x10) \ if (SRC&0x10) \
{ m37710i_push_16(REG_D); CLK(2); } \ { m37710i_push_16(REG_DPR); CLK(2); } \
if (SRC&0x20) \ if (SRC&0x20) \
{ m37710i_push_8(REG_DB>>16); CLK(1); } \ { m37710i_push_8(REG_DT>>16); CLK(1); } \
if (SRC&0x40) \ if (SRC&0x40) \
{ m37710i_push_8(REG_PB>>16); CLK(1); } \ { m37710i_push_8(REG_PG>>16); CLK(1); } \
if (SRC&0x80) \ if (SRC&0x80) \
{ m37710i_push_8(m_ipl); m37710i_push_8(m37710i_get_reg_p()); CLK(2); } { m37710i_push_8(m_ipl); m37710i_push_8(m37710i_get_reg_ps()); CLK(2); }
#endif // FLAG_SET_X #endif // FLAG_SET_X
#else // FLAG_SET_M #else // FLAG_SET_M
#if FLAG_SET_X #if FLAG_SET_X
@ -157,13 +157,13 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
if (SRC&0x8) \ if (SRC&0x8) \
{ m37710i_push_8(REG_Y); CLK(2); } \ { m37710i_push_8(REG_Y); CLK(2); } \
if (SRC&0x10) \ if (SRC&0x10) \
{ m37710i_push_16(REG_D); CLK(2); } \ { m37710i_push_16(REG_DPR); CLK(2); } \
if (SRC&0x20) \ if (SRC&0x20) \
{ m37710i_push_8(REG_DB>>16); CLK(1); } \ { m37710i_push_8(REG_DT>>16); CLK(1); } \
if (SRC&0x40) \ if (SRC&0x40) \
{ m37710i_push_8(REG_PB>>16); CLK(1); } \ { m37710i_push_8(REG_PG>>16); CLK(1); } \
if (SRC&0x80) \ if (SRC&0x80) \
{ m37710i_push_8(m_ipl); m37710i_push_8(m37710i_get_reg_p()); CLK(2); } { m37710i_push_8(m_ipl); m37710i_push_8(m37710i_get_reg_ps()); CLK(2); }
#else // FLAG_SET_X #else // FLAG_SET_X
#define OP_PSH(MODE) \ #define OP_PSH(MODE) \
SRC = OPER_8_##MODE(); \ SRC = OPER_8_##MODE(); \
@ -177,13 +177,13 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
if (SRC&0x8) \ if (SRC&0x8) \
{ m37710i_push_16(REG_Y); CLK(2); } \ { m37710i_push_16(REG_Y); CLK(2); } \
if (SRC&0x10) \ if (SRC&0x10) \
{ m37710i_push_16(REG_D); CLK(2); } \ { m37710i_push_16(REG_DPR); CLK(2); } \
if (SRC&0x20) \ if (SRC&0x20) \
{ m37710i_push_8(REG_DB>>16); CLK(1); } \ { m37710i_push_8(REG_DT>>16); CLK(1); } \
if (SRC&0x40) \ if (SRC&0x40) \
{ m37710i_push_8(REG_PB>>16); CLK(1); } \ { m37710i_push_8(REG_PG>>16); CLK(1); } \
if (SRC&0x80) \ if (SRC&0x80) \
{ m37710i_push_8(m_ipl); m37710i_push_8(m37710i_get_reg_p()); CLK(2); } { m37710i_push_8(m_ipl); m37710i_push_8(m37710i_get_reg_ps()); CLK(2); }
#endif // FLAG_SET_X #endif // FLAG_SET_X
#endif // FLAG_SET_M #endif // FLAG_SET_M
@ -194,12 +194,12 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
SRC = OPER_8_##MODE(); \ SRC = OPER_8_##MODE(); \
CLK(14); \ CLK(14); \
if (SRC&0x80) \ if (SRC&0x80) \
{ m37710i_set_reg_p(m37710i_pull_8()); m37710i_set_reg_ipl(m37710i_pull_8()); CLK(3); } \ { m37710i_set_reg_ps(m37710i_pull_8()); m37710i_set_reg_ipl(m37710i_pull_8()); CLK(3); } \
if (SRC&0x20) \ if (SRC&0x20) \
{ REG_DB = m37710i_pull_8() << 16; CLK(3); } \ { REG_DT = m37710i_pull_8() << 16; CLK(3); } \
if (SRC&0x10) \ if (SRC&0x10) \
{ REG_D = m37710i_pull_16(); CLK(4); } \ { REG_DPR = m37710i_pull_16(); CLK(4); } \
if (m37710i_get_reg_p() & XFLAG_SET) \ if (m37710i_get_reg_ps() & XFLAG_SET) \
{ \ { \
if (SRC&0x8) \ if (SRC&0x8) \
{ REG_Y = m37710i_pull_8(); CLK(3); } \ { REG_Y = m37710i_pull_8(); CLK(3); } \
@ -213,7 +213,7 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
if (SRC&0x4) \ if (SRC&0x4) \
{ REG_X = m37710i_pull_16(); CLK(3); } \ { REG_X = m37710i_pull_16(); CLK(3); } \
} \ } \
if (m37710i_get_reg_p() & MFLAG_SET) \ if (m37710i_get_reg_ps() & MFLAG_SET) \
{ \ { \
if (SRC&0x2) \ if (SRC&0x2) \
{ REG_BA = m37710i_pull_8(); CLK(3); } \ { REG_BA = m37710i_pull_8(); CLK(3); } \
@ -462,7 +462,7 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
#undef OP_BRK #undef OP_BRK
#define OP_BRK() \ #define OP_BRK() \
REG_PC++; CLK(CLK_OP + CLK_R8 + CLK_IMM); \ REG_PC++; CLK(CLK_OP + CLK_R8 + CLK_IMM); \
logerror("error M37710: BRK at PC=%06x\n", REG_PB|REG_PC); \ logerror("error M37710: BRK at PC=%06x\n", REG_PG|REG_PC); \
m37710i_interrupt_software(0xfffa) m37710i_interrupt_software(0xfffa)
/* M37710 Branch Always */ /* M37710 Branch Always */
@ -704,7 +704,7 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
#undef OP_JMPAXI #undef OP_JMPAXI
#define OP_JMPAXI() \ #define OP_JMPAXI() \
CLK(CLK_OP + CLK_AXI); \ CLK(CLK_OP + CLK_AXI); \
m37710i_jump_16(read_16_AXI(REG_PB | (MAKE_UINT_16(OPER_16_IMM() + REG_X)))) m37710i_jump_16(read_16_AXI(REG_PG | (MAKE_UINT_16(OPER_16_IMM() + REG_X))))
/* M37710 Jump absolute long */ /* M37710 Jump absolute long */
#undef OP_JMPAL #undef OP_JMPAL
@ -717,7 +717,7 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
#define OP_JSL(MODE) \ #define OP_JSL(MODE) \
CLK(CLK_OP + CLK_W24 + CLK_##MODE + 1); \ CLK(CLK_OP + CLK_W24 + CLK_##MODE + 1); \
DST = EA_##MODE(); \ DST = EA_##MODE(); \
m37710i_push_8(REG_PB>>16); \ m37710i_push_8(REG_PG>>16); \
m37710i_push_16(REG_PC); \ m37710i_push_16(REG_PC); \
m37710i_jump_24(DST) m37710i_jump_24(DST)
@ -733,7 +733,7 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
#undef OP_JSRAXI #undef OP_JSRAXI
#define OP_JSRAXI() \ #define OP_JSRAXI() \
CLK(CLK_OP + CLK_W16 + CLK_AXI); \ CLK(CLK_OP + CLK_W16 + CLK_AXI); \
DST = read_16_AXI(REG_PB | (MAKE_UINT_16(OPER_16_IMM() + REG_X))); \ DST = read_16_AXI(REG_PG | (MAKE_UINT_16(OPER_16_IMM() + REG_X))); \
m37710i_push_16(REG_PC); \ m37710i_push_16(REG_PC); \
m37710i_jump_16(DST) m37710i_jump_16(DST)
@ -769,14 +769,14 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
#define OP_LDM(MODE) \ #define OP_LDM(MODE) \
CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
REG_IM2 = EA_##MODE(); \ REG_IM2 = EA_##MODE(); \
REG_IM = read_8_IMM(REG_PB | REG_PC); \ REG_IM = read_8_IMM(REG_PG | REG_PC); \
REG_PC++; \ REG_PC++; \
write_8_##MODE(REG_IM2, REG_IM) write_8_##MODE(REG_IM2, REG_IM)
#else #else
#define OP_LDM(MODE) \ #define OP_LDM(MODE) \
CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
REG_IM2 = EA_##MODE(); \ REG_IM2 = EA_##MODE(); \
REG_IM = read_16_IMM(REG_PB | REG_PC); \ REG_IM = read_16_IMM(REG_PG | REG_PC); \
REG_PC+=2; \ REG_PC+=2; \
write_16_##MODE(REG_IM2, REG_IM) write_16_##MODE(REG_IM2, REG_IM)
#endif #endif
@ -787,7 +787,7 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
#define OP_BBS(MODE) \ #define OP_BBS(MODE) \
CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
REG_IM2 = read_8_NORM(EA_##MODE()); \ REG_IM2 = read_8_NORM(EA_##MODE()); \
REG_IM = read_8_IMM(REG_PB | REG_PC); \ REG_IM = read_8_IMM(REG_PG | REG_PC); \
REG_PC++; \ REG_PC++; \
DST = OPER_8_IMM(); \ DST = OPER_8_IMM(); \
if ((REG_IM2 & REG_IM) == REG_IM) \ if ((REG_IM2 & REG_IM) == REG_IM) \
@ -800,7 +800,7 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
#define OP_BBS(MODE) \ #define OP_BBS(MODE) \
CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
REG_IM2 = read_16_NORM(EA_##MODE()); \ REG_IM2 = read_16_NORM(EA_##MODE()); \
REG_IM = read_16_IMM(REG_PB | REG_PC); \ REG_IM = read_16_IMM(REG_PG | REG_PC); \
REG_PC++; \ REG_PC++; \
REG_PC++; \ REG_PC++; \
DST = OPER_8_IMM(); \ DST = OPER_8_IMM(); \
@ -818,7 +818,7 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
#define OP_BBC(MODE) \ #define OP_BBC(MODE) \
CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
REG_IM2 = read_8_NORM(EA_##MODE()); \ REG_IM2 = read_8_NORM(EA_##MODE()); \
REG_IM = read_8_IMM(REG_PB | REG_PC); \ REG_IM = read_8_IMM(REG_PG | REG_PC); \
REG_PC++; \ REG_PC++; \
DST = OPER_8_IMM(); \ DST = OPER_8_IMM(); \
if ((REG_IM2 & REG_IM) == 0) \ if ((REG_IM2 & REG_IM) == 0) \
@ -831,7 +831,7 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
#define OP_BBC(MODE) \ #define OP_BBC(MODE) \
CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
REG_IM2 = read_16_NORM(EA_##MODE()); \ REG_IM2 = read_16_NORM(EA_##MODE()); \
REG_IM = read_16_IMM(REG_PB | REG_PC); \ REG_IM = read_16_IMM(REG_PG | REG_PC); \
REG_PC++; \ REG_PC++; \
REG_PC++; \ REG_PC++; \
DST = OPER_8_IMM(); \ DST = OPER_8_IMM(); \
@ -933,7 +933,7 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
#define OP_MVN() \ #define OP_MVN() \
DST = OPER_8_IMM()<<16; \ DST = OPER_8_IMM()<<16; \
SRC = OPER_8_IMM()<<16; \ SRC = OPER_8_IMM()<<16; \
REG_DB = DST; \ REG_DT = DST; \
REG_A |= REG_B; \ REG_A |= REG_B; \
CLK(7); \ CLK(7); \
if (REG_A > 0) \ if (REG_A > 0) \
@ -963,7 +963,7 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
#define OP_MVN() \ #define OP_MVN() \
DST = OPER_8_IMM()<<16; \ DST = OPER_8_IMM()<<16; \
SRC = OPER_8_IMM()<<16; \ SRC = OPER_8_IMM()<<16; \
REG_DB = DST; \ REG_DT = DST; \
REG_A |= REG_B; \ REG_A |= REG_B; \
CLK(7); \ CLK(7); \
if (REG_A > 0) \ if (REG_A > 0) \
@ -997,7 +997,7 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
#define OP_MVP() \ #define OP_MVP() \
DST = OPER_8_IMM()<<16; \ DST = OPER_8_IMM()<<16; \
SRC = OPER_8_IMM()<<16; \ SRC = OPER_8_IMM()<<16; \
REG_DB = DST; \ REG_DT = DST; \
REG_A |= REG_B; \ REG_A |= REG_B; \
CLK(7); \ CLK(7); \
if (REG_A > 0) \ if (REG_A > 0) \
@ -1027,7 +1027,7 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
#define OP_MVP() \ #define OP_MVP() \
DST = OPER_8_IMM()<<16; \ DST = OPER_8_IMM()<<16; \
SRC = OPER_8_IMM()<<16; \ SRC = OPER_8_IMM()<<16; \
REG_DB = DST; \ REG_DT = DST; \
REG_A |= REG_B; \ REG_A |= REG_B; \
CLK(7); \ CLK(7); \
if (REG_A > 0) \ if (REG_A > 0) \
@ -1145,26 +1145,26 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
#undef OP_PHT #undef OP_PHT
#define OP_PHT() \ #define OP_PHT() \
CLK(CLK_OP + CLK_W8 + 1); \ CLK(CLK_OP + CLK_W8 + 1); \
m37710i_push_8(REG_DB>>16) m37710i_push_8(REG_DT>>16)
/* M37710 Push direct register */ /* M37710 Push direct page register */
#undef OP_PHD #undef OP_PHD
#define OP_PHD() \ #define OP_PHD() \
CLK(CLK_OP + CLK_W16 + 1); \ CLK(CLK_OP + CLK_W16 + 1); \
m37710i_push_16(REG_D) m37710i_push_16(REG_DPR)
/* M37710 Push program bank register */ /* M37710 Push program bank register */
#undef OP_PHK #undef OP_PHK
#define OP_PHK() \ #define OP_PHK() \
CLK(CLK_OP + CLK_W8 + 1); \ CLK(CLK_OP + CLK_W8 + 1); \
m37710i_push_8(REG_PB>>16) m37710i_push_8(REG_PG>>16)
/* M37710 Push the Processor Status Register to the stack */ /* M37710 Push the Processor Status Register to the stack */
#undef OP_PHP #undef OP_PHP
#define OP_PHP() \ #define OP_PHP() \
CLK(CLK_OP + CLK_W8 + 1); \ CLK(CLK_OP + CLK_W8 + 1); \
m37710i_push_8(m_ipl); \ m37710i_push_8(m_ipl); \
m37710i_push_8(m37710i_get_reg_p()) m37710i_push_8(m37710i_get_reg_ps())
/* M37710 Pull accumulator from the stack */ /* M37710 Pull accumulator from the stack */
#undef OP_PLA #undef OP_PLA
@ -1210,19 +1210,19 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
#define OP_PLT() \ #define OP_PLT() \
CLK(CLK_OP + CLK_R8 + 2); \ CLK(CLK_OP + CLK_R8 + 2); \
FLAG_N = FLAG_Z = m37710i_pull_8(); \ FLAG_N = FLAG_Z = m37710i_pull_8(); \
REG_DB = FLAG_Z << 16 REG_DT = FLAG_Z << 16
/* M37710 Pull direct register */ /* M37710 Pull direct page register */
#undef OP_PLD #undef OP_PLD
#define OP_PLD() \ #define OP_PLD() \
CLK(CLK_OP + CLK_R16 + 2); \ CLK(CLK_OP + CLK_R16 + 2); \
REG_D = m37710i_pull_16() REG_DPR = m37710i_pull_16()
/* M37710 Pull the Processor Status Register from the stack */ /* M37710 Pull the Processor Status Register from the stack */
#undef OP_PLP #undef OP_PLP
#define OP_PLP() \ #define OP_PLP() \
CLK(CLK_OP + CLK_R8 + 2); \ CLK(CLK_OP + CLK_R8 + 2); \
m37710i_set_reg_p(m37710i_pull_8()); \ m37710i_set_reg_ps(m37710i_pull_8()); \
m37710i_set_reg_ipl(m37710i_pull_8()); \ m37710i_set_reg_ipl(m37710i_pull_8()); \
m37710i_update_irqs() m37710i_update_irqs()
@ -1230,14 +1230,14 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
#undef OP_REP #undef OP_REP
#define OP_REP() \ #define OP_REP() \
CLK(CLK_OP + CLK_R8 + 1); \ CLK(CLK_OP + CLK_R8 + 1); \
m37710i_set_reg_p(m37710i_get_reg_p() & ~OPER_8_IMM()); \ m37710i_set_reg_ps(m37710i_get_reg_ps() & ~OPER_8_IMM()); \
m37710i_update_irqs() m37710i_update_irqs()
/* M37710 Clear "M" status bit */ /* M37710 Clear "M" status bit */
#undef OP_CLM #undef OP_CLM
#define OP_CLM() \ #define OP_CLM() \
CLK(CLK_OP + CLK_R8 + 1); \ CLK(CLK_OP + CLK_R8 + 1); \
m37710i_set_reg_p(m37710i_get_reg_p() & ~FLAGPOS_M) m37710i_set_reg_ps(m37710i_get_reg_ps() & ~FLAGPOS_M)
/* M37710 Rotate Left the accumulator */ /* M37710 Rotate Left the accumulator */
#undef OP_ROL #undef OP_ROL
@ -1360,10 +1360,10 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
#undef OP_RTI #undef OP_RTI
#define OP_RTI() \ #define OP_RTI() \
CLK(8); \ CLK(8); \
m37710i_set_reg_p(m37710i_pull_8()); \ m37710i_set_reg_ps(m37710i_pull_8()); \
m37710i_set_reg_ipl(m37710i_pull_8()); \ m37710i_set_reg_ipl(m37710i_pull_8()); \
m37710i_jump_16(m37710i_pull_16()); \ m37710i_jump_16(m37710i_pull_16()); \
REG_PB = m37710i_pull_8() << 16; \ REG_PG = m37710i_pull_8() << 16; \
m37710i_update_irqs() m37710i_update_irqs()
/* M37710 Return from Subroutine Long */ /* M37710 Return from Subroutine Long */
@ -1513,13 +1513,13 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
#undef OP_SEP #undef OP_SEP
#define OP_SEP() \ #define OP_SEP() \
CLK(CLK_OP + CLK_R8 + 1); \ CLK(CLK_OP + CLK_R8 + 1); \
m37710i_set_reg_p(m37710i_get_reg_p() | OPER_8_IMM()) m37710i_set_reg_ps(m37710i_get_reg_ps() | OPER_8_IMM())
/* M37710 Set "M" status bit */ /* M37710 Set "M" status bit */
#undef OP_SEM #undef OP_SEM
#define OP_SEM() \ #define OP_SEM() \
CLK(CLK_OP + CLK_R8 + 1); \ CLK(CLK_OP + CLK_R8 + 1); \
m37710i_set_reg_p(m37710i_get_reg_p() | FLAGPOS_M) m37710i_set_reg_ps(m37710i_get_reg_ps() | FLAGPOS_M)
/* M37710 Store accumulator to memory */ /* M37710 Store accumulator to memory */
#undef OP_STA #undef OP_STA
@ -1648,59 +1648,59 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
FLAG_N = NFLAG_16(FLAG_Z) FLAG_N = NFLAG_16(FLAG_Z)
#endif #endif
/* M37710 Transfer accumulator to direct register */ /* M37710 Transfer accumulator to direct page register */
#undef OP_TAD #undef OP_TAD
#if FLAG_SET_M #if FLAG_SET_M
#define OP_TAD() \ #define OP_TAD() \
CLK(CLK_OP + CLK_IMPLIED); \ CLK(CLK_OP + CLK_IMPLIED); \
REG_D = REG_A | REG_B REG_DPR = REG_A | REG_B
#else #else
#define OP_TAD() \ #define OP_TAD() \
CLK(CLK_OP + CLK_IMPLIED); \ CLK(CLK_OP + CLK_IMPLIED); \
REG_D = REG_A REG_DPR = REG_A
#endif #endif
/* M37710 Transfer accumulator B to direct register */ /* M37710 Transfer accumulator B to direct page register */
#undef OP_TBD #undef OP_TBD
#if FLAG_SET_M #if FLAG_SET_M
#define OP_TBD() \ #define OP_TBD() \
CLK(CLK_OP + CLK_IMPLIED); \ CLK(CLK_OP + CLK_IMPLIED); \
REG_D = REG_BA | REG_BB REG_DPR = REG_BA | REG_BB
#else #else
#define OP_TBD() \ #define OP_TBD() \
CLK(CLK_OP + CLK_IMPLIED); \ CLK(CLK_OP + CLK_IMPLIED); \
REG_D = REG_BA REG_DPR = REG_BA
#endif #endif
/* M37710 Transfer direct register to accumulator */ /* M37710 Transfer direct page register to accumulator */
#undef OP_TDA #undef OP_TDA
#if FLAG_SET_M #if FLAG_SET_M
#define OP_TDA() \ #define OP_TDA() \
CLK(CLK_OP + CLK_IMPLIED); \ CLK(CLK_OP + CLK_IMPLIED); \
FLAG_Z = REG_D; \ FLAG_Z = REG_DPR; \
FLAG_N = NFLAG_16(FLAG_Z); \ FLAG_N = NFLAG_16(FLAG_Z); \
REG_A = MAKE_UINT_8(REG_D); \ REG_A = MAKE_UINT_8(REG_DPR); \
REG_B = REG_D & 0xff00 REG_B = REG_DPR & 0xff00
#else #else
#define OP_TDA() \ #define OP_TDA() \
CLK(CLK_OP + CLK_IMPLIED); \ CLK(CLK_OP + CLK_IMPLIED); \
FLAG_Z = REG_A = REG_D; \ FLAG_Z = REG_A = REG_DPR; \
FLAG_N = NFLAG_16(FLAG_Z) FLAG_N = NFLAG_16(FLAG_Z)
#endif #endif
/* M37710 Transfer direct register to accumulator B */ /* M37710 Transfer direct page register to accumulator B */
#undef OP_TDB #undef OP_TDB
#if FLAG_SET_M #if FLAG_SET_M
#define OP_TDB() \ #define OP_TDB() \
CLK(CLK_OP + CLK_IMPLIED); \ CLK(CLK_OP + CLK_IMPLIED); \
FLAG_Z = REG_D; \ FLAG_Z = REG_DPR; \
FLAG_N = NFLAG_16(FLAG_Z); \ FLAG_N = NFLAG_16(FLAG_Z); \
REG_BA = MAKE_UINT_8(REG_D); \ REG_BA = MAKE_UINT_8(REG_DPR); \
REG_BB = REG_D & 0xff00 REG_BB = REG_DPR & 0xff00
#else #else
#define OP_TDB() \ #define OP_TDB() \
CLK(CLK_OP + CLK_IMPLIED); \ CLK(CLK_OP + CLK_IMPLIED); \
FLAG_Z = REG_BA = REG_D; \ FLAG_Z = REG_BA = REG_DPR; \
FLAG_N = NFLAG_16(FLAG_Z) FLAG_N = NFLAG_16(FLAG_Z)
#endif #endif
@ -1821,7 +1821,7 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \ CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \
DST = EA_##MODE(); \ DST = EA_##MODE(); \
REG_IM = read_8_##MODE(DST); \ REG_IM = read_8_##MODE(DST); \
REG_IM2 = read_8_IMM(REG_PB | REG_PC); \ REG_IM2 = read_8_IMM(REG_PG | REG_PC); \
REG_PC++; \ REG_PC++; \
write_8_##MODE(DST, REG_IM & ~REG_IM2); write_8_##MODE(DST, REG_IM & ~REG_IM2);
#else #else
@ -1829,7 +1829,7 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \ CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \
DST = EA_##MODE(); \ DST = EA_##MODE(); \
REG_IM = read_16_##MODE(DST); \ REG_IM = read_16_##MODE(DST); \
REG_IM2 = read_16_IMM(REG_PB | REG_PC); \ REG_IM2 = read_16_IMM(REG_PG | REG_PC); \
REG_PC+=2; \ REG_PC+=2; \
write_16_##MODE(DST, REG_IM & ~REG_IM2); write_16_##MODE(DST, REG_IM & ~REG_IM2);
#endif #endif
@ -1841,7 +1841,7 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \ CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \
DST = EA_##MODE(); \ DST = EA_##MODE(); \
REG_IM = read_8_##MODE(DST); \ REG_IM = read_8_##MODE(DST); \
REG_IM2 = read_8_IMM(REG_PB | REG_PC); \ REG_IM2 = read_8_IMM(REG_PG | REG_PC); \
REG_PC++; \ REG_PC++; \
write_8_##MODE(DST, REG_IM | REG_IM2); write_8_##MODE(DST, REG_IM | REG_IM2);
#else #else
@ -1849,7 +1849,7 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \ CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \
DST = EA_##MODE(); \ DST = EA_##MODE(); \
REG_IM = read_16_##MODE(DST); \ REG_IM = read_16_##MODE(DST); \
REG_IM2 = read_16_IMM(REG_PB | REG_PC); \ REG_IM2 = read_16_IMM(REG_PG | REG_PC); \
REG_PC+=2; \ REG_PC+=2; \
write_16_##MODE(DST, REG_IM | REG_IM2); write_16_##MODE(DST, REG_IM | REG_IM2);
#endif #endif
@ -1864,7 +1864,7 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
#undef OP_LDT #undef OP_LDT
#define OP_LDT(MODE) \ #define OP_LDT(MODE) \
CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
REG_DB = OPER_8_##MODE()<<16; REG_DT = OPER_8_##MODE()<<16;
/* M37710 prefix for B accumulator (0x42) */ /* M37710 prefix for B accumulator (0x42) */
@ -1872,7 +1872,7 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
#undef OP_PFB #undef OP_PFB
#define OP_PFB() \ #define OP_PFB() \
CLK(2); \ CLK(2); \
REG_IR = read_8_IMM(REG_PB | REG_PC); \ REG_IR = read_8_IMM(REG_PG | REG_PC); \
REG_PC++; \ REG_PC++; \
(this->*m_opcodes42[REG_IR])(); (this->*m_opcodes42[REG_IR])();
@ -1880,7 +1880,7 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
/* M37710 prefix for multiply / divide instructions (0x89) */ /* M37710 prefix for multiply / divide instructions (0x89) */
#undef OP_PFXM #undef OP_PFXM
#define OP_PFXM() \ #define OP_PFXM() \
REG_IR = read_8_IMM(REG_PB | REG_PC); \ REG_IR = read_8_IMM(REG_PG | REG_PC); \
REG_PC++; \ REG_PC++; \
(this->*m_opcodes89[REG_IR])(); (this->*m_opcodes89[REG_IR])();
@ -1888,7 +1888,7 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
/* M37710 unimplemented opcode */ /* M37710 unimplemented opcode */
#undef OP_UNIMP #undef OP_UNIMP
#define OP_UNIMP() \ #define OP_UNIMP() \
logerror("error M37710: UNIMPLEMENTED OPCODE! K=%x PC=%x\n", REG_PB, REG_PPC); logerror("error M37710: UNIMPLEMENTED OPCODE! K=%x PC=%x\n", REG_PG, REG_PPC);
/* ======================================================================== */ /* ======================================================================== */
/* ======================== OPCODE & FUNCTION TABLES ====================== */ /* ======================== OPCODE & FUNCTION TABLES ====================== */
@ -2497,10 +2497,10 @@ TABLE_FUNCTION(uint32_t, get_reg, (int regnum))
case M37710_Y: return REG_Y; case M37710_Y: return REG_Y;
case M37710_S: return REG_S; case M37710_S: return REG_S;
case M37710_PC: return REG_PC; case M37710_PC: return REG_PC;
case M37710_PB: return REG_PB >> 16; case M37710_PG: return REG_PG >> 16;
case M37710_DB: return REG_DB >> 16; case M37710_DT: return REG_DT >> 16;
case M37710_D: return REG_D; case M37710_DPR: return REG_DPR;
case M37710_P: return m37710i_get_reg_p(); case M37710_PS: return m37710i_get_reg_ps();
case M37710_IRQ_STATE: return LINE_IRQ; case M37710_IRQ_STATE: return LINE_IRQ;
case STATE_GENPCBASE: return REG_PPC; case STATE_GENPCBASE: return REG_PPC;
} }
@ -2513,7 +2513,7 @@ TABLE_FUNCTION(void, set_reg, (int regnum, uint32_t val))
{ {
case M37710_PC: REG_PC = MAKE_UINT_16(val); break; case M37710_PC: REG_PC = MAKE_UINT_16(val); break;
case M37710_S: REG_S = MAKE_UINT_16(val); break; case M37710_S: REG_S = MAKE_UINT_16(val); break;
case M37710_P: m37710i_set_reg_p(val); break; case M37710_PS: m37710i_set_reg_ps(val); break;
#if FLAG_SET_M #if FLAG_SET_M
case M37710_A: REG_A = MAKE_UINT_8(val); REG_B = val&0xff00; break; case M37710_A: REG_A = MAKE_UINT_8(val); REG_B = val&0xff00; break;
case M37710_B: REG_BA = MAKE_UINT_8(val); REG_BB = val&0xff00; break; case M37710_B: REG_BA = MAKE_UINT_8(val); REG_BB = val&0xff00; break;
@ -2540,9 +2540,9 @@ TABLE_FUNCTION(int, execute, (int clocks))
do do
{ {
REG_PPC = REG_PC; REG_PPC = REG_PC;
M37710_CALL_DEBUGGER(REG_PB | REG_PC); M37710_CALL_DEBUGGER(REG_PG | REG_PC);
REG_PC++; REG_PC++;
REG_IR = read_8_IMM(REG_PB | REG_PPC); REG_IR = read_8_IMM(REG_PG | REG_PPC);
(this->*m_opcodes[REG_IR])(); (this->*m_opcodes[REG_IR])();
} while(CLOCKS > 0); } while(CLOCKS > 0);
return clocks - CLOCKS; return clocks - CLOCKS;

16
src/devices/cpu/m37710/m7700ds.cpp
View File

@ -319,9 +319,9 @@ offs_t m7700_disassembler::disassemble(std::ostream &stream, offs_t pc, const da
uint32_t flags = 0; uint32_t flags = 0;
offs_t address = pc; offs_t address = pc;
u32 pb = pc & 0xffff0000; u32 pg = pc & 0xff0000;
pc &= 0xffff; pc &= 0xffff;
address = pc | pb; address = pc | pg;
instruction = opcodes.r8(address); instruction = opcodes.r8(address);
@ -370,13 +370,13 @@ offs_t m7700_disassembler::disassemble(std::ostream &stream, offs_t pc, const da
case RELB: case RELB:
varS = opcodes.r8(address + 1); varS = opcodes.r8(address + 1);
length++; length++;
util::stream_format(stream, " %06x (%s)", pb | ((pc + length + varS)&0xffff), int_8_str(varS)); util::stream_format(stream, " %06x (%s)", pg | ((pc + length + varS)&0xffff), int_8_str(varS));
break; break;
case RELW: case RELW:
case PER : case PER :
var = opcodes.r16(address + 1); var = opcodes.r16(address + 1);
length += 2; length += 2;
util::stream_format(stream, " %06x (%s)", pb | ((pc + length + var)&0xffff), int_16_str(var)); util::stream_format(stream, " %06x (%s)", pg | ((pc + length + var)&0xffff), int_16_str(var));
break; break;
case IMM : case IMM :
if((opcode->flag == M && !m_flag) || (opcode->flag == X && !x_flag)) if((opcode->flag == M && !m_flag) || (opcode->flag == X && !x_flag))
@ -395,13 +395,13 @@ offs_t m7700_disassembler::disassemble(std::ostream &stream, offs_t pc, const da
{ {
varS = opcodes.r8(address + 4); varS = opcodes.r8(address + 4);
length += 4; length += 4;
util::stream_format(stream, " #$%04x, $%02x, %06x (%s)", opcodes.r16(address + 2), opcodes.r8(address + 1), pb | ((pc + length + varS)&0xffff), int_8_str(varS)); util::stream_format(stream, " #$%04x, $%02x, %06x (%s)", opcodes.r16(address + 2), opcodes.r8(address + 1), pg | ((pc + length + varS)&0xffff), int_8_str(varS));
} }
else else
{ {
varS = opcodes.r8(address + 3); varS = opcodes.r8(address + 3);
length += 3; length += 3;
util::stream_format(stream, " #$%02x, $%02x, %06x (%s)", opcodes.r8(address + 2), opcodes.r8(address + 1), pb | ((pc + length + varS)&0xffff), int_8_str(varS)); util::stream_format(stream, " #$%02x, $%02x, %06x (%s)", opcodes.r8(address + 2), opcodes.r8(address + 1), pg | ((pc + length + varS)&0xffff), int_8_str(varS));
} }
break; break;
case BBCA: case BBCA:
@ -409,13 +409,13 @@ offs_t m7700_disassembler::disassemble(std::ostream &stream, offs_t pc, const da
{ {
length += 5; length += 5;
varS = opcodes.r8(address + 5); varS = opcodes.r8(address + 5);
util::stream_format(stream, " #$%04x, $%04x, %06x (%s)", opcodes.r16(address + 3), opcodes.r16(address + 1), pb | ((pc + length + varS)&0xffff), int_8_str(varS)); util::stream_format(stream, " #$%04x, $%04x, %06x (%s)", opcodes.r16(address + 3), opcodes.r16(address + 1), pg | ((pc + length + varS)&0xffff), int_8_str(varS));
} }
else else
{ {
length += 4; length += 4;
varS = opcodes.r8(address + 4); varS = opcodes.r8(address + 4);
util::stream_format(stream, " #$%02x, $%04x, %06x (%s)", opcodes.r8(address + 3), opcodes.r16(address + 1), pb | ((pc + length + varS)&0xffff), int_8_str(varS)); util::stream_format(stream, " #$%02x, $%04x, %06x (%s)", opcodes.r8(address + 3), opcodes.r16(address + 1), pg | ((pc + length + varS)&0xffff), int_8_str(varS));
} }
break; break;
case LDM4: case LDM4: