mirror of
https://github.com/holub/mame
synced 2025-05-29 17:13:05 +03:00
moved some snes stuff into the driver class. nw.
This commit is contained in:
Fabio Priuli
parent
eef0a7fdf2
commit
a5aa8f846c
@ -793,31 +793,6 @@ static INPUT_PORTS_START( snes )
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INPUT_PORTS_END
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static MACHINE_CONFIG_START( snes, nss_state )
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/* basic machine hardware */
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MCFG_CPU_ADD("maincpu", _5A22, MCLK_NTSC) /* 2.68Mhz, also 3.58Mhz */
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MCFG_CPU_PROGRAM_MAP(snes_map)
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MCFG_CPU_ADD("soundcpu", SPC700, 2048000/2) /* 2.048 Mhz, but internal divider */
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MCFG_CPU_PROGRAM_MAP(spc_mem)
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MCFG_QUANTUM_PERFECT_CPU("maincpu")
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/* video hardware */
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MCFG_VIDEO_START( snes )
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MCFG_SCREEN_ADD("screen", RASTER)
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MCFG_SCREEN_RAW_PARAMS(DOTCLK_NTSC, SNES_HTOTAL, 0, SNES_SCR_WIDTH, SNES_VTOTAL_NTSC, 0, SNES_SCR_HEIGHT_NTSC)
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MCFG_SCREEN_UPDATE_DRIVER( snes_state, snes_screen_update )
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/* sound hardware */
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MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
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MCFG_SOUND_ADD("spc700", SNES, 0)
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MCFG_SOUND_ROUTE(0, "lspeaker", 1.00)
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MCFG_SOUND_ROUTE(1, "rspeaker", 1.00)
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MACHINE_CONFIG_END
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INTERRUPT_GEN_MEMBER(nss_state::nss_vblank_irq)
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{
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if(m_nmi_enable)
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@ -841,8 +816,18 @@ static M50458_INTERFACE( m50458_intf )
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"osd"
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};
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static MACHINE_CONFIG_DERIVED( nss, snes )
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static MACHINE_CONFIG_START( nss, nss_state )
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/* base snes hardware */
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MCFG_CPU_ADD("maincpu", _5A22, MCLK_NTSC) /* 2.68Mhz, also 3.58Mhz */
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MCFG_CPU_PROGRAM_MAP(snes_map)
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MCFG_CPU_ADD("soundcpu", SPC700, 2048000/2) /* 2.048 Mhz, but internal divider */
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MCFG_CPU_PROGRAM_MAP(spc_mem)
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MCFG_QUANTUM_PERFECT_CPU("maincpu")
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/* nss hardware */
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MCFG_CPU_ADD("bios", Z80, 4000000)
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MCFG_CPU_PROGRAM_MAP(bios_map)
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MCFG_CPU_IO_MAP(bios_io_map)
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@ -853,9 +838,24 @@ static MACHINE_CONFIG_DERIVED( nss, snes )
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MCFG_RP5H01_ADD("rp5h01")
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MCFG_M6M80011AP_ADD("m6m80011ap")
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/* sound hardware */
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MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
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MCFG_SOUND_ADD("spc700", SNES, 0)
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MCFG_SOUND_ROUTE(0, "lspeaker", 1.00)
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MCFG_SOUND_ROUTE(1, "rspeaker", 1.00)
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/* video hardware */
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MCFG_VIDEO_START( snes )
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/* TODO: the screen should actually superimpose, but for the time being let's just separate outputs */
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MCFG_DEFAULT_LAYOUT(layout_dualhsxs)
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// SNES PPU
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MCFG_SCREEN_ADD("screen", RASTER)
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MCFG_SCREEN_RAW_PARAMS(DOTCLK_NTSC, SNES_HTOTAL, 0, SNES_SCR_WIDTH, SNES_VTOTAL_NTSC, 0, SNES_SCR_HEIGHT_NTSC)
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MCFG_SCREEN_UPDATE_DRIVER( snes_state, screen_update )
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// NSS
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MCFG_SCREEN_ADD("osd", RASTER)
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MCFG_SCREEN_REFRESH_RATE(60)
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MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500))
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@ -148,8 +148,8 @@ public:
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DECLARE_WRITE8_MEMBER( port_83_w );
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DECLARE_WRITE8_MEMBER( snes_map_0_w );
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DECLARE_WRITE8_MEMBER( snes_map_1_w );
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DECLARE_MACHINE_START(sfcbox);
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DECLARE_MACHINE_RESET(sfcbox);
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virtual void machine_start();
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virtual void machine_reset();
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DECLARE_READ8_MEMBER(spc_ram_100_r);
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DECLARE_WRITE8_MEMBER(spc_ram_100_w);
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};
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@ -438,43 +438,14 @@ static INPUT_PORTS_START( snes )
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#endif
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INPUT_PORTS_END
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static MACHINE_CONFIG_START( snes, sfcbox_state )
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/* basic machine hardware */
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MCFG_CPU_ADD("maincpu", _5A22, 3580000*6) /* 2.68Mhz, also 3.58Mhz */
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MCFG_CPU_PROGRAM_MAP(snes_map)
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MCFG_CPU_ADD("soundcpu", SPC700, 2048000/2) /* 2.048 Mhz, but internal divider */
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MCFG_CPU_PROGRAM_MAP(spc_mem)
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MCFG_QUANTUM_PERFECT_CPU("maincpu")
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MCFG_MACHINE_START( snes )
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MCFG_MACHINE_RESET( snes )
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/* video hardware */
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MCFG_VIDEO_START( snes )
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MCFG_SCREEN_ADD("screen", RASTER)
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MCFG_SCREEN_RAW_PARAMS(DOTCLK_NTSC, SNES_HTOTAL, 0, SNES_SCR_WIDTH, SNES_VTOTAL_NTSC, 0, SNES_SCR_HEIGHT_NTSC)
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MCFG_SCREEN_UPDATE_DRIVER( snes_state, snes_screen_update )
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/* sound hardware */
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MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
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MCFG_SOUND_ADD("spc700", SNES, 0)
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MCFG_SOUND_ROUTE(0, "lspeaker", 1.00)
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MCFG_SOUND_ROUTE(1, "rspeaker", 1.00)
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MACHINE_CONFIG_END
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MACHINE_START_MEMBER(sfcbox_state,sfcbox)
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void sfcbox_state::machine_start()
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{
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MACHINE_START_CALL_LEGACY(snes);
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m_is_sfcbox = 1;
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}
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MACHINE_RESET_MEMBER(sfcbox_state,sfcbox)
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void sfcbox_state::machine_reset()
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{
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MACHINE_RESET_CALL_LEGACY( snes );
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@ -483,8 +454,18 @@ MACHINE_RESET_MEMBER(sfcbox_state,sfcbox)
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m_soundcpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
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}
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static MACHINE_CONFIG_DERIVED( sfcbox, snes )
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static MACHINE_CONFIG_START( sfcbox, sfcbox_state )
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/* base snes hardware */
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MCFG_CPU_ADD("maincpu", _5A22, 3580000*6) /* 2.68Mhz, also 3.58Mhz */
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MCFG_CPU_PROGRAM_MAP(snes_map)
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MCFG_CPU_ADD("soundcpu", SPC700, 2048000/2) /* 2.048 Mhz, but internal divider */
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MCFG_CPU_PROGRAM_MAP(spc_mem)
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MCFG_QUANTUM_PERFECT_CPU("maincpu")
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/* sfcbox hardware */
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MCFG_CPU_ADD("bios", Z180, XTAL_12MHz / 2) /* HD64180RF6X */
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MCFG_CPU_PROGRAM_MAP(sfcbox_map)
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MCFG_CPU_IO_MAP(sfcbox_io)
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@ -492,12 +473,24 @@ static MACHINE_CONFIG_DERIVED( sfcbox, snes )
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MCFG_MB90082_ADD("mb90082",XTAL_12MHz / 2) /* TODO: correct clock */
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MCFG_S3520CF_ADD("s3520cf") /* RTC */
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MCFG_MACHINE_START_OVERRIDE(sfcbox_state, sfcbox )
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MCFG_MACHINE_RESET_OVERRIDE(sfcbox_state, sfcbox )
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/* sound hardware */
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MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
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MCFG_SOUND_ADD("spc700", SNES, 0)
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MCFG_SOUND_ROUTE(0, "lspeaker", 1.00)
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MCFG_SOUND_ROUTE(1, "rspeaker", 1.00)
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/* video hardware */
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MCFG_VIDEO_START( snes )
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/* TODO: the screen should actually superimpose, but for the time being let's just separate outputs */
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MCFG_DEFAULT_LAYOUT(layout_dualhsxs)
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// SNES PPU
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MCFG_SCREEN_ADD("screen", RASTER)
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MCFG_SCREEN_RAW_PARAMS(DOTCLK_NTSC, SNES_HTOTAL, 0, SNES_SCR_WIDTH, SNES_VTOTAL_NTSC, 0, SNES_SCR_HEIGHT_NTSC)
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MCFG_SCREEN_UPDATE_DRIVER( snes_state, screen_update )
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// SFCBOX
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MCFG_SCREEN_ADD("osd", RASTER)
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MCFG_SCREEN_REFRESH_RATE(60)
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MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500))
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@ -646,7 +646,7 @@ static MACHINE_CONFIG_START( kinstb, snesb_state )
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MCFG_SCREEN_ADD("screen", RASTER)
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MCFG_SCREEN_RAW_PARAMS(DOTCLK_NTSC, SNES_HTOTAL, 0, SNES_SCR_WIDTH, SNES_VTOTAL_NTSC, 0, SNES_SCR_HEIGHT_NTSC)
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MCFG_SCREEN_UPDATE_DRIVER( snes_state, snes_screen_update )
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MCFG_SCREEN_UPDATE_DRIVER( snes_state, screen_update )
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/* sound hardware */
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MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
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@ -660,7 +660,7 @@ public:
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snes_cart_info m_cart[2]; // the second one is used by MESS for Sufami Turbo and, eventually, BS-X
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snes_ppu_class m_ppu;
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UINT32 snes_screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
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UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
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/* devices */
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_5a22_device *m_maincpu;
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@ -677,6 +677,17 @@ public:
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DECLARE_DRIVER_INIT(snes_mess);
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DECLARE_DRIVER_INIT(snesst);
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inline int dma_abus_valid(UINT32 address);
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inline UINT8 abus_read(address_space &space, UINT32 abus);
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inline void dma_transfer(address_space &space, UINT8 dma, UINT32 abus, UINT16 bbus);
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inline int is_last_active_channel(int dma);
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inline UINT32 get_hdma_addr(int dma);
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inline UINT32 get_hdma_iaddr(int dma);
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void dma(address_space &space, UINT8 channels);
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void hdma(address_space &space);
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void hdma_init(address_space &space);
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void hdma_update(address_space &space, int dma);
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void hirq_tick();
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TIMER_CALLBACK_MEMBER(snes_nmi_tick);
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TIMER_CALLBACK_MEMBER(snes_hirq_tick_callback);
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@ -31,10 +31,6 @@
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/* -- Globals -- */
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UINT8 *snes_ram = NULL; /* 65816 ram */
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static void snes_dma(address_space &space, UINT8 channels);
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static void snes_hdma_init(address_space &space);
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static void snes_hdma(address_space &space);
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static DECLARE_READ8_HANDLER(snes_io_dma_r);
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static DECLARE_WRITE8_HANDLER(snes_io_dma_w);
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@ -102,7 +98,7 @@ VIDEO_START( snes )
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state->m_ppu.ppu_start(machine);
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}
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UINT32 snes_state::snes_screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
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UINT32 snes_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
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{
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/* NTSC SNES draw range is 1-225. */
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for (int y = cliprect.min_y; y <= cliprect.max_y; y++)
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@ -127,23 +123,21 @@ TIMER_CALLBACK_MEMBER(snes_state::snes_nmi_tick)
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m_nmi_timer->adjust(attotime::never);
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}
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static void snes_hirq_tick( running_machine &machine )
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void snes_state::hirq_tick()
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{
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snes_state *state = machine.driver_data<snes_state>();
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// latch the counters and pull IRQ
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// (don't need to switch to the 65816 context, we don't do anything dependant on it)
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state->m_ppu.latch_counters(machine);
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m_ppu.latch_counters(machine());
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snes_ram[TIMEUP] = 0x80; /* Indicate that irq occurred */
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state->m_maincpu->set_input_line(G65816_LINE_IRQ, ASSERT_LINE);
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m_maincpu->set_input_line(G65816_LINE_IRQ, ASSERT_LINE);
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// don't happen again
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state->m_hirq_timer->adjust(attotime::never);
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m_hirq_timer->adjust(attotime::never);
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}
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TIMER_CALLBACK_MEMBER(snes_state::snes_hirq_tick_callback)
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{
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snes_hirq_tick(machine());
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hirq_tick();
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}
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TIMER_CALLBACK_MEMBER(snes_state::snes_reset_oam_address)
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@ -162,7 +156,7 @@ TIMER_CALLBACK_MEMBER(snes_state::snes_reset_oam_address)
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TIMER_CALLBACK_MEMBER(snes_state::snes_reset_hdma)
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{
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address_space &cpu0space = m_maincpu->space(AS_PROGRAM);
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snes_hdma_init(cpu0space);
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hdma_init(cpu0space);
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}
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TIMER_CALLBACK_MEMBER(snes_state::snes_update_io)
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@ -213,7 +207,7 @@ TIMER_CALLBACK_MEMBER(snes_state::snes_scanline_tick)
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// printf("HIRQ @ %d, %d\n", pixel * m_ppu.m_htmult, m_ppu.m_beam.current_vert);
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if (pixel == 0)
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{
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snes_hirq_tick(machine());
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hirq_tick();
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}
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else
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{
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@ -244,7 +238,7 @@ TIMER_CALLBACK_MEMBER(snes_state::snes_scanline_tick)
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if (m_ppu.m_beam.current_vert == 0)
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{
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address_space &cpu0space = m_maincpu->space(AS_PROGRAM);
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snes_hdma_init(cpu0space);
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hdma_init(cpu0space);
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}
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if (m_ppu.m_beam.current_vert == 0)
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@ -281,7 +275,7 @@ TIMER_CALLBACK_MEMBER(snes_state::snes_hblank_tick)
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{
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/* Do HDMA */
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if (snes_ram[HDMAEN])
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snes_hdma(cpu0space);
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hdma(cpu0space);
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machine().primary_screen->update_partial((m_ppu.m_interlace == 2) ? (m_ppu.m_beam.current_vert * m_ppu.m_interlace) : m_ppu.m_beam.current_vert - 1);
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}
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@ -727,7 +721,7 @@ WRITE8_HANDLER( snes_w_io )
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state->m_vtime &= 0x1ff;
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return;
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case MDMAEN: /* DMA channel designation and trigger */
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snes_dma(space, data);
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state->dma(space, data);
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data = 0; /* Once DMA is done we need to reset all bits to 0 */
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break;
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case HDMAEN: /* HDMA channel designation */
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@ -1949,7 +1943,7 @@ DRIVER_INIT_MEMBER(snes_state,snes_hirom)
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*************************************/
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INLINE int dma_abus_valid( UINT32 address )
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inline int snes_state::dma_abus_valid( UINT32 address )
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{
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if((address & 0x40ff00) == 0x2100) return 0; //$[00-3f|80-bf]:[2100-21ff]
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if((address & 0x40fe00) == 0x4000) return 0; //$[00-3f|80-bf]:[4000-41ff]
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@ -1959,7 +1953,7 @@ INLINE int dma_abus_valid( UINT32 address )
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return 1;
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}
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INLINE UINT8 snes_abus_read( address_space &space, UINT32 abus )
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inline UINT8 snes_state::abus_read( address_space &space, UINT32 abus )
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{
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if (!dma_abus_valid(abus))
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return 0;
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@ -1967,11 +1961,9 @@ INLINE UINT8 snes_abus_read( address_space &space, UINT32 abus )
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return space.read_byte(abus);
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}
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INLINE void snes_dma_transfer( address_space &space, UINT8 dma, UINT32 abus, UINT16 bbus )
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inline void snes_state::dma_transfer( address_space &space, UINT8 dma, UINT32 abus, UINT16 bbus )
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{
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snes_state *state = space.machine().driver_data<snes_state>();
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if (state->m_dma_channel[dma].dmap & 0x80) /* PPU->CPU */
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if (m_dma_channel[dma].dmap & 0x80) /* PPU->CPU */
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{
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if (bbus == 0x2180 && ((abus & 0xfe0000) == 0x7e0000 || (abus & 0x40e000) == 0x0000))
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{
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@ -2000,7 +1992,7 @@ INLINE void snes_dma_transfer( address_space &space, UINT8 dma, UINT32 abus, UIN
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}
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else
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{
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space.write_byte(bbus, snes_abus_read(space, abus));
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space.write_byte(bbus, abus_read(space, abus));
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return;
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}
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}
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@ -2008,26 +2000,21 @@ INLINE void snes_dma_transfer( address_space &space, UINT8 dma, UINT32 abus, UIN
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/* WIP: These have the advantage to automatically update the address, but then we would need to
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check again if the transfer is direct/indirect at each step... is it worth? */
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INLINE UINT32 snes_get_hdma_addr( running_machine &machine, int dma )
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inline UINT32 snes_state::get_hdma_addr( int dma )
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{
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snes_state *state = machine.driver_data<snes_state>();
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return (state->m_dma_channel[dma].bank << 16) | (state->m_dma_channel[dma].hdma_addr++);
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return (m_dma_channel[dma].bank << 16) | (m_dma_channel[dma].hdma_addr++);
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}
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INLINE UINT32 snes_get_hdma_iaddr( running_machine &machine, int dma )
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inline UINT32 snes_state::get_hdma_iaddr( int dma )
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{
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snes_state *state = machine.driver_data<snes_state>();
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return (state->m_dma_channel[dma].ibank << 16) | (state->m_dma_channel[dma].trans_size++);
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return (m_dma_channel[dma].ibank << 16) | (m_dma_channel[dma].trans_size++);
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}
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|
||||
INLINE int is_last_active_channel( running_machine &machine, int dma )
|
||||
inline int snes_state::is_last_active_channel( int dma )
|
||||
{
|
||||
snes_state *state = machine.driver_data<snes_state>();
|
||||
int i;
|
||||
|
||||
for (i = dma + 1; i < 8; i++)
|
||||
for (int i = dma + 1; i < 8; i++)
|
||||
{
|
||||
if (BIT(state->m_hdmaen, i) && state->m_dma_channel[i].hdma_line_counter)
|
||||
if (BIT(m_hdmaen, i) && m_dma_channel[i].hdma_line_counter)
|
||||
return 0; // there is still at least another channel with incomplete HDMA
|
||||
}
|
||||
|
||||
@ -2035,141 +2022,133 @@ INLINE int is_last_active_channel( running_machine &machine, int dma )
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void snes_hdma_update( address_space &space, int dma )
|
||||
void snes_state::hdma_update( address_space &space, int dma )
|
||||
{
|
||||
snes_state *state = space.machine().driver_data<snes_state>();
|
||||
UINT32 abus = snes_get_hdma_addr(space.machine(), dma);
|
||||
UINT32 abus = get_hdma_addr(dma);
|
||||
|
||||
state->m_dma_channel[dma].hdma_line_counter = snes_abus_read(space, abus);
|
||||
m_dma_channel[dma].hdma_line_counter = abus_read(space, abus);
|
||||
|
||||
if (state->m_dma_channel[dma].dmap & 0x40)
|
||||
if (m_dma_channel[dma].dmap & 0x40)
|
||||
{
|
||||
/* One oddity: if $43xA is 0 and this is the last active HDMA channel for this scanline, only load
|
||||
one byte for Address, and use the $00 for the low byte. So Address ends up incremented one less than
|
||||
otherwise expected */
|
||||
|
||||
abus = snes_get_hdma_addr(space.machine(), dma);
|
||||
state->m_dma_channel[dma].trans_size = snes_abus_read(space, abus) << 8;
|
||||
abus = get_hdma_addr(dma);
|
||||
m_dma_channel[dma].trans_size = abus_read(space, abus) << 8;
|
||||
|
||||
if (state->m_dma_channel[dma].hdma_line_counter || !is_last_active_channel(space.machine(), dma))
|
||||
if (m_dma_channel[dma].hdma_line_counter || !is_last_active_channel(dma))
|
||||
{
|
||||
// we enter here if we have more transfers to be done or if there are other active channels after this one
|
||||
abus = snes_get_hdma_addr(space.machine(), dma);
|
||||
state->m_dma_channel[dma].trans_size >>= 8;
|
||||
state->m_dma_channel[dma].trans_size |= snes_abus_read(space, abus) << 8;
|
||||
abus = get_hdma_addr(dma);
|
||||
m_dma_channel[dma].trans_size >>= 8;
|
||||
m_dma_channel[dma].trans_size |= abus_read(space, abus) << 8;
|
||||
}
|
||||
}
|
||||
|
||||
if (!state->m_dma_channel[dma].hdma_line_counter)
|
||||
state->m_hdmaen &= ~(1 << dma);
|
||||
if (!m_dma_channel[dma].hdma_line_counter)
|
||||
m_hdmaen &= ~(1 << dma);
|
||||
|
||||
state->m_dma_channel[dma].do_transfer = 1;
|
||||
m_dma_channel[dma].do_transfer = 1;
|
||||
}
|
||||
|
||||
static void snes_hdma_init( address_space &space )
|
||||
void snes_state::hdma_init( address_space &space )
|
||||
{
|
||||
snes_state *state = space.machine().driver_data<snes_state>();
|
||||
int i;
|
||||
|
||||
state->m_hdmaen = snes_ram[HDMAEN];
|
||||
for (i = 0; i < 8; i++)
|
||||
m_hdmaen = snes_ram[HDMAEN];
|
||||
for (int i = 0; i < 8; i++)
|
||||
{
|
||||
if (BIT(state->m_hdmaen, i))
|
||||
if (BIT(m_hdmaen, i))
|
||||
{
|
||||
state->m_dma_channel[i].hdma_addr = state->m_dma_channel[i].src_addr;
|
||||
snes_hdma_update(space, i);
|
||||
m_dma_channel[i].hdma_addr = m_dma_channel[i].src_addr;
|
||||
hdma_update(space, i);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void snes_hdma( address_space &space )
|
||||
void snes_state::hdma( address_space &space )
|
||||
{
|
||||
snes_state *state = space.machine().driver_data<snes_state>();
|
||||
UINT16 bbus;
|
||||
UINT32 abus;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 8; i++)
|
||||
for (int i = 0; i < 8; i++)
|
||||
{
|
||||
if (BIT(state->m_hdmaen, i))
|
||||
if (BIT(m_hdmaen, i))
|
||||
{
|
||||
if (state->m_dma_channel[i].do_transfer)
|
||||
if (m_dma_channel[i].do_transfer)
|
||||
{
|
||||
/* Get transfer addresses */
|
||||
if (state->m_dma_channel[i].dmap & 0x40) /* Indirect */
|
||||
abus = (state->m_dma_channel[i].ibank << 16) + state->m_dma_channel[i].trans_size;
|
||||
if (m_dma_channel[i].dmap & 0x40) /* Indirect */
|
||||
abus = (m_dma_channel[i].ibank << 16) + m_dma_channel[i].trans_size;
|
||||
else /* Absolute */
|
||||
abus = (state->m_dma_channel[i].bank << 16) + state->m_dma_channel[i].hdma_addr;
|
||||
abus = (m_dma_channel[i].bank << 16) + m_dma_channel[i].hdma_addr;
|
||||
|
||||
bbus = state->m_dma_channel[i].dest_addr + 0x2100;
|
||||
bbus = m_dma_channel[i].dest_addr + 0x2100;
|
||||
|
||||
|
||||
|
||||
switch (state->m_dma_channel[i].dmap & 0x07)
|
||||
switch (m_dma_channel[i].dmap & 0x07)
|
||||
{
|
||||
case 0: /* 1 register write once (1 byte: p ) */
|
||||
snes_dma_transfer(space, i, abus++, bbus);
|
||||
dma_transfer(space, i, abus++, bbus);
|
||||
break;
|
||||
case 5: /* 2 registers write twice alternate (4 bytes: p, p+1, p, p+1) */
|
||||
snes_dma_transfer(space, i, abus++, bbus);
|
||||
snes_dma_transfer(space, i, abus++, bbus + 1);
|
||||
snes_dma_transfer(space, i, abus++, bbus);
|
||||
snes_dma_transfer(space, i, abus++, bbus + 1);
|
||||
dma_transfer(space, i, abus++, bbus);
|
||||
dma_transfer(space, i, abus++, bbus + 1);
|
||||
dma_transfer(space, i, abus++, bbus);
|
||||
dma_transfer(space, i, abus++, bbus + 1);
|
||||
break;
|
||||
case 1: /* 2 registers write once (2 bytes: p, p+1 ) */
|
||||
snes_dma_transfer(space, i, abus++, bbus);
|
||||
snes_dma_transfer(space, i, abus++, bbus + 1);
|
||||
dma_transfer(space, i, abus++, bbus);
|
||||
dma_transfer(space, i, abus++, bbus + 1);
|
||||
break;
|
||||
case 2: /* 1 register write twice (2 bytes: p, p ) */
|
||||
case 6:
|
||||
snes_dma_transfer(space, i, abus++, bbus);
|
||||
snes_dma_transfer(space, i, abus++, bbus);
|
||||
dma_transfer(space, i, abus++, bbus);
|
||||
dma_transfer(space, i, abus++, bbus);
|
||||
break;
|
||||
case 3: /* 2 registers write twice each (4 bytes: p, p, p+1, p+1) */
|
||||
case 7:
|
||||
snes_dma_transfer(space, i, abus++, bbus);
|
||||
snes_dma_transfer(space, i, abus++, bbus);
|
||||
snes_dma_transfer(space, i, abus++, bbus + 1);
|
||||
snes_dma_transfer(space, i, abus++, bbus + 1);
|
||||
dma_transfer(space, i, abus++, bbus);
|
||||
dma_transfer(space, i, abus++, bbus);
|
||||
dma_transfer(space, i, abus++, bbus + 1);
|
||||
dma_transfer(space, i, abus++, bbus + 1);
|
||||
break;
|
||||
case 4: /* 4 registers write once (4 bytes: p, p+1, p+2, p+3) */
|
||||
snes_dma_transfer(space, i, abus++, bbus);
|
||||
snes_dma_transfer(space, i, abus++, bbus + 1);
|
||||
snes_dma_transfer(space, i, abus++, bbus + 2);
|
||||
snes_dma_transfer(space, i, abus++, bbus + 3);
|
||||
dma_transfer(space, i, abus++, bbus);
|
||||
dma_transfer(space, i, abus++, bbus + 1);
|
||||
dma_transfer(space, i, abus++, bbus + 2);
|
||||
dma_transfer(space, i, abus++, bbus + 3);
|
||||
break;
|
||||
default:
|
||||
#ifdef MAME_DEBUG
|
||||
mame_printf_debug( " HDMA of unsupported type: %d\n", state->m_dma_channel[i].dmap & 0x07);
|
||||
mame_printf_debug( " HDMA of unsupported type: %d\n", m_dma_channel[i].dmap & 0x07);
|
||||
#endif
|
||||
break;
|
||||
}
|
||||
|
||||
if (state->m_dma_channel[i].dmap & 0x40) /* Indirect */
|
||||
state->m_dma_channel[i].trans_size = abus;
|
||||
if (m_dma_channel[i].dmap & 0x40) /* Indirect */
|
||||
m_dma_channel[i].trans_size = abus;
|
||||
else /* Absolute */
|
||||
state->m_dma_channel[i].hdma_addr = abus;
|
||||
m_dma_channel[i].hdma_addr = abus;
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
for (i = 0; i < 8; i++)
|
||||
for (int i = 0; i < 8; i++)
|
||||
{
|
||||
if (BIT(state->m_hdmaen, i))
|
||||
if (BIT(m_hdmaen, i))
|
||||
{
|
||||
state->m_dma_channel[i].do_transfer = (--state->m_dma_channel[i].hdma_line_counter) & 0x80;
|
||||
m_dma_channel[i].do_transfer = (--m_dma_channel[i].hdma_line_counter) & 0x80;
|
||||
|
||||
if (!(state->m_dma_channel[i].hdma_line_counter & 0x7f))
|
||||
snes_hdma_update(space, i);
|
||||
if (!(m_dma_channel[i].hdma_line_counter & 0x7f))
|
||||
hdma_update(space, i);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void snes_dma( address_space &space, UINT8 channels )
|
||||
void snes_state::dma( address_space &space, UINT8 channels )
|
||||
{
|
||||
snes_state *state = space.machine().driver_data<snes_state>();
|
||||
int i;
|
||||
INT8 increment;
|
||||
UINT16 bbus;
|
||||
UINT32 abus, abus_bank;
|
||||
@ -2178,113 +2157,113 @@ static void snes_dma( address_space &space, UINT8 channels )
|
||||
/* FIXME: we also need to round to the nearest 8 master cycles */
|
||||
|
||||
/* Assume priority of the 8 DMA channels is 0-7 */
|
||||
for (i = 0; i < 8; i++)
|
||||
for (int i = 0; i < 8; i++)
|
||||
{
|
||||
if (BIT(channels, i))
|
||||
{
|
||||
/* FIXME: the following should be used to stop DMA if the same channel is used by HDMA (being set to 1 in snes_hdma)
|
||||
However, this cannot be implemented as is atm, because currently DMA transfers always happen as soon as they are enabled... */
|
||||
state->m_dma_channel[i].dma_disabled = 0;
|
||||
m_dma_channel[i].dma_disabled = 0;
|
||||
|
||||
//printf( "Making a transfer on channel %d\n", i );
|
||||
/* Find transfer addresses */
|
||||
abus = state->m_dma_channel[i].src_addr;
|
||||
abus_bank = state->m_dma_channel[i].bank << 16;
|
||||
bbus = state->m_dma_channel[i].dest_addr + 0x2100;
|
||||
abus = m_dma_channel[i].src_addr;
|
||||
abus_bank = m_dma_channel[i].bank << 16;
|
||||
bbus = m_dma_channel[i].dest_addr + 0x2100;
|
||||
|
||||
//printf("Address: %06x\n", abus | abus_bank);
|
||||
/* Auto increment */
|
||||
if (state->m_dma_channel[i].dmap & 0x8)
|
||||
if (m_dma_channel[i].dmap & 0x8)
|
||||
increment = 0;
|
||||
else
|
||||
{
|
||||
if (state->m_dma_channel[i].dmap & 0x10)
|
||||
if (m_dma_channel[i].dmap & 0x10)
|
||||
increment = -1;
|
||||
else
|
||||
increment = 1;
|
||||
}
|
||||
|
||||
/* Number of bytes to transfer */
|
||||
length = state->m_dma_channel[i].trans_size;
|
||||
length = m_dma_channel[i].trans_size;
|
||||
|
||||
// printf( "DMA-Ch %d: len: %X, abus: %X, bbus: %X, incr: %d, dir: %s, type: %d\n", i, length, abus | abus_bank, bbus, increment, state->m_dma_channel[i].dmap & 0x80 ? "PPU->CPU" : "CPU->PPU", state->m_dma_channel[i].dmap & 0x07);
|
||||
// printf( "DMA-Ch %d: len: %X, abus: %X, bbus: %X, incr: %d, dir: %s, type: %d\n", i, length, abus | abus_bank, bbus, increment, m_dma_channel[i].dmap & 0x80 ? "PPU->CPU" : "CPU->PPU", m_dma_channel[i].dmap & 0x07);
|
||||
|
||||
#ifdef SNES_DBG_DMA
|
||||
mame_printf_debug( "DMA-Ch %d: len: %X, abus: %X, bbus: %X, incr: %d, dir: %s, type: %d\n", i, length, abus | abus_bank, bbus, increment, state->m_dma_channel[i].dmap & 0x80 ? "PPU->CPU" : "CPU->PPU", state->m_dma_channel[i].dmap & 0x07);
|
||||
mame_printf_debug( "DMA-Ch %d: len: %X, abus: %X, bbus: %X, incr: %d, dir: %s, type: %d\n", i, length, abus | abus_bank, bbus, increment, m_dma_channel[i].dmap & 0x80 ? "PPU->CPU" : "CPU->PPU", m_dma_channel[i].dmap & 0x07);
|
||||
#endif
|
||||
|
||||
switch (state->m_dma_channel[i].dmap & 0x07)
|
||||
switch (m_dma_channel[i].dmap & 0x07)
|
||||
{
|
||||
case 0: /* 1 register write once */
|
||||
case 2: /* 1 register write twice */
|
||||
case 6: /* 1 register write twice */
|
||||
do
|
||||
{
|
||||
snes_dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus);
|
||||
dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus);
|
||||
abus += increment;
|
||||
} while (--length && !state->m_dma_channel[i].dma_disabled);
|
||||
} while (--length && !m_dma_channel[i].dma_disabled);
|
||||
break;
|
||||
case 1: /* 2 registers write once */
|
||||
case 5: /* 2 registers write twice alternate */
|
||||
do
|
||||
{
|
||||
snes_dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus);
|
||||
dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus);
|
||||
abus += increment;
|
||||
if (!(--length) || state->m_dma_channel[i].dma_disabled)
|
||||
if (!(--length) || m_dma_channel[i].dma_disabled)
|
||||
break;
|
||||
snes_dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus + 1);
|
||||
dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus + 1);
|
||||
abus += increment;
|
||||
} while (--length && !state->m_dma_channel[i].dma_disabled);
|
||||
} while (--length && !m_dma_channel[i].dma_disabled);
|
||||
break;
|
||||
case 3: /* 2 registers write twice each */
|
||||
case 7: /* 2 registers write twice each */
|
||||
do
|
||||
{
|
||||
snes_dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus);
|
||||
dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus);
|
||||
abus += increment;
|
||||
if (!(--length) || state->m_dma_channel[i].dma_disabled)
|
||||
if (!(--length) || m_dma_channel[i].dma_disabled)
|
||||
break;
|
||||
snes_dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus);
|
||||
dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus);
|
||||
abus += increment;
|
||||
if (!(--length) || state->m_dma_channel[i].dma_disabled)
|
||||
if (!(--length) || m_dma_channel[i].dma_disabled)
|
||||
break;
|
||||
snes_dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus + 1);
|
||||
dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus + 1);
|
||||
abus += increment;
|
||||
if (!(--length) || state->m_dma_channel[i].dma_disabled)
|
||||
if (!(--length) || m_dma_channel[i].dma_disabled)
|
||||
break;
|
||||
snes_dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus + 1);
|
||||
dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus + 1);
|
||||
abus += increment;
|
||||
} while (--length && !state->m_dma_channel[i].dma_disabled);
|
||||
} while (--length && !m_dma_channel[i].dma_disabled);
|
||||
break;
|
||||
case 4: /* 4 registers write once */
|
||||
do
|
||||
{
|
||||
snes_dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus);
|
||||
dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus);
|
||||
abus += increment;
|
||||
if (!(--length) || state->m_dma_channel[i].dma_disabled)
|
||||
if (!(--length) || m_dma_channel[i].dma_disabled)
|
||||
break;
|
||||
snes_dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus + 1);
|
||||
dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus + 1);
|
||||
abus += increment;
|
||||
if (!(--length) || state->m_dma_channel[i].dma_disabled)
|
||||
if (!(--length) || m_dma_channel[i].dma_disabled)
|
||||
break;
|
||||
snes_dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus + 2);
|
||||
dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus + 2);
|
||||
abus += increment;
|
||||
if (!(--length) || state->m_dma_channel[i].dma_disabled)
|
||||
if (!(--length) || m_dma_channel[i].dma_disabled)
|
||||
break;
|
||||
snes_dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus + 3);
|
||||
dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus + 3);
|
||||
abus += increment;
|
||||
} while (--length && !state->m_dma_channel[i].dma_disabled);
|
||||
} while (--length && !m_dma_channel[i].dma_disabled);
|
||||
break;
|
||||
default:
|
||||
#ifdef MAME_DEBUG
|
||||
mame_printf_debug(" DMA of unsupported type: %d\n", state->m_dma_channel[i].dmap & 0x07);
|
||||
mame_printf_debug(" DMA of unsupported type: %d\n", m_dma_channel[i].dmap & 0x07);
|
||||
#endif
|
||||
break;
|
||||
}
|
||||
|
||||
/* We're done, so write the new abus back to the registers */
|
||||
state->m_dma_channel[i].src_addr = abus;
|
||||
state->m_dma_channel[i].trans_size = 0;
|
||||
m_dma_channel[i].src_addr = abus;
|
||||
m_dma_channel[i].trans_size = 0;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -724,7 +724,7 @@ static MACHINE_CONFIG_START( snes_base, snes_state )
|
||||
|
||||
MCFG_SCREEN_ADD("screen", RASTER)
|
||||
MCFG_SCREEN_RAW_PARAMS(DOTCLK_NTSC * 2, SNES_HTOTAL * 2, 0, SNES_SCR_WIDTH * 2, SNES_VTOTAL_NTSC, 0, SNES_SCR_HEIGHT_NTSC)
|
||||
MCFG_SCREEN_UPDATE_DRIVER( snes_state, snes_screen_update )
|
||||
MCFG_SCREEN_UPDATE_DRIVER( snes_state, screen_update )
|
||||
|
||||
/* sound hardware */
|
||||
MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
|
||||
|
||||
Loading…
Reference in New Issue
Block a user