mirror of
https://github.com/holub/mame
synced 2025-10-05 16:50:57 +03:00
mc68hc11: Add internal latches and direction registers for ports
Related changes (nw): - Split up hc11_regs_r/w into many separate handlers - Give each MC68HC11 model its own specific io_map - Remove now-unnecessary readback handlers from skeetsht.cpp and taitojc.cpp
This commit is contained in:
AJR
parent
245d7f11d0
commit
a5d3c4cca0
@ -69,12 +69,6 @@ void mc68hc11_cpu_device::ram_map(address_map &map)
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map(0, m_internal_ram_size - 1).ram();
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}
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void mc68hc11_cpu_device::io_map(address_map &map)
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{
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/* defaults it to the HC11M0 version for now (I might strip this down on a later date) */
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map(0, m_reg_block_size - 1).rw(FUNC(mc68hc11_cpu_device::hc11_regs_r), FUNC(mc68hc11_cpu_device::hc11_regs_w));
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}
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mc68hc11a1_device::mc68hc11a1_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: mc68hc11_cpu_device(mconfig, MC68HC11A1, tag, owner, clock, 6, 256, 0x01,
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address_map_constructor(FUNC(mc68hc11a1_device::io_map), this)) // TODO: also has 512 bytes EEPROM
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@ -131,235 +125,355 @@ std::unique_ptr<util::disasm_interface> mc68hc11_cpu_device::create_disassembler
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/*****************************************************************************/
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/* Internal registers */
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uint8_t mc68hc11_cpu_device::hc11_regs_r(uint32_t address)
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template <int P>
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uint8_t mc68hc11_cpu_device::port_r()
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{
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int reg = address & 0xff;
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switch(reg)
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{
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case 0x00: /* PORTA */
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return m_port_input_cb[0]();
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case 0x01: /* DDRA */
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return 0;
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case 0x02: /* PIOC */
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return 0;
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case 0x03: /* PORTC */
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return m_port_input_cb[2]();
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case 0x04: /* PORTB */
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return m_port_input_cb[1]();
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case 0x08: /* PORTD */
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return m_port_input_cb[3]();
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case 0x09: /* DDRD */
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return 0;
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case 0x0a: /* PORTE */
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return m_port_input_cb[4]();
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case 0x0e: /* TCNT */
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return m_tcnt >> 8;
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case 0x0f:
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return m_tcnt & 0xff;
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case 0x16: /* TOC1 */
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return m_toc1 >> 8;
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case 0x17:
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return m_toc1 & 0xff;
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case 0x23:
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return m_tflg1;
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case 0x28: /* SPCR1 */
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return 0;
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case 0x30: /* ADCTL */
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return 0x80;
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case 0x31: /* ADR1 */
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{
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if (m_adctl & 0x10)
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{
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return m_analog_cb[m_adctl & 0x4]();
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}
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else
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{
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return m_analog_cb[m_adctl & 0x7]();
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}
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}
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case 0x32: /* ADR2 */
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{
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if (m_adctl & 0x10)
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{
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return m_analog_cb[m_adctl & 0x4]();
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}
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else
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{
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return m_analog_cb[m_adctl & 0x7]();
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}
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}
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case 0x33: /* ADR3 */
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{
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if (m_adctl & 0x10)
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{
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return m_analog_cb[m_adctl & 0x4]();
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}
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else
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{
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return m_analog_cb[m_adctl & 0x7]();
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}
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}
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case 0x34: /* ADR4 */
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{
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if (m_adctl & 0x10)
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{
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return m_analog_cb[m_adctl & 0x4]();
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}
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else
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{
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return m_analog_cb[m_adctl & 0x7]();
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}
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}
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case 0x38: /* OPT2 */
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return 0;
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case 0x70: /* SCBDH */
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return 0;
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case 0x71: /* SCBDL */
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return 0;
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case 0x72: /* SCCR1 */
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return 0;
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case 0x73: /* SCCR2 */
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return 0;
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case 0x74: /* SCSR1 */
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return 0x40;
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case 0x7c: /* PORTH */
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return m_port_input_cb[7]();
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case 0x7e: /* PORTG */
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return m_port_input_cb[6]();
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case 0x7f: /* DDRG */
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return 0;
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case 0x88: /* SPCR2 */
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return 0;
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case 0x89: /* SPSR2 */
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return 0x80;
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case 0x8a: /* SPDR2 */
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return m_spi2_data_input_cb();
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case 0x8b: /* OPT4 */
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return 0;
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}
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if (!machine().side_effects_disabled())
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logerror("HC11: regs_r %02X\n", reg);
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return 0; // Dummy
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uint8_t dir = m_port_dir[P];
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return (m_port_data[P] & dir) | (dir == 0xff ? 0 : m_port_input_cb[P](0, ~dir) & ~dir);
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}
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void mc68hc11_cpu_device::hc11_regs_w(uint32_t address, uint8_t value)
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template <int P>
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void mc68hc11_cpu_device::port_w(uint8_t data)
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{
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int reg = address & 0xff;
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uint8_t dir = m_port_dir[P];
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uint8_t old_data = std::exchange(m_port_data[P], data);
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if ((old_data & dir) != (data & dir))
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m_port_output_cb[P](0, data & dir, dir);
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}
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switch(reg)
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template <int P>
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uint8_t mc68hc11_cpu_device::ddr_r()
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{
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return m_port_dir[P];
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}
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template <int P>
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void mc68hc11_cpu_device::ddr_w(uint8_t data)
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{
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m_port_dir[P] = data;
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if (data != 0x00)
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m_port_output_cb[P](0, m_port_data[P] & data, data);
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}
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uint8_t mc68hc11_cpu_device::pioc_r()
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{
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return 0;
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}
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uint8_t mc68hc11a1_device::pactl_r()
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{
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return ddr_r<0>() & 0x80;
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}
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void mc68hc11a1_device::pactl_w(uint8_t data)
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{
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ddr_w<0>((data & 0x80) | 0x78);
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}
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uint8_t mc68hc11d0_device::pactl_r()
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{
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return ddr_r<0>() & 0x88;
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}
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void mc68hc11d0_device::pactl_w(uint8_t data)
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{
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ddr_w<0>((data & 0x88) | 0x70);
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}
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uint8_t mc68hc11_cpu_device::tcnt_r(offs_t offset)
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{
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return (m_tcnt >> (BIT(offset, 0) ? 0 : 8)) & 0xff;
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}
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void mc68hc11_cpu_device::tcnt_w(offs_t offset, uint8_t data)
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{
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logerror("HC11: TCNT%c register write %02x!\n", BIT(offset, 0) ? 'L' : 'H', data);
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}
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uint8_t mc68hc11_cpu_device::toc1_r(offs_t offset)
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{
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return (m_toc1 >> (BIT(offset, 0) ? 0 : 8)) & 0xff;
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}
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void mc68hc11_cpu_device::toc1_w(offs_t offset, uint8_t data)
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{
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if (BIT(offset, 0))
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m_toc1 = (data & 0xff) | (m_toc1 & 0xff00);
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else // TODO: inhibit count for one bus cycle
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m_toc1 = (data << 8) | (m_toc1 & 0xff);
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}
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uint8_t mc68hc11_cpu_device::tmsk1_r()
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{
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return m_tmsk1;
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}
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void mc68hc11_cpu_device::tmsk1_w(uint8_t data)
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{
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m_tmsk1 = data;
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}
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uint8_t mc68hc11_cpu_device::tflg1_r()
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{
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return m_tflg1;
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}
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void mc68hc11_cpu_device::tflg1_w(uint8_t data)
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{
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m_tflg1 &= ~data;
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}
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void mc68hc11_cpu_device::tmsk2_w(uint8_t data)
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{
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m_pr = data & 3;
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}
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template <int N>
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uint8_t mc68hc11_cpu_device::spcr_r()
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{
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return 0;
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}
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template <int N>
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uint8_t mc68hc11_cpu_device::spsr_r()
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{
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return 0x80;
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}
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template <int N>
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uint8_t mc68hc11_cpu_device::spdr_r()
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{
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if (N == 1)
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return m_spi2_data_input_cb();
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else
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return 0;
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}
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template <int N>
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void mc68hc11_cpu_device::spdr_w(uint8_t data)
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{
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if (N == 1)
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m_spi2_data_output_cb(data);
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}
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uint8_t mc68hc11_cpu_device::adctl_r()
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{
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return 0x80;
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}
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void mc68hc11_cpu_device::adctl_w(uint8_t data)
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{
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m_adctl = data;
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}
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uint8_t mc68hc11_cpu_device::adr_r(offs_t offset)
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{
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if (m_adctl & 0x10)
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return m_analog_cb[(m_adctl & 0x4) + offset]();
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else
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return m_analog_cb[m_adctl & 0x7]();
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}
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uint8_t mc68hc11_cpu_device::opt2_r()
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{
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return 0;
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}
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uint8_t mc68hc11_cpu_device::init_r()
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{
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int reg_page = (m_reg_position >> 12) & 0xf;
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int ram_page = (m_ram_position >> 12) & 0xf;
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return (ram_page << 4) | reg_page;
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}
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void mc68hc11_cpu_device::init_w(uint8_t data)
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{
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// TODO: only writeable during first 64 E cycles
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int reg_page = data & 0xf;
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int ram_page = (data >> 4) & 0xf;
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if (reg_page == ram_page && m_init_value == 0x00)
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{
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case 0x00: /* PORTA */
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m_port_output_cb[0](value);
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return;
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case 0x01: /* DDRA */
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//osd_printf_debug("HC11: ddra = %02X\n", value);
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return;
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case 0x03: /* PORTC */
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m_port_output_cb[2](value);
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return;
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case 0x04: /* PORTC */
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m_port_output_cb[1](value);
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return;
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case 0x08: /* PORTD */
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m_port_output_cb[3](value); //mask & 0x3f?
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return;
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case 0x09: /* DDRD */
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//osd_printf_debug("HC11: ddrd = %02X\n", value);
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return;
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case 0x0a: /* PORTE */
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m_port_output_cb[4](value);
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return;
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case 0x0e: /* TCNT */
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case 0x0f:
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logerror("HC11: TCNT register write %02x %02x!\n",address,value);
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return;
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case 0x16: /* TOC1 */
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/* TODO: inhibit for one bus cycle */
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m_toc1 = (value << 8) | (m_toc1 & 0xff);
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return;
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case 0x17:
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m_toc1 = (value & 0xff) | (m_toc1 & 0xff00);
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return;
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case 0x22: /* TMSK1 */
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m_tmsk1 = value;
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return;
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case 0x23:
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m_tflg1 &= ~value;
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return;
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case 0x24: /* TMSK2 */
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m_pr = value & 3;
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return;
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case 0x28: /* SPCR1 */
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return;
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case 0x30: /* ADCTL */
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m_adctl = value;
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return;
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case 0x38: /* OPT2 */
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return;
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case 0x39: /* OPTION */
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return;
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case 0x3a: /* COPRST (watchdog) */
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return;
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case 0x3d: /* INIT */
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{
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int reg_page = value & 0xf;
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int ram_page = (value >> 4) & 0xf;
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if (reg_page == ram_page && m_init_value == 0x00) {
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m_reg_position = reg_page << 12;
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m_ram_position = (ram_page << 12) + m_reg_block_size;
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} else {
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m_reg_position = reg_page << 12;
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m_ram_position = ram_page << 12;
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}
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return;
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}
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case 0x3f: /* CONFIG */
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return;
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case 0x70: /* SCBDH */
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return;
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case 0x71: /* SCBDL */
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return;
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case 0x72: /* SCCR1 */
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return;
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case 0x73: /* SCCR2 */
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return;
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case 0x77: /* SCDRL */
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return;
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case 0x7c: /* PORTH */
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m_port_output_cb[7](value);
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return;
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case 0x7d: /* DDRH */
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//osd_printf_debug("HC11: ddrh = %02X at %04X\n", value, m_pc);
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return;
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case 0x7e: /* PORTG */
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m_port_output_cb[6](value);
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return;
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case 0x7f: /* DDRG */
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//osd_printf_debug("HC11: ddrg = %02X at %04X\n", value, m_pc);
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return;
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case 0x88: /* SPCR2 */
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return;
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case 0x89: /* SPSR2 */
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return;
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case 0x8a: /* SPDR2 */
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m_spi2_data_output_cb(value);
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return;
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case 0x8b: /* OPT4 */
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return;
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m_reg_position = reg_page << 12;
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m_ram_position = (ram_page << 12) + m_reg_block_size;
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}
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else
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{
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m_reg_position = reg_page << 12;
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m_ram_position = ram_page << 12;
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}
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}
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logerror("HC11: regs_w %02X, %02X\n", reg, value);
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uint8_t mc68hc11_cpu_device::scbd_r(offs_t offset)
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{
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return 0;
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}
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uint8_t mc68hc11_cpu_device::sccr1_r()
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{
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return 0;
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}
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uint8_t mc68hc11_cpu_device::sccr2_r()
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{
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return 0;
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}
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uint8_t mc68hc11_cpu_device::scsr1_r()
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{
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return 0x40;
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}
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uint8_t mc68hc11_cpu_device::scrdl_r()
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{
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return 0;
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}
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uint8_t mc68hc11_cpu_device::opt4_r()
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{
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return 0;
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}
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void mc68hc11a1_device::io_map(address_map &map)
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{
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map(0x00, 0x00).rw(FUNC(mc68hc11a1_device::port_r<0>), FUNC(mc68hc11a1_device::port_w<0>)); // PORTA
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map(0x02, 0x02).r(FUNC(mc68hc11a1_device::pioc_r)); // PIOC
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map(0x03, 0x03).rw(FUNC(mc68hc11a1_device::port_r<2>), FUNC(mc68hc11a1_device::port_w<2>)); // PORTC
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map(0x04, 0x04).rw(FUNC(mc68hc11a1_device::port_r<1>), FUNC(mc68hc11a1_device::port_w<1>)); // PORTB
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map(0x05, 0x05).nopw(); // PORTCL
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map(0x07, 0x07).rw(FUNC(mc68hc11a1_device::ddr_r<2>), FUNC(mc68hc11a1_device::ddr_w<2>)); // DDRC
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map(0x08, 0x08).rw(FUNC(mc68hc11a1_device::port_r<3>), FUNC(mc68hc11a1_device::port_w<3>)); // PORTD
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map(0x09, 0x09).rw(FUNC(mc68hc11a1_device::ddr_r<3>), FUNC(mc68hc11a1_device::ddr_w<3>)); // DDRD
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map(0x0a, 0x0a).r(FUNC(mc68hc11a1_device::port_r<4>)); // PORTE
|
||||
map(0x0e, 0x0f).rw(FUNC(mc68hc11a1_device::tcnt_r), FUNC(mc68hc11a1_device::tcnt_w)); // TCNT
|
||||
map(0x16, 0x17).rw(FUNC(mc68hc11a1_device::toc1_r), FUNC(mc68hc11a1_device::toc1_w)); // TOC1
|
||||
map(0x22, 0x22).rw(FUNC(mc68hc11a1_device::tmsk1_r), FUNC(mc68hc11a1_device::tmsk1_w)); // TMSK1
|
||||
map(0x23, 0x23).rw(FUNC(mc68hc11a1_device::tflg1_r), FUNC(mc68hc11a1_device::tflg1_w)); // TFLG1
|
||||
map(0x24, 0x24).w(FUNC(mc68hc11a1_device::tmsk2_w)); // TMSK2
|
||||
map(0x26, 0x26).rw(FUNC(mc68hc11a1_device::pactl_r), FUNC(mc68hc11a1_device::pactl_w)); // PACTL
|
||||
map(0x28, 0x28).r(FUNC(mc68hc11a1_device::spcr_r<0>)).nopw(); // SPCR
|
||||
map(0x29, 0x29).r(FUNC(mc68hc11a1_device::spsr_r<0>)).nopw(); // SPSR
|
||||
map(0x2a, 0x2a).rw(FUNC(mc68hc11a1_device::spdr_r<0>), FUNC(mc68hc11a1_device::spdr_w<0>)); // SPDR
|
||||
map(0x2c, 0x2c).r(FUNC(mc68hc11a1_device::sccr1_r)).nopw(); // SCCR1
|
||||
map(0x2d, 0x2d).r(FUNC(mc68hc11a1_device::sccr2_r)).nopw(); // SCCR2
|
||||
map(0x30, 0x30).rw(FUNC(mc68hc11a1_device::adctl_r), FUNC(mc68hc11a1_device::adctl_w)); // ADCTL
|
||||
map(0x31, 0x34).r(FUNC(mc68hc11a1_device::adr_r)); // ADR1-ADR4
|
||||
map(0x39, 0x39).nopw(); // OPTION
|
||||
map(0x3a, 0x3a).nopw(); // COPRST (watchdog)
|
||||
map(0x3b, 0x3b).nopw(); // PPROG (EEPROM programming)
|
||||
map(0x3d, 0x3d).rw(FUNC(mc68hc11a1_device::init_r), FUNC(mc68hc11a1_device::init_w)); // INIT
|
||||
map(0x3f, 0x3f).nopw(); // CONFIG
|
||||
}
|
||||
|
||||
void mc68hc11d0_device::io_map(address_map &map)
|
||||
{
|
||||
map(0x00, 0x00).rw(FUNC(mc68hc11d0_device::port_r<0>), FUNC(mc68hc11d0_device::port_w<0>)); // PORTA
|
||||
map(0x02, 0x02).r(FUNC(mc68hc11d0_device::pioc_r)); // PIOC
|
||||
map(0x03, 0x03).rw(FUNC(mc68hc11d0_device::port_r<2>), FUNC(mc68hc11d0_device::port_w<2>)); // PORTC
|
||||
map(0x04, 0x04).rw(FUNC(mc68hc11d0_device::port_r<1>), FUNC(mc68hc11d0_device::port_w<1>)); // PORTB
|
||||
map(0x06, 0x06).rw(FUNC(mc68hc11d0_device::ddr_r<1>), FUNC(mc68hc11d0_device::ddr_w<1>)); // DDRB
|
||||
map(0x07, 0x07).rw(FUNC(mc68hc11d0_device::ddr_r<2>), FUNC(mc68hc11d0_device::ddr_w<2>)); // DDRC
|
||||
map(0x08, 0x08).rw(FUNC(mc68hc11d0_device::port_r<3>), FUNC(mc68hc11d0_device::port_w<3>)); // PORTD
|
||||
map(0x09, 0x09).rw(FUNC(mc68hc11d0_device::ddr_r<3>), FUNC(mc68hc11d0_device::ddr_w<3>)); // DDRD
|
||||
map(0x0e, 0x0f).rw(FUNC(mc68hc11d0_device::tcnt_r), FUNC(mc68hc11d0_device::tcnt_w)); // TCNT
|
||||
map(0x16, 0x17).rw(FUNC(mc68hc11d0_device::toc1_r), FUNC(mc68hc11d0_device::toc1_w)); // TOC1
|
||||
map(0x22, 0x22).rw(FUNC(mc68hc11d0_device::tmsk1_r), FUNC(mc68hc11d0_device::tmsk1_w)); // TMSK1
|
||||
map(0x23, 0x23).rw(FUNC(mc68hc11d0_device::tflg1_r), FUNC(mc68hc11d0_device::tflg1_w)); // TFLG1
|
||||
map(0x24, 0x24).w(FUNC(mc68hc11d0_device::tmsk2_w)); // TMSK2
|
||||
map(0x26, 0x26).rw(FUNC(mc68hc11d0_device::pactl_r), FUNC(mc68hc11d0_device::pactl_w)); // PACTL
|
||||
map(0x28, 0x28).r(FUNC(mc68hc11d0_device::spcr_r<0>)).nopw(); // SPCR
|
||||
map(0x29, 0x29).r(FUNC(mc68hc11d0_device::spsr_r<0>)).nopw(); // SPSR
|
||||
map(0x2a, 0x2a).rw(FUNC(mc68hc11d0_device::spdr_r<0>), FUNC(mc68hc11d0_device::spdr_w<0>)); // SPDR
|
||||
map(0x2c, 0x2c).r(FUNC(mc68hc11d0_device::sccr1_r)).nopw(); // SCCR1
|
||||
map(0x2d, 0x2d).r(FUNC(mc68hc11d0_device::sccr2_r)).nopw(); // SCCR2
|
||||
map(0x39, 0x39).nopw(); // OPTION
|
||||
map(0x3a, 0x3a).nopw(); // COPRST (watchdog)
|
||||
map(0x3d, 0x3d).rw(FUNC(mc68hc11d0_device::init_r), FUNC(mc68hc11d0_device::init_w)); // INIT
|
||||
map(0x3f, 0x3f).nopw(); // CONFIG
|
||||
}
|
||||
|
||||
void mc68hc11k1_device::io_map(address_map &map)
|
||||
{
|
||||
map(0x00, 0x00).rw(FUNC(mc68hc11k1_device::port_r<0>), FUNC(mc68hc11k1_device::port_w<0>)); // PORTA
|
||||
map(0x01, 0x01).rw(FUNC(mc68hc11k1_device::ddr_r<0>), FUNC(mc68hc11k1_device::ddr_w<0>)); // DDRA
|
||||
map(0x02, 0x02).rw(FUNC(mc68hc11k1_device::ddr_r<1>), FUNC(mc68hc11k1_device::ddr_w<1>)); // DDRB
|
||||
map(0x03, 0x03).rw(FUNC(mc68hc11k1_device::ddr_r<5>), FUNC(mc68hc11k1_device::ddr_w<5>)); // DDRF
|
||||
map(0x04, 0x04).rw(FUNC(mc68hc11k1_device::port_r<1>), FUNC(mc68hc11k1_device::port_w<1>)); // PORTB
|
||||
map(0x05, 0x05).rw(FUNC(mc68hc11k1_device::port_r<5>), FUNC(mc68hc11k1_device::port_w<5>)); // PORTF
|
||||
map(0x06, 0x06).rw(FUNC(mc68hc11k1_device::port_r<2>), FUNC(mc68hc11k1_device::port_w<2>)); // PORTC
|
||||
map(0x07, 0x07).rw(FUNC(mc68hc11k1_device::ddr_r<2>), FUNC(mc68hc11k1_device::ddr_w<2>)); // DDRC
|
||||
map(0x08, 0x08).rw(FUNC(mc68hc11k1_device::port_r<3>), FUNC(mc68hc11k1_device::port_w<3>)); // PORTD
|
||||
map(0x09, 0x09).rw(FUNC(mc68hc11k1_device::ddr_r<3>), FUNC(mc68hc11k1_device::ddr_w<3>)); // DDRD
|
||||
map(0x0a, 0x0a).r(FUNC(mc68hc11k1_device::port_r<4>)); // PORTE
|
||||
map(0x0e, 0x0f).rw(FUNC(mc68hc11k1_device::tcnt_r), FUNC(mc68hc11k1_device::tcnt_w)); // TCNT
|
||||
map(0x16, 0x17).rw(FUNC(mc68hc11k1_device::toc1_r), FUNC(mc68hc11k1_device::toc1_w)); // TOC1
|
||||
map(0x22, 0x22).rw(FUNC(mc68hc11k1_device::tmsk1_r), FUNC(mc68hc11k1_device::tmsk1_w)); // TMSK1
|
||||
map(0x23, 0x23).rw(FUNC(mc68hc11k1_device::tflg1_r), FUNC(mc68hc11k1_device::tflg1_w)); // TFLG1
|
||||
map(0x24, 0x24).w(FUNC(mc68hc11k1_device::tmsk2_w)); // TMSK2
|
||||
map(0x28, 0x28).r(FUNC(mc68hc11k1_device::spcr_r<0>)).nopw(); // SPCR
|
||||
map(0x29, 0x29).r(FUNC(mc68hc11k1_device::spsr_r<0>)).nopw(); // SPSR
|
||||
map(0x2a, 0x2a).rw(FUNC(mc68hc11k1_device::spdr_r<0>), FUNC(mc68hc11k1_device::spdr_w<0>)); // SPDR
|
||||
map(0x30, 0x30).rw(FUNC(mc68hc11k1_device::adctl_r), FUNC(mc68hc11k1_device::adctl_w)); // ADCTL
|
||||
map(0x31, 0x34).r(FUNC(mc68hc11k1_device::adr_r)); // ADR1-ADR4
|
||||
map(0x38, 0x38).r(FUNC(mc68hc11k1_device::opt2_r)).nopw(); // OPT2
|
||||
map(0x39, 0x39).nopw(); // OPTION
|
||||
map(0x3a, 0x3a).nopw(); // COPRST (watchdog)
|
||||
map(0x3b, 0x3b).nopw(); // PPROG (EEPROM programming)
|
||||
map(0x3d, 0x3d).rw(FUNC(mc68hc11k1_device::init_r), FUNC(mc68hc11k1_device::init_w)); // INIT
|
||||
map(0x3f, 0x3f).nopw(); // CONFIG
|
||||
map(0x70, 0x71).r(FUNC(mc68hc11k1_device::scbd_r)).nopw(); // SCBD
|
||||
map(0x72, 0x72).r(FUNC(mc68hc11k1_device::sccr1_r)).nopw(); // SCCR1
|
||||
map(0x73, 0x73).r(FUNC(mc68hc11k1_device::sccr2_r)).nopw(); // SCCR2
|
||||
map(0x74, 0x74).r(FUNC(mc68hc11k1_device::scsr1_r)).nopw(); // SCSR1
|
||||
map(0x77, 0x77).r(FUNC(mc68hc11k1_device::scrdl_r)).nopw(); // SCRDL
|
||||
map(0x7c, 0x7c).rw(FUNC(mc68hc11k1_device::port_r<7>), FUNC(mc68hc11k1_device::port_w<7>)); // PORTH
|
||||
map(0x7d, 0x7d).rw(FUNC(mc68hc11k1_device::ddr_r<7>), FUNC(mc68hc11k1_device::ddr_w<7>)); // DDRH
|
||||
map(0x7e, 0x7e).rw(FUNC(mc68hc11k1_device::port_r<6>), FUNC(mc68hc11k1_device::port_w<6>)); // PORTG
|
||||
map(0x7f, 0x7f).rw(FUNC(mc68hc11k1_device::ddr_r<6>), FUNC(mc68hc11k1_device::ddr_w<6>)); // DDRG
|
||||
}
|
||||
|
||||
void mc68hc11m0_device::io_map(address_map &map)
|
||||
{
|
||||
map(0x00, 0x00).rw(FUNC(mc68hc11m0_device::port_r<0>), FUNC(mc68hc11m0_device::port_w<0>)); // PORTA
|
||||
map(0x01, 0x01).rw(FUNC(mc68hc11m0_device::ddr_r<0>), FUNC(mc68hc11m0_device::ddr_w<0>)); // DDRA
|
||||
map(0x02, 0x02).rw(FUNC(mc68hc11m0_device::ddr_r<1>), FUNC(mc68hc11m0_device::ddr_w<1>)); // DDRB
|
||||
map(0x03, 0x03).rw(FUNC(mc68hc11m0_device::ddr_r<5>), FUNC(mc68hc11m0_device::ddr_w<5>)); // DDRF
|
||||
map(0x04, 0x04).rw(FUNC(mc68hc11m0_device::port_r<1>), FUNC(mc68hc11m0_device::port_w<1>)); // PORTB
|
||||
map(0x05, 0x05).rw(FUNC(mc68hc11m0_device::port_r<5>), FUNC(mc68hc11m0_device::port_w<5>)); // PORTF
|
||||
map(0x06, 0x06).rw(FUNC(mc68hc11m0_device::port_r<2>), FUNC(mc68hc11m0_device::port_w<2>)); // PORTC
|
||||
map(0x07, 0x07).rw(FUNC(mc68hc11m0_device::ddr_r<2>), FUNC(mc68hc11m0_device::ddr_w<2>)); // DDRC
|
||||
map(0x08, 0x08).rw(FUNC(mc68hc11m0_device::port_r<3>), FUNC(mc68hc11m0_device::port_w<3>)); // PORTD
|
||||
map(0x09, 0x09).rw(FUNC(mc68hc11m0_device::ddr_r<3>), FUNC(mc68hc11m0_device::ddr_w<3>)); // DDRD
|
||||
map(0x0a, 0x0a).r(FUNC(mc68hc11m0_device::port_r<4>)); // PORTE
|
||||
map(0x0e, 0x0f).rw(FUNC(mc68hc11m0_device::tcnt_r), FUNC(mc68hc11m0_device::tcnt_w)); // TCNT
|
||||
map(0x16, 0x17).rw(FUNC(mc68hc11m0_device::toc1_r), FUNC(mc68hc11m0_device::toc1_w)); // TOC1
|
||||
map(0x22, 0x22).rw(FUNC(mc68hc11m0_device::tmsk1_r), FUNC(mc68hc11m0_device::tmsk1_w)); // TMSK1
|
||||
map(0x23, 0x23).rw(FUNC(mc68hc11m0_device::tflg1_r), FUNC(mc68hc11m0_device::tflg1_w)); // TFLG1
|
||||
map(0x24, 0x24).w(FUNC(mc68hc11m0_device::tmsk2_w)); // TMSK2
|
||||
map(0x28, 0x28).r(FUNC(mc68hc11m0_device::spcr_r<0>)).nopw(); // SPCR1
|
||||
map(0x29, 0x29).r(FUNC(mc68hc11m0_device::spsr_r<0>)).nopw(); // SPSR1
|
||||
map(0x2a, 0x2a).rw(FUNC(mc68hc11m0_device::spdr_r<0>), FUNC(mc68hc11m0_device::spdr_w<0>)); // SPDR1
|
||||
map(0x30, 0x30).rw(FUNC(mc68hc11m0_device::adctl_r), FUNC(mc68hc11m0_device::adctl_w)); // ADCTL
|
||||
map(0x31, 0x34).r(FUNC(mc68hc11m0_device::adr_r)); // ADR1-ADR4
|
||||
map(0x38, 0x38).r(FUNC(mc68hc11m0_device::opt2_r)).nopw(); // OPT2
|
||||
map(0x39, 0x39).nopw(); // OPTION
|
||||
map(0x3a, 0x3a).nopw(); // COPRST (watchdog)
|
||||
map(0x3d, 0x3d).rw(FUNC(mc68hc11m0_device::init_r), FUNC(mc68hc11m0_device::init_w)); // INIT
|
||||
map(0x3f, 0x3f).nopw(); // CONFIG
|
||||
map(0x70, 0x71).r(FUNC(mc68hc11m0_device::scbd_r)).nopw(); // SCBD
|
||||
map(0x72, 0x72).r(FUNC(mc68hc11m0_device::sccr1_r)).nopw(); // SCCR1
|
||||
map(0x73, 0x73).r(FUNC(mc68hc11m0_device::sccr2_r)).nopw(); // SCCR2
|
||||
map(0x74, 0x74).r(FUNC(mc68hc11m0_device::scsr1_r)); // SCSR1
|
||||
map(0x77, 0x77).r(FUNC(mc68hc11m0_device::scrdl_r)).nopw(); // SCRDL
|
||||
map(0x7c, 0x7c).rw(FUNC(mc68hc11m0_device::port_r<7>), FUNC(mc68hc11m0_device::port_w<7>)); // PORTH
|
||||
map(0x7d, 0x7d).rw(FUNC(mc68hc11m0_device::ddr_r<7>), FUNC(mc68hc11m0_device::ddr_w<7>)); // DDRH
|
||||
map(0x7e, 0x7e).rw(FUNC(mc68hc11m0_device::port_r<6>), FUNC(mc68hc11m0_device::port_w<6>)); // PORTG
|
||||
map(0x7f, 0x7f).rw(FUNC(mc68hc11m0_device::ddr_r<6>), FUNC(mc68hc11m0_device::ddr_w<6>)); // DDRG
|
||||
map(0x88, 0x88).r(FUNC(mc68hc11m0_device::spcr_r<1>)).nopw(); // SPCR2
|
||||
map(0x89, 0x89).r(FUNC(mc68hc11m0_device::spsr_r<1>)).nopw(); // SPSR2
|
||||
map(0x8a, 0x8a).rw(FUNC(mc68hc11m0_device::spdr_r<1>), FUNC(mc68hc11m0_device::spdr_w<1>)); // SPDR2
|
||||
map(0x8b, 0x8b).r(FUNC(mc68hc11m0_device::opt4_r)).nopw(); // OPT4
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
@ -480,6 +594,8 @@ void mc68hc11_cpu_device::device_start()
|
||||
// save_item(NAME(m_por));
|
||||
save_item(NAME(m_pr));
|
||||
save_item(NAME(m_frc_base));
|
||||
save_item(NAME(m_port_data));
|
||||
save_item(NAME(m_port_dir));
|
||||
|
||||
m_pc = 0;
|
||||
m_d.d16 = 0;
|
||||
@ -494,6 +610,7 @@ void mc68hc11_cpu_device::device_start()
|
||||
m_reg_position = 0;
|
||||
m_tflg1 = 0;
|
||||
m_tmsk1 = 0;
|
||||
std::fill(std::begin(m_port_data), std::end(m_port_data), 0x00);
|
||||
|
||||
state_add( HC11_PC, "PC", m_pc).formatstr("%04X");
|
||||
state_add( HC11_SP, "SP", m_sp).formatstr("%04X");
|
||||
@ -535,12 +652,31 @@ void mc68hc11_cpu_device::device_reset()
|
||||
m_wait_state = 0;
|
||||
m_stop_state = 0;
|
||||
m_ccr = CC_X | CC_I | CC_S;
|
||||
hc11_regs_w(0x3d,m_init_value);
|
||||
init_w(m_init_value);
|
||||
m_toc1 = 0xffff;
|
||||
m_tcnt = 0xffff;
|
||||
// m_por = 1; // for first timer overflow / compare stuff
|
||||
m_pr = 3; // timer prescale
|
||||
m_frc_base = 0;
|
||||
std::fill(std::begin(m_port_dir), std::end(m_port_dir), 0x00);
|
||||
}
|
||||
|
||||
void mc68hc11a1_device::device_reset()
|
||||
{
|
||||
mc68hc11_cpu_device::device_reset();
|
||||
|
||||
m_port_data[0] &= 0x87;
|
||||
m_port_data[1] = 0x00;
|
||||
ddr_w<0>(0x78);
|
||||
ddr_w<1>(0xff);
|
||||
}
|
||||
|
||||
void mc68hc11d0_device::device_reset()
|
||||
{
|
||||
mc68hc11_cpu_device::device_reset();
|
||||
|
||||
m_port_data[0] &= 0x7f;
|
||||
ddr_w<0>(0x70);
|
||||
}
|
||||
|
||||
/*
|
||||
|
||||
@ -71,7 +71,36 @@ protected:
|
||||
// device_disasm_interface overrides
|
||||
virtual std::unique_ptr<util::disasm_interface> create_disassembler() override;
|
||||
|
||||
void io_map(address_map &map);
|
||||
template <int P> uint8_t port_r();
|
||||
template <int P> void port_w(uint8_t data);
|
||||
template <int P> uint8_t ddr_r();
|
||||
template <int P> void ddr_w(uint8_t data);
|
||||
uint8_t pioc_r();
|
||||
uint8_t tcnt_r(offs_t offset);
|
||||
void tcnt_w(offs_t offset, uint8_t data);
|
||||
uint8_t toc1_r(offs_t offset);
|
||||
void toc1_w(offs_t offset, uint8_t data);
|
||||
uint8_t tmsk1_r();
|
||||
void tmsk1_w(uint8_t data);
|
||||
uint8_t tflg1_r();
|
||||
void tflg1_w(uint8_t data);
|
||||
void tmsk2_w(uint8_t data);
|
||||
template <int N> uint8_t spcr_r();
|
||||
template <int N> uint8_t spsr_r();
|
||||
template <int N> uint8_t spdr_r();
|
||||
template <int N> void spdr_w(uint8_t data);
|
||||
uint8_t adctl_r();
|
||||
void adctl_w(uint8_t data);
|
||||
uint8_t adr_r(offs_t offset);
|
||||
uint8_t opt2_r();
|
||||
uint8_t init_r();
|
||||
void init_w(uint8_t data);
|
||||
uint8_t scbd_r(offs_t offset);
|
||||
uint8_t sccr1_r();
|
||||
uint8_t sccr2_r();
|
||||
uint8_t scsr1_r();
|
||||
uint8_t scrdl_r();
|
||||
uint8_t opt4_r();
|
||||
|
||||
private:
|
||||
address_space_config m_program_config;
|
||||
@ -98,6 +127,11 @@ private:
|
||||
uint16_t m_ppc;
|
||||
uint8_t m_ccr;
|
||||
|
||||
protected:
|
||||
uint8_t m_port_data[8];
|
||||
private:
|
||||
uint8_t m_port_dir[8];
|
||||
|
||||
uint8_t m_adctl;
|
||||
int m_ad_channel;
|
||||
|
||||
@ -147,8 +181,8 @@ private:
|
||||
ophandler hc11_optable_page4[256];
|
||||
|
||||
void ram_map(address_map &map);
|
||||
uint8_t hc11_regs_r(uint32_t address);
|
||||
void hc11_regs_w(uint32_t address, uint8_t value);
|
||||
|
||||
uint8_t FETCH();
|
||||
uint16_t FETCH16();
|
||||
uint8_t READ8(uint32_t address);
|
||||
@ -480,6 +514,14 @@ class mc68hc11a1_device : public mc68hc11_cpu_device
|
||||
public:
|
||||
// construction/destruction
|
||||
mc68hc11a1_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
|
||||
protected:
|
||||
virtual void device_reset() override;
|
||||
|
||||
uint8_t pactl_r();
|
||||
void pactl_w(uint8_t data);
|
||||
|
||||
void io_map(address_map &map);
|
||||
};
|
||||
|
||||
class mc68hc11d0_device : public mc68hc11_cpu_device
|
||||
@ -487,6 +529,14 @@ class mc68hc11d0_device : public mc68hc11_cpu_device
|
||||
public:
|
||||
// construction/destruction
|
||||
mc68hc11d0_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
|
||||
protected:
|
||||
virtual void device_reset() override;
|
||||
|
||||
uint8_t pactl_r();
|
||||
void pactl_w(uint8_t data);
|
||||
|
||||
void io_map(address_map &map);
|
||||
};
|
||||
|
||||
class mc68hc11k1_device : public mc68hc11_cpu_device
|
||||
@ -494,6 +544,9 @@ class mc68hc11k1_device : public mc68hc11_cpu_device
|
||||
public:
|
||||
// construction/destruction
|
||||
mc68hc11k1_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
|
||||
protected:
|
||||
void io_map(address_map &map);
|
||||
};
|
||||
|
||||
class mc68hc11m0_device : public mc68hc11_cpu_device
|
||||
@ -501,6 +554,9 @@ class mc68hc11m0_device : public mc68hc11_cpu_device
|
||||
public:
|
||||
// construction/destruction
|
||||
mc68hc11m0_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
|
||||
protected:
|
||||
void io_map(address_map &map);
|
||||
};
|
||||
|
||||
#endif // MAME_CPU_MC68HC11_MC68HC11_H
|
||||
|
||||
@ -53,7 +53,6 @@ private:
|
||||
DECLARE_WRITE16_MEMBER(ramdac_w);
|
||||
DECLARE_WRITE8_MEMBER(tms_w);
|
||||
DECLARE_READ8_MEMBER(tms_r);
|
||||
DECLARE_READ8_MEMBER(hc11_porta_r);
|
||||
DECLARE_WRITE8_MEMBER(hc11_porta_w);
|
||||
DECLARE_WRITE8_MEMBER(ay8910_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(tms_irq);
|
||||
@ -161,11 +160,6 @@ READ8_MEMBER(skeetsht_state::tms_r)
|
||||
*
|
||||
*************************************/
|
||||
|
||||
READ8_MEMBER(skeetsht_state::hc11_porta_r)
|
||||
{
|
||||
return m_porta_latch;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(skeetsht_state::hc11_porta_w)
|
||||
{
|
||||
if (!(data & 0x8) && (m_porta_latch & 8))
|
||||
@ -233,7 +227,6 @@ void skeetsht_state::skeetsht(machine_config &config)
|
||||
{
|
||||
MC68HC11A1(config, m_68hc11, 4000000); // ?
|
||||
m_68hc11->set_addrmap(AS_PROGRAM, &skeetsht_state::hc11_pgm_map);
|
||||
m_68hc11->in_pa_callback().set(FUNC(skeetsht_state::hc11_porta_r));
|
||||
m_68hc11->out_pa_callback().set(FUNC(skeetsht_state::hc11_porta_w));
|
||||
|
||||
TMS34010(config, m_tms, 48000000);
|
||||
|
||||
@ -713,11 +713,6 @@ WRITE8_MEMBER(taitojc_state::hc11_data_w)
|
||||
m_mcu_data_main = data;
|
||||
}
|
||||
|
||||
READ8_MEMBER(taitojc_state::hc11_output_r)
|
||||
{
|
||||
return m_mcu_output;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(taitojc_state::hc11_output_w)
|
||||
{
|
||||
/*
|
||||
@ -741,8 +736,6 @@ WRITE8_MEMBER(taitojc_state::hc11_output_w)
|
||||
*/
|
||||
for (int i = 0; i < 8; i++)
|
||||
m_lamps[i] = BIT(data, i);
|
||||
|
||||
m_mcu_output = data;
|
||||
}
|
||||
|
||||
template <int Ch>
|
||||
@ -1065,7 +1058,6 @@ void taitojc_state::machine_start()
|
||||
save_item(NAME(m_mcu_comm_hc11));
|
||||
save_item(NAME(m_mcu_data_main));
|
||||
save_item(NAME(m_mcu_data_hc11));
|
||||
save_item(NAME(m_mcu_output));
|
||||
|
||||
save_item(NAME(m_speed_meter));
|
||||
save_item(NAME(m_brake_meter));
|
||||
@ -1088,7 +1080,6 @@ void taitojc_state::taitojc(machine_config &config)
|
||||
sub.in_pa_callback().set_constant(0); // ?
|
||||
sub.in_pg_callback().set(FUNC(taitojc_state::hc11_comm_r));
|
||||
sub.out_pg_callback().set(FUNC(taitojc_state::hc11_comm_w));
|
||||
sub.in_ph_callback().set(FUNC(taitojc_state::hc11_output_r));
|
||||
sub.out_ph_callback().set(FUNC(taitojc_state::hc11_output_w));
|
||||
sub.in_spi2_data_callback().set(FUNC(taitojc_state::hc11_data_r));
|
||||
sub.out_spi2_data_callback().set(FUNC(taitojc_state::hc11_data_w));
|
||||
|
||||
@ -33,7 +33,6 @@ public:
|
||||
m_lamps(*this, "lamp%u", 0U),
|
||||
m_counters(*this, "counter%u", 0U)
|
||||
{
|
||||
m_mcu_output = 0;
|
||||
m_speed_meter = 0;
|
||||
m_brake_meter = 0;
|
||||
}
|
||||
@ -85,7 +84,6 @@ private:
|
||||
uint8_t m_mcu_comm_hc11;
|
||||
uint8_t m_mcu_data_main;
|
||||
uint8_t m_mcu_data_hc11;
|
||||
uint8_t m_mcu_output;
|
||||
|
||||
uint8_t m_has_dsp_hack;
|
||||
|
||||
@ -107,7 +105,6 @@ private:
|
||||
DECLARE_WRITE8_MEMBER(hc11_comm_w);
|
||||
DECLARE_WRITE8_MEMBER(hc11_output_w);
|
||||
DECLARE_READ8_MEMBER(hc11_data_r);
|
||||
DECLARE_READ8_MEMBER(hc11_output_r);
|
||||
DECLARE_WRITE8_MEMBER(hc11_data_w);
|
||||
template <int Ch> uint8_t hc11_analog_r();
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user