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https://github.com/holub/mame
synced 2025-04-19 23:12:11 +03:00
netlist: fix power pin names for CMOS devices.
* For truthtable cmos devices the power pin names will now be set according to the logic family. * Fix some issues for CD4538 * Change "already connected" warning to info level. Some ICs (CD4538) connect pins internally to GND and the schematics again externally. This will cause this info to be printed. The warning now is a lot more verbose.
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@ -79,8 +79,8 @@ namespace netlist
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//, m_power_pins(*this)
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{
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register_subalias("GND", m_RN.N());
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register_subalias("VCC", m_RP.P());
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register_subalias(pstring(D::gnd()), m_RN.N());
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register_subalias(pstring(D::vcc()), m_RP.P());
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register_subalias("C", m_RN.N());
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register_subalias("RC", m_RN.P());
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@ -197,6 +197,9 @@ namespace netlist
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return ((in[1]() | (in[2]() ^ 1)) ^ 1) & in[0](); // ((m_A() | (m_B() ^ 1)) ^ 1) & m_CLRQ()
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}
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template<typename T> static constexpr netlist_sig_t clear(const T &in) { return in[0]();}
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static constexpr const char *vcc() { return "VCC"; }
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static constexpr const char *gnd() { return "GND"; }
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};
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struct desc_74121 : public desc_74123
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@ -232,6 +235,8 @@ namespace netlist
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{
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return (in[1]() | (in[2]() ^ 1)); // m_A() | (m_B() ^ 1)
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}
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static constexpr const char *vcc() { return "VDD"; }
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static constexpr const char *gnd() { return "VSS"; }
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};
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using NETLIB_NAME(74123) = NETLIB_NAME(74123_base)<desc_74123>;
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@ -61,6 +61,6 @@
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NET_REGISTER_DEV(TTL_9602, name)
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#define CD4538(name) \
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NET_REGISTER_DEV(TTL_4538, name)
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NET_REGISTER_DEV(CD4538, name)
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#endif /* NLD_74123_H_ */
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@ -50,7 +50,7 @@ namespace devices
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, m_ign(*this, "m_ign", 0)
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, m_ttp(ttp)
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/* FIXME: the family should provide the names of the power-terminals! */
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, m_power_pins(*this)
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, m_power_pins(*this, logic_family()->vcc_pin(), logic_family()->gnd_pin())
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{
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init(desc);
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}
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@ -84,6 +84,7 @@ NETLIST_START(congo_bongo)
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NET_C(R94.1, SJ1)
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NET_C(SOU1, amp.AMPIN1)
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NET_C(GND, amp.GND)
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#if USE_OPTIMIZATIONS
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/* The opamp has an UGF of about 1000k. This doesn't work here and causes oscillations.
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@ -366,7 +367,8 @@ NETLIST_START(CongoBongo_amp)
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ALIAS(AMPIN1, R83.1)
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ALIAS(AMPOUT1, R77.1)
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ANALOG_INPUT(I_V12, 12)
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ANALOG_INPUT(GND, 0)
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//ANALOG_INPUT(GND, 0)
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ALIAS(GND, C66.2)
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CAP(C124, CAP_U(470))
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CAP(C51, CAP_U(10))
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CAP(C53, CAP_U(200))
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@ -404,7 +406,8 @@ NETLIST_START(CongoBongo_amp)
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NET_C(R77.2, C53.1)
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NET_C(C66.1, U2.4, C124.1, R89.1, I_V12.Q)
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NET_C(R83.1, R91.1)
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NET_C(GND, C66.2, U2.11, C124.2, C56.2, C55.2, C57.2, C59.2, R90.2, C53.2, XVR1.3)
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//NET_C(GND, C66.2, U2.11, C124.2, C56.2, C55.2, C57.2, C59.2, R90.2, C53.2, XVR1.3)
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NET_C(GND, U2.11, C124.2, C56.2, C55.2, C57.2, C59.2, R90.2, C53.2, XVR1.3)
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NET_C(R83.2, U2.13, U2.14, R86.1)
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NET_C(U2.1, R88.1, C51.1)
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NET_C(U2.7, R85.1, R87.2)
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@ -292,7 +292,7 @@ static NETLIST_START(CD4538_DIP)
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ALIAS(5, A.B)
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ALIAS(6, A.Q)
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ALIAS(7, A.QQ)
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ALIAS(8, A.C)
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ALIAS(8, A.VSS)
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ALIAS(9, B.QQ)
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ALIAS(10, B.Q)
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@ -301,10 +301,10 @@ static NETLIST_START(CD4538_DIP)
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ALIAS(13, B.CLRQ)
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ALIAS(14, B.RC) // RC2
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ALIAS(15, B.C) // C2
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ALIAS(16, A.RP.1)
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ALIAS(16, A.VDD)
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NET_C(A.VCC, B.VCC)
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NET_C(A.GND, B.GND)
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NET_C(A.VDD, B.VDD)
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NET_C(A.VSS, B.VSS)
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NETLIST_END()
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@ -27,16 +27,16 @@ static NETLIST_START(MC14584B_DIP)
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MC14584B_GATE(E)
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MC14584B_GATE(F)
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NET_C(A.VCC, B.VCC, C.VCC, D.VCC, E.VCC, F.VCC)
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NET_C(A.GND, B.GND, C.GND, D.GND, E.GND, F.GND)
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NET_C(A.VDD, B.VDD, C.VDD, D.VDD, E.VDD, F.VDD)
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NET_C(A.VSS, B.VSS, C.VSS, D.VSS, E.VSS, F.VSS)
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DIPPINS( /* +--------------+ */
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A.A, /* A1 |1 ++ 14| VCC */ A.VCC,
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A.A, /* A1 |1 ++ 14| VDD */ A.VDD,
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A.Q, /* Y1 |2 13| A6 */ F.A,
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B.A, /* A2 |3 12| Y6 */ F.Q,
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B.Q, /* Y2 |4 MC14584B 11| A5 */ E.A,
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C.A, /* A3 |5 10| Y5 */ E.Q,
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C.Q, /* Y3 |6 9| A4 */ D.A,
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A.GND,/* GND |7 8| Y4 */ D.Q
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A.VSS,/* VSS |7 8| Y4 */ D.Q
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/* +--------------+ */
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)
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NETLIST_END()
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@ -274,12 +274,17 @@ namespace netlist
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bool is_below_low_thresh_V(nl_fptype V, nl_fptype VN, nl_fptype VP) const noexcept
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{ return V < low_thresh_V(VN, VP); }
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pstring vcc_pin() const { return pstring(m_vcc); }
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pstring gnd_pin() const { return pstring(m_gnd); }
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nl_fptype m_low_thresh_PCNT; //!< low input threshhold offset. If the input voltage is below this value times supply voltage, a "0" input is signalled
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nl_fptype m_high_thresh_PCNT; //!< high input threshhold offset. If the input voltage is above the value times supply voltage, a "0" input is signalled
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nl_fptype m_low_VO; //!< low output voltage offset. This voltage is output if the ouput is "0"
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nl_fptype m_high_VO; //!< high output voltage offset. The supply voltage minus this offset is output if the ouput is "1"
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nl_fptype m_R_low; //!< low output resistance. Value of series resistor used for low output
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nl_fptype m_R_high; //!< high output resistance. Value of series resistor used for high output
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const char *m_vcc; //!< default power pin name for positive supply
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const char *m_gnd; //!< default power pin name for negative supply
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};
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/// \brief Base class for devices, terminals, outputs and inputs which support
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@ -92,7 +92,10 @@ namespace netlist
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PERRMSGV(MI_OVERWRITING_PARAM_1_OLD_2_NEW_3, 3, "Overwriting {1} old <{2}> new <{3}>")
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PERRMSGV(MW_CONNECTING_1_TO_ITSELF, 1, "Connecting net {1} to itself.")
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PERRMSGV(MW_CONNECTING_1_TO_2_SAME_NET, 3, "Connecting terminals {1} and {2} which are already both on net {3}")
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PERRMSGV(MI_CONNECTING_1_TO_2_SAME_NET, 3, "Connecting terminals {1} and {2} which are already both on net {3}. "
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"It is ok if you read this warning and it relates to pin which is connected internally to GND and the schematics "
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"show an external connection as well. Onde example is the CD4538. In other cases this warning may indicate "
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"an error in your netlist.")
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PERRMSGV(ME_NC_PIN_1_WITH_CONNECTIONS, 1, "Found NC (not connected) terminal {1} with connections")
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PERRMSGV(MI_ANALOG_OUTPUT_1_WITHOUT_CONNECTIONS,1, "Found analog output {1} without connections")
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PERRMSGV(MI_LOGIC_OUTPUT_1_WITHOUT_CONNECTIONS, 1, "Found logic output {1} without connections")
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@ -868,9 +868,13 @@ void setup_t::connect_terminal_output(terminal_t &in, detail::core_terminal_t &o
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// no proxy needed, just merge existing terminal net
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if (in.has_net())
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{
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if (&out.net() == &in.net())
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log().warning(MW_CONNECTING_1_TO_2_SAME_NET(in.name(), out.name(), in.net().name()));
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merge_nets(out.net(), in.net());
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if (&out.net() != &in.net())
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merge_nets(out.net(), in.net());
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else
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// Only an info - some ICs (CD4538) connect pins internally to GND
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// and the schematics again externally. This will cause this warning.
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// FIXME: Add a hint to suppress the warning.
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log().info(MI_CONNECTING_1_TO_2_SAME_NET(in.name(), out.name(), in.net().name()));
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}
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else
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add_terminal(out.net(), in);
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@ -1447,6 +1451,22 @@ const logic_family_desc_t *setup_t::family_from_model(const pstring &model)
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ret->m_R_low = modv.m_ORL();
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ret->m_R_high = modv.m_ORH();
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switch (ft)
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{
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case family_type::CUSTOM:
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case family_type::TTL:
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ret->m_vcc = "VCC";
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ret->m_gnd = "GND";
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break;
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case family_type::MOS:
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case family_type::CMOS:
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case family_type::NMOS:
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case family_type::PMOS:
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ret->m_vcc = "VDD";
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ret->m_gnd = "VSS";
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break;
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}
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auto *retp = ret.get();
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m_nlstate.family_cache().emplace(model, std::move(ret));
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