mirror of
https://github.com/holub/mame
synced 2025-05-02 04:31:01 +03:00
SH-2 DRC updates:
- Moved IRQ handling front-end into recompiled code - Added TSTM/ANDM/XORM instructions - Added SH-1 CPU support, including lower precision on MAC.W and locking out SH-2 only instructions
This commit is contained in:
R. Belmont
parent
9c671d6ecf
commit
a6210713da
@ -456,10 +456,17 @@ $(CPUOBJ)/h83002/h8periph.o: $(CPUSRC)/h83002/h8periph.c \
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$(CPUSRC)/h83002/h8priv.h
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#-------------------------------------------------
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# Hitachi SH1/SH2
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#-------------------------------------------------
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#-------------------------------------------------
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# Hitachi SH2
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#-------------------------------------------------
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CPUDEFS += -DHAS_SH1=$(if $(filter SH1,$(CPUS)),1,0)
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ifneq ($(filter SH1,$(CPUS)),)
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OBJDIRS += $(CPUOBJ)/sh2
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CPUOBJS += $(CPUOBJ)/sh2/sh2.o $(CPUOBJ)/sh2/sh2comn.o $(CPUOBJ)/sh2/sh2drc.o $(CPUOBJ)/sh2/sh2fe.o
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DBGOBJS += $(CPUOBJ)/sh2/sh2dasm.o
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endif
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CPUDEFS += -DHAS_SH2=$(if $(filter SH2,$(CPUS)),1,0)
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@ -47,6 +47,9 @@ enum
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#define Rn ((opcode>>8)&15)
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#define Rm ((opcode>>4)&15)
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#define CPU_TYPE_SH1 (0)
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#define CPU_TYPE_SH2 (1)
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#define REGFLAG_R(n) (1 << (n))
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/* register flags 1 */
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@ -97,6 +100,7 @@ typedef struct
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UINT32 pending_irq;
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UINT32 test_irq;
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UINT32 pending_nmi;
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INT32 irqline;
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UINT32 evec; // exception vector for DRC
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UINT32 irqsr; // IRQ-time old SR for DRC
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UINT32 target; // target for jmp/jsr/etc so the delay slot can't kill it
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@ -123,7 +127,7 @@ typedef struct
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emu_timer *dma_timer[2];
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int dma_timer_active[2];
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int is_slave, cpu_number;
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int is_slave, cpu_number, cpu_type;
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void (*ftcsr_read_callback)(UINT32 data);
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@ -19,6 +19,7 @@
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#include "deprecat.h"
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#include "sh2.h"
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#include "sh2comn.h"
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#include "eminline.h"
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#ifdef USE_SH2DRC
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@ -125,6 +126,7 @@ static const char *log_desc_flags_to_string(UINT32 flags);
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static void cfunc_printf_probe(void *param);
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static void cfunc_unimplemented(void *param);
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static void cfunc_checkirqs(void *param);
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static void cfunc_fastirq(void *param);
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static void cfunc_MAC_W(void *param);
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static void cfunc_MAC_L(void *param);
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static void cfunc_DIV1(void *param);
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@ -139,6 +141,28 @@ SH2 *sh2;
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INLINE FUNCTIONS
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***************************************************************************/
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INLINE UINT16 RW(offs_t A)
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{
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if (A >= 0xe0000000)
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return sh2_internal_r(Machine, (A & 0x1fc)>>2, 0xffff << (((~A) & 2)*8)) >> (((~A) & 2)*8);
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if (A >= 0xc0000000)
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return program_read_word_32be(A);
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return program_read_word_32be(A & AM);
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}
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INLINE UINT32 RL(offs_t A)
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{
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if (A >= 0xe0000000)
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return sh2_internal_r(Machine, (A & 0x1fc)>>2, 0xffffffff);
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if (A >= 0xc0000000)
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return program_read_dword_32be(A);
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return program_read_dword_32be(A & AM);
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}
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/*-------------------------------------------------
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epc - compute the exception PC from a
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descriptor
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@ -264,15 +288,12 @@ static void cfunc_checkirqs(void *param)
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}
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}
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INLINE UINT16 RW(offs_t A)
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/*-------------------------------------------------
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cfunc_fastirq - checks for pending IRQs
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-------------------------------------------------*/
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static void cfunc_fastirq(void *param)
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{
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if (A >= 0xe0000000)
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return sh2_internal_r(Machine, (A & 0x1fc)>>2, 0xffff << (((~A) & 2)*8)) >> (((~A) & 2)*8);
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if (A >= 0xc0000000)
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return program_read_word_32be(A);
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return program_read_word_32be(A & AM);
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sh2_exception("fastirq",sh2->irqline);
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}
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/*-------------------------------------------------
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@ -324,6 +345,11 @@ static void cfunc_MAC_W(void *param)
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{
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if (ans == 1)
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{
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if ((sh2->cpu_type == CPU_TYPE_SH1) && ((src == 0) || (src == 2)))
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{
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sh2->mach |= 0x00000001;
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}
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if (src == 0)
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sh2->macl = 0x7fffffff;
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if (src == 2)
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@ -335,20 +361,24 @@ static void cfunc_MAC_W(void *param)
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sh2->mach += tempn;
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if (templ > sh2->macl)
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sh2->mach += 1;
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// SH-1 has limited precision
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if (sh2->cpu_type == CPU_TYPE_SH1)
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{
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if ((sh2->mach & 0x200) == 0)
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{
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sh2->mach &= 0x3ff;
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}
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else
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{
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sh2->mach |= 0xfffffc00;
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}
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}
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}
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}
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INLINE UINT32 RL(offs_t A)
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{
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if (A >= 0xe0000000)
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return sh2_internal_r(Machine, (A & 0x1fc)>>2, 0xffffffff);
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if (A >= 0xc0000000)
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return program_read_dword_32be(A);
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return program_read_dword_32be(A & AM);
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}
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/*-------------------------------------------------
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cfunc_MAC_L - implementation of MAC_L Rm,Rn
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-------------------------------------------------*/
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@ -795,6 +825,18 @@ static void sh2_reset(void)
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sh2->internal_irq_level = -1;
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sh2->cache_dirty = TRUE;
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sh2->cpu_type = CPU_TYPE_SH2;
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}
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/*-------------------------------------------------
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sh1_reset - reset the processor
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-------------------------------------------------*/
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static void sh1_reset(void)
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{
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sh2_reset();
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sh2->cpu_type = CPU_TYPE_SH1;
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}
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/*-------------------------------------------------
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@ -992,7 +1034,35 @@ static void static_generate_entry_point(drcuml_state *drcuml)
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load_fast_iregs(block);
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/* check for interrupts */
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UML_CALLC(block, cfunc_checkirqs, NULL);
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UML_CMP(block, MEM(&sh2->pending_nmi), IMM(0)); // cmp pending_nmi, #0
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UML_JMPc(block, IF_Z, skip+2); // jz skip+2
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UML_MOV(block, MEM(&sh2->pending_nmi), IMM(0)); // zap pending_nmi
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UML_JMP(block, skip+1); // and then go take it (evec is already set)
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UML_LABEL(block, skip+2); // skip+2:
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UML_MOV(block, MEM(&sh2->evec), IMM(0xffffffff)); // mov evec, -1
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UML_MOV(block, IREG(0), IMM(0xffffffff)); // mov r0, -1 (r0 = irq)
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UML_AND(block, IREG(1), IREG(0), IMM(0xffff)); // and r1, 0xffff
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UML_LZCNT(block, IREG(1), MEM(&sh2->pending_irq)); // lzcnt r1, r1
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UML_CMP(block, IREG(1), IMM(32)); // cmp r1, #32
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UML_JMPc(block, IF_Z, skip+1); // jz skip+1
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UML_SUB(block, MEM(&sh2->irqline), IMM(31), IREG(1)); // sub irqline, #31, r1
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UML_CMP(block, MEM(&sh2->internal_irq_level), IMM(0xffffffff)); // cmp internal_irq_level, #-1
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UML_JMPc(block, IF_Z, skip+3); // jz skip+3
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UML_CMP(block, MEM(&sh2->internal_irq_level), MEM(&sh2->irqline)); // cmp internal_irq_level, irqline
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UML_JMPc(block, IF_BE, skip+3); // ja skip+3
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UML_MOV(block, MEM(&sh2->irqline), MEM(&sh2->internal_irq_level)); // mov r0, internal_irq_level
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UML_LABEL(block, skip+3); // skip+3:
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UML_CMP(block, MEM(&sh2->irqline), IMM(0xffffffff)); // cmp irqline, #-1
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UML_JMPc(block, IF_Z, skip+1); // jz skip+1
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UML_CALLC(block, cfunc_fastirq, NULL); // callc fastirq
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UML_LABEL(block, skip+1); // skip+1:
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UML_CMP(block, MEM(&sh2->evec), IMM(0xffffffff)); // cmp evec, 0xffffffff
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UML_JMPc(block, IF_Z, skip); // jz skip
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@ -1344,10 +1414,38 @@ static void generate_update_cycles(drcuml_block *block, compiler_state *compiler
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drcuml_codelabel skip = compiler->labelnum++;
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compiler->checkints = FALSE;
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compiler->labelnum += 3;
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/* check for interrupts */
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UML_CALLC(block, cfunc_checkirqs, NULL);
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UML_CMP(block, MEM(&sh2->pending_nmi), IMM(0)); // cmp pending_nmi, #0
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UML_JMPc(block, IF_Z, skip+2); // jz skip+2
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UML_MOV(block, MEM(&sh2->pending_nmi), IMM(0)); // zap pending_nmi
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UML_JMP(block, skip+1); // and then go take it (evec is already set)
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UML_LABEL(block, skip+2); // skip+2:
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UML_MOV(block, MEM(&sh2->evec), IMM(0xffffffff)); // mov evec, -1
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UML_MOV(block, IREG(0), IMM(0xffffffff)); // mov r0, -1 (r0 = irq)
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UML_AND(block, IREG(1), IREG(0), IMM(0xffff)); // and r1, 0xffff
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UML_LZCNT(block, IREG(1), MEM(&sh2->pending_irq)); // lzcnt r1, r1
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UML_CMP(block, IREG(1), IMM(32)); // cmp r1, #32
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UML_JMPc(block, IF_Z, skip+1); // jz skip+1
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UML_SUB(block, MEM(&sh2->irqline), IMM(31), IREG(1)); // sub irqline, #31, r1
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UML_CMP(block, MEM(&sh2->internal_irq_level), IMM(0xffffffff)); // cmp internal_irq_level, #-1
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UML_JMPc(block, IF_Z, skip+3); // jz skip+3
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UML_CMP(block, MEM(&sh2->internal_irq_level), MEM(&sh2->irqline)); // cmp internal_irq_level, irqline
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UML_JMPc(block, IF_BE, skip+3); // ja skip+3
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UML_MOV(block, MEM(&sh2->irqline), MEM(&sh2->internal_irq_level)); // mov r0, internal_irq_level
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UML_LABEL(block, skip+3); // skip+3:
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UML_CMP(block, MEM(&sh2->irqline), IMM(0xffffffff)); // cmp irqline, #-1
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UML_JMPc(block, IF_Z, skip+1); // jz skip+1
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UML_CALLC(block, cfunc_fastirq, NULL); // callc fastirq
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UML_LABEL(block, skip+1); // skip+1:
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UML_CMP(block, MEM(&sh2->evec), IMM(0xffffffff)); // cmp evec, 0xffffffff
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UML_JMPc(block, IF_Z, skip); // jz skip
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@ -1713,16 +1811,19 @@ static int generate_group_0(drcuml_block *block, compiler_state *compiler, const
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break;
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case 0x03: // BSRF(Rn);
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UML_ADD(block, MEM(&sh2->target), R32(Rn), IMM(4)); // add target, Rm, #4
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UML_ADD(block, MEM(&sh2->target), MEM(&sh2->target), IMM(desc->pc)); // add target, target, pc
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if (sh2->cpu_type > CPU_TYPE_SH1)
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{
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UML_ADD(block, MEM(&sh2->target), R32(Rn), IMM(4)); // add target, Rm, #4
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UML_ADD(block, MEM(&sh2->target), MEM(&sh2->target), IMM(desc->pc)); // add target, target, pc
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generate_delay_slot(block, compiler, desc);
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generate_delay_slot(block, compiler, desc);
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UML_ADD(block, MEM(&sh2->pr), IMM(desc->pc), IMM(4)); // add sh2->pr, desc->pc, #4 (skip the current insn & delay slot)
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UML_ADD(block, MEM(&sh2->pr), IMM(desc->pc), IMM(4)); // add sh2->pr, desc->pc, #4 (skip the current insn & delay slot)
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generate_update_cycles(block, compiler, MEM(&sh2->target), TRUE); // <subtract cycles>
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UML_HASHJMP(block, IMM(0), MEM(&sh2->target), sh2->nocode); // jmp target
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return TRUE;
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generate_update_cycles(block, compiler, MEM(&sh2->target), TRUE); // <subtract cycles>
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UML_HASHJMP(block, IMM(0), MEM(&sh2->target), sh2->nocode); // jmp target
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return TRUE;
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}
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break;
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case 0x04: // MOVBS0(Rm, Rn);
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@ -1770,8 +1871,11 @@ static int generate_group_0(drcuml_block *block, compiler_state *compiler, const
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case 0x17: // MULL(Rm, Rn);
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case 0x27: // MULL(Rm, Rn);
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case 0x37: // MULL(Rm, Rn);
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UML_MULU(block, MEM(&sh2->macl), MEM(&sh2->ea), R32(Rn), R32(Rm)); // mulu macl, ea, Rn, Rm
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return TRUE;
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if (sh2->cpu_type > CPU_TYPE_SH1)
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{
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UML_MULU(block, MEM(&sh2->macl), MEM(&sh2->ea), R32(Rn), R32(Rm)); // mulu macl, ea, Rn, Rm
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return TRUE;
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}
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break;
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case 0x08: // CLRT();
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@ -1837,10 +1941,13 @@ static int generate_group_0(drcuml_block *block, compiler_state *compiler, const
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case 0x1f: // MAC_L(Rm, Rn);
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case 0x2f: // MAC_L(Rm, Rn);
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case 0x3f: // MAC_L(Rm, Rn);
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save_fast_iregs(block);
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UML_CALLC(block, cfunc_MAC_L, desc->opptr.w);
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load_fast_iregs(block);
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return TRUE;
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if (sh2->cpu_type > CPU_TYPE_SH1)
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{
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save_fast_iregs(block);
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UML_CALLC(block, cfunc_MAC_L, desc->opptr.w);
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load_fast_iregs(block);
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return TRUE;
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}
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break;
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case 0x12: // STCGBR(Rn);
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@ -1906,13 +2013,17 @@ static int generate_group_0(drcuml_block *block, compiler_state *compiler, const
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return TRUE;
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break;
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case 0x23: // BRAF(Rn); 0x40 + 9054 = 9098
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UML_ADD(block, MEM(&sh2->target), R32(Rn), IMM(desc->pc+4)); // add target, Rn, pc+4
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case 0x23: // BRAF(Rn);
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if (sh2->cpu_type > CPU_TYPE_SH1)
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{
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UML_ADD(block, MEM(&sh2->target), R32(Rn), IMM(desc->pc+4)); // add target, Rn, pc+4
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generate_delay_slot(block, compiler, desc);
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generate_delay_slot(block, compiler, desc);
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generate_update_cycles(block, compiler, MEM(&sh2->target), TRUE); // <subtract cycles>
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UML_HASHJMP(block, IMM(0), MEM(&sh2->target), sh2->nocode); // jmp target
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generate_update_cycles(block, compiler, MEM(&sh2->target), TRUE); // <subtract cycles>
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UML_HASHJMP(block, IMM(0), MEM(&sh2->target), sh2->nocode); // jmp target
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return TRUE;
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}
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break;
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case 0x28: // CLRMAC();
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@ -2195,13 +2306,19 @@ static int generate_group_3(drcuml_block *block, compiler_state *compiler, const
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break;
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case 5: // DMULU(Rm, Rn);
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UML_MULU(block, MEM(&sh2->macl), MEM(&sh2->mach), R32(Rn), R32(Rm));
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return TRUE;
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if (sh2->cpu_type > CPU_TYPE_SH1)
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{
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UML_MULU(block, MEM(&sh2->macl), MEM(&sh2->mach), R32(Rn), R32(Rm));
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return TRUE;
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}
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break;
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case 13: // DMULS(Rm, Rn);
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UML_MULS(block, MEM(&sh2->macl), MEM(&sh2->mach), R32(Rn), R32(Rm));
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return TRUE;
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if (sh2->cpu_type > CPU_TYPE_SH1)
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{
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UML_MULS(block, MEM(&sh2->macl), MEM(&sh2->mach), R32(Rn), R32(Rm));
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return TRUE;
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}
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break;
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case 8: // SUB(Rm, Rn);
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@ -2407,15 +2524,18 @@ static int generate_group_4(drcuml_block *block, compiler_state *compiler, const
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break;
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case 0x10: // DT(Rn);
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UML_AND(block, IREG(0), MEM(&sh2->sr), IMM(~T)); // and r0, sr, ~T (clear the T bit)
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UML_SUB(block, R32(Rn), R32(Rn), IMM(1)); // sub Rn, Rn, 1
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UML_JMPc(block, IF_NZ, compiler->labelnum); // jz compiler->labelnum
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if (sh2->cpu_type > CPU_TYPE_SH1)
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{
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UML_AND(block, IREG(0), MEM(&sh2->sr), IMM(~T)); // and r0, sr, ~T (clear the T bit)
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UML_SUB(block, R32(Rn), R32(Rn), IMM(1)); // sub Rn, Rn, 1
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UML_JMPc(block, IF_NZ, compiler->labelnum); // jz compiler->labelnum
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UML_OR(block, IREG(0), IREG(0), IMM(T)); // or r0, r0, T
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UML_LABEL(block, compiler->labelnum++); // desc->pc:
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UML_OR(block, IREG(0), IREG(0), IMM(T)); // or r0, r0, T
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UML_LABEL(block, compiler->labelnum++); // desc->pc:
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|
||||
UML_MOV(block, MEM(&sh2->sr), IREG(0)); // mov sh2->sr, r0
|
||||
return TRUE;
|
||||
UML_MOV(block, MEM(&sh2->sr), IREG(0)); // mov sh2->sr, r0
|
||||
return TRUE;
|
||||
}
|
||||
break;
|
||||
|
||||
case 0x11: // CMPPZ(Rn);
|
||||
@ -2924,39 +3044,45 @@ static int generate_group_8(drcuml_block *block, compiler_state *compiler, const
|
||||
break;
|
||||
|
||||
case 13<< 8: // BTS(opcode & 0xff);
|
||||
UML_TEST(block, MEM(&sh2->sr), IMM(T)); // test sh2->sr, T
|
||||
UML_JMPc(block, IF_Z, compiler->labelnum); // jz compiler->labelnum
|
||||
if (sh2->cpu_type > CPU_TYPE_SH1)
|
||||
{
|
||||
UML_TEST(block, MEM(&sh2->sr), IMM(T)); // test sh2->sr, T
|
||||
UML_JMPc(block, IF_Z, compiler->labelnum); // jz compiler->labelnum
|
||||
|
||||
templabel = compiler->labelnum; // save our label
|
||||
compiler->labelnum++; // make sure the delay slot doesn't use it
|
||||
generate_delay_slot(block, compiler, desc);
|
||||
templabel = compiler->labelnum; // save our label
|
||||
compiler->labelnum++; // make sure the delay slot doesn't use it
|
||||
generate_delay_slot(block, compiler, desc);
|
||||
|
||||
disp = ((INT32)opcode << 24) >> 24;
|
||||
sh2->ea = (desc->pc + 2) + disp * 2 + 2; // sh2->ea = destination
|
||||
disp = ((INT32)opcode << 24) >> 24;
|
||||
sh2->ea = (desc->pc + 2) + disp * 2 + 2; // sh2->ea = destination
|
||||
|
||||
generate_update_cycles(block, compiler, IMM(sh2->ea), TRUE); // <subtract cycles>
|
||||
UML_HASHJMP(block, IMM(0), IMM(sh2->ea), sh2->nocode); // jmp sh2->ea
|
||||
generate_update_cycles(block, compiler, IMM(sh2->ea), TRUE); // <subtract cycles>
|
||||
UML_HASHJMP(block, IMM(0), IMM(sh2->ea), sh2->nocode); // jmp sh2->ea
|
||||
|
||||
UML_LABEL(block, templabel); // labelnum:
|
||||
return TRUE;
|
||||
UML_LABEL(block, templabel); // labelnum:
|
||||
return TRUE;
|
||||
}
|
||||
break;
|
||||
|
||||
case 15<< 8: // BFS(opcode & 0xff);
|
||||
UML_TEST(block, MEM(&sh2->sr), IMM(T)); // test sh2->sr, T
|
||||
UML_JMPc(block, IF_NZ, compiler->labelnum); // jnz compiler->labelnum
|
||||
if (sh2->cpu_type > CPU_TYPE_SH1)
|
||||
{
|
||||
UML_TEST(block, MEM(&sh2->sr), IMM(T)); // test sh2->sr, T
|
||||
UML_JMPc(block, IF_NZ, compiler->labelnum); // jnz compiler->labelnum
|
||||
|
||||
templabel = compiler->labelnum; // save our label
|
||||
compiler->labelnum++; // make sure the delay slot doesn't use it
|
||||
generate_delay_slot(block, compiler, desc); // delay slot only if the branch is taken
|
||||
templabel = compiler->labelnum; // save our label
|
||||
compiler->labelnum++; // make sure the delay slot doesn't use it
|
||||
generate_delay_slot(block, compiler, desc); // delay slot only if the branch is taken
|
||||
|
||||
disp = ((INT32)opcode << 24) >> 24;
|
||||
sh2->ea = (desc->pc + 2) + disp * 2 + 2; // sh2->ea = destination
|
||||
disp = ((INT32)opcode << 24) >> 24;
|
||||
sh2->ea = (desc->pc + 2) + disp * 2 + 2; // sh2->ea = destination
|
||||
|
||||
generate_update_cycles(block, compiler, IMM(sh2->ea), TRUE); // <subtract cycles>
|
||||
UML_HASHJMP(block, IMM(0), IMM(sh2->ea), sh2->nocode); // jmp sh2->ea
|
||||
generate_update_cycles(block, compiler, IMM(sh2->ea), TRUE); // <subtract cycles>
|
||||
UML_HASHJMP(block, IMM(0), IMM(sh2->ea), sh2->nocode); // jmp sh2->ea
|
||||
|
||||
UML_LABEL(block, templabel); // labelnum:
|
||||
return TRUE;
|
||||
UML_LABEL(block, templabel); // labelnum:
|
||||
return TRUE;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
@ -3094,8 +3220,39 @@ static int generate_group_12(drcuml_block *block, compiler_state *compiler, cons
|
||||
break;
|
||||
|
||||
case 12<<8: // TSTM(opcode & 0xff);
|
||||
UML_AND(block, MEM(&sh2->sr), MEM(&sh2->sr), IMM(~T)); // and sr, sr, ~T (clear the T bit)
|
||||
UML_ADD(block, IREG(0), R32(0), MEM(&sh2->gbr)); // add r0, R0, gbr
|
||||
UML_CALLH(block, sh2->read8); // read8
|
||||
|
||||
UML_CMP(block, IREG(0), IMM(0)); // cmp r0, #0
|
||||
UML_JMPc(block, IF_NZ, compiler->labelnum); // jnz labelnum
|
||||
|
||||
UML_OR(block, MEM(&sh2->sr), MEM(&sh2->sr), IMM(T)); // or sr, sr, T
|
||||
|
||||
UML_LABEL(block, compiler->labelnum++); // labelnum:
|
||||
return TRUE;
|
||||
break;
|
||||
|
||||
case 13<<8: // ANDM(opcode & 0xff);
|
||||
UML_ADD(block, IREG(0), R32(0), MEM(&sh2->gbr)); // add r0, R0, gbr
|
||||
UML_CALLH(block, sh2->read8); // read8
|
||||
|
||||
UML_AND(block, IREG(1), IREG(0), IMM(opcode&0xff)); // and r1, r0, #opcode&0xff
|
||||
UML_ADD(block, IREG(0), R32(0), MEM(&sh2->gbr)); // add r0, R0, gbr
|
||||
SETEA(0);
|
||||
UML_CALLH(block, sh2->write8); // write8
|
||||
return TRUE;
|
||||
break;
|
||||
|
||||
case 14<<8: // XORM(opcode & 0xff);
|
||||
UML_ADD(block, IREG(0), R32(0), MEM(&sh2->gbr)); // add r0, R0, gbr
|
||||
UML_CALLH(block, sh2->read8); // read8
|
||||
|
||||
UML_XOR(block, IREG(1), IREG(0), IMM(opcode&0xff)); // xor r1, r0, #opcode&0xff
|
||||
UML_ADD(block, IREG(0), R32(0), MEM(&sh2->gbr)); // add r0, R0, gbr
|
||||
SETEA(0);
|
||||
UML_CALLH(block, sh2->write8); // write8
|
||||
return TRUE;
|
||||
break;
|
||||
|
||||
case 15<<8: // ORM(opcode & 0xff);
|
||||
@ -3334,7 +3491,7 @@ void sh2_get_info(UINT32 state, cpuinfo *info)
|
||||
|
||||
/* --- the following bits of info are returned as NULL-terminated strings --- */
|
||||
case CPUINFO_STR_NAME: strcpy(info->s, "SH-2"); break;
|
||||
case CPUINFO_STR_CORE_FAMILY: strcpy(info->s, "Hitachi SH7600"); break;
|
||||
case CPUINFO_STR_CORE_FAMILY: strcpy(info->s, "Hitachi SuperH RISC"); break;
|
||||
case CPUINFO_STR_CORE_VERSION: strcpy(info->s, "2.0"); break;
|
||||
case CPUINFO_STR_CORE_FILE: strcpy(info->s, __FILE__); break;
|
||||
case CPUINFO_STR_CORE_CREDITS: strcpy(info->s, "Copyright Nicola Salmoria and the MAME team, all rights reserved."); break;
|
||||
@ -3378,4 +3535,23 @@ void sh2_get_info(UINT32 state, cpuinfo *info)
|
||||
}
|
||||
}
|
||||
|
||||
/*-------------------------------------------------
|
||||
sh1_get_info - return information about a
|
||||
given CPU instance
|
||||
-------------------------------------------------*/
|
||||
|
||||
void sh1_get_info(UINT32 state, cpuinfo *info)
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
/* --- the following bits of info are returned as pointers to data or functions --- */
|
||||
case CPUINFO_PTR_RESET: info->reset = sh1_reset; break;
|
||||
|
||||
/* --- the following bits of info are returned as NULL-terminated strings --- */
|
||||
case CPUINFO_STR_NAME: strcpy(info->s, "SH-1"); break;
|
||||
|
||||
default: sh2_get_info(state, info); break;
|
||||
}
|
||||
}
|
||||
|
||||
#endif // USE_SH2DRC
|
||||
|
||||
@ -165,6 +165,7 @@ enum _cpu_type
|
||||
CPU_RM7000LE,
|
||||
CPU_ARM,
|
||||
CPU_ARM7,
|
||||
CPU_SH1,
|
||||
CPU_SH2,
|
||||
CPU_SH4,
|
||||
CPU_DSP32C,
|
||||
|
||||
@ -137,6 +137,7 @@ void rm7000be_get_info(UINT32 state, cpuinfo *info);
|
||||
void rm7000le_get_info(UINT32 state, cpuinfo *info);
|
||||
void arm_get_info(UINT32 state, cpuinfo *info);
|
||||
void arm7_get_info(UINT32 state, cpuinfo *info);
|
||||
void sh1_get_info(UINT32 state, cpuinfo *info);
|
||||
void sh2_get_info(UINT32 state, cpuinfo *info);
|
||||
void sh4_get_info(UINT32 state, cpuinfo *info);
|
||||
void dsp32c_get_info(UINT32 state, cpuinfo *info);
|
||||
@ -612,6 +613,9 @@ static const struct
|
||||
#if (HAS_ARM7)
|
||||
{ CPU_ARM7, arm7_get_info },
|
||||
#endif
|
||||
#if (HAS_SH1)
|
||||
{ CPU_SH1, sh1_get_info },
|
||||
#endif
|
||||
#if (HAS_SH2)
|
||||
{ CPU_SH2, sh2_get_info },
|
||||
#endif
|
||||
|
||||
@ -163,7 +163,7 @@ static MACHINE_DRIVER_START( coolridr )
|
||||
MDRV_CPU_ADD("sound", M68000, 12000000) // ?? mhz
|
||||
MDRV_CPU_PROGRAM_MAP(system_h1_sound_map,0)
|
||||
|
||||
MDRV_CPU_ADD("sub", SH2, 8000000) // SH7032 HD6417032F20!! ?? mhz
|
||||
MDRV_CPU_ADD("sub", SH1, 8000000) // SH7032 HD6417032F20!! ?? mhz
|
||||
MDRV_CPU_PROGRAM_MAP(coolridr_submap,0)
|
||||
MDRV_CPU_VBLANK_INT_HACK(system_h1_sub, 2)
|
||||
|
||||
|
||||
@ -145,6 +145,7 @@ CPUS += R4700
|
||||
CPUS += R5000
|
||||
CPUS += QED5271
|
||||
CPUS += RM7000
|
||||
CPUS += SH1
|
||||
CPUS += SH2
|
||||
CPUS += SH4
|
||||
CPUS += DSP32C
|
||||
|
||||
Loading…
Reference in New Issue
Block a user