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h8: improve cycle timing for pre-h8s arch

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This commit is contained in:
hap 2024-02-09 15:10:35 +01:00
parent e58e062d0e
commit a63db1b147
5 changed files with 69 additions and 43 deletions
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41
src/devices/cpu/h8/h8.cpp
View File

@ -232,26 +232,6 @@ void h8_device::request_state(int state)
m_requested_state = state;
}
uint32_t h8_device::execute_min_cycles() const noexcept
{
return 1;
}
uint32_t h8_device::execute_max_cycles() const noexcept
{
return 1;
}
uint32_t h8_device::execute_input_lines() const noexcept
{
return 0;
}
bool h8_device::execute_input_edge_triggered(int inputnum) const noexcept
{
return inputnum == INPUT_LINE_NMI;
}
void h8_device::recompute_bcount(uint64_t event_time)
{
if(!event_time || event_time >= total_cycles() + m_icount) {
@ -409,36 +389,33 @@ void h8_device::state_string_export(const device_state_entry &entry, std::string
}
}
// FIXME: one-state bus cycles are only provided for on-chip ROM & RAM in H8S/2000 and H8S/2600.
// All other accesses take *at least* two states each, and additional wait states are often programmed for external memory!
uint16_t h8_device::read16i(uint32_t adr)
{
m_icount--;
m_icount -= 2;
return m_cache.read_word(adr & ~1);
}
uint8_t h8_device::read8(uint32_t adr)
{
m_icount--;
m_icount -= 2;
return m_program.read_byte(adr);
}
void h8_device::write8(uint32_t adr, uint8_t data)
{
m_icount--;
m_icount -= 2;
m_program.write_byte(adr, data);
}
uint16_t h8_device::read16(uint32_t adr)
{
m_icount--;
m_icount -= 2;
return m_program.read_word(adr & ~1);
}
void h8_device::write16(uint32_t adr, uint16_t data)
{
m_icount--;
m_icount -= 2;
m_program.write_word(adr & ~1, data);
}
@ -488,11 +465,9 @@ void h8_device::set_irq(int irq_vector, int irq_level, bool irq_nmi)
void h8_device::internal(int cycles)
{
m_icount -= cycles;
// All internal operations take an even number of states (at least 2 each) on H8/300L and H8/300H
if(!m_has_exr)
m_icount--;
// all internal operations take an even number of states (at least 2 each)
// this only applies to: H8/300, H8/300L, H8/300H (not H8S)
m_icount -= cycles + 1;
}
void h8_device::illegal()

20
src/devices/cpu/h8/h8.h
View File

@ -111,10 +111,10 @@ protected:
// device_execute_interface overrides
virtual bool cpu_is_interruptible() const override { return true; }
virtual uint32_t execute_min_cycles() const noexcept override;
virtual uint32_t execute_max_cycles() const noexcept override;
virtual uint32_t execute_input_lines() const noexcept override;
virtual bool execute_input_edge_triggered(int inputnum) const noexcept override;
virtual uint32_t execute_min_cycles() const noexcept override { return 2; }
virtual uint32_t execute_max_cycles() const noexcept override { return 12; }
virtual uint32_t execute_input_lines() const noexcept override { return 0; }
virtual bool execute_input_edge_triggered(int inputnum) const noexcept override { return inputnum == INPUT_LINE_NMI; }
virtual void execute_run() override;
// device_memory_interface overrides
@ -177,12 +177,12 @@ protected:
virtual int trapa_setup();
virtual void irq_setup() = 0;
uint16_t read16i(uint32_t adr);
uint8_t read8(uint32_t adr);
void write8(uint32_t adr, uint8_t data);
uint16_t read16(uint32_t adr);
void write16(uint32_t adr, uint16_t data);
void internal(int cycles);
virtual uint16_t read16i(uint32_t adr);
virtual uint8_t read8(uint32_t adr);
virtual void write8(uint32_t adr, uint8_t data);
virtual uint16_t read16(uint32_t adr);
virtual void write16(uint32_t adr, uint16_t data);
virtual void internal(int cycles);
void prefetch_switch(uint32_t pc, uint16_t ir) { m_NPC = pc & 0xffffff; m_PC = pc+2; m_PIR = ir; }
void prefetch_done();
void prefetch_done_noirq();

3
src/devices/cpu/h8/h8h.h
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@ -22,6 +22,9 @@ class h8h_device : public h8_device {
protected:
h8h_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, address_map_constructor map_delegate);
virtual uint32_t execute_min_cycles() const noexcept override { return 2; }
virtual uint32_t execute_max_cycles() const noexcept override { return 20; }
virtual std::unique_ptr<util::disasm_interface> create_disassembler() override;
virtual void do_exec_full() override;

38
src/devices/cpu/h8/h8s2000.cpp
View File

@ -15,4 +15,42 @@ std::unique_ptr<util::disasm_interface> h8s2000_device::create_disassembler()
return std::make_unique<h8s2000_disassembler>();
}
// FIXME: one-state bus cycles are only provided for on-chip ROM & RAM in H8S/2000 and H8S/2600.
// All other accesses take *at least* two states each, and additional wait states are often programmed for external memory!
uint16_t h8s2000_device::read16i(uint32_t adr)
{
m_icount--;
return m_cache.read_word(adr & ~1);
}
uint8_t h8s2000_device::read8(uint32_t adr)
{
m_icount--;
return m_program.read_byte(adr);
}
void h8s2000_device::write8(uint32_t adr, uint8_t data)
{
m_icount--;
m_program.write_byte(adr, data);
}
uint16_t h8s2000_device::read16(uint32_t adr)
{
m_icount--;
return m_program.read_word(adr & ~1);
}
void h8s2000_device::write16(uint32_t adr, uint16_t data)
{
m_icount--;
m_program.write_word(adr & ~1, data);
}
void h8s2000_device::internal(int cycles)
{
m_icount -= cycles;
}
#include "cpu/h8/h8s2000.hxx"

10
src/devices/cpu/h8/h8s2000.h
View File

@ -24,8 +24,18 @@ class h8s2000_device : public h8h_device {
protected:
h8s2000_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, address_map_constructor map_delegate);
virtual uint32_t execute_min_cycles() const noexcept override { return 1; }
virtual uint32_t execute_max_cycles() const noexcept override { return 19; }
virtual std::unique_ptr<util::disasm_interface> create_disassembler() override;
virtual uint16_t read16i(uint32_t adr) override;
virtual uint8_t read8(uint32_t adr) override;
virtual void write8(uint32_t adr, uint8_t data) override;
virtual uint16_t read16(uint32_t adr) override;
virtual void write16(uint32_t adr, uint16_t data) override;
virtual void internal(int cycles) override;
virtual void do_exec_full() override;
virtual void do_exec_partial() override;