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https://github.com/holub/mame
synced 2025-07-02 00:29:37 +03:00
hooked v53 irq ack callback so that it can get the correct vector from the controller, make a note of which ones get unmasked (nw)
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@ -215,6 +215,8 @@ void v53_base_device::device_start()
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m_out_dack_1_cb.resolve_safe();
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m_out_dack_2_cb.resolve_safe();
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m_out_dack_3_cb.resolve_safe();
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static_set_irq_acknowledge_callback(*this, device_irq_acknowledge_delegate(FUNC(pic8259_device::inta_cb), (pic8259_device*)m_v53icu));
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}
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void v53_base_device::install_peripheral_io()
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@ -484,6 +486,7 @@ static MACHINE_CONFIG_FRAGMENT( v53 )
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MCFG_PIT8253_OUT0_HANDLER(WRITELINE( v53_base_device, tcu_out0_trampoline_cb ))
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MCFG_PIT8253_OUT1_HANDLER(WRITELINE( v53_base_device, tcu_out1_trampoline_cb ))
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MCFG_PIT8253_OUT2_HANDLER(WRITELINE( v53_base_device, tcu_out2_trampoline_cb ))
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MCFG_DEVICE_ADD("upd71071dma", V53_DMAU, 4000000)
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MCFG_AM9517A_OUT_HREQ_CB(WRITELINE(v53_base_device, hreq_trampoline_cb))
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@ -506,6 +509,8 @@ static MACHINE_CONFIG_FRAGMENT( v53 )
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MCFG_PIC8259_ADD( "upd71059pic", WRITELINE(v53_base_device, internal_irq_w), VCC, READ8(v53_base_device,get_pic_ack))
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MCFG_DEVICE_ADD("v53scu", V53_SCU, 0)
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MCFG_I8251_TXD_HANDLER(WRITELINE(v53_base_device, scu_txd_trampoline_cb))
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MCFG_I8251_DTR_HANDLER(WRITELINE(v53_base_device, scu_dtr_trampoline_cb))
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@ -14,12 +14,15 @@ buriki (#)SNK R&D Center (R) HYPER NEOGEO64 Sound Driver Ver 1.15. (#)Copyrig
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The earlier revisions appear to have 2 banks of code (there are vectors at the end of the 0x1e0000 block and the 0x1f0000 block)
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Those first two revisions also spam the entire range of I/O ports with values several times on startup causing some unexpected
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writes to the V53 internal registers. The important ones are reinitialized after this however, I'm guessing this is harmless
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on real hardware, as the code flow seems to be correct.
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If the banking setup is wrong then those first two revisions also spam the entire range of I/O ports with values several times
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on startup causing some unexpected writes to the V53 internal registers.
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data structures look very similar between all of them
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IRQ mask register on the internal interrupt controller is set to 0xd8
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so levels 0,1,2,5 are unmasked
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*/
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@ -298,6 +301,7 @@ WRITE_LINE_MEMBER(hng64_state::tcu_tm1_cb)
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{
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// these are very active, maybe they feed back into the v53 via one of the IRQ pins? TM2 toggles more rapidly than TM1
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// printf("tcu_tm1_cb %02x\n", state);
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m_audiocpu->set_input_line(0, state? ASSERT_LINE:CLEAR_LINE);
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}
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WRITE_LINE_MEMBER(hng64_state::tcu_tm2_cb)
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