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Merge branch 'master' into patch-144

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cam900 2020-05-16 09:12:47 +09:00 committed by GitHub
commit a673be1ebb
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697 changed files with 8264 additions and 5839 deletions
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318
hash/amigaocs_flop.xml
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File diff suppressed because it is too large Load Diff

92
hash/compis.xml
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@ -330,4 +330,96 @@ Systemskiva för hårdskiveenhet [version 7242]
</dataarea>
</part>
</software>
<software name="matett">
<description>MätEtt (enanvändare)</description>
<year>1987</year>
<publisher>Esselte Studium</publisher>
<info name="serial" value="24-33748" />
<info name="release" value="19870831" />
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="2209452">
<rom name="matett.mfm" size="2209452" crc="f3c96357" sha1="4f8ca5fef4f22ad73a1101ab971118730fff102f"/>
</dataarea>
</part>
</software>
<!-- Requires a hardware key which isn't dumped -->
<software name="millikan">
<description>Millikans försök (enanvändare)</description>
<year>1987</year>
<publisher>Esselte Studium</publisher>
<info name="serial" value="24-33764" />
<info name="release" value="19870729" />
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="2209538">
<rom name="Millikans forsok.mfm" size="2209538" crc="40e161ad" sha1="704f1c23f02206c5e28166cf149bb39f7c24bb45"/>
</dataarea>
</part>
</software>
<software name="ritett">
<description>RitEtt (enanvändare)</description>
<year>1986</year>
<publisher>Esselte Studium</publisher>
<info name="serial" value="24-34250" />
<info name="release" value="19860404" />
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="2217597">
<rom name="RitEtt.mfm" size="2217597" crc="e7cf88d0" sha1="225396bc29cb2ba158949a9286fcee9201617265"/>
</dataarea>
</part>
</software>
<software name="datmatte">
<description>Datorn i matematik (nät/skollicens)</description>
<year>1986</year>
<publisher>Esselte Studium</publisher>
<info name="serial" value="24-34175" />
<info name="release" value="19861003" />
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="2217631">
<rom name="Datorn i matematik.mfm" size="2217631" crc="0a19fc5b" sha1="5d764656e8428c3767bf3cc1a2e3ce6c0451df88"/>
</dataarea>
</part>
</software>
<software name="matenergi">
<description>Mät energi (enanvändare)</description>
<year>1986</year>
<publisher>Esselte Studium</publisher>
<info name="serial" value="24-34051" />
<info name="release" value="19860701" />
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="2209441">
<rom name="Mat energi.mfm" size="2209441" crc="5e6b2fcb" sha1="91d79cc4f190a7069a54abd818922540e915837c"/>
</dataarea>
</part>
</software>
<software name="latinet">
<description>Internationella ord från latinet (nät/skollicens)</description>
<year>1988</year>
<publisher>Almqvist &amp; Wiksell</publisher>
<info name="serial" value="21-98004" />
<info name="release" value="19880101" />
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="2209554">
<rom name="Internationella ord fran latinet.mfm" size="2209554" crc="55de0713" sha1="0c117ffdd0c1e83ee0f0ad28cf792986b6655ba7"/>
</dataarea>
</part>
</software>
<software name="grekiskan">
<description>Internationella ord från grekiskan (nät/skollicens)</description>
<year>1988</year>
<publisher>Almqvist &amp; Wiksell</publisher>
<info name="serial" value="21-98006" />
<info name="release" value="19880101" />
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="2217724">
<rom name="Internationella ord fran grekiskan.mfm" size="2217724" crc="bb4e2e86" sha1="be6651cc0728b07d636b069324dd1d77ed10f470"/>
</dataarea>
</part>
</software>
</softwarelist>

11
hash/jaguar.xml
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@ -168,7 +168,7 @@ Unreleased (possibly no prototypes exist):
</part>
</software>
<!-- black screen -->
<!-- boot OK, gameplay graphics have clipping/alignment issues, eventually throws an exception, no sound -->
<software name="atarikrt" supported="no">
<description>Atari Karts</description>
<year>1995</year>
@ -181,8 +181,8 @@ Unreleased (possibly no prototypes exist):
</part>
</software>
<!-- black screen -->
<software name="mutntpng" supported="no">
<!-- boot OK, title screen foreground layer not drawn properly, no sound -->
<software name="mutntpng" supported="partial">
<description>Attack of the Mutant Penguins</description>
<year>1996</year>
<publisher>Atari</publisher>
@ -592,7 +592,8 @@ Unreleased (possibly no prototypes exist):
</part>
</software>
<!-- hangs at the NBA Jam TE logo -->
<!-- exception on non-debug, on debug gameplay sports no sprite GFXs -->
<!-- minor glitch on team box when selecting one (blitter not filling properly) -->
<software name="nbajamte" supported="no">
<description>NBA Jam T.E. - Tournament Edition</description>
<year>1996</year>
@ -966,7 +967,7 @@ Unreleased (possibly no prototypes exist):
</software>
<!-- boot OK, no BGMs, has minor GFX pitch issue when action summary message pops up after a play -->
<software name="troyaik" supported="no">
<software name="troyaik" supported="partial">
<description>Troy Aikman NFL Football</description>
<year>1995</year>
<publisher>Williams Entertainment</publisher>

258
hash/sgi_mips.xml
View File

@ -7,6 +7,18 @@ license:CC0
<!-- Apps and utilities -->
<software name="adv_vis_4_2">
<description>Alias|Wavefront Advanced Visualizer 4.2</description>
<year>199?</year>
<publisher>Alias|Wavefront</publisher>
<part name="cdrom" interface="cdrom">
<!-- Origin: unknown -->
<diskarea name="cdrom">
<disk name="alias_wavefront_advanced_visualizer_4_2" sha1="1f048130f8df40cceb15dddc276f973ab96819fc" />
</diskarea>
</part>
</software>
<software name="barco_7_2">
<description>Barco Creator 7.2</description>
<year>1999</year> <!-- 08/04/99 -->
@ -169,6 +181,18 @@ license:CC0
</part>
</software>
<software name="effect_6_1_3">
<description>Discreet Effect 6.1.3</description>
<year>2000</year> <!-- 03/00 -->
<publisher>Discreet</publisher>
<part name="cdrom" interface="cdrom">
<!-- Origin: unknown -->
<diskarea name="cdrom">
<disk name="discreet_effect_6_1_3_irix" sha1="869b62d2f9042034601ce4b08ff7113af564941c" />
</diskarea>
</part>
</software>
<software name="enldsm_1_1">
<description>ENlightenDSM 1.1 for UNIX and NT</description>
<year>1998</year> <!-- 7/98 -->
@ -222,6 +246,31 @@ license:CC0
</part>
</software>
<software name="flame_4_0_2">
<description>Discreet Flame 4.0.2</description>
<year>1996</year>
<publisher>Discreet Logic</publisher>
<part name="cdrom" interface="cdrom">
<feature name="part_number" value="TODO"/>
<!-- Origin: unknown -->
<diskarea name="cdrom">
<disk name="flame402" sha1="ce03c782b5947c2f4795f8dde63687da1567e15f" />
</diskarea>
</part>
</software>
<software name="flame_7_6">
<description>Discreet Flame 7.6</description>
<year>2002</year>
<publisher>Discreet Logic</publisher>
<part name="cdrom" interface="cdrom">
<!-- Origin: unixfiles.org -->
<diskarea name="cdrom">
<disk name="flame7_6" sha1="c27275a052bf56c720f31d20c21ef66e0a016426" />
</diskarea>
</part>
</software>
<software name="freeware_2_0">
<description>Freeware 2.0 - Unsupported Software compatible with IRIX 6.2 and later</description>
<year>1996</year> <!-- 04/96 -->
@ -392,6 +441,18 @@ license:CC0
</part>
</software>
<software name="maya_comp_5_5">
<description>Alias|Wavefront Maya Composer 5.5</description>
<year>1999</year>
<publisher>Alias|Wavefront</publisher>
<part name="cdrom" interface="cdrom">
<!-- Origin: unknown -->
<diskarea name="cdrom">
<disk name="alias_wavefront_maya_composer5_5" sha1="2443df75803449d3d5603beebf4536ab79a1a401" />
</diskarea>
</part>
</software>
<software name="mineset_2_0_1">
<description>MineSet 2.0.1 for IRIX 6.2 and later</description>
<year>1998</year> <!-- 01/98 -->
@ -592,7 +653,7 @@ license:CC0
<software name="o2oobe_2_4">
<description>O2 Out of Box Experience 2.4 for IRIX 6.5 and later</description>
<year>2000</year> <!-- 02/00 -->
<publisher>Silicon Graphics</publisher>
<publisher>SGI</publisher>
<part name="cdrom" interface="cdrom">
<feature name="part_number" value="812-0782-003"/>
<!-- Origin: jrra.zone -->
@ -757,6 +818,48 @@ license:CC0
</part>
</software>
<software name="power_anim_7_51">
<description>Alias|Wavefront PowerAnimator 7.51</description>
<year>1996</year> <!-- 10/96 -->
<publisher>Alias|Wavefront</publisher>
<part name="cdrom" interface="cdrom">
<!-- Origin: unknown -->
<diskarea name="cdrom">
<disk name="alias_wavefront_poweranimator_7_51_oct_1996" sha1="1065292902536290278d1d9571501def43806256" />
</diskarea>
</part>
</software>
<software name="power_anim_8_2">
<description>Alias|Wavefront PowerAnimator 8.2</description>
<year>1997</year> <!-- 07/97 -->
<publisher>Alias|Wavefront</publisher>
<part name="cdrom1" interface="cdrom">
<!-- Origin: unknown -->
<diskarea name="cdrom">
<disk name="v08_2_irix_cd_1_of_2" sha1="77fd71891480f826ae455543d0a9f9583c9de00b" />
</diskarea>
</part>
<part name="cdrom2" interface="cdrom">
<!-- Origin: unknown -->
<diskarea name="cdrom">
<disk name="v08_2_irix_cd_2_of_2" sha1="2927c3aa5d7bd74709fa465401b11dab2ff7f723" />
</diskarea>
</part>
</software>
<software name="prisms_6_4">
<description>PRISMS 6.4</description>
<year>1997</year>
<publisher>Side Effects Software</publisher>
<part name="cdrom" interface="cdrom">
<!-- Origin: unknown -->
<diskarea name="cdrom">
<disk name="prisms_6_4" sha1="dc777c86168394b44f71dcbaaf2a8c15932a971f" />
</diskarea>
</part>
</software>
<software name="samba_2_0_0">
<description>Samba 2.0.0 for IRIX for IRIX 6.5 and later</description>
<year>1998</year> <!-- 12/98 -->
@ -773,7 +876,7 @@ license:CC0
<software name="sgi_demos_6_5_12">
<description>Silicon Graphics General and Platform Demos 6.5.12</description>
<year>2001</year> <!-- 05/01 -->
<publisher>Silicon Graphics</publisher>
<publisher>SGI</publisher>
<part name="cdrom1" interface="cdrom">
<feature name="part_number" value="812-1066-002"/>
<feature name="part_id" value="Silicon Graphics General and Platform Demos 6.5.12 (1 of 2)"/>
@ -848,7 +951,7 @@ license:CC0
<software name="multilink_doc">
<description>Silicon Graphics MultiLink Adapter Documentation</description>
<year>2000</year> <!-- 05/00 -->
<publisher>Silicon Graphics</publisher>
<publisher>SGI</publisher>
<part name="cdrom" interface="cdrom">
<feature name="part_number" value="812-0811-001"/>
<!-- Origin: BitSavers -->
@ -1398,7 +1501,7 @@ license:CC0
<feature name="part_number" value="812-8101-011"/>
<!-- Origin: private dump -->
<diskarea name="cdrom">
<disk name="hot_mix_volume_11" sha1="ee725db3a52ff482e03b7806889763619f584859" />
<disk name="hot_mix_volume_11" sha1="fa371c5dd27f8ba4235e4200299d08b210491788" />
</diskarea>
</part>
</software>
@ -1411,7 +1514,7 @@ license:CC0
<feature name="part_number" value="812-8101-012"/>
<!-- Origin: private dump -->
<diskarea name="cdrom">
<disk name="hot_mix_volume_12" sha1="ee725db3a52ff482e03b7806889763619f584859" />
<disk name="hot_mix_volume_12" sha1="34f76d048973a2b4a7ae8471420f87ab2ac4d762" />
</diskarea>
</part>
</software>
@ -1681,19 +1784,6 @@ license:CC0
</part>
</software>
<software name="apps_6_5_aug_01">
<description>IRIX 6.5 Applications August 2001</description>
<year>2001</year> <!-- 08/01 -->
<publisher>Silicon Graphics</publisher>
<part name="cdrom" interface="cdrom">
<feature name="part_number" value="812-0877-012"/>
<!-- Origin: private dump -->
<diskarea name="cdrom">
<disk name="irix_6_5_13_applications_august_2001" sha1="a73ae9f7d0c5e42b948580463c8bc2c741c9629a" />
</diskarea>
</part>
</software>
<!-- IRIX patches (loose CDs) -->
<software name="patch_sg0000466">
@ -2074,6 +2164,7 @@ license:CC0
<year>1995</year> <!-- 02/95 -->
<publisher>Silicon Graphics</publisher>
<part name="cdrom" interface="cdrom">
<!-- Also distributed as IRIX 5.3 for Indy R4000, R4400, R4600 100-200 MHz with P/N 812-0336-002 and identical contents -->
<feature name="part_number" value="812-0336-001"/>
<!-- Origin: BitSavers -->
<diskarea name="cdrom">
@ -2108,19 +2199,6 @@ license:CC0
</part>
</software>
<software name="irix_5_3_d" cloneof="irix_5_3">
<description>IRIX 5.3 for Indy R4000, R4400, R4600 (100-200 MHz)</description>
<year>1995</year> <!-- 08/95 -->
<publisher>Silicon Graphics</publisher>
<part name="cdrom" interface="cdrom">
<feature name="part_number" value="812-0336-002"/>
<!-- Origin: jrra.zone -->
<diskarea name="cdrom">
<disk name="irix_5_3_for_indy" sha1="dcc05e3637e4ab20c4fceb43bded2f1f2bd64518" />
</diskarea>
</part>
</software>
<software name="irix_6_0_1">
<description>IRIX 6.0.1</description>
<year>1994</year> <!-- 12/94 -->
@ -2605,7 +2683,7 @@ license:CC0
<software name="irix_6_5_7">
<description>IRIX 6.5.7</description>
<year>2000</year> <!-- 02/00 -->
<publisher>Silicon Graphics</publisher>
<publisher>SGI</publisher>
<part name="cdrom1" interface="cdrom">
<feature name="part_number" value="812-0818-007"/>
<feature name="part_id" value="IRIX 6.5.7 Installation Tools and Overlays (1 of 2) February 2000"/>
@ -2659,7 +2737,7 @@ license:CC0
<software name="irix_6_5_8">
<description>IRIX 6.5.8</description>
<year>2000</year> <!-- 05/00 -->
<publisher>Silicon Graphics</publisher>
<publisher>SGI</publisher>
<part name="cdrom1" interface="cdrom">
<feature name="part_number" value="812-0818-008"/>
<feature name="part_id" value="IRIX 6.5.8 Installation Tools and Overlays (1 of 3) May 2000"/>
@ -2713,7 +2791,7 @@ license:CC0
<software name="irix_6_5_9">
<description>IRIX 6.5.9</description>
<year>2000</year> <!-- 08/00 -->
<publisher>Silicon Graphics</publisher>
<publisher>SGI</publisher>
<part name="cdrom1" interface="cdrom">
<feature name="part_number" value="812-0818-009"/>
<feature name="part_id" value="IRIX 6.5.9 Installation Tools and Overlays (1 of 3) August 2000"/>
@ -2775,7 +2853,7 @@ license:CC0
<software name="irix_6_5_10">
<description>IRIX 6.5.10</description>
<year>2000</year> <!-- 11/00 -->
<publisher>Silicon Graphics</publisher>
<publisher>SGI</publisher>
<part name="cdrom1" interface="cdrom">
<feature name="part_number" value="812-0818-010"/>
<feature name="part_id" value="IRIX 6.5.10 Installation Tools and Overlays (1 of 3)"/>
@ -2805,7 +2883,7 @@ license:CC0
<software name="irix_6_5_11">
<description>IRIX 6.5.11</description>
<year>2001</year> <!-- 02/01 -->
<publisher>Silicon Graphics</publisher>
<publisher>SGI</publisher>
<part name="cdrom1" interface="cdrom">
<feature name="part_number" value="812-0818-011"/>
<feature name="part_id" value="IRIX 6.5.11 Installation Tools and Overlays (1 of 3)"/>
@ -2835,7 +2913,7 @@ license:CC0
<software name="irix_6_5_12">
<description>IRIX 6.5.12</description>
<year>2001</year> <!-- 05/01 -->
<publisher>Silicon Graphics</publisher>
<publisher>SGI</publisher>
<part name="cdrom1" interface="cdrom">
<feature name="part_number" value="812-0818-012"/>
<feature name="part_id" value="IRIX 6.5.12 Installation Tools and Overlays (1 of 3)"/>
@ -2873,7 +2951,7 @@ license:CC0
<software name="irix_6_5_13">
<description>IRIX 6.5.13</description>
<year>2001</year> <!-- 08/01 -->
<publisher>Silicon Graphics</publisher>
<publisher>SGI</publisher>
<part name="cdrom1" interface="cdrom">
<feature name="part_number" value="812-0818-013"/>
<feature name="part_id" value="IRIX 6.5.13 Installation Tools and Overlays (1 of 3) August 2001"/>
@ -2911,7 +2989,7 @@ license:CC0
<software name="irix_6_5_14">
<description>IRIX 6.5.14</description>
<year>2001</year> <!-- 11/01 -->
<publisher>Silicon Graphics</publisher>
<publisher>SGI</publisher>
<part name="cdrom1" interface="cdrom">
<feature name="part_number" value="812-0818-014"/>
<feature name="part_id" value="IRIX 6.5.14 Installation Tools and Overlays (1 of 3)"/>
@ -2941,7 +3019,7 @@ license:CC0
<software name="irix_6_5_15">
<description>IRIX 6.5.15</description>
<year>2002</year> <!-- 02/02 -->
<publisher>Silicon Graphics</publisher>
<publisher>SGI</publisher>
<part name="cdrom1" interface="cdrom">
<feature name="part_number" value="812-0818-015"/>
<feature name="part_id" value="IRIX 6.5.15 Installation Tools and Overlays (1 of 4)"/>
@ -2987,7 +3065,7 @@ license:CC0
<software name="irix_6_5_16">
<description>IRIX 6.5.16</description>
<year>2002</year> <!-- 05/2002 -->
<publisher>Silicon Graphics</publisher>
<publisher>SGI</publisher>
<part name="cdrom1" interface="cdrom">
<feature name="part_number" value="812-0818-016"/>
<feature name="part_id" value="IRIX 6.5.16 Installation Tools and Overlays (1 of 4)"/>
@ -3025,7 +3103,7 @@ license:CC0
<software name="irix_6_5_17">
<description>IRIX 6.5.17</description>
<year>2002</year> <!-- 08/02 -->
<publisher>Silicon Graphics</publisher>
<publisher>SGI</publisher>
<part name="cdrom1" interface="cdrom">
<feature name="part_number" value="812-0818-017"/>
<feature name="part_id" value="IRIX 6.5.17 Installation Tools and Overlays (1 of 4)"/>
@ -3063,7 +3141,7 @@ license:CC0
<software name="irix_6_5_18">
<description>IRIX 6.5.18</description>
<year>2002</year> <!-- 11/02 -->
<publisher>Silicon Graphics</publisher>
<publisher>SGI</publisher>
<part name="cdrom1" interface="cdrom">
<feature name="part_number" value="812-0818-018"/>
<feature name="part_id" value="IRIX 6.5.18 Installation Tools and Overlays (1 of 4)"/>
@ -3114,10 +3192,88 @@ license:CC0
</part>
</software>
<software name="irix_6_5_19">
<description>IRIX 6.5.19</description>
<year>2003</year> <!-- 02/03 -->
<publisher>SGI</publisher>
<part name="cdrom1" interface="cdrom">
<feature name="part_number" value="812-0818-019"/>
<feature name="part_id" value="IRIX 6.5.19 Installation Tools and Overlays (1 of 4)"/>
<!-- Origin: jrra.zone -->
<diskarea name="cdrom">
<disk name="irix_6_5_19_installation_tools_and_overlays_1_of_4" sha1="bf125d76296927cc6f24fd2ea3b806de9a992ad2" />
</diskarea>
</part>
<part name="cdrom2" interface="cdrom">
<feature name="part_number" value="812-0819-019"/>
<feature name="part_id" value="IRIX 6.5.19 Overlays (2 of 4)"/>
<!-- Origin: jrra.zone -->
<diskarea name="cdrom">
<disk name="irix_6_5_19_overlays_2_of_4" sha1="42b99d8667f199f74600585f5ba334cd7da98034" />
</diskarea>
</part>
<part name="cdrom3" interface="cdrom">
<feature name="part_number" value="812-0817-019"/>
<feature name="part_id" value="IRIX 6.5.19 Overlays (3 of 4)"/>
<!-- Origin: jrra.zone -->
<diskarea name="cdrom">
<disk name="irix_6_5_19_overlays_3_of_4" sha1="8ee7979cfac23a76f3414ebbee22357efbc31c75" />
</diskarea>
</part>
<part name="cdrom4" interface="cdrom">
<feature name="part_number" value="812-1123-019"/>
<feature name="part_id" value="IRIX 6.5.19 Overlays (4 of 4)"/>
<!-- Origin: jrra.zone -->
<diskarea name="cdrom">
<disk name="irix_6_5_19_overlays_4_of_4" sha1="4ed9a9590c6916c19bbce488b2deb8fb3c4bf9b9" />
</diskarea>
</part>
<part name="cdrom5" interface="cdrom">
<feature name="part_number" value="812-0779-019"/>
<feature name="part_id" value="IRIX 6.5.19 Base Documentation"/>
<!-- Origin: jrra.zone -->
<diskarea name="cdrom">
<disk name="irix_6_5_19_base_documentation" sha1="32337db1b3894207cb826f37d8d6a79b0f7aee5a" />
</diskarea>
</part>
<part name="cdrom6" interface="cdrom">
<feature name="part_number" value="812-0773-019"/>
<feature name="part_id" value="Freeware (part 1 of 4)"/>
<!-- Origin: jrra.zone -->
<diskarea name="cdrom">
<disk name="freeware_part_1_of_4" sha1="9a875278a0a3bae9883cd69306fd75abf1ca412c" />
</diskarea>
</part>
<part name="cdrom7" interface="cdrom">
<feature name="part_number" value="812-0964-019"/>
<feature name="part_id" value="Freeware (part 2 of 4)"/>
<!-- Origin: jrra.zone -->
<diskarea name="cdrom">
<disk name="freeware_part_2_of_4" sha1="60933e32cd3b2f2da8aa49c5070a05082c8e9d2f" />
</diskarea>
</part>
<part name="cdrom8" interface="cdrom">
<feature name="part_number" value="812-1085-019"/>
<feature name="part_id" value="Freeware (part 3 of 4)"/>
<!-- Origin: jrra.zone -->
<diskarea name="cdrom">
<disk name="freeware_part_3_of_4" sha1="fcb1d992b26d7e19952dfaffac076c319af1f508" />
</diskarea>
</part>
<part name="cdrom9" interface="cdrom">
<feature name="part_number" value="812-1137-019"/>
<feature name="part_id" value="Freeware (part 4 of 4)"/>
<!-- Origin: jrra.zone -->
<diskarea name="cdrom">
<disk name="freeware_part_4_of_4" sha1="c270b7181a080f44f4384d2d28c042a476fac8f4" />
</diskarea>
</part>
</software>
<software name="irix_6_5_21">
<description>IRIX 6.5.21</description>
<year>2003</year> <!-- 08/03 -->
<publisher>Silicon Graphics</publisher>
<publisher>SGI</publisher>
<part name="cdrom1" interface="cdrom">
<feature name="part_number" value="812-0818-021"/>
<feature name="part_id" value="IRIX 6.5.21 Installation Tools and Overlays (1 of 4)"/>
@ -3155,7 +3311,7 @@ license:CC0
<software name="irix_6_5_22">
<description>IRIX 6.5.22</description>
<year>2003</year> <!-- 11/03 -->
<publisher>Silicon Graphics</publisher>
<publisher>SGI</publisher>
<part name="cdrom1" interface="cdrom">
<feature name="part_number" value="812-0818-022"/>
<feature name="part_id" value="IRIX 6.5.22 Installation Tools and Overlays 1 of 3"/>
@ -3193,7 +3349,7 @@ license:CC0
<software name="irix_6_5_23">
<description>IRIX 6.5.23</description>
<year>2004</year> <!-- 02/04 -->
<publisher>Silicon Graphics</publisher>
<publisher>SGI</publisher>
<part name="cdrom1" interface="cdrom">
<feature name="part_number" value="812-0818-023"/>
<feature name="part_id" value="IRIX 6.5.23 Installation Tools and Overlays (1 of 3)"/>
@ -3223,7 +3379,7 @@ license:CC0
<software name="irix_6_5_26">
<description>IRIX 6.5.26</description>
<year>2004</year> <!-- 11/04 -->
<publisher>Silicon Graphics</publisher>
<publisher>SGI</publisher>
<part name="cdrom1" interface="cdrom">
<feature name="part_number" value="812-0818-026"/>
<feature name="part_id" value="IRIX 6.5.26 Installation Tools and Overlays (1 of 3)"/>
@ -3269,7 +3425,7 @@ license:CC0
<software name="irix_6_5_27">
<description>IRIX 6.5.27</description>
<year>2005</year> <!-- 02/05 -->
<publisher>Silicon Graphics</publisher>
<publisher>SGI</publisher>
<part name="cdrom1" interface="cdrom">
<feature name="part_number" value="812-0818-027"/>
<feature name="part_id" value="IRIX 6.5.27 Installation Tools and Overlays (1 of 3)"/>
@ -3299,7 +3455,7 @@ license:CC0
<software name="irix_6_5_28">
<description>IRIX 6.5.28</description>
<year>2005</year> <!-- 08/05 -->
<publisher>Silicon Graphics</publisher>
<publisher>SGI</publisher>
<part name="cdrom1" interface="cdrom">
<feature name="part_number" value="812-0818-028"/>
<feature name="part_id" value="RIX 6.5.28 Installation Tools and Overlays (1 of 3)"/>
@ -3329,7 +3485,7 @@ license:CC0
<software name="irix_6_5_29">
<description>IRIX 6.5.29</description>
<year>2006</year> <!-- 02/06 -->
<publisher>Silicon Graphics</publisher>
<publisher>SGI</publisher>
<part name="cdrom1" interface="cdrom">
<feature name="part_number" value="812-0818-029"/>
<feature name="part_id" value="IRIX 6.5.29 Installation Tools and Overlays 1 of 3 February 06"/>
@ -3383,7 +3539,7 @@ license:CC0
<software name="irix_6_5_30">
<description>IRIX 6.5.30</description>
<year>2006</year> <!-- 08/06 -->
<publisher>Silicon Graphics</publisher>
<publisher>SGI</publisher>
<part name="cdrom1" interface="cdrom">
<feature name="part_number" value="812-0818-030"/>
<feature name="part_id" value="IRIX 6.5.30 Installation Tools and Overlays (1 of 3)"/>

35
hash/st_flop.xml
View File

@ -4294,6 +4294,41 @@ license:CC0
</part>
</software>
<software name="sf2" supported="no">
<description>Street Fighter II: The World Warrior (Euro)</description>
<year>1992</year>
<publisher>U.S. Gold</publisher>
<sharedfeat name="compatibility" value="PAL"/>
<part name="flop1" interface="floppy_3_5">
<feature name="part_id" value="Disk 1" />
<dataarea name="flop" size="2131682">
<rom name="Street Fighter 2 Disk 1.mfm" size="2131682" crc="2712b1aa" sha1="9fc407a84590f18d2c5225e3ad25cc9800281936" />
</dataarea>
</part>
<part name="flop2" interface="floppy_3_5">
<feature name="part_id" value="Disk 2" />
<dataarea name="flop" size="2141960">
<rom name="Street Fighter 2 Disk 2.mfm" size="2141960" crc="9d569238" sha1="658ea036f65fa9ff0b9ec06cec40c3a36860de51" />
</dataarea>
</part>
<part name="flop3" interface="floppy_3_5">
<feature name="part_id" value="Disk 3" />
<dataarea name="flop" size="2139383">
<rom name="Street Fighter 2 Disk 3.mfm" size="2139383" crc="526ec0bd" sha1="a13c85ec80e06b35055ca70b85f6c519e44e8fd4" />
</dataarea>
</part>
<part name="flop4" interface="floppy_3_5">
<feature name="part_id" value="Disk 4" />
<dataarea name="flop" size="2139380">
<rom name="Street Fighter 2 Disk 4.mfm" size="2139380" crc="eda4a515" sha1="be40cb13b26bd22f3b10fc798fd1803ef675287d" />
</dataarea>
</part>
</software>
<software name="strider" supported="no">
<!-- SPS (CAPS) release 3193 -->
<description>Strider (Euro, Les Chevaliers)</description>

4
scripts/src/netlist.lua
View File

@ -158,6 +158,8 @@ project "netlist"
MAME_DIR .. "src/lib/netlist/devices/nld_74107.h",
MAME_DIR .. "src/lib/netlist/devices/nld_74123.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_74123.h",
MAME_DIR .. "src/lib/netlist/devices/nld_74125.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_74125.h",
MAME_DIR .. "src/lib/netlist/devices/nld_74153.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_74153.h",
MAME_DIR .. "src/lib/netlist/devices/nld_74161.cpp",
@ -178,6 +180,8 @@ project "netlist"
MAME_DIR .. "src/lib/netlist/devices/nld_74193.h",
MAME_DIR .. "src/lib/netlist/devices/nld_74194.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_74194.h",
MAME_DIR .. "src/lib/netlist/devices/nld_74377.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_74377.h",
MAME_DIR .. "src/lib/netlist/devices/nld_74393.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_74393.h",
MAME_DIR .. "src/lib/netlist/devices/nld_74365.cpp",

2
scripts/target/mame/arcade.lua
View File

@ -1219,6 +1219,8 @@ files {
MAME_DIR .. "src/mame/drivers/jaguar.cpp",
MAME_DIR .. "src/mame/includes/jaguar.h",
MAME_DIR .. "src/mame/audio/jaguar.cpp",
MAME_DIR .. "src/mame/video/jag_blitter.cpp",
MAME_DIR .. "src/mame/video/jag_blitter.h",
MAME_DIR .. "src/mame/video/jaguar.cpp",
MAME_DIR .. "src/mame/video/jagblit.h",
MAME_DIR .. "src/mame/video/jagblit.hxx",

4
scripts/target/mame/mess.lua
View File

@ -1666,7 +1666,8 @@ files {
MAME_DIR .. "src/mame/includes/pc1512.h",
MAME_DIR .. "src/mame/machine/pc1512kb.cpp",
MAME_DIR .. "src/mame/machine/pc1512kb.h",
MAME_DIR .. "src/mame/video/pc1512.cpp",
MAME_DIR .. "src/mame/video/ams40041.cpp",
MAME_DIR .. "src/mame/video/ams40041.h",
MAME_DIR .. "src/mame/drivers/pcw.cpp",
MAME_DIR .. "src/mame/includes/pcw.h",
MAME_DIR .. "src/mame/video/pcw.cpp",
@ -2673,6 +2674,7 @@ createMESSProjects(_target, _subtarget, "korg")
files {
MAME_DIR .. "src/mame/drivers/korgds8.cpp",
MAME_DIR .. "src/mame/drivers/korgdss1.cpp",
MAME_DIR .. "src/mame/drivers/korgdvp1.cpp",
MAME_DIR .. "src/mame/drivers/korgdw8k.cpp",
MAME_DIR .. "src/mame/drivers/korgm1.cpp",
MAME_DIR .. "src/mame/drivers/korgz3.cpp",

8
src/devices/bus/a1bus/a1cffa.cpp
View File

@ -97,7 +97,7 @@ READ8_MEMBER(a1bus_cffa_device::cffa_r)
break;
case 0x8:
m_lastdata = m_ata->read_cs0((offset & 0xf) - 8, 0xff);
m_lastdata = m_ata->cs0_r((offset & 0xf) - 8, 0xff);
return m_lastdata & 0x00ff;
case 0x9:
@ -107,7 +107,7 @@ READ8_MEMBER(a1bus_cffa_device::cffa_r)
case 0xd:
case 0xe:
case 0xf:
return m_ata->read_cs0((offset & 0xf) - 8, 0xff);
return m_ata->cs0_r((offset & 0xf) - 8, 0xff);
}
return 0xff;
@ -132,7 +132,7 @@ WRITE8_MEMBER(a1bus_cffa_device::cffa_w)
case 0x8:
m_ata->write_cs0((offset & 0xf) - 8, data, 0xff);
m_ata->cs0_w((offset & 0xf) - 8, data, 0xff);
break;
case 0x9:
@ -142,7 +142,7 @@ WRITE8_MEMBER(a1bus_cffa_device::cffa_w)
case 0xd:
case 0xe:
case 0xf:
m_ata->write_cs0((offset & 0xf) - 8, data, 0xff);
m_ata->cs0_w((offset & 0xf) - 8, data, 0xff);
break;
}

8
src/devices/bus/a2bus/a2cffa.cpp
View File

@ -145,7 +145,7 @@ uint8_t a2bus_cffa2000_device::read_c0nx(uint8_t offset)
// Apple /// driver uses sta $c080,x when writing, which causes spurious reads of c088
if (!m_inwritecycle)
{
m_lastreaddata = m_ata->read_cs0(offset - 8);
m_lastreaddata = m_ata->cs0_r(offset - 8);
}
return m_lastreaddata & 0xff;
@ -156,7 +156,7 @@ uint8_t a2bus_cffa2000_device::read_c0nx(uint8_t offset)
case 0xd:
case 0xe:
case 0xf:
return m_ata->read_cs0(offset-8, 0xff);
return m_ata->cs0_r(offset-8, 0xff);
}
return 0xff;
@ -192,7 +192,7 @@ void a2bus_cffa2000_device::write_c0nx(uint8_t offset, uint8_t data)
m_lastdata &= 0xff00;
m_lastdata |= data;
// printf("%02x to 8, m_lastdata = %x\n", data, m_lastdata);
m_ata->write_cs0(offset-8, m_lastdata);
m_ata->cs0_w(offset-8, m_lastdata);
break;
case 9:
@ -202,7 +202,7 @@ void a2bus_cffa2000_device::write_c0nx(uint8_t offset, uint8_t data)
case 0xd:
case 0xe:
case 0xf:
m_ata->write_cs0(offset-8, data, 0xff);
m_ata->cs0_w(offset-8, data, 0xff);
break;
}
}

12
src/devices/bus/a2bus/a2vulcan.cpp
View File

@ -191,7 +191,7 @@ uint8_t a2bus_vulcanbase_device::read_c0nx(uint8_t offset)
switch (offset)
{
case 0:
m_lastdata = m_ata->read_cs0(offset);
m_lastdata = m_ata->cs0_r(offset);
// printf("IDE: read %04x\n", m_lastdata);
m_last_read_was_0 = true;
return m_lastdata&0xff;
@ -204,7 +204,7 @@ uint8_t a2bus_vulcanbase_device::read_c0nx(uint8_t offset)
}
else
{
return m_ata->read_cs0(offset, 0xff);
return m_ata->cs0_r(offset, 0xff);
}
case 2:
@ -213,7 +213,7 @@ uint8_t a2bus_vulcanbase_device::read_c0nx(uint8_t offset)
case 5:
case 6:
case 7:
return m_ata->read_cs0(offset, 0xff);
return m_ata->cs0_r(offset, 0xff);
default:
logerror("a2vulcan: unknown read @ C0n%x\n", offset);
@ -245,11 +245,11 @@ void a2bus_vulcanbase_device::write_c0nx(uint8_t offset, uint8_t data)
m_lastdata &= 0x00ff;
m_lastdata |= (data << 8);
// printf("IDE: write %04x\n", m_lastdata);
m_ata->write_cs0(0, m_lastdata);
m_ata->cs0_w(0, m_lastdata);
}
else
{
m_ata->write_cs0(offset, data, 0xff);
m_ata->cs0_w(offset, data, 0xff);
}
break;
@ -260,7 +260,7 @@ void a2bus_vulcanbase_device::write_c0nx(uint8_t offset, uint8_t data)
case 6:
case 7:
// printf("%02x to IDE controller @ %x\n", data, offset);
m_ata->write_cs0(offset, data, 0xff);
m_ata->cs0_w(offset, data, 0xff);
break;
case 9: // ROM bank

20
src/devices/bus/a2bus/a2zipdrive.cpp
View File

@ -175,10 +175,10 @@ uint8_t a2bus_zipdrivebase_device::read_c0nx(uint8_t offset)
case 5:
case 6:
case 7:
return m_ata->read_cs0(offset, 0xff);
return m_ata->cs0_r(offset, 0xff);
case 8: // data port
m_lastdata = m_ata->read_cs0(0, 0xffff);
m_lastdata = m_ata->cs0_r(0, 0xffff);
// printf("%04x @ IDE data\n", m_lastdata);
return m_lastdata&0xff;
@ -205,10 +205,10 @@ uint8_t a2bus_focusdrive_device::read_c0nx(uint8_t offset)
case 0xd:
case 0xe:
case 0xf:
return m_ata->read_cs0(offset&7, 0xff);
return m_ata->cs0_r(offset&7, 0xff);
case 0: // data port
m_lastdata = m_ata->read_cs0(0, 0xffff);
m_lastdata = m_ata->cs0_r(0, 0xffff);
//printf("%04x @ IDE data\n", m_lastdata);
return m_lastdata&0xff;
@ -240,7 +240,7 @@ void a2bus_zipdrivebase_device::write_c0nx(uint8_t offset, uint8_t data)
case 6:
case 7:
// printf("%02x to IDE controller @ %x\n", data, offset);
m_ata->write_cs0(offset, data, 0xff);
m_ata->cs0_w(offset, data, 0xff);
break;
case 8:
@ -252,7 +252,7 @@ void a2bus_zipdrivebase_device::write_c0nx(uint8_t offset, uint8_t data)
// printf("%02x to IDE data hi\n", data);
m_lastdata &= 0x00ff;
m_lastdata |= (data << 8);
m_ata->write_cs0(0, m_lastdata, 0xffff);
m_ata->cs0_w(0, m_lastdata, 0xffff);
break;
default:
@ -275,14 +275,14 @@ void a2bus_focusdrive_device::write_c0nx(uint8_t offset, uint8_t data)
case 0xf:
// due to a bug in the 6502 firmware, eat data if DRQ is set
#if 0
while (m_ata->read_cs0(7, 0xff) & 0x08)
while (m_ata->cs0_r(7, 0xff) & 0x08)
{
m_ata->read_cs0(0, 0xffff);
m_ata->cs0_r(0, 0xffff);
printf("eating 2 bytes to clear DRQ\n");
}
#endif
// printf("%02x to IDE controller @ %x\n", data, offset);
m_ata->write_cs0(offset & 7, data, 0xff);
m_ata->cs0_w(offset & 7, data, 0xff);
break;
case 0:
@ -294,7 +294,7 @@ void a2bus_focusdrive_device::write_c0nx(uint8_t offset, uint8_t data)
// printf("%02x to IDE data hi\n", data);
m_lastdata &= 0x00ff;
m_lastdata |= (data << 8);
m_ata->write_cs0(0, m_lastdata, 0xffff);
m_ata->cs0_w(0, m_lastdata, 0xffff);
break;
default:

10
src/devices/bus/adam/ide.cpp
View File

@ -116,7 +116,7 @@ uint8_t powermate_ide_device::adam_bd_r(offs_t offset, uint8_t data, int bmreq,
case 0x05:
case 0x06:
case 0x07:
data = m_ata->read_cs0(offset & 0x07, 0xff);
data = m_ata->cs0_r(offset & 0x07, 0xff);
break;
case 0x40: // Printer status
@ -137,7 +137,7 @@ uint8_t powermate_ide_device::adam_bd_r(offs_t offset, uint8_t data, int bmreq,
break;
case 0x58:
m_ata_data = m_ata->read_cs0(0);
m_ata_data = m_ata->cs0_r(0);
data = m_ata_data & 0xff;
break;
@ -147,7 +147,7 @@ uint8_t powermate_ide_device::adam_bd_r(offs_t offset, uint8_t data, int bmreq,
break;
case 0x5a:
data = m_ata->read_cs1(6, 0xff);
data = m_ata->cs1_r(6, 0xff);
break;
case 0x5b: // Digital Input Register
@ -176,7 +176,7 @@ void powermate_ide_device::adam_bd_w(offs_t offset, uint8_t data, int bmreq, int
case 0x05:
case 0x06:
case 0x07:
m_ata->write_cs0(offset & 0x07, data, 0xff);
m_ata->cs0_w(offset & 0x07, data, 0xff);
break;
case 0x40:
@ -188,7 +188,7 @@ void powermate_ide_device::adam_bd_w(offs_t offset, uint8_t data, int bmreq, int
case 0x58:
m_ata_data |= data;
m_ata->write_cs0(0, m_ata_data);
m_ata->cs0_w(0, m_ata_data);
break;
case 0x59:

16
src/devices/bus/amiga/zorro/buddha.cpp
View File

@ -248,7 +248,7 @@ WRITE16_MEMBER( buddha_device::ide_interrupt_enable_w )
READ16_MEMBER( buddha_device::ide_0_cs0_r )
{
uint16_t data = m_ata_0->read_cs0((offset >> 1) & 0x07, (mem_mask << 8) | (mem_mask >> 8));
uint16_t data = m_ata_0->cs0_r((offset >> 1) & 0x07, (mem_mask << 8) | (mem_mask >> 8));
data = (data << 8) | (data >> 8);
LOG("ide_0_cs0_r(%04x) %04x [mask = %04x]\n", offset, data, mem_mask);
@ -263,12 +263,12 @@ WRITE16_MEMBER( buddha_device::ide_0_cs0_w )
mem_mask = (mem_mask << 8) | (mem_mask >> 8);
data = (data << 8) | (data >> 8);
m_ata_0->write_cs0((offset >> 1) & 0x07, data, mem_mask);
m_ata_0->cs0_w((offset >> 1) & 0x07, data, mem_mask);
}
READ16_MEMBER( buddha_device::ide_0_cs1_r )
{
uint16_t data = m_ata_0->read_cs1((offset >> 1) & 0x07, (mem_mask << 8) | (mem_mask >> 8));
uint16_t data = m_ata_0->cs1_r((offset >> 1) & 0x07, (mem_mask << 8) | (mem_mask >> 8));
data = (data << 8) | (data >> 8);
LOG("ide_0_cs1_r(%04x) %04x [mask = %04x]\n", offset, data, mem_mask);
@ -283,12 +283,12 @@ WRITE16_MEMBER( buddha_device::ide_0_cs1_w )
mem_mask = (mem_mask << 8) | (mem_mask >> 8);
data = (data << 8) | (data >> 8);
m_ata_0->write_cs1((offset >> 1) & 0x07, data, mem_mask);
m_ata_0->cs1_w((offset >> 1) & 0x07, data, mem_mask);
}
READ16_MEMBER( buddha_device::ide_1_cs0_r )
{
uint16_t data = m_ata_1->read_cs0((offset >> 1) & 0x07, (mem_mask << 8) | (mem_mask >> 8));
uint16_t data = m_ata_1->cs0_r((offset >> 1) & 0x07, (mem_mask << 8) | (mem_mask >> 8));
data = (data << 8) | (data >> 8);
LOG("ide_1_cs0_r(%04x) %04x [mask = %04x]\n", offset, data, mem_mask);
@ -303,12 +303,12 @@ WRITE16_MEMBER( buddha_device::ide_1_cs0_w )
mem_mask = (mem_mask << 8) | (mem_mask >> 8);
data = (data << 8) | (data >> 8);
m_ata_1->write_cs0((offset >> 1) & 0x07, data, mem_mask);
m_ata_1->cs0_w((offset >> 1) & 0x07, data, mem_mask);
}
READ16_MEMBER( buddha_device::ide_1_cs1_r )
{
uint16_t data = m_ata_1->read_cs1((offset >> 1) & 0x07, (mem_mask << 8) | (mem_mask >> 8));
uint16_t data = m_ata_1->cs1_r((offset >> 1) & 0x07, (mem_mask << 8) | (mem_mask >> 8));
data = (data << 8) | (data >> 8);
LOG("ide_1_cs1_r(%04x) %04x [mask = %04x]\n", offset, data, mem_mask);
@ -323,7 +323,7 @@ WRITE16_MEMBER( buddha_device::ide_1_cs1_w )
mem_mask = (mem_mask << 8) | (mem_mask >> 8);
data = (data << 8) | (data >> 8);
m_ata_1->write_cs1((offset >> 1) & 0x07, data, mem_mask);
m_ata_1->cs1_w((offset >> 1) & 0x07, data, mem_mask);
}
} } } // namespace bus::amiga::zorro

13
src/devices/bus/ata/ataintf.h
View File

@ -133,15 +133,10 @@ public:
return *this;
}
uint16_t read_cs0(offs_t offset, uint16_t mem_mask = 0xffff) { return internal_read_cs0(offset, mem_mask); }
uint16_t read_cs1(offs_t offset, uint16_t mem_mask = 0xffff) { return internal_read_cs1(offset, mem_mask); }
void write_cs0(offs_t offset, uint16_t data, uint16_t mem_mask = 0xffff) { internal_write_cs0(offset, data, mem_mask); }
void write_cs1(offs_t offset, uint16_t data, uint16_t mem_mask = 0xffff) { internal_write_cs1(offset, data, mem_mask); }
DECLARE_READ16_MEMBER(cs0_r) { return read_cs0(offset, mem_mask); }
DECLARE_READ16_MEMBER(cs1_r) { return read_cs1(offset, mem_mask); }
DECLARE_WRITE16_MEMBER(cs0_w) { write_cs0(offset, data, mem_mask); }
DECLARE_WRITE16_MEMBER(cs1_w) { write_cs1(offset, data, mem_mask); }
uint16_t cs0_r(offs_t offset, uint16_t mem_mask = 0xffff) { return internal_read_cs0(offset, mem_mask); }
uint16_t cs1_r(offs_t offset, uint16_t mem_mask = 0xffff) { return internal_read_cs1(offset, mem_mask); }
void cs0_w(offs_t offset, uint16_t data, uint16_t mem_mask = 0xffff) { internal_write_cs0(offset, data, mem_mask); }
void cs1_w(offs_t offset, uint16_t data, uint16_t mem_mask = 0xffff) { internal_write_cs1(offset, data, mem_mask); }
};
DECLARE_DEVICE_TYPE(ATA_INTERFACE, ata_interface_device)

12
src/devices/bus/bbc/1mhzbus/datacentre.cpp
View File

@ -149,18 +149,18 @@ uint8_t bbc_datacentre_device::fred_r(offs_t offset)
case 0x40:
if (offset & 0x07)
{
data = m_ide->read_cs0(offset & 0x07, 0xff);
data = m_ide->cs0_r(offset & 0x07, 0xff);
}
else
{
m_ide_data = m_ide->read_cs0(offset & 0x07);
m_ide_data = m_ide->cs0_r(offset & 0x07);
data = m_ide_data & 0xff;
}
break;
case 0x48:
if (offset & 0x04)
{
data = m_ide->read_cs1(offset & 0x07, 0xff);
data = m_ide->cs1_r(offset & 0x07, 0xff);
}
else
{
@ -206,18 +206,18 @@ void bbc_datacentre_device::fred_w(offs_t offset, uint8_t data)
case 0x40:
if (offset & 0x07)
{
m_ide->write_cs0(offset & 0x07, data, 0xff);
m_ide->cs0_w(offset & 0x07, data, 0xff);
}
else
{
m_ide_data = (m_ide_data & 0xff00) | data;
m_ide->write_cs0(offset & 0x07, m_ide_data);
m_ide->cs0_w(offset & 0x07, m_ide_data);
}
break;
case 0x48:
if (offset & 0x04)
{
m_ide->write_cs1(offset & 0x07, data, 0xff);
m_ide->cs1_w(offset & 0x07, data, 0xff);
}
else
{

16
src/devices/bus/bbc/1mhzbus/ide.cpp
View File

@ -117,7 +117,7 @@ uint8_t bbc_ide8_device::fred_r(offs_t offset)
switch (offset & 0xf8)
{
case 0x40:
data = m_ide->read_cs0(offset & 0x07, 0xff);
data = m_ide->cs0_r(offset & 0x07, 0xff);
break;
}
@ -129,7 +129,7 @@ void bbc_ide8_device::fred_w(offs_t offset, uint8_t data)
switch (offset & 0xf8)
{
case 0x40:
m_ide->write_cs0(offset & 0x07, data, 0xff);
m_ide->cs0_w(offset & 0x07, data, 0xff);
break;
}
}
@ -146,18 +146,18 @@ uint8_t bbc_beebide_device::fred_r(offs_t offset)
case 0x40:
if (offset & 0x07)
{
data = m_ide->read_cs0(offset & 0x07, 0xff);
data = m_ide->cs0_r(offset & 0x07, 0xff);
}
else
{
m_ide_data = m_ide->read_cs0(offset & 0x07);
m_ide_data = m_ide->cs0_r(offset & 0x07);
data = m_ide_data & 0xff;
}
break;
case 0x48:
if (offset & 0x04)
{
data = m_ide->read_cs1(offset & 0x07, 0xff);
data = m_ide->cs1_r(offset & 0x07, 0xff);
}
else
{
@ -181,18 +181,18 @@ void bbc_beebide_device::fred_w(offs_t offset, uint8_t data)
case 0x40:
if (offset & 0x07)
{
m_ide->write_cs0(offset & 0x07, data, 0xff);
m_ide->cs0_w(offset & 0x07, data, 0xff);
}
else
{
m_ide_data = (m_ide_data & 0xff00) | data;
m_ide->write_cs0(offset & 0x07, m_ide_data);
m_ide->cs0_w(offset & 0x07, m_ide_data);
}
break;
case 0x48:
if (offset & 0x04)
{
m_ide->write_cs1(offset & 0x07, data, 0xff);
m_ide->cs1_w(offset & 0x07, data, 0xff);
}
else
{

8
src/devices/bus/c64/ide64.cpp
View File

@ -173,13 +173,13 @@ uint8_t c64_ide64_cartridge_device::c64_cd_r(offs_t offset, uint8_t data, int sp
if (io1_offset >= 0x20 && io1_offset < 0x28)
{
m_ata_data = m_ata->read_cs0(offset & 0x07);
m_ata_data = m_ata->cs0_r(offset & 0x07);
data = m_ata_data & 0xff;
}
else if (io1_offset >= 0x28 && io1_offset < 0x30)
{
m_ata_data = m_ata->read_cs1(offset & 0x07);
m_ata_data = m_ata->cs1_r(offset & 0x07);
data = m_ata_data & 0xff;
}
@ -276,13 +276,13 @@ void c64_ide64_cartridge_device::c64_cd_w(offs_t offset, uint8_t data, int sphi2
{
m_ata_data = (m_ata_data & 0xff00) | data;
m_ata->write_cs0(offset & 0x07, m_ata_data);
m_ata->cs0_w(offset & 0x07, m_ata_data);
}
else if (io1_offset >= 0x28 && io1_offset < 0x30)
{
m_ata_data = (m_ata_data & 0xff00) | data;
m_ata->write_cs1(offset & 0x07, m_ata_data);
m_ata->cs1_w(offset & 0x07, m_ata_data);
}
else if (io1_offset == 0x31)
{

8
src/devices/bus/cgenie/parallel/parallel.cpp
View File

@ -56,7 +56,7 @@ void cg_parallel_slot_device::device_start()
// I/O PORTS
//**************************************************************************
READ8_MEMBER( cg_parallel_slot_device::pa_r )
uint8_t cg_parallel_slot_device::pa_r()
{
if (m_cart)
return m_cart->pa_r();
@ -64,13 +64,13 @@ READ8_MEMBER( cg_parallel_slot_device::pa_r )
return 0xff;
}
WRITE8_MEMBER( cg_parallel_slot_device::pa_w )
void cg_parallel_slot_device::pa_w(uint8_t data)
{
if (m_cart)
m_cart->pa_w(data);
}
READ8_MEMBER( cg_parallel_slot_device::pb_r )
uint8_t cg_parallel_slot_device::pb_r()
{
if (m_cart)
return m_cart->pb_r();
@ -78,7 +78,7 @@ READ8_MEMBER( cg_parallel_slot_device::pb_r )
return 0xff;
}
WRITE8_MEMBER( cg_parallel_slot_device::pb_w )
void cg_parallel_slot_device::pb_w(uint8_t data)
{
if (m_cart)
m_cart->pb_w(data);

8
src/devices/bus/cgenie/parallel/parallel.h
View File

@ -49,12 +49,12 @@ public:
virtual ~cg_parallel_slot_device();
// IOA
DECLARE_READ8_MEMBER(pa_r);
DECLARE_WRITE8_MEMBER(pa_w);
uint8_t pa_r();
void pa_w(uint8_t data);
// IOB
DECLARE_READ8_MEMBER(pb_r);
DECLARE_WRITE8_MEMBER(pb_w);
uint8_t pb_r();
void pb_w(uint8_t data);
protected:
// device-level overrides

2
src/devices/bus/comx35/exp.cpp
View File

@ -157,7 +157,7 @@ READ_LINE_MEMBER(comx_expansion_slot_device::ef4_r)
// sc_w - state code/N0-N2 write
//-------------------------------------------------
WRITE8_MEMBER(comx_expansion_slot_device::sc_w)
void comx_expansion_slot_device::sc_w(offs_t offset, uint8_t data)
{
if (m_card != nullptr)
m_card->comx_sc_w(offset, data);

2
src/devices/bus/comx35/exp.h
View File

@ -73,7 +73,7 @@ public:
DECLARE_WRITE_LINE_MEMBER(irq_w) { m_write_irq(state); }
DECLARE_WRITE8_MEMBER(sc_w);
void sc_w(offs_t offset, uint8_t data);
DECLARE_WRITE_LINE_MEMBER(tpb_w);
protected:

10
src/devices/bus/cpc/symbfac2.cpp
View File

@ -133,27 +133,27 @@ READ8_MEMBER(cpc_symbiface2_device::ide_cs0_r)
else
{
m_iohigh = true;
m_ide_data = m_ide->read_cs0(offset);
m_ide_data = m_ide->cs0_r(offset);
return m_ide_data & 0xff;
}
}
else
return m_ide->read_cs0(offset);
return m_ide->cs0_r(offset);
}
WRITE8_MEMBER(cpc_symbiface2_device::ide_cs0_w)
{
m_ide->write_cs0(offset, data);
m_ide->cs0_w(offset, data);
}
READ8_MEMBER(cpc_symbiface2_device::ide_cs1_r)
{
return m_ide->read_cs1(offset);
return m_ide->cs1_r(offset);
}
WRITE8_MEMBER(cpc_symbiface2_device::ide_cs1_w)
{
m_ide->write_cs1(offset, data);
m_ide->cs1_w(offset, data);
}
// RTC (Dallas DS1287A)

4
src/devices/bus/hp80_io/82937.cpp
View File

@ -158,7 +158,7 @@ READ8_MEMBER(hp82937_io_card_device::dio_r)
if (m_dio_out) {
return 0xff;
} else {
return m_ieee488->read_dio();
return m_ieee488->dio_r();
}
}
@ -252,7 +252,7 @@ void hp82937_io_card_device::device_reset()
void hp82937_io_card_device::update_data_out()
{
m_ieee488->write_dio(m_dio_out ? m_cpu->p2_r() : 0xff);
m_ieee488->host_dio_w(m_dio_out ? m_cpu->p2_r() : 0xff);
}
void hp82937_io_card_device::update_signals()

4
src/devices/bus/hp9845_io/98034.cpp
View File

@ -245,7 +245,7 @@ READ8_MEMBER(hp98034_io_card_device::hpib_ctrl_r)
READ8_MEMBER(hp98034_io_card_device::hpib_data_r)
{
return ~m_ieee488->read_dio();
return ~m_ieee488->dio_r();
}
READ8_MEMBER(hp98034_io_card_device::idr_r)
@ -331,7 +331,7 @@ void hp98034_io_card_device::update_data_out()
if (m_clr_hpib) {
m_data_out = 0;
}
m_ieee488->write_dio(~m_data_out);
m_ieee488->host_dio_w(~m_data_out);
}
void hp98034_io_card_device::update_ctrl_out()

2
src/devices/bus/hp_dio/human_interface.cpp
View File

@ -217,7 +217,7 @@ WRITE8_MEMBER(human_interface_device::gpib_w)
if (m_ppoll_sc & PPOLL_IE) {
LOG("%s: start parallel poll\n", __func__);
ieee488_dio_w(space, 0, m_ieee488->dio_r(space, 0));
ieee488_dio_w(space, 0, m_ieee488->dio_r());
}
break;
case 4:

2
src/devices/bus/ieee488/c2031.cpp
View File

@ -94,7 +94,7 @@ READ8_MEMBER( c2031_device::via0_pa_r )
*/
return m_bus->read_dio();
return m_bus->dio_r();
}
WRITE8_MEMBER( c2031_device::via0_pa_w )

2
src/devices/bus/ieee488/c2040.cpp
View File

@ -222,7 +222,7 @@ READ8_MEMBER( c2040_device::dio_r )
*/
return m_bus->read_dio();
return m_bus->dio_r();
}
WRITE8_MEMBER( c2040_device::dio_w )

2
src/devices/bus/ieee488/c8050.cpp
View File

@ -274,7 +274,7 @@ READ8_MEMBER( c8050_device::dio_r )
*/
return m_bus->read_dio();
return m_bus->dio_r();
}
WRITE8_MEMBER( c8050_device::dio_w )

2
src/devices/bus/ieee488/c8280.cpp
View File

@ -127,7 +127,7 @@ READ8_MEMBER( c8280_device::dio_r )
*/
return m_bus->read_dio();
return m_bus->dio_r();
}
WRITE8_MEMBER( c8280_device::dio_w )

2
src/devices/bus/ieee488/d9060.cpp
View File

@ -153,7 +153,7 @@ READ8_MEMBER( d9060_device_base::dio_r )
*/
return m_bus->read_dio();
return m_bus->dio_r();
}

8
src/devices/bus/ieee488/grid2102.cpp
View File

@ -91,9 +91,9 @@ void grid210x_device::device_start() {
void grid210x_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) {
if (m_floppy_loop_state == GRID210X_STATE_READING_DATA) {
uint8_t data[io_size];
std::unique_ptr<uint8_t[]> data(new uint8_t[io_size]);
fseek(floppy_sector_number * 512, SEEK_SET);
fread(data, io_size);
fread(data.get(), io_size);
for (int i = 0; i < io_size; i++) {
m_output_data_buffer.push(data[i]);
}
@ -160,7 +160,7 @@ void grid210x_device::ieee488_dav(int state) {
// read data and wait for transfer end
int atn = m_bus->atn_r() ^ 1;
m_bus->nrfd_w(this, 0);
uint8_t data = m_bus->read_dio() ^ 0xFF;
uint8_t data = m_bus->dio_r() ^ 0xFF;
int eoi = m_bus->eoi_r() ^ 1;
LOG_BYTES("grid210x_device byte recv %02x atn %d eoi %d\n", data, atn, eoi);
m_last_recv_byte = data;
@ -235,7 +235,7 @@ void grid210x_device::ieee488_dav(int state) {
void grid210x_device::ieee488_nrfd(int state) {
if (state == 1 && m_gpib_loop_state == GRID210X_GPIB_STATE_SEND_DATA_START) {
// set dio and assert dav
m_bus->write_dio(m_byte_to_send ^ 0xFF);
m_bus->host_dio_w(m_byte_to_send ^ 0xFF);
m_bus->eoi_w(this, m_send_eoi ^ 1);
m_bus->dav_w(this, 0);
m_bus->ndac_w(this, 1);

2
src/devices/bus/ieee488/hardbox.cpp
View File

@ -131,7 +131,7 @@ void hardbox_device::hardbox_io(address_map &map)
READ8_MEMBER( hardbox_device::ppi0_pa_r )
{
return m_bus->read_dio() ^ 0xff;
return m_bus->dio_r() ^ 0xff;
}
WRITE8_MEMBER( hardbox_device::ppi0_pb_w )

2
src/devices/bus/ieee488/hp9122c.cpp
View File

@ -257,7 +257,7 @@ void hp9122c_device::update_intsel()
READ8_MEMBER(hp9122c_device::i8291a_dio_r)
{
return m_bus->read_dio();
return m_bus->dio_r();
}
WRITE8_MEMBER(hp9122c_device::i8291a_dio_w)

2
src/devices/bus/ieee488/hp9895.cpp
View File

@ -473,7 +473,7 @@ WRITE_LINE_MEMBER(hp9895_device::phi_ren_w)
READ8_MEMBER(hp9895_device::phi_dio_r)
{
return m_bus->read_dio();
return m_bus->dio_r();
}
WRITE8_MEMBER(hp9895_device::phi_dio_w)

6
src/devices/bus/ieee488/ieee488.h
View File

@ -61,8 +61,7 @@ public:
void add_device(ieee488_slot_device *slot, device_t *target);
// reads for both host and peripherals
uint8_t read_dio() { return get_data(); }
DECLARE_READ8_MEMBER( dio_r ) { return get_data(); }
uint8_t dio_r() { return get_data(); }
DECLARE_READ_LINE_MEMBER( eoi_r ) { return get_signal(EOI); }
DECLARE_READ_LINE_MEMBER( dav_r ) { return get_signal(DAV); }
DECLARE_READ_LINE_MEMBER( nrfd_r ) { return get_signal(NRFD); }
@ -73,8 +72,7 @@ public:
DECLARE_READ_LINE_MEMBER( ren_r ) { return get_signal(REN); }
// writes for host (driver_device)
void write_dio(uint8_t data) { set_data(this, data); }
DECLARE_WRITE8_MEMBER( host_dio_w ) { set_data(this, data); }
void host_dio_w(uint8_t data) { set_data(this, data); }
DECLARE_WRITE_LINE_MEMBER( host_eoi_w ) { set_signal(this, EOI, state); }
DECLARE_WRITE_LINE_MEMBER( host_dav_w ) { set_signal(this, DAV, state); }
DECLARE_WRITE_LINE_MEMBER( host_nrfd_w ) { set_signal(this, NRFD, state); }

2
src/devices/bus/ieee488/remote488.cpp
View File

@ -707,7 +707,7 @@ void remote488_device::update_ah_fsm()
if (m_bus->dav_r()) {
m_ah_state = REM_AH_ACRS;
} else if (!m_waiting_cp) {
uint8_t dio = ~m_bus->read_dio();
uint8_t dio = ~m_bus->dio_r();
if (!m_bus->eoi_r()) {
send_update(MSG_END_BYTE , dio);

2
src/devices/bus/ieee488/softbox.cpp
View File

@ -100,7 +100,7 @@ void softbox_device::softbox_io(address_map &map)
READ8_MEMBER( softbox_device::ppi0_pa_r )
{
return m_bus->read_dio() ^ 0xff;
return m_bus->dio_r() ^ 0xff;
}
WRITE8_MEMBER( softbox_device::ppi0_pb_w )

12
src/devices/bus/isa/side116.cpp
View File

@ -135,13 +135,13 @@ READ8_MEMBER( side116_device::read )
if (offset == 0)
{
uint16_t ide_data = m_ata->read_cs0(0);
uint16_t ide_data = m_ata->cs0_r(0);
data = ide_data & 0xff;
m_latch = ide_data >> 8;
}
else if (offset < 8)
{
data = m_ata->read_cs0(offset & 7, 0xff);
data = m_ata->cs0_r(offset & 7, 0xff);
}
else if (offset == 8)
{
@ -149,7 +149,7 @@ READ8_MEMBER( side116_device::read )
}
else
{
data = m_ata->read_cs1(offset & 7, 0xff);
data = m_ata->cs1_r(offset & 7, 0xff);
}
return data;
@ -160,11 +160,11 @@ WRITE8_MEMBER( side116_device::write )
if (offset == 0)
{
uint16_t ide_data = (m_latch << 8) | data;
m_ata->write_cs0(0, ide_data);
m_ata->cs0_w(0, ide_data);
}
else if (offset < 8)
{
m_ata->write_cs0(offset & 7, data, 0xff);
m_ata->cs0_w(offset & 7, data, 0xff);
}
else if (offset == 8)
{
@ -172,7 +172,7 @@ WRITE8_MEMBER( side116_device::write )
}
else
{
m_ata->write_cs1(offset & 7, data, 0xff);
m_ata->cs1_w(offset & 7, data, 0xff);
}
}

12
src/devices/bus/isa/xtide.cpp
View File

@ -63,13 +63,13 @@ READ8_MEMBER( xtide_device::read )
if (offset == 0)
{
uint16_t data16 = m_ata->read_cs0(offset & 7);
uint16_t data16 = m_ata->cs0_r(offset & 7);
result = data16 & 0xff;
m_d8_d15_latch = data16 >> 8;
}
else if (offset < 8)
{
result = m_ata->read_cs0(offset & 7, 0xff);
result = m_ata->cs0_r(offset & 7, 0xff);
}
else if (offset == 8)
{
@ -77,7 +77,7 @@ READ8_MEMBER( xtide_device::read )
}
else
{
result = m_ata->read_cs1(offset & 7, 0xff);
result = m_ata->cs1_r(offset & 7, 0xff);
}
// logerror("%s xtide_device::read: offset=%d, result=%2X\n",device->machine().describe_context(),offset,result);
@ -93,11 +93,11 @@ WRITE8_MEMBER( xtide_device::write )
{
// Data register transfer low byte and latched high
uint16_t data16 = (m_d8_d15_latch << 8) | data;
m_ata->write_cs0(offset & 7, data16);
m_ata->cs0_w(offset & 7, data16);
}
else if (offset < 8)
{
m_ata->write_cs0(offset & 7, data, 0xff);
m_ata->cs0_w(offset & 7, data, 0xff);
}
else if (offset == 8)
{
@ -105,7 +105,7 @@ WRITE8_MEMBER( xtide_device::write )
}
else
{
m_ata->write_cs1(offset & 7, data, 0xff);
m_ata->cs1_w(offset & 7, data, 0xff);
}
}

8
src/devices/bus/kc/d004.cpp
View File

@ -440,11 +440,11 @@ READ8_MEMBER(kc_d004_gide_device::gide_r)
{
if (ide_cs == 0 )
{
m_ata_data = m_ata->read_cs0(io_addr & 0x07);
m_ata_data = m_ata->cs0_r(io_addr & 0x07);
}
else
{
m_ata_data = m_ata->read_cs1(io_addr & 0x07);
m_ata_data = m_ata->cs1_r(io_addr & 0x07);
}
}
@ -489,11 +489,11 @@ WRITE8_MEMBER(kc_d004_gide_device::gide_w)
{
if (ide_cs == 0)
{
m_ata->write_cs0(io_addr & 0x07, m_ata_data);
m_ata->cs0_w(io_addr & 0x07, m_ata_data);
}
else
{
m_ata->write_cs1(io_addr & 0x07, m_ata_data);
m_ata->cs1_w(io_addr & 0x07, m_ata_data);
}
}
}

14
src/devices/bus/ql/qubide.cpp
View File

@ -211,15 +211,15 @@ uint8_t qubide_device::read(offs_t offset, uint8_t data)
switch (offset & 0x0f)
{
case 0:
data = m_ata->read_cs1(0x07, 0xff);
data = m_ata->cs1_r(0x07, 0xff);
break;
default:
data = m_ata->read_cs0(offset & 0x07, 0xff);
data = m_ata->cs0_r(offset & 0x07, 0xff);
break;
case 0x08: case 0x0a: case 0x0c:
m_ata_data = m_ata->read_cs0(0);
m_ata_data = m_ata->cs0_r(0);
data = m_ata_data >> 8;
break;
@ -229,7 +229,7 @@ uint8_t qubide_device::read(offs_t offset, uint8_t data)
break;
case 0x0e: case 0x0f:
data = m_ata->read_cs1(0x05, 0xff);
data = m_ata->cs1_r(0x05, 0xff);
break;
}
}
@ -256,7 +256,7 @@ void qubide_device::write(offs_t offset, uint8_t data)
switch (offset & 0x0f)
{
case 0: case 0x0e: case 0x0f:
m_ata->write_cs1(0x05, data, 0xff);
m_ata->cs1_w(0x05, data, 0xff);
break;
case 0x08: case 0x0a: case 0x0c:
@ -266,11 +266,11 @@ void qubide_device::write(offs_t offset, uint8_t data)
case 0x09: case 0x0b: case 0x0d:
m_ata_data = (m_ata_data & 0xff00) | data;
m_ata->write_cs0(0, m_ata_data);
m_ata->cs0_w(0, m_ata_data);
break;
default:
m_ata->write_cs0(offset & 0x07, data, 0xff);
m_ata->cs0_w(offset & 0x07, data, 0xff);
break;
}
}

8
src/devices/bus/scv/rom.cpp
View File

@ -154,7 +154,7 @@ WRITE8_MEMBER(scv_rom32ram8_device::write_cart)
m_ram[offset & 0x1fff] = data;
}
WRITE8_MEMBER(scv_rom32ram8_device::write_bank)
void scv_rom32ram8_device::write_bank(uint8_t data)
{
m_ram_enabled = BIT(data, 5);
}
@ -165,7 +165,7 @@ READ8_MEMBER(scv_rom64_device::read_cart)
return m_rom[offset + (m_bank_base * 0x8000)];
}
WRITE8_MEMBER(scv_rom64_device::write_bank)
void scv_rom64_device::write_bank(uint8_t data)
{
m_bank_base = BIT(data, 5);
}
@ -176,7 +176,7 @@ READ8_MEMBER(scv_rom128_device::read_cart)
return m_rom[offset + (m_bank_base * 0x8000)];
}
WRITE8_MEMBER(scv_rom128_device::write_bank)
void scv_rom128_device::write_bank(uint8_t data)
{
m_bank_base = (data >> 5) & 0x03;
}
@ -196,7 +196,7 @@ WRITE8_MEMBER(scv_rom128ram4_device::write_cart)
m_ram[offset & 0xfff] = data;
}
WRITE8_MEMBER(scv_rom128ram4_device::write_bank)
void scv_rom128ram4_device::write_bank(uint8_t data)
{
m_bank_base = (data >> 5) & 0x03;
m_ram_enabled = BIT(data, 6);

8
src/devices/bus/scv/rom.h
View File

@ -65,7 +65,7 @@ public:
// reading and writing
virtual DECLARE_READ8_MEMBER(read_cart) override;
virtual DECLARE_WRITE8_MEMBER(write_cart) override;
virtual DECLARE_WRITE8_MEMBER(write_bank) override;
virtual void write_bank(uint8_t data) override;
protected:
// device-level overrides
@ -91,7 +91,7 @@ public:
// reading and writing
virtual DECLARE_READ8_MEMBER(read_cart) override;
virtual DECLARE_WRITE8_MEMBER(write_bank) override;
virtual void write_bank(uint8_t data) override;
private:
uint8_t m_bank_base;
@ -108,7 +108,7 @@ public:
// reading and writing
virtual DECLARE_READ8_MEMBER(read_cart) override;
virtual DECLARE_WRITE8_MEMBER(write_bank) override;
virtual void write_bank(uint8_t data) override;
protected:
// device-level overrides
@ -131,7 +131,7 @@ public:
// reading and writing
virtual DECLARE_READ8_MEMBER(read_cart) override;
virtual DECLARE_WRITE8_MEMBER(write_cart) override;
virtual DECLARE_WRITE8_MEMBER(write_bank) override;
virtual void write_bank(uint8_t data) override;
protected:
// device-level overrides

4
src/devices/bus/scv/slot.cpp
View File

@ -284,8 +284,8 @@ WRITE8_MEMBER(scv_cart_slot_device::write_cart)
write_bank
-------------------------------------------------*/
WRITE8_MEMBER(scv_cart_slot_device::write_bank)
void scv_cart_slot_device::write_bank(uint8_t data)
{
if (m_cart)
m_cart->write_bank(space, offset, data);
m_cart->write_bank(data);
}

4
src/devices/bus/scv/slot.h
View File

@ -37,7 +37,7 @@ public:
// reading and writing
virtual DECLARE_READ8_MEMBER(read_cart) { return 0xff; }
virtual DECLARE_WRITE8_MEMBER(write_cart) { }
virtual DECLARE_WRITE8_MEMBER(write_bank) { }
virtual void write_bank(uint8_t data) { }
void rom_alloc(uint32_t size, const char *tag);
void ram_alloc(uint32_t size);
@ -103,7 +103,7 @@ public:
// reading and writing
virtual DECLARE_READ8_MEMBER(read_cart);
virtual DECLARE_WRITE8_MEMBER(write_cart);
virtual DECLARE_WRITE8_MEMBER(write_bank);
virtual void write_bank(uint8_t data);
protected:
// device-level overrides

8
src/devices/bus/ti99/peb/tn_ide.cpp
View File

@ -252,9 +252,9 @@ READ8Z_MEMBER(nouspikel_ide_card_device::readz)
if (first && ((offset & 0x0010)==0))
{
if (cs1fx)
atavalue = m_ata->read_cs0(reg);
atavalue = m_ata->cs0_r(reg);
else
atavalue = m_ata->read_cs1(reg);
atavalue = m_ata->cs1_r(reg);
LOGMASKED(LOG_ATA, "%s %02x -> %04x\n", cs1fx? "cs1" : "cs3", reg, atavalue);
}
@ -420,9 +420,9 @@ void nouspikel_ide_card_device::write(offs_t offset, uint8_t data)
LOGMASKED(LOG_ATA, "%s %02x <- %04x\n", cs1fx? "cs1" : "cs3", reg, atavalue);
if (cs1fx)
m_ata->write_cs0(reg, atavalue);
m_ata->cs0_w(reg, atavalue);
else
m_ata->write_cs1(reg, atavalue);
m_ata->cs1_w(reg, atavalue);
}
}
}

2
src/devices/cpu/clipper/clipper.cpp
View File

@ -333,7 +333,7 @@ bool clipper_device::memory_translate(int spacenum, int intention, offs_t &addre
return ((intention & TRANSLATE_TYPE_MASK) == TRANSLATE_FETCH ? get_icammu() : get_dcammu()).memory_translate(m_ssw, spacenum, intention, address);
}
WRITE16_MEMBER(clipper_device::set_exception)
void clipper_device::set_exception(u16 data)
{
LOGMASKED(LOG_EXCEPTION, "external exception 0x%04x triggered\n", data);

4
src/devices/cpu/clipper/clipper.h
View File

@ -18,8 +18,8 @@
class clipper_device : public cpu_device
{
public:
DECLARE_WRITE8_MEMBER(set_ivec) { m_ivec = data; }
DECLARE_WRITE16_MEMBER(set_exception);
void set_ivec(u8 data) { m_ivec = data; }
void set_exception(u16 data);
// branch conditions (first description for comparison, second for move/logical)
enum branch_conditions : u8

1
src/devices/cpu/i8085/i8085.cpp
View File

@ -878,7 +878,6 @@ void i8085a_cpu_device::execute_run()
check_for_interrupts();
m_in_acknowledge = false;
logerror("PC=%04X\n", m_PC.d);
debugger_instruction_hook(m_PC.d);
/* here we go... */

1
src/devices/cpu/i86/i186.cpp
View File

@ -677,6 +677,7 @@ void i80186_cpu_device::device_start()
memset(&m_intr, 0, sizeof(intr_state));
memset(&m_mem, 0, sizeof(mem_state));
m_reloc = 0;
m_last_dma = 0;
m_timer[0].int_timer = timer_alloc(TIMER_INT0);
m_timer[1].int_timer = timer_alloc(TIMER_INT1);

579
src/devices/cpu/jaguar/jaguar.cpp
View File

@ -10,7 +10,9 @@
- Implement pipeline, actually instruction cycles;
Currently implementation is similar to single stepping
with single cycle
- Implement and acknowlodge remain registers
- Implement and acknowlodge remain registers;
- Improve delay slot display in debugger (highlight current instruction
doesn't work but instruction hook does);
***************************************************************************/
@ -53,13 +55,13 @@ enum : u32
CINT5FLAG = 0x20000 // DSP only
};
inline void jaguar_cpu_device::CLR_Z() { m_ctrl[G_FLAGS] &= ~ZFLAG; }
inline void jaguar_cpu_device::CLR_ZN() { m_ctrl[G_FLAGS] &= ~(ZFLAG | NFLAG); }
inline void jaguar_cpu_device::CLR_ZNC() { m_ctrl[G_FLAGS] &= ~(CFLAG | ZFLAG | NFLAG); }
inline void jaguar_cpu_device::SET_Z(u32 r) { m_ctrl[G_FLAGS] |= (r == 0); }
inline void jaguar_cpu_device::SET_C_ADD(u32 a, u32 b) { m_ctrl[G_FLAGS] |= (b > (~a)) << 1; }
inline void jaguar_cpu_device::SET_C_SUB(u32 a, u32 b) { m_ctrl[G_FLAGS] |= (b > a) << 1; }
inline void jaguar_cpu_device::SET_N(u32 r) { m_ctrl[G_FLAGS] |= ((r >> 29) & 4); }
inline void jaguar_cpu_device::CLR_Z() { m_flags &= ~ZFLAG; }
inline void jaguar_cpu_device::CLR_ZN() { m_flags &= ~(ZFLAG | NFLAG); }
inline void jaguar_cpu_device::CLR_ZNC() { m_flags &= ~(CFLAG | ZFLAG | NFLAG); }
inline void jaguar_cpu_device::SET_Z(u32 r) { m_flags |= (r == 0); }
inline void jaguar_cpu_device::SET_C_ADD(u32 a, u32 b) { m_flags |= (b > (~a)) << 1; }
inline void jaguar_cpu_device::SET_C_SUB(u32 a, u32 b) { m_flags |= (b > a) << 1; }
inline void jaguar_cpu_device::SET_N(u32 r) { m_flags |= ((r >> 29) & 4); }
inline void jaguar_cpu_device::SET_ZN(u32 r) { SET_N(r); SET_Z(r); }
inline void jaguar_cpu_device::SET_ZNC_ADD(u32 a, u32 b, u32 r) { SET_N(r); SET_Z(r); SET_C_ADD(a, b); }
inline void jaguar_cpu_device::SET_ZNC_SUB(u32 a, u32 b, u32 r) { SET_N(r); SET_Z(r); SET_C_SUB(a, b); }
@ -69,12 +71,9 @@ inline void jaguar_cpu_device::SET_ZNC_SUB(u32 a, u32 b, u32 r) { SET_N(r); SET_
MACROS
***************************************************************************/
#define PC m_ctrl[G_PC]
#define FLAGS m_ctrl[G_FLAGS]
inline u8 jaguar_cpu_device::CONDITION(u8 x)
{
return condition_table[x + ((m_ctrl[G_FLAGS] & 7) << 5)];
return condition_table[x + ((m_flags & 7) << 5)];
}
inline u8 jaguar_cpu_device::READBYTE(offs_t a) { return m_program->read_byte(a); }
@ -151,15 +150,33 @@ DEFINE_DEVICE_TYPE(JAGUARGPU, jaguargpu_cpu_device, "jaguargpu", "Motorola Atari
DEFINE_DEVICE_TYPE(JAGUARDSP, jaguardsp_cpu_device, "jaguardsp", "Motorola Atari Jaguar DSP \"Jerry\"")
jaguar_cpu_device::jaguar_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, u8 version, bool isdsp)
jaguar_cpu_device::jaguar_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, u8 version, bool isdsp, address_map_constructor io_map)
: cpu_device(mconfig, type, tag, owner, clock)
, m_program_config("program", ENDIANNESS_BIG, 32, 24, 0)
, m_io_config("io", ENDIANNESS_BIG, 32, 8, 0, io_map)
, m_version(version) // 1 : Jaguar prototype, 2 : Jaguar first release, 3 : Midsummer prototype, Other : unknown/reserved
, m_isdsp(isdsp)
, m_cpu_interrupt(*this)
, m_tables_referenced(false)
, table_refcount(0)
, m_table(isdsp ? dsp_op_table : gpu_op_table)
, m_io_end(0x00070007)
, m_io_pc(0)
, m_io_status(0)
, m_pc(0)
, m_flags(0)
, m_imask(false)
, m_maddw(0)
, m_mwidth(0)
, m_mtxaddr(0)
, m_go(false)
, m_int_latch(0)
, m_int_mask(0)
, m_bus_hog(false)
, m_div_remainder(0)
, m_div_offset(false)
, m_hidata(0)
, m_modulo(0xffffffff)
{
if (isdsp)
{
@ -175,20 +192,21 @@ jaguar_cpu_device::jaguar_cpu_device(const machine_config &mconfig, device_type
jaguargpu_cpu_device::jaguargpu_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
: jaguar_cpu_device(mconfig, JAGUARGPU, tag, owner, clock, 2, false)
: jaguar_cpu_device(mconfig, JAGUARGPU, tag, owner, clock, 2, false, address_map_constructor(FUNC(jaguargpu_cpu_device::io_map), this))
{
}
jaguardsp_cpu_device::jaguardsp_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
: jaguar_cpu_device(mconfig, JAGUARDSP, tag, owner, clock, 2, true)
: jaguar_cpu_device(mconfig, JAGUARDSP, tag, owner, clock, 2, true, address_map_constructor(FUNC(jaguardsp_cpu_device::io_map), this))
{
}
device_memory_interface::space_config_vector jaguar_cpu_device::memory_space_config() const
{
return space_config_vector {
std::make_pair(AS_PROGRAM, &m_program_config)
std::make_pair(AS_PROGRAM, &m_program_config),
std::make_pair(AS_IO, &m_io_config)
};
}
@ -196,8 +214,8 @@ device_memory_interface::space_config_vector jaguar_cpu_device::memory_space_con
void jaguar_cpu_device::update_register_banks()
{
/* pick the bank */
u32 bank = FLAGS & RPAGEFLAG;
if (FLAGS & IFLAG) bank = 0;
u32 bank = m_flags & RPAGEFLAG;
if (m_imask == true) bank = 0;
/* do we need to swap? */
if ((bank == 0 && m_b0 != m_r) || (bank != 0 && m_b1 != m_r))
@ -237,51 +255,43 @@ void jaguar_cpu_device::check_irqs()
int which = 0;
/* if the IMASK is set, bail */
if (FLAGS & IFLAG)
if (m_imask == true)
return;
/* get the active interrupt bits */
u8 bits = (m_ctrl[G_CTRL] >> 6) & 0x1f;
bits |= (m_ctrl[G_CTRL] >> 10) & 0x20;
/* get the interrupt mask */
u8 mask = (FLAGS >> 4) & 0x1f;
mask |= (FLAGS >> 11) & 0x20;
u8 latch = m_int_latch;
u8 mask = m_int_mask;
/* bail if nothing is available */
bits &= mask;
if (bits == 0)
latch &= mask;
if (latch == 0)
return;
/* determine which interrupt */
if (bits & 0x01) which = 0;
if (bits & 0x02) which = 1;
if (bits & 0x04) which = 2;
if (bits & 0x08) which = 3;
if (bits & 0x10) which = 4;
if (bits & 0x20) which = 5;
for (int i = 0; i < 6; i++)
if (latch & (1 << i))
which = i;
/* set the interrupt flag */
FLAGS |= IFLAG;
m_imask = true;
update_register_banks();
/* push the PC-2 on the stack */
/* push the m_pc-2 on the stack */
m_r[31] -= 4;
WRITELONG(m_r[31], PC - 2);
WRITELONG(m_r[31], m_pc - 2);
/* dispatch */
PC = (m_isdsp) ? 0xf1b000 : 0xf03000;
PC += which * 0x10;
m_pc = m_internal_ram_start;
m_pc += which * 0x10;
}
void jaguar_cpu_device::execute_set_input(int irqline, int state)
{
const u32 mask = (irqline < 5) ? (0x40 << irqline) : 0x10000;
m_ctrl[G_CTRL] &= ~mask;
const u32 mask = (1 << irqline);
m_int_latch &= ~mask;
if (state != CLEAR_LINE)
{
m_ctrl[G_CTRL] |= mask;
m_int_latch |= mask;
check_irqs();
}
}
@ -346,14 +356,29 @@ void jaguar_cpu_device::device_start()
init_tables();
m_program = &space(AS_PROGRAM);
m_io = &space(AS_IO);
m_cache = m_program->cache<2, 0, ENDIANNESS_BIG>();
m_cpu_interrupt.resolve_safe();
save_item(NAME(m_r));
save_item(NAME(m_a));
save_item(NAME(m_ctrl));
save_item(NAME(m_ppc));
save_item(NAME(m_go));
save_item(NAME(m_int_latch));
save_item(NAME(m_int_mask));
save_item(NAME(m_bus_hog));
save_item(NAME(m_flags));
save_item(NAME(m_imask));
save_item(NAME(m_div_remainder));
save_item(NAME(m_div_offset));
save_item(NAME(m_io_end));
save_item(NAME(m_io_pc));
save_item(NAME(m_io_status));
save_item(NAME(m_io_mtxc));
save_item(NAME(m_io_mtxa));
// TODO: data map
if (m_isdsp)
{
m_internal_ram_start = 0xf1b000;
@ -367,13 +392,12 @@ void jaguar_cpu_device::device_start()
std::fill(std::begin(m_r), std::end(m_r), 0);
std::fill(std::begin(m_a), std::end(m_a), 0);
std::fill(std::begin(m_ctrl), std::end(m_ctrl), 0);
m_ppc = 0;
m_accum = 0;
m_bankswitch_icount = 0;
state_add( JAGUAR_PC, "PC", PC).formatstr("%08X");
state_add( JAGUAR_FLAGS, "FLAGS", FLAGS).formatstr("%08X");
state_add( JAGUAR_PC, "PC", m_pc).formatstr("%08X");
state_add( JAGUAR_FLAGS, "FLAGS", m_flags).formatstr("%08X");
state_add( JAGUAR_R0, "R0", m_r[0]).formatstr("%08X");
state_add( JAGUAR_R1, "R1", m_r[1]).formatstr("%08X");
state_add( JAGUAR_R2, "R2", m_r[2]).formatstr("%08X");
@ -407,9 +431,9 @@ void jaguar_cpu_device::device_start()
state_add( JAGUAR_R30, "R30", m_r[30]).formatstr("%08X");
state_add( JAGUAR_R31, "R31", m_r[31]).formatstr("%08X");
state_add( STATE_GENPC, "GENPC", PC).noshow();
state_add( STATE_GENPC, "GENPC", m_pc).noshow();
state_add( STATE_GENPCBASE, "CURPC", m_ppc).noshow();
state_add( STATE_GENFLAGS, "GENFLAGS", FLAGS).formatstr("%11s").noshow();
state_add( STATE_GENFLAGS, "GENFLAGS", m_flags).formatstr("%11s").noshow();
set_icountptr(m_icount);
}
@ -421,17 +445,17 @@ void jaguar_cpu_device::state_string_export(const device_state_entry &entry, std
{
case STATE_GENFLAGS:
str = string_format("%c%c%c%c%c%c%c%c%c%c%c",
FLAGS & 0x8000 ? 'D':'.',
FLAGS & 0x4000 ? 'A':'.',
FLAGS & 0x0100 ? '4':'.',
FLAGS & 0x0080 ? '3':'.',
FLAGS & 0x0040 ? '2':'.',
FLAGS & 0x0020 ? '1':'.',
FLAGS & 0x0010 ? '0':'.',
FLAGS & 0x0008 ? 'I':'.',
FLAGS & 0x0004 ? 'N':'.',
FLAGS & 0x0002 ? 'C':'.',
FLAGS & 0x0001 ? 'Z':'.');
m_flags & 0x8000 ? 'D':'.',
m_flags & 0x4000 ? 'A':'.',
m_flags & 0x0100 ? '4':'.',
m_flags & 0x0080 ? '3':'.',
m_flags & 0x0040 ? '2':'.',
m_flags & 0x0020 ? '1':'.',
m_flags & 0x0010 ? '0':'.',
m_imask == true ? 'I':'.',
m_flags & 0x0004 ? 'N':'.',
m_flags & 0x0002 ? 'C':'.',
m_flags & 0x0001 ? 'Z':'.');
break;
}
}
@ -441,6 +465,7 @@ void jaguar_cpu_device::device_reset()
{
m_b0 = m_r;
m_b1 = m_a;
m_modulo = 0xffffffff;
}
@ -464,7 +489,7 @@ jaguar_cpu_device::~jaguar_cpu_device()
void jaguargpu_cpu_device::execute_run()
{
/* if we're halted, we shouldn't be here */
if (!(m_ctrl[G_CTRL] & 1))
if (m_go == false)
{
//device->execute().set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
m_icount = 0;
@ -481,13 +506,13 @@ void jaguargpu_cpu_device::execute_run()
do
{
/* debugging */
//if ((m_version < 3) && (PC < 0xf03000 || PC > 0xf04000)) { fatalerror("GPU: PC = %06X (ppc = %06X)\n", PC, m_ppc); }
m_ppc = PC;
debugger_instruction_hook(PC);
//if ((m_version < 3) && (m_pc < 0xf03000 || m_pc > 0xf04000)) { fatalerror("GPU: m_pc = %06X (ppc = %06X)\n", m_pc, m_ppc); }
m_ppc = m_pc;
debugger_instruction_hook(m_pc);
/* instruction fetch */
const u16 op = ROPCODE(PC);
PC += 2;
const u16 op = ROPCODE(m_pc);
m_pc += 2;
/* parse the instruction */
(this->*gpu_op_table[op >> 10])(op);
@ -499,7 +524,7 @@ void jaguargpu_cpu_device::execute_run()
void jaguardsp_cpu_device::execute_run()
{
/* if we're halted, we shouldn't be here */
if (!(m_ctrl[G_CTRL] & 1))
if (m_go == false)
{
//device->execute().set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
m_icount = 0;
@ -516,13 +541,13 @@ void jaguardsp_cpu_device::execute_run()
do
{
/* debugging */
//if (PC < 0xf1b000 || PC > 0xf1d000) { fatalerror(stderr, "DSP: PC = %06X\n", PC); }
m_ppc = PC;
debugger_instruction_hook(PC);
//if (m_pc < 0xf1b000 || m_pc > 0xf1d000) { fatalerror(stderr, "DSP: m_pc = %06X\n", m_pc); }
m_ppc = m_pc;
debugger_instruction_hook(m_pc);
/* instruction fetch */
const u16 op = ROPCODE(PC);
PC += 2;
const u16 op = ROPCODE(m_pc);
m_pc += 2;
/* parse the instruction */
(this->*dsp_op_table[op >> 10])(op);
@ -544,7 +569,7 @@ void jaguar_cpu_device::abs_rn(u16 op)
if (res & 0x80000000)
{
m_r[dreg] = res = -res;
FLAGS |= CFLAG;
m_flags |= CFLAG;
}
SET_Z(res);
}
@ -564,7 +589,7 @@ void jaguar_cpu_device::addc_rn_rn(u16 op)
const u8 dreg = op & 31;
const u32 r1 = m_r[(op >> 5) & 31];
const u32 r2 = m_r[dreg];
u32 c = ((FLAGS >> 1) & 1);
u32 c = ((m_flags >> 1) & 1);
const u32 res = r2 + r1 + c;
m_r[dreg] = res;
CLR_ZNC(); SET_ZNC_ADD(r2, r1 + c, res);
@ -586,7 +611,7 @@ void jaguar_cpu_device::addqmod_n_rn(u16 op) /* DSP only */
const u32 r1 = convert_zero[(op >> 5) & 31];
const u32 r2 = m_r[dreg];
u32 res = r2 + r1;
res = (res & ~m_ctrl[D_MOD]) | (r2 & ~m_ctrl[D_MOD]);
res = (res & ~m_modulo) | (r2 & m_modulo);
m_r[dreg] = res;
CLR_ZNC(); SET_ZNC_ADD(r2, r1, res);
}
@ -634,7 +659,7 @@ void jaguar_cpu_device::btst_n_rn(u16 op)
{
const u32 r1 = (op >> 5) & 31;
const u32 r2 = m_r[op & 31];
CLR_Z(); FLAGS |= (~r2 >> r1) & 1;
CLR_Z(); m_flags |= (~r2 >> r1) & 1;
}
void jaguar_cpu_device::cmp_rn_rn(u16 op)
@ -660,19 +685,23 @@ void jaguar_cpu_device::div_rn_rn(u16 op)
const u32 r2 = m_r[dreg];
if (r1)
{
if (m_ctrl[D_DIVCTRL] & 1)
if (m_div_offset & 1)
{
m_r[dreg] = ((u64)r2 << 16) / r1;
m_ctrl[D_REMAINDER] = ((u64)r2 << 16) % r1;
m_div_remainder = ((u64)r2 << 16) % r1;
}
else
{
m_r[dreg] = r2 / r1;
m_ctrl[D_REMAINDER] = r2 % r1;
m_div_remainder = r2 % r1;
}
}
else
{
// TODO: exact values for divide by zero
m_r[dreg] = 0xffffffff;
m_div_remainder = 0xffffffff;
}
}
void jaguar_cpu_device::illegal(u16 op)
@ -684,6 +713,7 @@ void jaguar_cpu_device::imacn_rn_rn(u16 op)
const u32 r1 = m_r[(op >> 5) & 31];
const u32 r2 = m_r[op & 31];
m_accum += (s64)((int16_t)r1 * (int16_t)r2);
// TODO: what's really "unexpected"?
logerror("Unexpected IMACN instruction!\n");
}
@ -706,18 +736,18 @@ void jaguar_cpu_device::imultn_rn_rn(u16 op)
m_accum = (s32)res;
CLR_ZN(); SET_ZN(res);
op = ROPCODE(PC);
op = ROPCODE(m_pc);
while ((op >> 10) == 20)
{
r1 = m_r[(op >> 5) & 31];
r2 = m_r[op & 31];
m_accum += (s64)((int16_t)r1 * (int16_t)r2);
PC += 2;
op = ROPCODE(PC);
m_pc += 2;
op = ROPCODE(m_pc);
}
if ((op >> 10) == 19)
{
PC += 2;
m_pc += 2;
m_r[op & 31] = (u32)m_accum;
}
}
@ -727,10 +757,10 @@ void jaguar_cpu_device::jr_cc_n(u16 op)
if (CONDITION(op & 31))
{
const s32 r1 = (s8)((op >> 2) & 0xf8) >> 2;
const u32 newpc = PC + r1;
debugger_instruction_hook(PC);
op = ROPCODE(PC);
PC = newpc;
const u32 newpc = m_pc + r1;
debugger_instruction_hook(m_pc);
op = ROPCODE(m_pc);
m_pc = newpc;
(this->*m_table[op >> 10])(op);
m_icount -= 3; /* 3 wait states guaranteed */
@ -745,9 +775,9 @@ void jaguar_cpu_device::jump_cc_rn(u16 op)
/* special kludge for risky code in the cojag DSP interrupt handlers */
const u32 newpc = (m_icount == m_bankswitch_icount) ? m_a[reg] : m_r[reg];
debugger_instruction_hook(PC);
op = ROPCODE(PC);
PC = newpc;
debugger_instruction_hook(m_pc);
op = ROPCODE(m_pc);
m_pc = newpc;
(this->*m_table[op >> 10])(op);
m_icount -= 3; /* 3 wait states guaranteed */
@ -819,7 +849,7 @@ void jaguar_cpu_device::loadp_rn_rn(u16 op) /* GPU only */
}
else
{
m_ctrl[G_HIDATA] = READLONG(r1);
m_hidata = READLONG(r1);
m_r[op & 31] = READLONG(r1+4);
}
}
@ -835,13 +865,13 @@ void jaguar_cpu_device::mirror_rn(u16 op) /* DSP only */
void jaguar_cpu_device::mmult_rn_rn(u16 op)
{
const u8 count = m_ctrl[G_MTXC] & 15;
const u8 count = m_mwidth;
const u8 sreg = (op >> 5) & 31;
const u8 dreg = op & 31;
u32 addr = m_ctrl[G_MTXA];
u32 addr = m_mtxaddr;
s64 accum = 0;
if (!(m_ctrl[G_MTXC] & 0x10))
if (m_maddw == false)
{
for (int i = 0; i < count; i++)
{
@ -879,8 +909,8 @@ void jaguar_cpu_device::movefa_rn_rn(u16 op)
void jaguar_cpu_device::movei_n_rn(u16 op)
{
const u32 res = ROPCODE(PC) | (ROPCODE(PC + 2) << 16);
PC += 4;
const u32 res = ROPCODE(m_pc) | (ROPCODE(m_pc + 2) << 16);
m_pc += 4;
m_r[op & 31] = res;
}
@ -987,7 +1017,7 @@ void jaguar_cpu_device::ror_rn_rn(u16 op)
const u32 r2 = m_r[dreg];
const u32 res = (r2 >> r1) | (r2 << (32 - r1));
m_r[dreg] = res;
CLR_ZNC(); SET_ZN(res); FLAGS |= (r2 >> 30) & 2;
CLR_ZNC(); SET_ZN(res); m_flags |= (r2 >> 30) & 2;
}
void jaguar_cpu_device::rorq_n_rn(u16 op)
@ -997,7 +1027,7 @@ void jaguar_cpu_device::rorq_n_rn(u16 op)
const u32 r2 = m_r[dreg];
const u32 res = (r2 >> r1) | (r2 << (32 - r1));
m_r[dreg] = res;
CLR_ZNC(); SET_ZN(res); FLAGS |= (r2 >> 30) & 2;
CLR_ZNC(); SET_ZN(res); m_flags |= (r2 >> 30) & 2;
}
void jaguar_cpu_device::sat8_rn(u16 op) /* GPU only */
@ -1057,12 +1087,12 @@ void jaguar_cpu_device::sh_rn_rn(u16 op)
if (r1 < 0)
{
res = (r1 <= -32) ? 0 : (r2 << -r1);
FLAGS |= (r2 >> 30) & 2;
m_flags |= (r2 >> 30) & 2;
}
else
{
res = (r1 >= 32) ? 0 : (r2 >> r1);
FLAGS |= (r2 << 1) & 2;
m_flags |= (r2 << 1) & 2;
}
m_r[dreg] = res;
SET_ZN(res);
@ -1079,12 +1109,12 @@ void jaguar_cpu_device::sha_rn_rn(u16 op)
if (r1 < 0)
{
res = (r1 <= -32) ? 0 : (r2 << -r1);
FLAGS |= (r2 >> 30) & 2;
m_flags |= (r2 >> 30) & 2;
}
else
{
res = (r1 >= 32) ? ((s32)r2 >> 31) : ((s32)r2 >> r1);
FLAGS |= (r2 << 1) & 2;
m_flags |= (r2 << 1) & 2;
}
m_r[dreg] = res;
SET_ZN(res);
@ -1097,7 +1127,7 @@ void jaguar_cpu_device::sharq_n_rn(u16 op)
const u32 r2 = m_r[dreg];
const u32 res = (s32)r2 >> r1;
m_r[dreg] = res;
CLR_ZNC(); SET_ZN(res); FLAGS |= (r2 << 1) & 2;
CLR_ZNC(); SET_ZN(res); m_flags |= (r2 << 1) & 2;
}
void jaguar_cpu_device::shlq_n_rn(u16 op)
@ -1107,7 +1137,7 @@ void jaguar_cpu_device::shlq_n_rn(u16 op)
const u32 r2 = m_r[dreg];
const u32 res = r2 << (32 - r1);
m_r[dreg] = res;
CLR_ZNC(); SET_ZN(res); FLAGS |= (r2 >> 30) & 2;
CLR_ZNC(); SET_ZN(res); m_flags |= (r2 >> 30) & 2;
}
void jaguar_cpu_device::shrq_n_rn(u16 op)
@ -1117,7 +1147,7 @@ void jaguar_cpu_device::shrq_n_rn(u16 op)
const u32 r2 = m_r[dreg];
const u32 res = r2 >> r1;
m_r[dreg] = res;
CLR_ZNC(); SET_ZN(res); FLAGS |= (r2 << 1) & 2;
CLR_ZNC(); SET_ZN(res); m_flags |= (r2 << 1) & 2;
}
void jaguar_cpu_device::store_rn_rn(u16 op)
@ -1185,7 +1215,7 @@ void jaguar_cpu_device::storep_rn_rn(u16 op) /* GPU only */
}
else
{
WRITELONG(r1, m_ctrl[G_HIDATA]);
WRITELONG(r1, m_hidata);
WRITELONG(r1+4, m_r[op & 31]);
}
}
@ -1205,7 +1235,7 @@ void jaguar_cpu_device::subc_rn_rn(u16 op)
const u8 dreg = op & 31;
const u32 r1 = m_r[(op >> 5) & 31];
const u32 r2 = m_r[dreg];
u32 c = ((FLAGS >> 1) & 1);
u32 c = ((m_flags >> 1) & 1);
const u32 res = r2 - r1 - c;
m_r[dreg] = res;
CLR_ZNC(); SET_ZNC_SUB(r2, r1 + c, res);
@ -1227,7 +1257,7 @@ void jaguar_cpu_device::subqmod_n_rn(u16 op) /* DSP only */
const u32 r1 = convert_zero[(op >> 5) & 31];
const u32 r2 = m_r[dreg];
u32 res = r2 - r1;
res = (res & ~m_ctrl[D_MOD]) | (r2 & ~m_ctrl[D_MOD]);
res = (res & ~m_modulo) | (r2 & m_modulo);
m_r[dreg] = res;
CLR_ZNC(); SET_ZNC_SUB(r2, r1, res);
}
@ -1257,191 +1287,212 @@ void jaguar_cpu_device::xor_rn_rn(u16 op)
I/O HANDLING
***************************************************************************/
u32 jaguargpu_cpu_device::ctrl_r(offs_t offset)
void jaguar_cpu_device::io_common_map(address_map &map)
{
if (LOG_GPU_IO) logerror("GPU read register @ F021%02X\n", offset * 4);
u32 res = m_ctrl[offset];
if (offset == G_CTRL)
res |= (m_version & 0xf) << 12;
return res;
map(0x00, 0x03).rw(FUNC(jaguar_cpu_device::flags_r), FUNC(jaguar_cpu_device::flags_w));
map(0x04, 0x07).w(FUNC(jaguar_cpu_device::matrix_control_w));
map(0x08, 0x0b).w(FUNC(jaguar_cpu_device::matrix_address_w));
// map(0x0c, 0x0f) endian
map(0x10, 0x13).w(FUNC(jaguar_cpu_device::pc_w));
map(0x14, 0x17).rw(FUNC(jaguar_cpu_device::status_r), FUNC(jaguar_cpu_device::control_w));
// map(0x18, 0x1b) implementation specific
map(0x1c, 0x1f).rw(FUNC(jaguar_cpu_device::div_remainder_r), FUNC(jaguar_cpu_device::div_control_w));
}
void jaguargpu_cpu_device::ctrl_w(offs_t offset, u32 data, u32 mem_mask)
// $f02100
void jaguargpu_cpu_device::io_map(address_map &map)
{
if (LOG_GPU_IO && offset != G_HIDATA)
logerror("GPU write register @ F021%02X = %08X\n", offset * 4, data);
jaguar_cpu_device::io_common_map(map);
map(0x0c, 0x0f).w(FUNC(jaguargpu_cpu_device::end_w));
map(0x18, 0x1b).rw(FUNC(jaguargpu_cpu_device::hidata_r), FUNC(jaguargpu_cpu_device::hidata_w));
}
/* remember the old and set the new */
const u32 oldval = m_ctrl[offset];
u32 newval = oldval;
COMBINE_DATA(&newval);
/* handle the various registers */
switch (offset)
// $f0a100
void jaguardsp_cpu_device::io_map(address_map &map)
{
case G_FLAGS:
jaguar_cpu_device::io_common_map(map);
map(0x0c, 0x0f).w(FUNC(jaguardsp_cpu_device::dsp_end_w));
map(0x18, 0x1b).w(FUNC(jaguardsp_cpu_device::modulo_w));
map(0x20, 0x23).r(FUNC(jaguardsp_cpu_device::high_accum_r));
}
/* combine the data properly */
m_ctrl[offset] = newval & (ZFLAG | CFLAG | NFLAG | EINT04FLAGS | RPAGEFLAG);
if (newval & IFLAG)
m_ctrl[offset] |= oldval & IFLAG;
READ32_MEMBER(jaguar_cpu_device::flags_r)
{
return (m_flags & 0x1c1f7) | (m_imask << 3);
}
/* clear interrupts */
m_ctrl[G_CTRL] &= ~((newval & CINT04FLAGS) >> 3);
WRITE32_MEMBER(jaguar_cpu_device::flags_w)
{
COMBINE_DATA(&m_flags);
// clear imask only on bit 3 clear (1 has no effect)
if ((m_flags & 0x08) == 0)
m_imask = false;
// update int latch & mask
m_int_mask = (m_flags >> 4) & 0x1f;
m_int_latch &= ~((m_flags >> 9) & 0x1f);
// TODO: move to specific handler
if (m_isdsp)
{
m_int_mask |= (BIT(m_flags, 16) << 5);
m_int_latch &= ~(BIT(m_flags, 17) << 5);
}
// TODO: DMAEN (bit 15)
/* determine which register bank should be active */
update_register_banks();
/* update IRQs */
check_irqs();
break;
}
case G_MTXC:
case G_MTXA:
m_ctrl[offset] = newval;
break;
case G_END:
m_ctrl[offset] = newval;
if ((newval & 7) != 7)
logerror("GPU to set to little-endian!\n");
break;
case G_PC:
PC = newval & 0xffffff;
break;
case G_CTRL:
m_ctrl[offset] = newval;
if ((oldval ^ newval) & 0x01)
WRITE32_MEMBER(jaguar_cpu_device::matrix_control_w)
{
set_input_line(INPUT_LINE_HALT, (newval & 1) ? CLEAR_LINE : ASSERT_LINE);
COMBINE_DATA(&m_io_mtxc);
m_mwidth = m_io_mtxc & 0xf;
m_maddw = BIT(m_io_mtxc, 4);
}
WRITE32_MEMBER(jaguar_cpu_device::matrix_address_w)
{
COMBINE_DATA(&m_io_mtxa);
// matrix can be long word address only, and only read from internal RAM
m_mtxaddr = m_internal_ram_start | (m_io_mtxa & 0xffc);
}
WRITE32_MEMBER(jaguar_cpu_device::pc_w)
{
COMBINE_DATA(&m_io_pc);
if (m_go == false)
m_pc = m_io_pc & 0xffffff;
else
throw emu_fatalerror("%s: inflight PC write %08x", this->tag(), m_pc);
}
/*
* Data Organization Register
* Note: The canonical way to set this up from 68k is $00070007,
* so that Power-On endianness doesn't matter. 1=Big Endian
* ---- -x-- Instruction endianness
* ---- --x- Pixel endianness (GPU only)
* ---- ---x I/O endianness
*/
// TODO: just log if anything farts for now, change to bit struct once we have something to test out
WRITE32_MEMBER(jaguar_cpu_device::end_w)
{
COMBINE_DATA(&m_io_end);
// sburnout sets bit 1 == 0
if ((m_io_end & 0x7) != 0x7)
throw emu_fatalerror("%s: fatal endian setup %08x", this->tag(), m_io_end);
}
WRITE32_MEMBER(jaguardsp_cpu_device::dsp_end_w)
{
COMBINE_DATA(&m_io_end);
// wolfn3d writes a '0' to bit 1 (which is a NOP for DSP)
if ((m_io_end & 0x5) != 0x5)
throw emu_fatalerror("%s: fatal endian setup %08x", this->tag(), m_io_end);
}
/*
* Control/Status Register
* - xxxx ---- ---- ---- chip version number
* - ---- x--- ---- ---- bus hog (increase self chip priority on bus)
* y ---- -xxx xx-- ---- interrupt latch (y is DSP specific) (r/o)
* - ---- ---- --0- ---- <unused>
* - ---- ---- ---x x--- single step regs
* - ---- ---- ---- -x-- GPUINT0 or DSPINT0
* - ---- ---- ---- --x- Host interrupt (w/o)
* - ---- ---- ---- ---x GPUGO or DSPGO flag
*
*/
READ32_MEMBER(jaguar_cpu_device::status_r)
{
u32 result = ((m_version & 0xf)<<12) | (m_bus_hog<<11) | m_go;
result|= (m_int_latch & 0x1f) << 6;
// TODO: make it DSP specific
if (m_isdsp == true)
result|= (m_int_latch & 0x20) << 11;
return result;
}
WRITE_LINE_MEMBER(jaguar_cpu_device::go_w)
{
m_go = state;
set_input_line(INPUT_LINE_HALT, (m_go == true) ? CLEAR_LINE : ASSERT_LINE);
yield();
}
if (newval & 0x02)
WRITE32_MEMBER(jaguar_cpu_device::control_w)
{
COMBINE_DATA(&m_io_status);
bool new_go = BIT(m_io_status, 0);
if (new_go != m_go)
go_w(new_go);
if (BIT(m_io_status, 1))
m_cpu_interrupt(ASSERT_LINE);
m_ctrl[offset] &= ~0x02;
}
if (newval & 0x04)
// TODO: following does nothing if set by itself, or acts as a trap?
if (BIT(m_io_status, 2))
{
m_ctrl[G_CTRL] |= 1 << 6;
m_ctrl[offset] &= ~0x04;
m_int_latch |= 1;
check_irqs();
}
if (newval & 0x18)
// TODO: single step handling
m_bus_hog = BIT(m_io_status, 11);
// TODO: protect/protectse uses this, why?
if (m_bus_hog == true)
logerror("%s: bus hog enabled\n", this->tag());
}
READ32_MEMBER(jaguargpu_cpu_device::hidata_r)
{
logerror("GPU single stepping was enabled!\n");
}
break;
case G_HIDATA:
case G_DIVCTRL:
m_ctrl[offset] = newval;
break;
}
return m_hidata;
}
WRITE32_MEMBER(jaguargpu_cpu_device::hidata_w)
{
COMBINE_DATA(&m_hidata);
}
READ32_MEMBER(jaguar_cpu_device::div_remainder_r)
{
// TODO: truly 32-bit?
return m_div_remainder;
}
WRITE32_MEMBER(jaguar_cpu_device::div_control_w)
{
m_div_offset = BIT(data, 0);
}
WRITE32_MEMBER(jaguardsp_cpu_device::modulo_w)
{
COMBINE_DATA(&m_modulo);
}
READ32_MEMBER(jaguardsp_cpu_device::high_accum_r)
{
printf("%s: high 16-bit accumulator read\n", this->tag());
return (m_accum >> 32) & 0xff;
}
u32 jaguar_cpu_device::iobus_r(offs_t offset, u32 mem_mask)
{
return m_io->read_dword(offset*4, mem_mask);
}
void jaguar_cpu_device::iobus_w(offs_t offset, u32 data, u32 mem_mask)
{
m_io->write_dword(offset*4, data, mem_mask);
}
/***************************************************************************
I/O HANDLING
DASM
***************************************************************************/
u32 jaguardsp_cpu_device::ctrl_r(offs_t offset)
{
if (LOG_DSP_IO && offset != D_FLAGS)
logerror("DSP read register @ F1A1%02X\n", offset * 4);
/* switch to the target context */
u32 res = m_ctrl[offset];
if (offset == D_CTRL)
res |= (m_version & 0xf) << 12;
return res;
}
void jaguardsp_cpu_device::ctrl_w(offs_t offset, u32 data, u32 mem_mask)
{
if (LOG_DSP_IO && offset != D_FLAGS)
logerror("DSP write register @ F1A1%02X = %08X\n", offset * 4, data);
/* remember the old and set the new */
const u32 oldval = m_ctrl[offset];
u32 newval = oldval;
COMBINE_DATA(&newval);
/* handle the various registers */
switch (offset)
{
case D_FLAGS:
/* combine the data properly */
m_ctrl[offset] = newval & (ZFLAG | CFLAG | NFLAG | EINT04FLAGS | EINT5FLAG | RPAGEFLAG);
if (newval & IFLAG)
m_ctrl[offset] |= oldval & IFLAG;
/* clear interrupts */
m_ctrl[D_CTRL] &= ~((newval & CINT04FLAGS) >> 3);
m_ctrl[D_CTRL] &= ~((newval & CINT5FLAG) >> 1);
/* determine which register bank should be active */
update_register_banks();
/* update IRQs */
check_irqs();
break;
case D_MTXC:
case D_MTXA:
m_ctrl[offset] = newval;
break;
case D_END:
m_ctrl[offset] = newval;
if ((newval & 7) != 7)
logerror("DSP to set to little-endian!\n");
break;
case D_PC:
PC = newval & 0xffffff;
break;
case D_CTRL:
m_ctrl[offset] = newval;
if ((oldval ^ newval) & 0x01)
{
set_input_line(INPUT_LINE_HALT, (newval & 1) ? CLEAR_LINE : ASSERT_LINE);
yield();
}
if (newval & 0x02)
{
m_cpu_interrupt(ASSERT_LINE);
m_ctrl[offset] &= ~0x02;
}
if (newval & 0x04)
{
m_ctrl[D_CTRL] |= 1 << 6;
m_ctrl[offset] &= ~0x04;
check_irqs();
}
if (newval & 0x18)
{
logerror("DSP single stepping was enabled!\n");
}
break;
case D_MOD:
case D_DIVCTRL:
m_ctrl[offset] = newval;
break;
}
}
std::unique_ptr<util::disasm_interface> jaguargpu_cpu_device::create_disassembler()
{
return std::make_unique<jaguar_disassembler>(jaguar_disassembler::variant::GPU);

125
src/devices/cpu/jaguar/jaguar.h
View File

@ -28,38 +28,6 @@ enum
JAGUAR_R24,JAGUAR_R25,JAGUAR_R26,JAGUAR_R27,JAGUAR_R28,JAGUAR_R29,JAGUAR_R30,JAGUAR_R31
};
enum
{
G_FLAGS = 0,
G_MTXC,
G_MTXA,
G_END,
G_PC,
G_CTRL,
G_HIDATA,
G_DIVCTRL,
G_DUMMY,
G_REMAINDER,
G_CTRLMAX
};
enum
{
D_FLAGS = 0,
D_MTXC,
D_MTXA,
D_END,
D_PC,
D_CTRL,
D_MOD,
D_DIVCTRL,
D_MACHI,
D_REMAINDER,
D_CTRLMAX
};
/***************************************************************************
INTERRUPT CONSTANTS
***************************************************************************/
@ -90,11 +58,13 @@ public:
// configuration helpers
auto irq() { return m_cpu_interrupt.bind(); }
virtual void ctrl_w(offs_t offset, u32 data, u32 mem_mask = ~0) = 0;
virtual u32 ctrl_r(offs_t offset) = 0;
// TODO: add which device triggered the I/O
void iobus_w(offs_t offset, u32 data, u32 mem_mask = ~0);
u32 iobus_r(offs_t offset, u32 mem_mask = ~0);
DECLARE_WRITE_LINE_MEMBER(go_w);
protected:
jaguar_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, u8 version, bool isdsp);
jaguar_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, u8 version, bool isdsp, address_map_constructor io_map);
// device-level overrides
virtual void device_start() override;
@ -113,6 +83,18 @@ protected:
// device_state_interface overrides
virtual void state_string_export(const device_state_entry &entry, std::string &str) const override;
// I/Os (common)
DECLARE_READ32_MEMBER(flags_r);
DECLARE_WRITE32_MEMBER(flags_w);
DECLARE_WRITE32_MEMBER(matrix_control_w);
DECLARE_WRITE32_MEMBER(matrix_address_w);
DECLARE_WRITE32_MEMBER(end_w);
DECLARE_WRITE32_MEMBER(pc_w);
DECLARE_READ32_MEMBER(status_r);
DECLARE_WRITE32_MEMBER(control_w);
DECLARE_READ32_MEMBER(div_remainder_r);
DECLARE_WRITE32_MEMBER(div_control_w);
// defines
inline void CLR_Z();
inline void CLR_ZN();
@ -138,6 +120,7 @@ protected:
inline u16 ROPCODE(offs_t pc);
address_space_config m_program_config;
address_space_config m_io_config;
/* core registers */
u32 m_r[32];
@ -146,7 +129,6 @@ protected:
u32 * m_b1;
/* control registers */
u32 m_ctrl[G_CTRLMAX];
u32 m_ppc;
u64 m_accum;
@ -157,6 +139,7 @@ protected:
int m_bankswitch_icount;
devcb_write_line m_cpu_interrupt;
address_space *m_program;
address_space *m_io;
memory_access_cache<2, 0, ENDIANNESS_BIG> *m_cache;
u32 m_internal_ram_start;
@ -164,8 +147,6 @@ protected:
typedef void (jaguar_cpu_device::*op_func)(u16 op);
static const op_func gpu_op_table[64];
static const op_func dsp_op_table[64];
static const u32 convert_zero[32];
bool m_tables_referenced;
@ -179,7 +160,6 @@ protected:
void add_rn_rn(u16 op);
void addc_rn_rn(u16 op);
void addq_n_rn(u16 op);
void addqmod_n_rn(u16 op); /* DSP only */
void addqt_n_rn(u16 op);
void and_rn_rn(u16 op);
void bclr_n_rn(u16 op);
@ -201,8 +181,6 @@ protected:
void load_r15rn_rn(u16 op);
void loadb_rn_rn(u16 op);
void loadw_rn_rn(u16 op);
void loadp_rn_rn(u16 op); /* GPU only */
void mirror_rn(u16 op); /* DSP only */
void mmult_rn_rn(u16 op);
void move_rn_rn(u16 op);
void move_pc_rn(u16 op);
@ -217,15 +195,10 @@ protected:
void normi_rn_rn(u16 op);
void not_rn(u16 op);
void or_rn_rn(u16 op);
void pack_rn(u16 op); /* GPU only */
void resmac_rn(u16 op);
void ror_rn_rn(u16 op);
void rorq_n_rn(u16 op);
void sat8_rn(u16 op); /* GPU only */
void sat16_rn(u16 op); /* GPU only */
void sat16s_rn(u16 op); /* DSP only */
void sat24_rn(u16 op); /* GPU only */
void sat32s_rn(u16 op); /* DSP only */
void sh_rn_rn(u16 op);
void sha_rn_rn(u16 op);
void sharq_n_rn(u16 op);
@ -238,16 +211,58 @@ protected:
void store_rn_r15rn(u16 op);
void storeb_rn_rn(u16 op);
void storew_rn_rn(u16 op);
void storep_rn_rn(u16 op); /* GPU only */
void sub_rn_rn(u16 op);
void subc_rn_rn(u16 op);
void subq_n_rn(u16 op);
void subqmod_n_rn(u16 op); /* DSP only */
void subqt_n_rn(u16 op);
void xor_rn_rn(u16 op);
// GPU only opcodes
void loadp_rn_rn(u16 op);
void pack_rn(u16 op);
void sat8_rn(u16 op);
void sat16_rn(u16 op);
void sat24_rn(u16 op);
void storep_rn_rn(u16 op);
// DSP only opcodes
void addqmod_n_rn(u16 op);
void mirror_rn(u16 op);
void sat16s_rn(u16 op);
void sat32s_rn(u16 op);
void subqmod_n_rn(u16 op);
void update_register_banks();
void check_irqs();
void init_tables();
// I/O internal regs
void io_common_map(address_map &map);
// TODO: the m_io* stubs are conventionally given for allowing a correct register setup from vanilla 68k.
// This is yet another reason about needing a bus device dispatcher for this system.
u32 m_io_end;
u32 m_io_pc;
u32 m_io_status;
u32 m_io_mtxc;
u32 m_io_mtxa;
u32 m_pc;
u32 m_flags;
bool m_imask;
bool m_maddw;
u8 m_mwidth;
u32 m_mtxaddr;
bool m_go;
u8 m_int_latch;
u8 m_int_mask;
bool m_bus_hog;
u32 m_div_remainder;
bool m_div_offset;
// GPU specific
u32 m_hidata;
static const op_func gpu_op_table[64];
// DSP specific
u32 m_modulo;
static const op_func dsp_op_table[64];
};
@ -257,12 +272,14 @@ public:
// construction/destruction
jaguargpu_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
void ctrl_w(offs_t offset, u32 data, u32 mem_mask = ~0) override;
u32 ctrl_r(offs_t offset) override;
void io_map(address_map &map);
protected:
virtual void execute_run() override;
virtual std::unique_ptr<util::disasm_interface> create_disassembler() override;
DECLARE_WRITE32_MEMBER(hidata_w);
DECLARE_READ32_MEMBER(hidata_r);
};
@ -272,14 +289,16 @@ public:
// construction/destruction
jaguardsp_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
void ctrl_w(offs_t offset, u32 data, u32 mem_mask = ~0) override;
u32 ctrl_r(offs_t offset) override;
void io_map(address_map &map);
protected:
virtual u32 execute_input_lines() const noexcept override { return 6; }
virtual void execute_run() override;
virtual std::unique_ptr<util::disasm_interface> create_disassembler() override;
DECLARE_WRITE32_MEMBER(modulo_w);
DECLARE_WRITE32_MEMBER(dsp_end_w);
DECLARE_READ32_MEMBER(high_accum_r);
};

110
src/devices/cpu/m37710/m37710.cpp
View File

@ -644,14 +644,14 @@ uint16_t m37710_cpu_device::ad_result_r(offs_t offset)
{
uint16_t result = m_ad_result[offset];
LOGMASKED(LOG_AD, "ad_result_r from %02x: A/D %d = %x (PC=%x)\n", (int)(offset * 2) + 0x20, offset, result, REG_PB<<16 | REG_PC);
LOGMASKED(LOG_AD, "ad_result_r from %02x: A/D %d = %x (PC=%x)\n", (int)(offset * 2) + 0x20, offset, result, REG_PG | REG_PC);
return result;
}
uint8_t m37710_cpu_device::uart0_mode_r()
{
LOGMASKED(LOG_UART, "uart0_mode_r: UART0 transmit/recv mode = %x (PC=%x)\n", m_uart_mode[0], REG_PB<<16 | REG_PC);
LOGMASKED(LOG_UART, "uart0_mode_r: UART0 transmit/recv mode = %x (PC=%x)\n", m_uart_mode[0], REG_PG | REG_PC);
return m_uart_mode[0];
}
@ -665,7 +665,7 @@ void m37710_cpu_device::uart0_mode_w(uint8_t data)
uint8_t m37710_cpu_device::uart1_mode_r()
{
LOGMASKED(LOG_UART, "uart1_mode_r: UART1 transmit/recv mode = %x (PC=%x)\n", m_uart_mode[1], REG_PB<<16 | REG_PC);
LOGMASKED(LOG_UART, "uart1_mode_r: UART1 transmit/recv mode = %x (PC=%x)\n", m_uart_mode[1], REG_PG | REG_PC);
return m_uart_mode[1];
}
@ -703,7 +703,7 @@ void m37710_cpu_device::uart1_tbuf_w(uint16_t data)
uint8_t m37710_cpu_device::uart0_ctrl_reg0_r()
{
LOGMASKED(LOG_UART, "uart0_ctrl_reg0_r: UART0 transmit/recv ctrl 0 = %x (PC=%x)\n", m_uart_ctrl_reg0[0], REG_PB<<16 | REG_PC);
LOGMASKED(LOG_UART, "uart0_ctrl_reg0_r: UART0 transmit/recv ctrl 0 = %x (PC=%x)\n", m_uart_ctrl_reg0[0], REG_PG | REG_PC);
return m_uart_ctrl_reg0[0];
}
@ -718,7 +718,7 @@ void m37710_cpu_device::uart0_ctrl_reg0_w(uint8_t data)
uint8_t m37710_cpu_device::uart1_ctrl_reg0_r()
{
LOGMASKED(LOG_UART, "uart1_ctrl_reg0_r: UART1 transmit/recv ctrl 0 = %x (PC=%x)\n", m_uart_ctrl_reg0[1], REG_PB<<16 | REG_PC);
LOGMASKED(LOG_UART, "uart1_ctrl_reg0_r: UART1 transmit/recv ctrl 0 = %x (PC=%x)\n", m_uart_ctrl_reg0[1], REG_PG | REG_PC);
return m_uart_ctrl_reg0[1];
}
@ -733,7 +733,7 @@ void m37710_cpu_device::uart1_ctrl_reg0_w(uint8_t data)
uint8_t m37710_cpu_device::uart0_ctrl_reg1_r()
{
LOGMASKED(LOG_UART, "uart0_ctrl_reg1_r: UART0 transmit/recv ctrl 1 = %x (PC=%x)\n", m_uart_ctrl_reg1[0], REG_PB<<16 | REG_PC);
LOGMASKED(LOG_UART, "uart0_ctrl_reg1_r: UART0 transmit/recv ctrl 1 = %x (PC=%x)\n", m_uart_ctrl_reg1[0], REG_PG | REG_PC);
return m_uart_ctrl_reg1[0];
}
@ -747,7 +747,7 @@ void m37710_cpu_device::uart0_ctrl_reg1_w(uint8_t data)
uint8_t m37710_cpu_device::uart1_ctrl_reg1_r()
{
LOGMASKED(LOG_UART, "uart1_ctrl_reg1_r: UART1 transmit/recv ctrl 1 = %x (PC=%x)\n", m_uart_ctrl_reg1[1], REG_PB<<16 | REG_PC);
LOGMASKED(LOG_UART, "uart1_ctrl_reg1_r: UART1 transmit/recv ctrl 1 = %x (PC=%x)\n", m_uart_ctrl_reg1[1], REG_PG | REG_PC);
return m_uart_ctrl_reg1[1];
}
@ -761,21 +761,21 @@ void m37710_cpu_device::uart1_ctrl_reg1_w(uint8_t data)
uint16_t m37710_cpu_device::uart0_rbuf_r()
{
LOGMASKED(LOG_UART, "uart0_rbuf_r: UART0 recv buf (PC=%x)\n", REG_PB<<16 | REG_PC);
LOGMASKED(LOG_UART, "uart0_rbuf_r: UART0 recv buf (PC=%x)\n", REG_PG | REG_PC);
return 0;
}
uint16_t m37710_cpu_device::uart1_rbuf_r()
{
LOGMASKED(LOG_UART, "uart1_rbuf_r: UART1 recv buf (PC=%x)\n", REG_PB<<16 | REG_PC);
LOGMASKED(LOG_UART, "uart1_rbuf_r: UART1 recv buf (PC=%x)\n", REG_PG | REG_PC);
return 0;
}
uint8_t m37710_cpu_device::count_start_r()
{
LOGMASKED(LOG_TIMER, "count_start_r: Count start = %x (PC=%x)\n", m_count_start, REG_PB<<16 | REG_PC);
LOGMASKED(LOG_TIMER, "count_start_r: Count start = %x (PC=%x)\n", m_count_start, REG_PG | REG_PC);
return m_count_start;
}
@ -801,7 +801,7 @@ void m37710_cpu_device::one_shot_start_w(uint8_t data)
uint8_t m37710_cpu_device::up_down_r()
{
LOGMASKED(LOG_TIMER, "up_down_r: Up-down register = %x (PC=%x)\n", m_up_down_reg, REG_PB<<16 | REG_PC);
LOGMASKED(LOG_TIMER, "up_down_r: Up-down register = %x (PC=%x)\n", m_up_down_reg, REG_PG | REG_PC);
// bits 7-5 read back as 0
return m_up_down_reg & 0x1f;
@ -828,7 +828,7 @@ void m37710_cpu_device::timer_reg_w(offs_t offset, uint16_t data, uint16_t mem_m
uint8_t m37710_cpu_device::timer_mode_r(offs_t offset)
{
LOGMASKED(LOG_TIMER, "timer_mode_r from %02x: Timer %s mode = %x (PC=%x)\n", (int)offset + 0x56, m37710_tnames[offset], m_timer_mode[offset], REG_PB<<16 | REG_PC);
LOGMASKED(LOG_TIMER, "timer_mode_r from %02x: Timer %s mode = %x (PC=%x)\n", (int)offset + 0x56, m37710_tnames[offset], m_timer_mode[offset], REG_PG | REG_PC);
return m_timer_mode[offset];
}
@ -842,7 +842,7 @@ void m37710_cpu_device::timer_mode_w(offs_t offset, uint8_t data)
uint8_t m37710_cpu_device::proc_mode_r(offs_t offset)
{
LOGMASKED(LOG_GENERAL, "proc_mode_r: Processor mode = %x (PC=%x)\n", m_proc_mode, REG_PB<<16 | REG_PC);
LOGMASKED(LOG_GENERAL, "proc_mode_r: Processor mode = %x (PC=%x)\n", m_proc_mode, REG_PG | REG_PC);
return m_proc_mode & 0xf7;
}
@ -873,7 +873,7 @@ void m37710_cpu_device::watchdog_freq_w(uint8_t data)
uint8_t m37710_cpu_device::waveform_mode_r()
{
LOGMASKED(LOG_GENERAL, "waveform_mode_r: Waveform output mode (PC=%x)\n", REG_PB<<16 | REG_PC);
LOGMASKED(LOG_GENERAL, "waveform_mode_r: Waveform output mode (PC=%x)\n", REG_PG | REG_PC);
return 0;
}
@ -885,7 +885,7 @@ void m37710_cpu_device::waveform_mode_w(uint8_t data)
uint8_t m37710_cpu_device::rto_control_r()
{
LOGMASKED(LOG_GENERAL, "rto_control_r: Real-time output control = %x (PC=%x)\n", m_rto_control, REG_PB<<16 | REG_PC);
LOGMASKED(LOG_GENERAL, "rto_control_r: Real-time output control = %x (PC=%x)\n", m_rto_control, REG_PG | REG_PC);
return m_rto_control;
}
@ -899,7 +899,7 @@ void m37710_cpu_device::rto_control_w(uint8_t data)
uint8_t m37710_cpu_device::dram_control_r()
{
LOGMASKED(LOG_GENERAL, "dram_control_r: DRAM control = %x (PC=%x)\n", m_dram_control, REG_PB<<16 | REG_PC);
LOGMASKED(LOG_GENERAL, "dram_control_r: DRAM control = %x (PC=%x)\n", m_dram_control, REG_PG | REG_PC);
return m_dram_control;
}
@ -932,7 +932,7 @@ uint8_t m37710_cpu_device::get_int_control(int level)
{
assert(level < M37710_MASKABLE_INTERRUPTS);
//LOGMASKED(LOG_INT, "int_control_r: %s IRQ ctrl = %x (PC=%x)\n", m37710_intnames[level], m_int_control[level], REG_PB<<16 | REG_PC);
//LOGMASKED(LOG_INT, "int_control_r: %s IRQ ctrl = %x (PC=%x)\n", m37710_intnames[level], m_int_control[level], REG_PG | REG_PC);
uint8_t result = m_int_control[level];
@ -1025,7 +1025,7 @@ void m37710_cpu_device::m37710i_update_irqs()
if (!FLAG_I && thispri > curpri && thispri > m_ipl)
{
// mark us as the best candidate
LOGMASKED(LOG_INT, "%s interrupt active with priority %d (PC=%x)\n", m37710_intnames[curirq], thispri, REG_PB<<16 | REG_PC);
LOGMASKED(LOG_INT, "%s interrupt active with priority %d (PC=%x)\n", m37710_intnames[curirq], thispri, REG_PG | REG_PC);
wantedIRQ = curirq;
curpri = thispri;
}
@ -1033,7 +1033,7 @@ void m37710_cpu_device::m37710i_update_irqs()
else
{
// non-maskable
LOGMASKED(LOG_INT, "%s interrupt active (PC=%x)\n", m37710_intnames[curirq], REG_PB<<16 | REG_PC);
LOGMASKED(LOG_INT, "%s interrupt active (PC=%x)\n", m37710_intnames[curirq], REG_PG | REG_PC);
wantedIRQ = curirq;
curpri = 7;
break; // no more processing, NMIs always win
@ -1054,16 +1054,16 @@ void m37710_cpu_device::m37710i_update_irqs()
// let's do it...
// push PB, then PC, then status
CLK(13);
m37710i_push_8(REG_PB>>16);
m37710i_push_8(REG_PG>>16);
m37710i_push_16(REG_PC);
m37710i_push_8(m_ipl);
m37710i_push_8(m37710i_get_reg_p());
m37710i_push_8(m37710i_get_reg_ps());
// set I to 1, set IPL to the interrupt we're taking
FLAG_I = IFLAG_SET;
m_ipl = curpri;
// then PB=0, PC=(vector)
REG_PB = 0;
// then PG=0, PC=(vector)
REG_PG = 0;
REG_PC = m37710_read_16(m37710_irq_vectors[wantedIRQ]);
}
}
@ -1131,9 +1131,9 @@ void m37710_cpu_device::device_reset()
IRQ_DELAY = 0;
/* 37710 boots in full native mode */
REG_D = 0;
REG_PB = 0;
REG_DB = 0;
REG_DPR = 0;
REG_PG = 0;
REG_DT = 0;
REG_S = (REG_S & 0xff) | 0x100;
REG_XH = REG_X & 0xff00; REG_X &= 0xff;
REG_YH = REG_Y & 0xff00; REG_Y &= 0xff;
@ -1268,9 +1268,9 @@ void m37710_cpu_device::device_start()
m_s = 0;
m_pc = 0;
m_ppc = 0;
m_pb = 0;
m_db = 0;
m_d = 0;
m_pg = 0;
m_dt = 0;
m_dpr = 0;
m_flag_e = 0;
m_flag_m = 0;
m_flag_x = 0;
@ -1339,9 +1339,9 @@ void m37710_cpu_device::device_start()
save_item(NAME(m_s));
save_item(NAME(m_pc));
save_item(NAME(m_ppc));
save_item(NAME(m_pb));
save_item(NAME(m_db));
save_item(NAME(m_d));
save_item(NAME(m_pg));
save_item(NAME(m_dt));
save_item(NAME(m_dpr));
save_item(NAME(m_flag_e));
save_item(NAME(m_flag_m));
save_item(NAME(m_flag_x));
@ -1390,11 +1390,11 @@ void m37710_cpu_device::device_start()
machine().save().register_postload(save_prepost_delegate(save_prepost_delegate(FUNC(m37710_cpu_device::m37710_restore_state), this)));
state_add( M37710_PC, "PC", m_pc).formatstr("%04X");
state_add( M37710_PB, "PB", m_debugger_pb).callimport().callexport().formatstr("%02X");
state_add( M37710_DB, "DB", m_debugger_db).callimport().callexport().formatstr("%02X");
state_add( M37710_D, "D", m_d).formatstr("%04X");
state_add( M37710_PG, "PG", m_debugger_pg).callimport().callexport().formatstr("%02X");
state_add( M37710_DT, "DT", m_debugger_dt).callimport().callexport().formatstr("%02X");
state_add( M37710_DPR, "DPR", m_dpr).formatstr("%04X");
state_add( M37710_S, "S", m_s).formatstr("%04X");
state_add( M37710_P, "P", m_debugger_p).callimport().callexport().formatstr("%04X");
state_add( M37710_PS, "PS", m_debugger_ps).callimport().callexport().formatstr("%04X");
state_add( M37710_E, "E", m_flag_e).formatstr("%01X");
state_add( M37710_A, "A", m_debugger_a).callimport().callexport().formatstr("%04X");
state_add( M37710_B, "B", m_debugger_b).callimport().callexport().formatstr("%04X");
@ -1404,7 +1404,7 @@ void m37710_cpu_device::device_start()
state_add( STATE_GENPC, "GENPC", m_debugger_pc ).callimport().callexport().noshow();
state_add( STATE_GENPCBASE, "CURPC", m_debugger_pc ).callimport().callexport().noshow();
state_add( STATE_GENFLAGS, "GENFLAGS", m_debugger_p ).formatstr("%8s").noshow();
state_add( STATE_GENFLAGS, "GENFLAGS", m_debugger_ps ).formatstr("%8s").noshow();
set_icountptr(m_ICount);
}
@ -1414,17 +1414,17 @@ void m37710_cpu_device::state_import(const device_state_entry &entry)
{
switch (entry.index())
{
case M37710_PB:
m37710_set_reg(M37710_PB, m_debugger_pb);
case M37710_PG:
m37710_set_reg(M37710_PG, m_debugger_pg);
break;
case M37710_DB:
m37710_set_reg(M37710_DB, m_debugger_db);
case M37710_DT:
m37710_set_reg(M37710_DT, m_debugger_dt);
break;
case M37710_P:
m37710_set_reg(M37710_P, m_debugger_p&0xff);
m_ipl = (m_debugger_p>>8)&0xff;
case M37710_PS:
m37710_set_reg(M37710_PS, m_debugger_ps&0xff);
m_ipl = (m_debugger_ps>>8)&0xff;
break;
case M37710_A:
@ -1437,7 +1437,7 @@ void m37710_cpu_device::state_import(const device_state_entry &entry)
case STATE_GENPC:
case STATE_GENPCBASE:
REG_PB = m_debugger_pc & 0xff0000;
REG_PG = m_debugger_pc & 0xff0000;
m37710_set_pc(m_debugger_pc & 0xffff);
break;
}
@ -1448,16 +1448,16 @@ void m37710_cpu_device::state_export(const device_state_entry &entry)
{
switch (entry.index())
{
case M37710_PB:
m_debugger_pb = m_pb >> 16;
case M37710_PG:
m_debugger_pg = m_pg >> 16;
break;
case M37710_DB:
m_debugger_db = m_db >> 16;
case M37710_DT:
m_debugger_dt = m_dt >> 16;
break;
case M37710_P:
m_debugger_p = (m_flag_n&0x80) | ((m_flag_v>>1)&0x40) | m_flag_m | m_flag_x | m_flag_d | m_flag_i | ((!m_flag_z)<<1) | ((m_flag_c>>8)&1) | (m_ipl<<8);
case M37710_PS:
m_debugger_ps = (m_flag_n&0x80) | ((m_flag_v>>1)&0x40) | m_flag_m | m_flag_x | m_flag_d | m_flag_i | ((!m_flag_z)<<1) | ((m_flag_c>>8)&1) | (m_ipl<<8);
break;
case M37710_A:
@ -1470,7 +1470,7 @@ void m37710_cpu_device::state_export(const device_state_entry &entry)
case STATE_GENPC:
case STATE_GENPCBASE:
m_debugger_pc = (REG_PB | REG_PC);
m_debugger_pc = (REG_PG | REG_PC);
break;
}
}
@ -1549,12 +1549,12 @@ void m37710_cpu_device::m37710i_set_execution_mode(uint32_t mode)
void m37710_cpu_device::m37710i_interrupt_software(uint32_t vector)
{
CLK(13);
m37710i_push_8(REG_PB>>16);
m37710i_push_8(REG_PG>>16);
m37710i_push_16(REG_PC);
m37710i_push_8(m_ipl);
m37710i_push_8(m37710i_get_reg_p());
m37710i_push_8(m37710i_get_reg_ps());
FLAG_I = IFLAG_SET;
REG_PB = 0;
REG_PG = 0;
REG_PC = m37710_read_16(vector);
}

31
src/devices/cpu/m37710/m37710.h
View File

@ -83,8 +83,8 @@ enum
/* Registers - used by m37710_set_reg() and m37710_get_reg() */
enum
{
M37710_PC=1, M37710_S, M37710_P, M37710_A, M37710_B, M37710_X, M37710_Y,
M37710_PB, M37710_DB, M37710_D, M37710_E,
M37710_PC=1, M37710_S, M37710_PS, M37710_A, M37710_B, M37710_X, M37710_Y,
M37710_PG, M37710_DT, M37710_DPR, M37710_E,
M37710_NMI_STATE, M37710_IRQ_STATE
};
@ -247,9 +247,9 @@ private:
uint32_t m_s; /* Stack Pointer */
uint32_t m_pc; /* Program Counter */
uint32_t m_ppc; /* Previous Program Counter */
uint32_t m_pb; /* Program Bank (shifted left 16) */
uint32_t m_db; /* Data Bank (shifted left 16) */
uint32_t m_d; /* Direct Register */
uint32_t m_pg; /* Program Bank (shifted left 16) */
uint32_t m_dt; /* Data Bank (shifted left 16) */
uint32_t m_dpr; /* Direct Page Register */
uint32_t m_flag_e; /* Emulation Mode Flag */
uint32_t m_flag_m; /* Memory/Accumulator Select Flag */
uint32_t m_flag_x; /* Index Select Flag */
@ -308,19 +308,16 @@ private:
uint16_t m_dmac_control;
// DMA
uint32_t m_dma0_src, m_dma0_dst, m_dma0_cnt, m_dma0_mode;
uint32_t m_dma1_src, m_dma1_dst, m_dma1_cnt, m_dma1_mode;
uint32_t m_dma2_src, m_dma2_dst, m_dma2_cnt, m_dma2_mode;
uint32_t m_dma3_src, m_dma3_dst, m_dma3_cnt, m_dma3_mode;
uint32_t m_dma_src[4], m_dma_dst[4], m_dma_cnt[4], m_dma_mode[4];
// interrupt controller
uint8_t m_int_control[M37710_MASKABLE_INTERRUPTS];
// for debugger
uint32_t m_debugger_pc;
uint32_t m_debugger_pb;
uint32_t m_debugger_db;
uint32_t m_debugger_p;
uint32_t m_debugger_pg;
uint32_t m_debugger_dt;
uint32_t m_debugger_ps;
uint32_t m_debugger_a;
uint32_t m_debugger_b;
@ -407,17 +404,17 @@ private:
void m37710i_jump_24(uint32_t address);
void m37710i_branch_8(uint32_t offset);
void m37710i_branch_16(uint32_t offset);
uint32_t m37710i_get_reg_p();
uint32_t m37710i_get_reg_ps();
void m37710i_set_reg_ipl(uint32_t value);
void m37710i_interrupt_software(uint32_t vector);
void m37710i_set_flag_m0x0(uint32_t value);
void m37710i_set_flag_m0x1(uint32_t value);
void m37710i_set_flag_m1x0(uint32_t value);
void m37710i_set_flag_m1x1(uint32_t value);
void m37710i_set_reg_p_m0x0(uint32_t value);
void m37710i_set_reg_p_m0x1(uint32_t value);
void m37710i_set_reg_p_m1x0(uint32_t value);
void m37710i_set_reg_p_m1x1(uint32_t value);
void m37710i_set_reg_ps_m0x0(uint32_t value);
void m37710i_set_reg_ps_m0x1(uint32_t value);
void m37710i_set_reg_ps_m1x0(uint32_t value);
void m37710i_set_reg_ps_m1x1(uint32_t value);
uint32_t EA_IMM8();
uint32_t EA_IMM16();
uint32_t EA_IMM24();

6
src/devices/cpu/m37710/m37710cm.h
View File

@ -73,9 +73,9 @@ static inline int MAKE_INT_8(int A) {return (A & 0x80) ? A | ~0xff : A & 0xff;}
#define REG_S m_s /* Stack Pointer */
#define REG_PC m_pc /* Program Counter */
#define REG_PPC m_ppc /* Previous Program Counter */
#define REG_PB m_pb /* Program Bank */
#define REG_DB m_db /* Data Bank */
#define REG_D m_d /* Direct Register */
#define REG_PG m_pg /* Program Bank */
#define REG_DT m_dt /* Data Bank */
#define REG_DPR m_dpr /* Direct Page Register */
#define FLAG_M m_flag_m /* Memory/Accumulator Select Flag */
#define FLAG_X m_flag_x /* Index Select Flag */
#define FLAG_N m_flag_n /* Negative Flag */

26
src/devices/cpu/m37710/m37710il.h
View File

@ -142,7 +142,7 @@ inline void m37710_cpu_device::m37710i_jump_16(uint32_t address)
inline void m37710_cpu_device::m37710i_jump_24(uint32_t address)
{
REG_PB = address&0xff0000;
REG_PG = address&0xff0000;
REG_PC = MAKE_UINT_16(address);
}
@ -161,7 +161,7 @@ inline void m37710_cpu_device::m37710i_branch_16(uint32_t offset)
/* ============================ STATUS REGISTER =========================== */
/* ======================================================================== */
inline uint32_t m37710_cpu_device::m37710i_get_reg_p()
inline uint32_t m37710_cpu_device::m37710i_get_reg_ps()
{
return (FLAG_N&0x80) |
((FLAG_V>>1)&0x40) |
@ -183,26 +183,26 @@ inline void m37710_cpu_device::m37710i_set_reg_ipl(uint32_t value)
/* ============================= ADDRESS MODES ============================ */
/* ======================================================================== */
inline uint32_t m37710_cpu_device::EA_IMM8() {REG_PC += 1; return REG_PB | MAKE_UINT_16(REG_PC-1);}
inline uint32_t m37710_cpu_device::EA_IMM16() {REG_PC += 2; return REG_PB | MAKE_UINT_16(REG_PC-2);}
inline uint32_t m37710_cpu_device::EA_IMM24() {REG_PC += 3; return REG_PB | MAKE_UINT_16(REG_PC-3);}
inline uint32_t m37710_cpu_device::EA_D() {if(MAKE_UINT_8(REG_D)) CLK(1); return MAKE_UINT_16(REG_D + OPER_8_IMM());}
inline uint32_t m37710_cpu_device::EA_A() {return REG_DB | OPER_16_IMM();}
inline uint32_t m37710_cpu_device::EA_IMM8() {REG_PC += 1; return REG_PG | MAKE_UINT_16(REG_PC-1);}
inline uint32_t m37710_cpu_device::EA_IMM16() {REG_PC += 2; return REG_PG | MAKE_UINT_16(REG_PC-2);}
inline uint32_t m37710_cpu_device::EA_IMM24() {REG_PC += 3; return REG_PG | MAKE_UINT_16(REG_PC-3);}
inline uint32_t m37710_cpu_device::EA_D() {if(MAKE_UINT_8(REG_DPR)) CLK(1); return MAKE_UINT_16(REG_DPR + OPER_8_IMM());}
inline uint32_t m37710_cpu_device::EA_A() {return REG_DT | OPER_16_IMM();}
inline uint32_t m37710_cpu_device::EA_AL() {return OPER_24_IMM();}
inline uint32_t m37710_cpu_device::EA_DX() {return MAKE_UINT_16(REG_D + OPER_8_IMM() + REG_X);}
inline uint32_t m37710_cpu_device::EA_DY() {return MAKE_UINT_16(REG_D + OPER_8_IMM() + REG_Y);}
inline uint32_t m37710_cpu_device::EA_DX() {return MAKE_UINT_16(REG_DPR + OPER_8_IMM() + REG_X);}
inline uint32_t m37710_cpu_device::EA_DY() {return MAKE_UINT_16(REG_DPR + OPER_8_IMM() + REG_Y);}
inline uint32_t m37710_cpu_device::EA_AX() {uint32_t tmp = EA_A(); if((tmp^(tmp+REG_X))&0xff00) CLK(1); return tmp + REG_X;}
inline uint32_t m37710_cpu_device::EA_ALX() {return EA_AL() + REG_X;}
inline uint32_t m37710_cpu_device::EA_AY() {uint32_t tmp = EA_A(); if((tmp^(tmp+REG_X))&0xff00) CLK(1); return tmp + REG_Y;}
inline uint32_t m37710_cpu_device::EA_DI() {return REG_DB | OPER_16_D();}
inline uint32_t m37710_cpu_device::EA_DI() {return REG_DT | OPER_16_D();}
inline uint32_t m37710_cpu_device::EA_DLI() {return OPER_24_D();}
inline uint32_t m37710_cpu_device::EA_AI() {return read_16_A(OPER_16_IMM());}
inline uint32_t m37710_cpu_device::EA_ALI() {return OPER_24_A();}
inline uint32_t m37710_cpu_device::EA_DXI() {return REG_DB | OPER_16_DX();}
inline uint32_t m37710_cpu_device::EA_DIY() {uint32_t tmp = REG_DB | OPER_16_D(); if((tmp^(tmp+REG_X))&0xff00) CLK(1); return tmp + REG_Y;}
inline uint32_t m37710_cpu_device::EA_DXI() {return REG_DT | OPER_16_DX();}
inline uint32_t m37710_cpu_device::EA_DIY() {uint32_t tmp = REG_DT | OPER_16_D(); if((tmp^(tmp+REG_X))&0xff00) CLK(1); return tmp + REG_Y;}
inline uint32_t m37710_cpu_device::EA_DLIY() {return OPER_24_D() + REG_Y;}
inline uint32_t m37710_cpu_device::EA_AXI() {return read_16_AXI(MAKE_UINT_16(OPER_16_IMM() + REG_X));}
inline uint32_t m37710_cpu_device::EA_S() {return MAKE_UINT_16(REG_S + OPER_8_IMM());}
inline uint32_t m37710_cpu_device::EA_SIY() {return MAKE_UINT_16(read_16_SIY(REG_S + OPER_8_IMM()) + REG_Y) | REG_DB;}
inline uint32_t m37710_cpu_device::EA_SIY() {return MAKE_UINT_16(read_16_SIY(REG_S + OPER_8_IMM()) + REG_Y) | REG_DT;}
#endif /* __M37710IL_H__ */

174
src/devices/cpu/m37710/m37710op.h
View File

@ -7,28 +7,28 @@
#undef FLAG_SET_M
#undef FLAG_SET_X
#undef m37710i_set_flag_mx
#undef m37710i_set_reg_p
#undef m37710i_set_reg_ps
#if EXECUTION_MODE == EXECUTION_MODE_M0X0
#define FLAG_SET_M 0
#define FLAG_SET_X 0
#define m37710i_set_flag_mx m37710i_set_flag_m0x0
#define m37710i_set_reg_p m37710i_set_reg_p_m0x0
#define m37710i_set_reg_ps m37710i_set_reg_ps_m0x0
#elif EXECUTION_MODE == EXECUTION_MODE_M0X1
#define FLAG_SET_M 0
#define FLAG_SET_X 1
#define m37710i_set_flag_mx m37710i_set_flag_m0x1
#define m37710i_set_reg_p m37710i_set_reg_p_m0x1
#define m37710i_set_reg_ps m37710i_set_reg_ps_m0x1
#elif EXECUTION_MODE == EXECUTION_MODE_M1X0
#define FLAG_SET_M 1
#define FLAG_SET_X 0
#define m37710i_set_flag_mx m37710i_set_flag_m1x0
#define m37710i_set_reg_p m37710i_set_reg_p_m1x0
#define m37710i_set_reg_ps m37710i_set_reg_ps_m1x0
#elif EXECUTION_MODE == EXECUTION_MODE_M1X1
#define FLAG_SET_M 1
#define FLAG_SET_X 1
#define m37710i_set_flag_mx m37710i_set_flag_m1x1
#define m37710i_set_reg_p m37710i_set_reg_p_m1x1
#define m37710i_set_reg_ps m37710i_set_reg_ps_m1x1
#endif
/* ======================================================================== */
@ -82,7 +82,7 @@ void m37710_cpu_device::m37710i_set_flag_mx(uint32_t value)
}
void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
void m37710_cpu_device::m37710i_set_reg_ps(uint32_t value)
{
FLAG_N = value;
FLAG_V = value << 1;
@ -115,13 +115,13 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
if (SRC&0x8) \
{ m37710i_push_8(REG_Y); CLK(2); } \
if (SRC&0x10) \
{ m37710i_push_16(REG_D); CLK(2); } \
{ m37710i_push_16(REG_DPR); CLK(2); } \
if (SRC&0x20) \
{ m37710i_push_8(REG_DB>>16); CLK(1); } \
{ m37710i_push_8(REG_DT>>16); CLK(1); } \
if (SRC&0x40) \
{ m37710i_push_8(REG_PB>>16); CLK(1); } \
{ m37710i_push_8(REG_PG>>16); CLK(1); } \
if (SRC&0x80) \
{ m37710i_push_8(m_ipl); m37710i_push_8(m37710i_get_reg_p()); CLK(2); }
{ m37710i_push_8(m_ipl); m37710i_push_8(m37710i_get_reg_ps()); CLK(2); }
#else // FLAG_SET_X
#define OP_PSH(MODE) \
SRC = OPER_8_##MODE(); \
@ -135,13 +135,13 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
if (SRC&0x8) \
{ m37710i_push_16(REG_Y); CLK(2); } \
if (SRC&0x10) \
{ m37710i_push_16(REG_D); CLK(2); } \
{ m37710i_push_16(REG_DPR); CLK(2); } \
if (SRC&0x20) \
{ m37710i_push_8(REG_DB>>16); CLK(1); } \
{ m37710i_push_8(REG_DT>>16); CLK(1); } \
if (SRC&0x40) \
{ m37710i_push_8(REG_PB>>16); CLK(1); } \
{ m37710i_push_8(REG_PG>>16); CLK(1); } \
if (SRC&0x80) \
{ m37710i_push_8(m_ipl); m37710i_push_8(m37710i_get_reg_p()); CLK(2); }
{ m37710i_push_8(m_ipl); m37710i_push_8(m37710i_get_reg_ps()); CLK(2); }
#endif // FLAG_SET_X
#else // FLAG_SET_M
#if FLAG_SET_X
@ -157,13 +157,13 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
if (SRC&0x8) \
{ m37710i_push_8(REG_Y); CLK(2); } \
if (SRC&0x10) \
{ m37710i_push_16(REG_D); CLK(2); } \
{ m37710i_push_16(REG_DPR); CLK(2); } \
if (SRC&0x20) \
{ m37710i_push_8(REG_DB>>16); CLK(1); } \
{ m37710i_push_8(REG_DT>>16); CLK(1); } \
if (SRC&0x40) \
{ m37710i_push_8(REG_PB>>16); CLK(1); } \
{ m37710i_push_8(REG_PG>>16); CLK(1); } \
if (SRC&0x80) \
{ m37710i_push_8(m_ipl); m37710i_push_8(m37710i_get_reg_p()); CLK(2); }
{ m37710i_push_8(m_ipl); m37710i_push_8(m37710i_get_reg_ps()); CLK(2); }
#else // FLAG_SET_X
#define OP_PSH(MODE) \
SRC = OPER_8_##MODE(); \
@ -177,13 +177,13 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
if (SRC&0x8) \
{ m37710i_push_16(REG_Y); CLK(2); } \
if (SRC&0x10) \
{ m37710i_push_16(REG_D); CLK(2); } \
{ m37710i_push_16(REG_DPR); CLK(2); } \
if (SRC&0x20) \
{ m37710i_push_8(REG_DB>>16); CLK(1); } \
{ m37710i_push_8(REG_DT>>16); CLK(1); } \
if (SRC&0x40) \
{ m37710i_push_8(REG_PB>>16); CLK(1); } \
{ m37710i_push_8(REG_PG>>16); CLK(1); } \
if (SRC&0x80) \
{ m37710i_push_8(m_ipl); m37710i_push_8(m37710i_get_reg_p()); CLK(2); }
{ m37710i_push_8(m_ipl); m37710i_push_8(m37710i_get_reg_ps()); CLK(2); }
#endif // FLAG_SET_X
#endif // FLAG_SET_M
@ -194,12 +194,12 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
SRC = OPER_8_##MODE(); \
CLK(14); \
if (SRC&0x80) \
{ m37710i_set_reg_p(m37710i_pull_8()); m37710i_set_reg_ipl(m37710i_pull_8()); CLK(3); } \
{ m37710i_set_reg_ps(m37710i_pull_8()); m37710i_set_reg_ipl(m37710i_pull_8()); CLK(3); } \
if (SRC&0x20) \
{ REG_DB = m37710i_pull_8() << 16; CLK(3); } \
{ REG_DT = m37710i_pull_8() << 16; CLK(3); } \
if (SRC&0x10) \
{ REG_D = m37710i_pull_16(); CLK(4); } \
if (m37710i_get_reg_p() & XFLAG_SET) \
{ REG_DPR = m37710i_pull_16(); CLK(4); } \
if (m37710i_get_reg_ps() & XFLAG_SET) \
{ \
if (SRC&0x8) \
{ REG_Y = m37710i_pull_8(); CLK(3); } \
@ -213,7 +213,7 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
if (SRC&0x4) \
{ REG_X = m37710i_pull_16(); CLK(3); } \
} \
if (m37710i_get_reg_p() & MFLAG_SET) \
if (m37710i_get_reg_ps() & MFLAG_SET) \
{ \
if (SRC&0x2) \
{ REG_BA = m37710i_pull_8(); CLK(3); } \
@ -462,7 +462,7 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
#undef OP_BRK
#define OP_BRK() \
REG_PC++; CLK(CLK_OP + CLK_R8 + CLK_IMM); \
logerror("error M37710: BRK at PC=%06x\n", REG_PB|REG_PC); \
logerror("error M37710: BRK at PC=%06x\n", REG_PG|REG_PC); \
m37710i_interrupt_software(0xfffa)
/* M37710 Branch Always */
@ -704,7 +704,7 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
#undef OP_JMPAXI
#define OP_JMPAXI() \
CLK(CLK_OP + CLK_AXI); \
m37710i_jump_16(read_16_AXI(REG_PB | (MAKE_UINT_16(OPER_16_IMM() + REG_X))))
m37710i_jump_16(read_16_AXI(REG_PG | (MAKE_UINT_16(OPER_16_IMM() + REG_X))))
/* M37710 Jump absolute long */
#undef OP_JMPAL
@ -717,7 +717,7 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
#define OP_JSL(MODE) \
CLK(CLK_OP + CLK_W24 + CLK_##MODE + 1); \
DST = EA_##MODE(); \
m37710i_push_8(REG_PB>>16); \
m37710i_push_8(REG_PG>>16); \
m37710i_push_16(REG_PC); \
m37710i_jump_24(DST)
@ -733,7 +733,7 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
#undef OP_JSRAXI
#define OP_JSRAXI() \
CLK(CLK_OP + CLK_W16 + CLK_AXI); \
DST = read_16_AXI(REG_PB | (MAKE_UINT_16(OPER_16_IMM() + REG_X))); \
DST = read_16_AXI(REG_PG | (MAKE_UINT_16(OPER_16_IMM() + REG_X))); \
m37710i_push_16(REG_PC); \
m37710i_jump_16(DST)
@ -769,14 +769,14 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
#define OP_LDM(MODE) \
CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
REG_IM2 = EA_##MODE(); \
REG_IM = read_8_IMM(REG_PB | REG_PC); \
REG_IM = read_8_IMM(REG_PG | REG_PC); \
REG_PC++; \
write_8_##MODE(REG_IM2, REG_IM)
#else
#define OP_LDM(MODE) \
CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
REG_IM2 = EA_##MODE(); \
REG_IM = read_16_IMM(REG_PB | REG_PC); \
REG_IM = read_16_IMM(REG_PG | REG_PC); \
REG_PC+=2; \
write_16_##MODE(REG_IM2, REG_IM)
#endif
@ -787,7 +787,7 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
#define OP_BBS(MODE) \
CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
REG_IM2 = read_8_NORM(EA_##MODE()); \
REG_IM = read_8_IMM(REG_PB | REG_PC); \
REG_IM = read_8_IMM(REG_PG | REG_PC); \
REG_PC++; \
DST = OPER_8_IMM(); \
if ((REG_IM2 & REG_IM) == REG_IM) \
@ -800,7 +800,7 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
#define OP_BBS(MODE) \
CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
REG_IM2 = read_16_NORM(EA_##MODE()); \
REG_IM = read_16_IMM(REG_PB | REG_PC); \
REG_IM = read_16_IMM(REG_PG | REG_PC); \
REG_PC++; \
REG_PC++; \
DST = OPER_8_IMM(); \
@ -818,7 +818,7 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
#define OP_BBC(MODE) \
CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
REG_IM2 = read_8_NORM(EA_##MODE()); \
REG_IM = read_8_IMM(REG_PB | REG_PC); \
REG_IM = read_8_IMM(REG_PG | REG_PC); \
REG_PC++; \
DST = OPER_8_IMM(); \
if ((REG_IM2 & REG_IM) == 0) \
@ -831,7 +831,7 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
#define OP_BBC(MODE) \
CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
REG_IM2 = read_16_NORM(EA_##MODE()); \
REG_IM = read_16_IMM(REG_PB | REG_PC); \
REG_IM = read_16_IMM(REG_PG | REG_PC); \
REG_PC++; \
REG_PC++; \
DST = OPER_8_IMM(); \
@ -933,7 +933,7 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
#define OP_MVN() \
DST = OPER_8_IMM()<<16; \
SRC = OPER_8_IMM()<<16; \
REG_DB = DST; \
REG_DT = DST; \
REG_A |= REG_B; \
CLK(7); \
if (REG_A > 0) \
@ -963,7 +963,7 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
#define OP_MVN() \
DST = OPER_8_IMM()<<16; \
SRC = OPER_8_IMM()<<16; \
REG_DB = DST; \
REG_DT = DST; \
REG_A |= REG_B; \
CLK(7); \
if (REG_A > 0) \
@ -997,7 +997,7 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
#define OP_MVP() \
DST = OPER_8_IMM()<<16; \
SRC = OPER_8_IMM()<<16; \
REG_DB = DST; \
REG_DT = DST; \
REG_A |= REG_B; \
CLK(7); \
if (REG_A > 0) \
@ -1027,7 +1027,7 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
#define OP_MVP() \
DST = OPER_8_IMM()<<16; \
SRC = OPER_8_IMM()<<16; \
REG_DB = DST; \
REG_DT = DST; \
REG_A |= REG_B; \
CLK(7); \
if (REG_A > 0) \
@ -1145,26 +1145,26 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
#undef OP_PHT
#define OP_PHT() \
CLK(CLK_OP + CLK_W8 + 1); \
m37710i_push_8(REG_DB>>16)
m37710i_push_8(REG_DT>>16)
/* M37710 Push direct register */
/* M37710 Push direct page register */
#undef OP_PHD
#define OP_PHD() \
CLK(CLK_OP + CLK_W16 + 1); \
m37710i_push_16(REG_D)
m37710i_push_16(REG_DPR)
/* M37710 Push program bank register */
#undef OP_PHK
#define OP_PHK() \
CLK(CLK_OP + CLK_W8 + 1); \
m37710i_push_8(REG_PB>>16)
m37710i_push_8(REG_PG>>16)
/* M37710 Push the Processor Status Register to the stack */
#undef OP_PHP
#define OP_PHP() \
CLK(CLK_OP + CLK_W8 + 1); \
m37710i_push_8(m_ipl); \
m37710i_push_8(m37710i_get_reg_p())
m37710i_push_8(m37710i_get_reg_ps())
/* M37710 Pull accumulator from the stack */
#undef OP_PLA
@ -1210,19 +1210,19 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
#define OP_PLT() \
CLK(CLK_OP + CLK_R8 + 2); \
FLAG_N = FLAG_Z = m37710i_pull_8(); \
REG_DB = FLAG_Z << 16
REG_DT = FLAG_Z << 16
/* M37710 Pull direct register */
/* M37710 Pull direct page register */
#undef OP_PLD
#define OP_PLD() \
CLK(CLK_OP + CLK_R16 + 2); \
REG_D = m37710i_pull_16()
REG_DPR = m37710i_pull_16()
/* M37710 Pull the Processor Status Register from the stack */
#undef OP_PLP
#define OP_PLP() \
CLK(CLK_OP + CLK_R8 + 2); \
m37710i_set_reg_p(m37710i_pull_8()); \
m37710i_set_reg_ps(m37710i_pull_8()); \
m37710i_set_reg_ipl(m37710i_pull_8()); \
m37710i_update_irqs()
@ -1230,14 +1230,14 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
#undef OP_REP
#define OP_REP() \
CLK(CLK_OP + CLK_R8 + 1); \
m37710i_set_reg_p(m37710i_get_reg_p() & ~OPER_8_IMM()); \
m37710i_set_reg_ps(m37710i_get_reg_ps() & ~OPER_8_IMM()); \
m37710i_update_irqs()
/* M37710 Clear "M" status bit */
#undef OP_CLM
#define OP_CLM() \
CLK(CLK_OP + CLK_R8 + 1); \
m37710i_set_reg_p(m37710i_get_reg_p() & ~FLAGPOS_M)
m37710i_set_reg_ps(m37710i_get_reg_ps() & ~FLAGPOS_M)
/* M37710 Rotate Left the accumulator */
#undef OP_ROL
@ -1360,10 +1360,10 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
#undef OP_RTI
#define OP_RTI() \
CLK(8); \
m37710i_set_reg_p(m37710i_pull_8()); \
m37710i_set_reg_ps(m37710i_pull_8()); \
m37710i_set_reg_ipl(m37710i_pull_8()); \
m37710i_jump_16(m37710i_pull_16()); \
REG_PB = m37710i_pull_8() << 16; \
REG_PG = m37710i_pull_8() << 16; \
m37710i_update_irqs()
/* M37710 Return from Subroutine Long */
@ -1513,13 +1513,13 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
#undef OP_SEP
#define OP_SEP() \
CLK(CLK_OP + CLK_R8 + 1); \
m37710i_set_reg_p(m37710i_get_reg_p() | OPER_8_IMM())
m37710i_set_reg_ps(m37710i_get_reg_ps() | OPER_8_IMM())
/* M37710 Set "M" status bit */
#undef OP_SEM
#define OP_SEM() \
CLK(CLK_OP + CLK_R8 + 1); \
m37710i_set_reg_p(m37710i_get_reg_p() | FLAGPOS_M)
m37710i_set_reg_ps(m37710i_get_reg_ps() | FLAGPOS_M)
/* M37710 Store accumulator to memory */
#undef OP_STA
@ -1648,59 +1648,59 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
FLAG_N = NFLAG_16(FLAG_Z)
#endif
/* M37710 Transfer accumulator to direct register */
/* M37710 Transfer accumulator to direct page register */
#undef OP_TAD
#if FLAG_SET_M
#define OP_TAD() \
CLK(CLK_OP + CLK_IMPLIED); \
REG_D = REG_A | REG_B
REG_DPR = REG_A | REG_B
#else
#define OP_TAD() \
CLK(CLK_OP + CLK_IMPLIED); \
REG_D = REG_A
REG_DPR = REG_A
#endif
/* M37710 Transfer accumulator B to direct register */
/* M37710 Transfer accumulator B to direct page register */
#undef OP_TBD
#if FLAG_SET_M
#define OP_TBD() \
CLK(CLK_OP + CLK_IMPLIED); \
REG_D = REG_BA | REG_BB
REG_DPR = REG_BA | REG_BB
#else
#define OP_TBD() \
CLK(CLK_OP + CLK_IMPLIED); \
REG_D = REG_BA
REG_DPR = REG_BA
#endif
/* M37710 Transfer direct register to accumulator */
/* M37710 Transfer direct page register to accumulator */
#undef OP_TDA
#if FLAG_SET_M
#define OP_TDA() \
CLK(CLK_OP + CLK_IMPLIED); \
FLAG_Z = REG_D; \
FLAG_Z = REG_DPR; \
FLAG_N = NFLAG_16(FLAG_Z); \
REG_A = MAKE_UINT_8(REG_D); \
REG_B = REG_D & 0xff00
REG_A = MAKE_UINT_8(REG_DPR); \
REG_B = REG_DPR & 0xff00
#else
#define OP_TDA() \
CLK(CLK_OP + CLK_IMPLIED); \
FLAG_Z = REG_A = REG_D; \
FLAG_Z = REG_A = REG_DPR; \
FLAG_N = NFLAG_16(FLAG_Z)
#endif
/* M37710 Transfer direct register to accumulator B */
/* M37710 Transfer direct page register to accumulator B */
#undef OP_TDB
#if FLAG_SET_M
#define OP_TDB() \
CLK(CLK_OP + CLK_IMPLIED); \
FLAG_Z = REG_D; \
FLAG_Z = REG_DPR; \
FLAG_N = NFLAG_16(FLAG_Z); \
REG_BA = MAKE_UINT_8(REG_D); \
REG_BB = REG_D & 0xff00
REG_BA = MAKE_UINT_8(REG_DPR); \
REG_BB = REG_DPR & 0xff00
#else
#define OP_TDB() \
CLK(CLK_OP + CLK_IMPLIED); \
FLAG_Z = REG_BA = REG_D; \
FLAG_Z = REG_BA = REG_DPR; \
FLAG_N = NFLAG_16(FLAG_Z)
#endif
@ -1821,7 +1821,7 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \
DST = EA_##MODE(); \
REG_IM = read_8_##MODE(DST); \
REG_IM2 = read_8_IMM(REG_PB | REG_PC); \
REG_IM2 = read_8_IMM(REG_PG | REG_PC); \
REG_PC++; \
write_8_##MODE(DST, REG_IM & ~REG_IM2);
#else
@ -1829,7 +1829,7 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \
DST = EA_##MODE(); \
REG_IM = read_16_##MODE(DST); \
REG_IM2 = read_16_IMM(REG_PB | REG_PC); \
REG_IM2 = read_16_IMM(REG_PG | REG_PC); \
REG_PC+=2; \
write_16_##MODE(DST, REG_IM & ~REG_IM2);
#endif
@ -1841,7 +1841,7 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \
DST = EA_##MODE(); \
REG_IM = read_8_##MODE(DST); \
REG_IM2 = read_8_IMM(REG_PB | REG_PC); \
REG_IM2 = read_8_IMM(REG_PG | REG_PC); \
REG_PC++; \
write_8_##MODE(DST, REG_IM | REG_IM2);
#else
@ -1849,7 +1849,7 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \
DST = EA_##MODE(); \
REG_IM = read_16_##MODE(DST); \
REG_IM2 = read_16_IMM(REG_PB | REG_PC); \
REG_IM2 = read_16_IMM(REG_PG | REG_PC); \
REG_PC+=2; \
write_16_##MODE(DST, REG_IM | REG_IM2);
#endif
@ -1864,7 +1864,7 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
#undef OP_LDT
#define OP_LDT(MODE) \
CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
REG_DB = OPER_8_##MODE()<<16;
REG_DT = OPER_8_##MODE()<<16;
/* M37710 prefix for B accumulator (0x42) */
@ -1872,7 +1872,7 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
#undef OP_PFB
#define OP_PFB() \
CLK(2); \
REG_IR = read_8_IMM(REG_PB | REG_PC); \
REG_IR = read_8_IMM(REG_PG | REG_PC); \
REG_PC++; \
(this->*m_opcodes42[REG_IR])();
@ -1880,7 +1880,7 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
/* M37710 prefix for multiply / divide instructions (0x89) */
#undef OP_PFXM
#define OP_PFXM() \
REG_IR = read_8_IMM(REG_PB | REG_PC); \
REG_IR = read_8_IMM(REG_PG | REG_PC); \
REG_PC++; \
(this->*m_opcodes89[REG_IR])();
@ -1888,7 +1888,7 @@ void m37710_cpu_device::m37710i_set_reg_p(uint32_t value)
/* M37710 unimplemented opcode */
#undef OP_UNIMP
#define OP_UNIMP() \
logerror("error M37710: UNIMPLEMENTED OPCODE! K=%x PC=%x\n", REG_PB, REG_PPC);
logerror("error M37710: UNIMPLEMENTED OPCODE! K=%x PC=%x\n", REG_PG, REG_PPC);
/* ======================================================================== */
/* ======================== OPCODE & FUNCTION TABLES ====================== */
@ -2497,10 +2497,10 @@ TABLE_FUNCTION(uint32_t, get_reg, (int regnum))
case M37710_Y: return REG_Y;
case M37710_S: return REG_S;
case M37710_PC: return REG_PC;
case M37710_PB: return REG_PB >> 16;
case M37710_DB: return REG_DB >> 16;
case M37710_D: return REG_D;
case M37710_P: return m37710i_get_reg_p();
case M37710_PG: return REG_PG >> 16;
case M37710_DT: return REG_DT >> 16;
case M37710_DPR: return REG_DPR;
case M37710_PS: return m37710i_get_reg_ps();
case M37710_IRQ_STATE: return LINE_IRQ;
case STATE_GENPCBASE: return REG_PPC;
}
@ -2513,7 +2513,7 @@ TABLE_FUNCTION(void, set_reg, (int regnum, uint32_t val))
{
case M37710_PC: REG_PC = MAKE_UINT_16(val); break;
case M37710_S: REG_S = MAKE_UINT_16(val); break;
case M37710_P: m37710i_set_reg_p(val); break;
case M37710_PS: m37710i_set_reg_ps(val); break;
#if FLAG_SET_M
case M37710_A: REG_A = MAKE_UINT_8(val); REG_B = val&0xff00; break;
case M37710_B: REG_BA = MAKE_UINT_8(val); REG_BB = val&0xff00; break;
@ -2540,9 +2540,9 @@ TABLE_FUNCTION(int, execute, (int clocks))
do
{
REG_PPC = REG_PC;
M37710_CALL_DEBUGGER(REG_PB | REG_PC);
M37710_CALL_DEBUGGER(REG_PG | REG_PC);
REG_PC++;
REG_IR = read_8_IMM(REG_PB | REG_PPC);
REG_IR = read_8_IMM(REG_PG | REG_PPC);
(this->*m_opcodes[REG_IR])();
} while(CLOCKS > 0);
return clocks - CLOCKS;

16
src/devices/cpu/m37710/m7700ds.cpp
View File

@ -319,9 +319,9 @@ offs_t m7700_disassembler::disassemble(std::ostream &stream, offs_t pc, const da
uint32_t flags = 0;
offs_t address = pc;
u32 pb = pc & 0xffff0000;
u32 pg = pc & 0xff0000;
pc &= 0xffff;
address = pc | pb;
address = pc | pg;
instruction = opcodes.r8(address);
@ -370,13 +370,13 @@ offs_t m7700_disassembler::disassemble(std::ostream &stream, offs_t pc, const da
case RELB:
varS = opcodes.r8(address + 1);
length++;
util::stream_format(stream, " %06x (%s)", pb | ((pc + length + varS)&0xffff), int_8_str(varS));
util::stream_format(stream, " %06x (%s)", pg | ((pc + length + varS)&0xffff), int_8_str(varS));
break;
case RELW:
case PER :
var = opcodes.r16(address + 1);
length += 2;
util::stream_format(stream, " %06x (%s)", pb | ((pc + length + var)&0xffff), int_16_str(var));
util::stream_format(stream, " %06x (%s)", pg | ((pc + length + var)&0xffff), int_16_str(var));
break;
case IMM :
if((opcode->flag == M && !m_flag) || (opcode->flag == X && !x_flag))
@ -395,13 +395,13 @@ offs_t m7700_disassembler::disassemble(std::ostream &stream, offs_t pc, const da
{
varS = opcodes.r8(address + 4);
length += 4;
util::stream_format(stream, " #$%04x, $%02x, %06x (%s)", opcodes.r16(address + 2), opcodes.r8(address + 1), pb | ((pc + length + varS)&0xffff), int_8_str(varS));
util::stream_format(stream, " #$%04x, $%02x, %06x (%s)", opcodes.r16(address + 2), opcodes.r8(address + 1), pg | ((pc + length + varS)&0xffff), int_8_str(varS));
}
else
{
varS = opcodes.r8(address + 3);
length += 3;
util::stream_format(stream, " #$%02x, $%02x, %06x (%s)", opcodes.r8(address + 2), opcodes.r8(address + 1), pb | ((pc + length + varS)&0xffff), int_8_str(varS));
util::stream_format(stream, " #$%02x, $%02x, %06x (%s)", opcodes.r8(address + 2), opcodes.r8(address + 1), pg | ((pc + length + varS)&0xffff), int_8_str(varS));
}
break;
case BBCA:
@ -409,13 +409,13 @@ offs_t m7700_disassembler::disassemble(std::ostream &stream, offs_t pc, const da
{
length += 5;
varS = opcodes.r8(address + 5);
util::stream_format(stream, " #$%04x, $%04x, %06x (%s)", opcodes.r16(address + 3), opcodes.r16(address + 1), pb | ((pc + length + varS)&0xffff), int_8_str(varS));
util::stream_format(stream, " #$%04x, $%04x, %06x (%s)", opcodes.r16(address + 3), opcodes.r16(address + 1), pg | ((pc + length + varS)&0xffff), int_8_str(varS));
}
else
{
length += 4;
varS = opcodes.r8(address + 4);
util::stream_format(stream, " #$%02x, $%04x, %06x (%s)", opcodes.r8(address + 3), opcodes.r16(address + 1), pb | ((pc + length + varS)&0xffff), int_8_str(varS));
util::stream_format(stream, " #$%02x, $%04x, %06x (%s)", opcodes.r8(address + 3), opcodes.r16(address + 1), pg | ((pc + length + varS)&0xffff), int_8_str(varS));
}
break;
case LDM4:

12
src/devices/machine/am79c30.cpp
View File

@ -386,7 +386,7 @@ void am79c30a_device::set_lmr1(u8 data)
if (BIT(data, 6) != BIT(m_lmr1, 6))
LOG("%s: LIU receiver/transmitter %sabled\n", machine().describe_context(), BIT(data, 6) ? "en" : "dis");
if (BIT(data, 7))
logerror("%s: LMR1 reserved bit 7 set\n");
logerror("%s: LMR1 reserved bit 7 set\n", machine().describe_context());
m_lmr1 = data;
}
@ -414,7 +414,7 @@ void am79c30a_device::set_lmr2(u8 data)
if (BIT(data, 6) != BIT(m_lmr2, 6))
LOG("%s: F7 change of state interrupt %sabled\n", machine().describe_context(), BIT(data, 6) ? "en" : "dis");
if (BIT(data, 7))
logerror("%s: LMR2 reserved bit 7 set\n");
logerror("%s: LMR2 reserved bit 7 set\n", machine().describe_context());
m_lmr2 = data;
}
@ -492,9 +492,9 @@ void am79c30a_device::set_mcr(unsigned n, u8 data)
if (data == 0)
LOG("%s: No connect (MCR%d)\n", machine().describe_context(), n + 1);
else if ((data & 0xf0) >> 4 == (data & 0x0f))
LOG("%s: %s loopback (MCR%d)\n", machine().describe_context(), data & 0x0f, n + 1);
LOG("%s: %s loopback (MCR%d)\n", machine().describe_context(), s_mcr_channels[data & 0x0f], n + 1);
else
LOG("%s: %s <-> %s (MCR%d)\n", machine().describe_context(), (data & 0xf0) >> 4, data & 0x0f, n + 1);
LOG("%s: %s <-> %s (MCR%d)\n", machine().describe_context(), s_mcr_channels[(data & 0xf0) >> 4], s_mcr_channels[data & 0x0f], n + 1);
}
m_mcr[n] = data;
@ -753,7 +753,9 @@ void am79c30a_device::set_stra(u8 data)
else
{
u8 a = 15 - ((data & 0xf0) >> 4);
LOG("%s: Secondary tone ringer %.2f V peak-to-peak, %d dB relative\n", BIT(a, 0) ? 3.53553390593274 : 5.0 / (1 << (a / 2)), a * -3);
LOG("%s: Secondary tone ringer %.2f V peak-to-peak, %d dB relative\n", machine().describe_context(),
BIT(a, 0) ? 3.53553390593274 : 5.0 / (1 << (a / 2)),
a * -3);
}
}

4
src/devices/machine/i8087.cpp
View File

@ -259,13 +259,13 @@ void i8087_device::execute()
m_timer->adjust(attotime::from_hz((m_icount ? m_icount : 1) * clock()));
}
WRITE32_MEMBER(i8087_device::insn_w)
void i8087_device::insn_w(uint32_t data)
{
m_ppc = m_pc;
m_pc = data;
}
WRITE32_MEMBER(i8087_device::addr_w)
void i8087_device::addr_w(uint32_t data)
{
m_ea = data;
execute();

4
src/devices/machine/i8087.h
View File

@ -19,8 +19,8 @@ public:
auto irq() { return m_int_handler.bind(); }
auto busy() { return m_busy_handler.bind(); }
DECLARE_WRITE32_MEMBER(insn_w); // the real 8087 sniffs the bus watching for esc, can't do that here so provide a poke spot
DECLARE_WRITE32_MEMBER(addr_w);
void insn_w(uint32_t data); // the real 8087 sniffs the bus watching for esc, can't do that here so provide a poke spot
void addr_w(uint32_t data);
protected:
i8087_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock);

2
src/devices/machine/i8155.cpp
View File

@ -245,10 +245,10 @@ inline uint8_t i8155_device::read_port(int port)
inline void i8155_device::write_port(int port, uint8_t data)
{
m_output[port] = data;
switch (get_port_mode(port))
{
case PORT_MODE_OUTPUT:
m_output[port] = data;
if (port == PORT_A)
m_out_pa_cb((offs_t)0, m_output[port]);
else if (port == PORT_B)

4
src/devices/machine/mm74c922.cpp
View File

@ -18,7 +18,7 @@
// DEVICE DEFINITIONS
//**************************************************************************
DEFINE_DEVICE_TYPE(MM74C922, mm74c922_device, "mm74c922", "MM74C923 16-Key Encoder")
DEFINE_DEVICE_TYPE(MM74C922, mm74c922_device, "mm74c922", "MM74C922 16-Key Encoder")
DEFINE_DEVICE_TYPE(MM74C923, mm74c923_device, "mm74c923", "MM74C923 20-Key Encoder")
@ -72,7 +72,7 @@ void mm74c922_device::device_start()
// allocate timers
m_scan_timer = timer_alloc();
m_scan_timer->adjust(attotime::zero, 0, attotime::from_hz(50));
m_scan_timer->adjust(attotime::zero, 0, attotime::from_hz(500)); // approximate rate from a 100n capacitor
// register for state saving
save_item(NAME(m_inhibit));

36
src/devices/machine/netlist.cpp
View File

@ -639,9 +639,9 @@ netlist::setup_t &netlist_mame_device::setup()
return m_netlist->setup();
}
void netlist_mame_device::register_memregion_source(netlist::nlparse_t &setup, device_t &dev, const char *name)
void netlist_mame_device::register_memregion_source(netlist::nlparse_t &parser, device_t &dev, const char *name)
{
setup.register_source<netlist_source_memregion_t>(dev, pstring(name));
parser.register_source<netlist_source_memregion_t>(dev, pstring(name));
}
void netlist_mame_analog_input_device::write(const double val)
@ -781,16 +781,14 @@ void netlist_mame_analog_output_device::custom_netlist_additions(netlist::netlis
{
const pstring pin(m_in);
pstring dname = pstring("OUT_") + pin;
pstring dfqn = nlstate.parser().build_fqn(dname);
/* ignore if no running machine -> called within device_validity_check context */
if (owner()->has_running_machine())
m_delegate.resolve();
auto dev = nlstate.make_object<NETLIB_NAME(analog_callback)>(nlstate, dfqn);
//static_cast<NETLIB_NAME(analog_callback) *>(dev.get())->register_callback(std::move(m_delegate));
auto dev = nlstate.make_object<NETLIB_NAME(analog_callback)>(nlstate, dname);
dev->register_callback(std::move(m_delegate));
nlstate.register_device(dfqn, std::move(dev));
nlstate.register_device(dname, std::move(dev));
nlstate.parser().register_link(dname + ".IN", pin);
}
@ -816,15 +814,14 @@ void netlist_mame_logic_output_device::custom_netlist_additions(netlist::netlist
{
pstring pin(m_in);
pstring dname = "OUT_" + pin;
pstring dfqn = nlstate.parser().build_fqn(dname);
/* ignore if no running machine -> called within device_validity_check context */
if (owner()->has_running_machine())
m_delegate.resolve();
auto dev = nlstate.make_object<NETLIB_NAME(logic_callback)>(nlstate, dfqn);
auto dev = nlstate.make_object<NETLIB_NAME(logic_callback)>(nlstate, dname);
dev->register_callback(std::move(m_delegate));
nlstate.register_device(dfqn, std::move(dev));
nlstate.register_device(dname, std::move(dev));
nlstate.parser().register_link(dname + ".IN", pin);
}
@ -1086,14 +1083,14 @@ void netlist_mame_device::common_dev_start(netlist::netlist_state_t *lnetlist) c
bool err=false;
bool v = plib::pstonum_ne<bool>(p, err);
if (err)
lsetup.parser().log().warning("NL_STATS: invalid value {1}", p);
lsetup.log().warning("NL_STATS: invalid value {1}", p);
else
lnetlist->exec().enable_stats(v);
}
// register additional devices
nl_register_devices(lsetup);
nl_register_devices(lsetup.parser());
/* let sub-devices add sources and do stuff prior to parsing */
for (device_t &d : subdevices())
@ -1102,7 +1099,7 @@ void netlist_mame_device::common_dev_start(netlist::netlist_state_t *lnetlist) c
if( sdev != nullptr )
{
LOGDEVCALLS("Preparse subdevice %s/%s\n", d.name(), d.shortname());
sdev->pre_parse_action(*lnetlist);
sdev->pre_parse_action(lsetup.parser());
}
}
@ -1112,7 +1109,6 @@ void netlist_mame_device::common_dev_start(netlist::netlist_state_t *lnetlist) c
m_setup_func(lsetup.parser());
#if 1
/* let sub-devices tweak the netlist */
for (device_t &d : subdevices())
{
@ -1123,8 +1119,6 @@ void netlist_mame_device::common_dev_start(netlist::netlist_state_t *lnetlist) c
sdev->custom_netlist_additions(*lnetlist);
}
}
lsetup.prepare_to_run();
#endif
}
plib::unique_ptr<netlist::netlist_state_t> netlist_mame_device::base_validity_check(validity_checker &valid) const
@ -1135,6 +1129,7 @@ plib::unique_ptr<netlist::netlist_state_t> netlist_mame_device::base_validity_ch
// enable validation mode
lnetlist->set_extended_validation(true);
common_dev_start(lnetlist.get());
lnetlist->setup().prepare_to_run();
for (device_t &d : subdevices())
{
@ -1184,6 +1179,7 @@ void netlist_mame_device::device_start()
}
common_dev_start(m_netlist.get());
m_netlist->setup().prepare_to_run();
m_netlist->save(*this, m_rem, pstring(this->name()), "m_rem");
m_netlist->save(*this, m_div, pstring(this->name()), "m_div");
@ -1334,9 +1330,9 @@ void netlist_mame_cpu_device::device_start()
}
void netlist_mame_cpu_device::nl_register_devices(netlist::setup_t &lsetup) const
void netlist_mame_cpu_device::nl_register_devices(netlist::nlparse_t &parser) const
{
lsetup.parser().factory().add<nld_analog_callback>( "NETDEV_CALLBACK", "-", __FILE__);
parser.factory().add<nld_analog_callback>( "NETDEV_CALLBACK", "-", __FILE__);
}
uint64_t netlist_mame_cpu_device::execute_clocks_to_cycles(uint64_t clocks) const noexcept
@ -1487,10 +1483,10 @@ void netlist_mame_sound_device::device_start()
}
void netlist_mame_sound_device::nl_register_devices(netlist::setup_t &lsetup) const
void netlist_mame_sound_device::nl_register_devices(netlist::nlparse_t &parser) const
{
lsetup.parser().factory().add<nld_sound_out>("NETDEV_SOUND_OUT", "+CHAN", __FILE__);
lsetup.parser().factory().add<nld_sound_in>("NETDEV_SOUND_IN", "-", __FILE__);
parser.factory().add<nld_sound_out>("NETDEV_SOUND_OUT", "+CHAN", __FILE__);
parser.factory().add<nld_sound_in>("NETDEV_SOUND_IN", "-", __FILE__);
}
void netlist_mame_sound_device::sound_stream_update(sound_stream &stream, stream_sample_t **inputs, stream_sample_t **outputs, int samples)

10
src/devices/machine/netlist.h
View File

@ -78,7 +78,7 @@ public:
void update_icount(netlist::netlist_time_ext time) noexcept;
void check_mame_abort_slice() noexcept;
static void register_memregion_source(netlist::nlparse_t &setup, device_t &dev, const char *name);
static void register_memregion_source(netlist::nlparse_t &parser, device_t &dev, const char *name);
int m_icount;
@ -99,7 +99,7 @@ protected:
netlist_mame_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
// Custom to netlist ...
virtual void nl_register_devices(netlist::setup_t &lsetup) const { }
virtual void nl_register_devices(netlist::nlparse_t &parser) const { }
// device_t overrides
virtual void device_config_complete() override;
@ -178,7 +178,7 @@ public:
protected:
// netlist_mame_device
virtual void nl_register_devices(netlist::setup_t &lsetup) const override;
virtual void nl_register_devices(netlist::nlparse_t &parser) const override;
// device_t overrides
virtual void device_start() override;
@ -238,7 +238,7 @@ public:
protected:
// netlist_mame_device
virtual void nl_register_devices(netlist::setup_t &lsetup) const override;
virtual void nl_register_devices(netlist::nlparse_t &parser) const override;
// device_t overrides
virtual void device_start() override;
@ -269,7 +269,7 @@ public:
}
virtual void custom_netlist_additions(netlist::netlist_state_t &nlstate) { }
virtual void pre_parse_action(netlist::netlist_state_t &nlstate) { }
virtual void pre_parse_action(netlist::nlparse_t &parser) { }
virtual void validity_helper(validity_checker &valid,
netlist::netlist_state_t &nlstate) const { }

2
src/devices/machine/phi.cpp
View File

@ -243,7 +243,7 @@ WRITE_LINE_MEMBER(phi_device::ren_w)
set_ext_signal(PHI_488_REN , state);
}
WRITE8_MEMBER(phi_device::bus_dio_w)
void phi_device::bus_dio_w(uint8_t data)
{
update_pp();
}

2
src/devices/machine/phi.h
View File

@ -60,7 +60,7 @@ public:
DECLARE_WRITE_LINE_MEMBER(atn_w);
DECLARE_WRITE_LINE_MEMBER(ren_w);
DECLARE_WRITE8_MEMBER(bus_dio_w);
void bus_dio_w(uint8_t data);
void set_ext_signal(phi_488_signal_t signal , int state);

12
src/devices/sound/dac.h
View File

@ -27,21 +27,21 @@ class dac_bit_interface
{
public:
virtual DECLARE_WRITE_LINE_MEMBER(write) = 0;
virtual DECLARE_WRITE8_MEMBER(data_w) = 0;
virtual void data_w(uint8_t data) = 0;
};
class dac_byte_interface
{
public:
virtual void write(unsigned char data) = 0;
virtual DECLARE_WRITE8_MEMBER(data_w) = 0;
virtual void data_w(uint8_t data) = 0;
};
class dac_word_interface
{
public:
virtual void write(unsigned short data) = 0;
virtual DECLARE_WRITE16_MEMBER(data_w) = 0;
virtual void data_w(uint16_t data) = 0;
};
template <unsigned bits>
@ -213,7 +213,7 @@ public:
}
virtual WRITE_LINE_MEMBER(write) override { this->setCode(state); }
virtual WRITE8_MEMBER(data_w) override { this->setCode(data); }
virtual void data_w(uint8_t data) override { this->setCode(data); }
};
template <typename _dac_code>
@ -228,7 +228,7 @@ public:
}
virtual void write(unsigned char data) override { this->setCode(data); }
virtual DECLARE_WRITE8_MEMBER(data_w) override { this->setCode(data); }
virtual void data_w(uint8_t data) override { this->setCode(data); }
};
template <typename _dac_code>
@ -243,7 +243,7 @@ public:
}
virtual void write(unsigned short data) override { this->setCode(data); }
virtual DECLARE_WRITE16_MEMBER(data_w) override { this->setCode(data); }
virtual void data_w(uint16_t data) override { this->setCode(data); }
};
constexpr double dac_gain_r2r = 1.0;

4
src/devices/sound/l7a1045_l6028_dsp_a.h
View File

@ -24,8 +24,8 @@ public:
DECLARE_READ8_MEMBER(dma_r_cb);
DECLARE_WRITE8_MEMBER(dma_w_cb);
DECLARE_READ16_MEMBER(dma_r16_cb) { m_voice[0].pos++; return 0; }
DECLARE_WRITE16_MEMBER(dma_w16_cb) { m_voice[0].pos++; }
uint16_t dma_r16_cb() { m_voice[0].pos++; return 0; }
void dma_w16_cb(uint16_t data) { m_voice[0].pos++; }
DECLARE_WRITE_LINE_MEMBER(dma_hreq_cb);
protected:

4
src/devices/sound/mos7360.cpp
View File

@ -818,7 +818,7 @@ void mos7360_device::soundport_w(int offset, int data)
// read - register read
//-------------------------------------------------
uint8_t mos7360_device::read(address_space &space, offs_t offset, int &cs0, int &cs1)
uint8_t mos7360_device::read(offs_t offset, int &cs0, int &cs1)
{
uint8_t val = m_last_data;
@ -902,7 +902,7 @@ uint8_t mos7360_device::read(address_space &space, offs_t offset, int &cs0, int
// write - register write
//-------------------------------------------------
void mos7360_device::write(address_space &space, offs_t offset, uint8_t data, int &cs0, int &cs1)
void mos7360_device::write(offs_t offset, uint8_t data, int &cs0, int &cs1)
{
int old;

4
src/devices/sound/mos7360.h
View File

@ -83,8 +83,8 @@ public:
virtual space_config_vector memory_space_config() const override;
uint8_t read(address_space &space, offs_t offset, int &cs0, int &cs1);
void write(address_space &space, offs_t offset, uint8_t data, int &cs0, int &cs1);
uint8_t read(offs_t offset, int &cs0, int &cs1);
void write(offs_t offset, uint8_t data, int &cs0, int &cs1);
uint32_t screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);

14
src/devices/video/hd44780.cpp
View File

@ -23,6 +23,7 @@
//**************************************************************************
DEFINE_DEVICE_TYPE(HD44780, hd44780_device, "hd44780_a00", "Hitachi HD44780 A00 LCD Controller")
DEFINE_DEVICE_TYPE(SED1278_0B, sed1278_0b_device, "sed1278_0b", "Epson SED1278-0B LCD Controller") // packaged as either SED1278F0B or SED1278D0B
DEFINE_DEVICE_TYPE(KS0066_F05, ks0066_f05_device, "ks0066_f05", "Samsung KS0066 F05 LCD Controller")
@ -35,6 +36,11 @@ ROM_START( hd44780_a00 )
ROM_LOAD( "hd44780_a00.bin", 0x0000, 0x1000, BAD_DUMP CRC(01d108e2) SHA1(bc0cdf0c9ba895f22e183c7bd35a3f655f2ca96f)) // from page 17 of the HD44780 datasheet
ROM_END
ROM_START( sed1278_0b )
ROM_REGION( 0x1000, "cgrom", 0 )
ROM_LOAD( "sed1278_0b.bin", 0x0000, 0x1000, BAD_DUMP CRC(eef342fa) SHA1(d6ac58a48e428e7cff26fb9c8ea9b4eeaa853038)) // from page 9-33 of the SED1278 datasheet
ROM_END
ROM_START( ks0066_f05 )
ROM_REGION( 0x1000, "cgrom", 0 )
ROM_LOAD( "ks0066_f05.bin", 0x0000, 0x1000, BAD_DUMP CRC(af9e7bd6) SHA1(0196e871584ee5d370856e7307c0f9d1466e3e51)) // from page 51 of the KS0066 datasheet
@ -67,6 +73,12 @@ hd44780_device::hd44780_device(const machine_config &mconfig, device_type type,
{
}
sed1278_0b_device::sed1278_0b_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
hd44780_device(mconfig, SED1278_0B, tag, owner, clock)
{
set_charset_type(CHARSET_SED1278_0B);
}
ks0066_f05_device::ks0066_f05_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
hd44780_device(mconfig, KS0066_F05, tag, owner, clock)
{
@ -83,6 +95,7 @@ const tiny_rom_entry *hd44780_device::device_rom_region() const
switch (m_charset_type)
{
case CHARSET_HD44780_A00: return ROM_NAME( hd44780_a00 );
case CHARSET_SED1278_0B: return ROM_NAME( sed1278_0b );
case CHARSET_KS0066_F05: return ROM_NAME( ks0066_f05 );
}
@ -479,6 +492,7 @@ void hd44780_device::control_write(u8 data)
logerror("HD44780: function set cannot be executed after other instructions unless the interface data length is changed\n");
return;
}
m_first_cmd = true;
m_char_size = BIT(m_ir, 2) ? 10 : 8;
m_data_len = BIT(m_ir, 4) ? 8 : 4;

11
src/devices/video/hd44780.h
View File

@ -66,6 +66,7 @@ protected:
enum
{
CHARSET_HD44780_A00,
CHARSET_SED1278_0B,
CHARSET_KS0066_F05 /*,
CHARSET_HD44780_A01,
CHARSET_HD44780_A02,
@ -138,6 +139,15 @@ private:
enum { DDRAM, CGRAM };
};
// ======================> sed1278_0b_device
class sed1278_0b_device : public hd44780_device
{
public:
// construction/destruction
sed1278_0b_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
};
// ======================> ks0066_f05_device
class ks0066_f05_device : public hd44780_device
@ -149,6 +159,7 @@ public:
// device type definition
DECLARE_DEVICE_TYPE(HD44780, hd44780_device)
DECLARE_DEVICE_TYPE(SED1278_0B, sed1278_0b_device)
DECLARE_DEVICE_TYPE(KS0066_F05, ks0066_f05_device)
#endif // MAME_VIDEO_HD44780_H

29
src/devices/video/mc6845.cpp
View File

@ -66,7 +66,6 @@ DEFINE_DEVICE_TYPE(HD6845S, hd6845s_device, "hd6845s", "Hitachi HD6845S CRTC"
DEFINE_DEVICE_TYPE(SY6545_1, sy6545_1_device, "sy6545_1", "Synertek SY6545-1 CRTC")
DEFINE_DEVICE_TYPE(SY6845E, sy6845e_device, "sy6845e", "Synertek SY6845E CRTC")
DEFINE_DEVICE_TYPE(HD6345, hd6345_device, "hd6345", "Hitachi HD6345 CRTC")
DEFINE_DEVICE_TYPE(AMS40041, ams40041_device, "ams40041", "AMS40041 CRTC")
DEFINE_DEVICE_TYPE(AMS40489, ams40489_device, "ams40489", "AMS40489 ASIC (CRTC)")
DEFINE_DEVICE_TYPE(MOS8563, mos8563_device, "mos8563", "MOS 8563 VDC")
DEFINE_DEVICE_TYPE(MOS8568, mos8568_device, "mos8568", "MOS 8568 VDC")
@ -1348,28 +1347,6 @@ void hd6345_device::device_start()
}
void ams40041_device::device_start()
{
mc6845_device::device_start();
m_horiz_char_total = 113;
m_horiz_disp = 80;
m_horiz_sync_pos = 90;
m_sync_width = 10;
m_vert_char_total = 127;
m_vert_total_adj = 6;
m_vert_disp = 100;
m_vert_sync_pos = 112;
m_mode_control = 2;
m_supports_disp_start_addr_r = false;
m_supports_vert_sync_width = false;
m_supports_status_reg_d5 = false;
m_supports_status_reg_d6 = false;
m_supports_status_reg_d7 = false;
m_supports_transparent = false;
}
void ams40489_device::device_start()
{
mc6845_device::device_start();
@ -1505,7 +1482,6 @@ void c6545_1_device::device_reset() { mc6845_device::device_reset(); }
void sy6545_1_device::device_reset() { mc6845_device::device_reset(); }
void sy6845e_device::device_reset() { mc6845_device::device_reset(); }
void hd6345_device::device_reset() { mc6845_device::device_reset(); }
void ams40041_device::device_reset() { mc6845_device::device_reset(); }
void ams40489_device::device_reset() { mc6845_device::device_reset(); }
void mos8563_device::device_reset()
@ -1586,11 +1562,6 @@ hd6345_device::hd6345_device(const machine_config &mconfig, const char *tag, dev
}
ams40041_device::ams40041_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: mc6845_device(mconfig, AMS40041, tag, owner, clock)
{
}
ams40489_device::ams40489_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: mc6845_device(mconfig, AMS40489, tag, owner, clock)
{

11
src/devices/video/mc6845.h
View File

@ -373,16 +373,6 @@ protected:
virtual void device_reset() override;
};
class ams40041_device : public mc6845_device
{
public:
ams40041_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:
virtual void device_start() override;
virtual void device_reset() override;
};
class ams40489_device : public mc6845_device
{
public:
@ -481,7 +471,6 @@ DECLARE_DEVICE_TYPE(HD6845S, hd6845s_device)
DECLARE_DEVICE_TYPE(SY6545_1, sy6545_1_device)
DECLARE_DEVICE_TYPE(SY6845E, sy6845e_device)
DECLARE_DEVICE_TYPE(HD6345, hd6345_device)
DECLARE_DEVICE_TYPE(AMS40041, ams40041_device)
DECLARE_DEVICE_TYPE(AMS40489, ams40489_device)
DECLARE_DEVICE_TYPE(MOS8563, mos8563_device)
DECLARE_DEVICE_TYPE(MOS8568, mos8568_device)

45
src/lib/netlist/analog/nld_bjt.cpp
View File

@ -47,6 +47,11 @@ namespace analog
// nld_Q - Base classes
// -----------------------------------------------------------------------------
enum class bjt_type {
BJT_NPN,
BJT_PNP
};
/// \brief Class representing the bjt model parameters.
///
/// This is the model representation of the bjt model. Typically, SPICE uses
@ -101,7 +106,8 @@ namespace analog
{
public:
bjt_model_t(param_model_t &model)
: m_IS (model, "IS")
: m_type((model.type() == "NPN") ? bjt_type::BJT_NPN : bjt_type::BJT_PNP)
, m_IS (model, "IS")
, m_BF (model, "BF")
, m_NF (model, "NF")
, m_BR (model, "BR")
@ -110,6 +116,7 @@ namespace analog
, m_CJC(model, "CJC")
{}
bjt_type m_type;
param_model_t::value_t m_IS; //!< transport saturation current
param_model_t::value_t m_BF; //!< ideal maximum forward beta
param_model_t::value_t m_NF; //!< forward current emission coefficient
@ -125,14 +132,10 @@ namespace analog
NETLIB_BASE_OBJECT(QBJT)
{
public:
enum q_type {
BJT_NPN,
BJT_PNP
};
NETLIB_CONSTRUCTOR_EX(QBJT, const pstring &model = "NPN")
, m_model(*this, "MODEL", model)
, m_qtype(BJT_NPN)
, m_qtype(bjt_type::BJT_NPN)
{
}
@ -141,14 +144,14 @@ namespace analog
//NETLIB_RESETI();
NETLIB_UPDATEI();
q_type qtype() const noexcept { return m_qtype; }
bool is_qtype(q_type atype) const noexcept { return m_qtype == atype; }
void set_qtype(q_type atype) noexcept { m_qtype = atype; }
bjt_type qtype() const noexcept { return m_qtype; }
bool is_qtype(bjt_type atype) const noexcept { return m_qtype == atype; }
void set_qtype(bjt_type atype) noexcept { m_qtype = atype; }
protected:
param_model_t m_model;
private:
q_type m_qtype;
bjt_type m_qtype;
};
// -----------------------------------------------------------------------------
@ -172,6 +175,7 @@ namespace analog
NETLIB_OBJECT_DERIVED(QBJT_switch, QBJT)
{
NETLIB_CONSTRUCTOR(QBJT_switch)
, m_modacc(m_model)
, m_RB(*this, "m_RB", true)
, m_RC(*this, "m_RC", true)
, m_BC(*this, "m_BC", true)
@ -195,6 +199,7 @@ namespace analog
NETLIB_UPDATE_TERMINALSI();
private:
bjt_model_t m_modacc;
nld_twoterm m_RB;
nld_twoterm m_RC;
nld_twoterm m_BC;
@ -314,15 +319,13 @@ namespace analog
NETLIB_UPDATE_PARAM(QBJT_switch)
{
bjt_model_t model(m_model);
nl_fptype IS = model.m_IS;
nl_fptype BF = model.m_BF;
nl_fptype NF = model.m_NF;
//nl_fptype VJE = model.dValue("VJE", 0.75);
nl_fptype IS = m_modacc.m_IS;
nl_fptype BF = m_modacc.m_BF;
nl_fptype NF = m_modacc.m_NF;
//nl_fptype VJE = m_modacc.dValue("VJE", 0.75);
// FIXME: check for PNP as well and bail out
set_qtype((m_model.type() == "NPN") ? BJT_NPN : BJT_PNP);
set_qtype(m_modacc.m_type);
nl_fptype alpha = BF / (nlconst::one() + BF);
@ -347,7 +350,7 @@ namespace analog
NETLIB_UPDATE_TERMINALS(QBJT_switch)
{
const nl_fptype m = (is_qtype( BJT_NPN) ? 1 : -1);
const nl_fptype m = (is_qtype( bjt_type::BJT_NPN) ? 1 : -1);
const unsigned new_state = (m_RB.deltaV() * m > m_V ) ? 1 : 0;
if (m_state_on ^ new_state)
@ -398,7 +401,7 @@ namespace analog
NETLIB_UPDATE_TERMINALS(QBJT_EB)
{
const nl_fptype polarity(qtype() == BJT_NPN ? nlconst::one() : -nlconst::one());
const nl_fptype polarity(qtype() == bjt_type::BJT_NPN ? nlconst::one() : -nlconst::one());
m_gD_BE.update_diode(-m_D_EB.deltaV() * polarity);
m_gD_BC.update_diode(-m_D_CB.deltaV() * polarity);
@ -430,10 +433,10 @@ namespace analog
nl_fptype NF = m_modacc.m_NF;
nl_fptype BR = m_modacc.m_BR;
nl_fptype NR = m_modacc.m_NR;
//nl_fptype VJE = m_model.dValue("VJE", 0.75);
//nl_fptype VJE = m_m_modacc.dValue("VJE", 0.75);
// FIXME: check for PNP as well and bail out
set_qtype((m_model.type() == "NPN") ? BJT_NPN : BJT_PNP);
set_qtype(m_modacc.m_type);
m_alpha_f = BF / (nlconst::one() + BF);
m_alpha_r = BR / (nlconst::one() + BR);

24
src/lib/netlist/analog/nlid_twoterm.cpp
View File

@ -145,9 +145,8 @@ namespace analog
NETLIB_RESET(D)
{
diode_model_t modacc(m_model);
nl_fptype Is = modacc.m_IS;
nl_fptype n = modacc.m_N;
nl_fptype Is = m_modacc.m_IS;
nl_fptype n = m_modacc.m_N;
m_D.set_param(Is, n, exec().gmin(), nlconst::T0());
set_G_V_I(m_D.G(), nlconst::zero(), m_D.Ieq());
@ -155,9 +154,8 @@ namespace analog
NETLIB_UPDATE_PARAM(D)
{
diode_model_t modacc(m_model);
nl_fptype Is = modacc.m_IS;
nl_fptype n = modacc.m_N;
nl_fptype Is = m_modacc.m_IS;
nl_fptype n = m_modacc.m_N;
m_D.set_param(Is, n, exec().gmin(), nlconst::T0());
}
@ -178,21 +176,19 @@ namespace analog
NETLIB_RESET(Z)
{
zdiode_model_t modacc(m_model);
nl_fptype IsBV = modacc.m_IBV / (plib::exp(modacc.m_BV / nlconst::np_VT(modacc.m_NBV)) - nlconst::one());
nl_fptype IsBV = m_modacc.m_IBV / (plib::exp(m_modacc.m_BV / nlconst::np_VT(m_modacc.m_NBV)) - nlconst::one());
m_D.set_param(modacc.m_IS, modacc.m_N, exec().gmin(), nlconst::T0());
m_R.set_param(IsBV, modacc.m_NBV, exec().gmin(), nlconst::T0());
m_D.set_param(m_modacc.m_IS, m_modacc.m_N, exec().gmin(), nlconst::T0());
m_R.set_param(IsBV, m_modacc.m_NBV, exec().gmin(), nlconst::T0());
set_G_V_I(m_D.G(), nlconst::zero(), m_D.Ieq());
}
NETLIB_UPDATE_PARAM(Z)
{
zdiode_model_t modacc(m_model);
nl_fptype IsBV = modacc.m_IBV / (plib::exp(modacc.m_BV / nlconst::np_VT(modacc.m_NBV)) - nlconst::one());
nl_fptype IsBV = m_modacc.m_IBV / (plib::exp(m_modacc.m_BV / nlconst::np_VT(m_modacc.m_NBV)) - nlconst::one());
m_D.set_param(modacc.m_IS, modacc.m_N, exec().gmin(), nlconst::T0());
m_R.set_param(IsBV, modacc.m_NBV, exec().gmin(), nlconst::T0());
m_D.set_param(m_modacc.m_IS, m_modacc.m_N, exec().gmin(), nlconst::T0());
m_R.set_param(IsBV, m_modacc.m_NBV, exec().gmin(), nlconst::T0());
set_G_V_I(m_D.G(), nlconst::zero(), m_D.Ieq());
}

4
src/lib/netlist/analog/nlid_twoterm.h
View File

@ -488,6 +488,7 @@ namespace analog
public:
NETLIB_CONSTRUCTOR_EX(D, const pstring &model = "D")
, m_model(*this, "MODEL", model)
, m_modacc(m_model)
, m_D(*this, "m_D")
{
register_subalias("A", P());
@ -504,6 +505,7 @@ namespace analog
private:
param_model_t m_model;
diode_model_t m_modacc;
generic_diode<diode_e::BIPOLAR> m_D;
};
@ -516,6 +518,7 @@ namespace analog
public:
NETLIB_CONSTRUCTOR_EX(Z, const pstring &model = "D")
, m_model(*this, "MODEL", model)
, m_modacc(m_model)
, m_D(*this, "m_D")
, m_R(*this, "m_R")
{
@ -533,6 +536,7 @@ namespace analog
private:
param_model_t m_model;
zdiode_model_t m_modacc;
generic_diode<diode_e::BIPOLAR> m_D;
// REVERSE diode
generic_diode<diode_e::BIPOLAR> m_R;

3
src/lib/netlist/build/makefile
View File

@ -145,6 +145,7 @@ NLOBJS := \
$(NLOBJ)/devices/nld_2716.o \
$(NLOBJ)/devices/nld_tms4800.o \
$(NLOBJ)/devices/nld_4006.o \
$(NLOBJ)/devices/nld_4013.o \
$(NLOBJ)/devices/nld_4020.o \
$(NLOBJ)/devices/nld_4066.o \
$(NLOBJ)/devices/nld_4316.o \
@ -162,6 +163,7 @@ NLOBJS := \
$(NLOBJ)/devices/nld_7497.o \
$(NLOBJ)/devices/nld_74107.o \
$(NLOBJ)/devices/nld_74123.o \
$(NLOBJ)/devices/nld_74125.o \
$(NLOBJ)/devices/nld_74153.o \
$(NLOBJ)/devices/nld_74161.o \
$(NLOBJ)/devices/nld_74164.o \
@ -173,6 +175,7 @@ NLOBJS := \
$(NLOBJ)/devices/nld_74193.o \
$(NLOBJ)/devices/nld_74194.o \
$(NLOBJ)/devices/nld_74365.o \
$(NLOBJ)/devices/nld_74377.o \
$(NLOBJ)/devices/nld_74393.o \
$(NLOBJ)/devices/nld_74ls629.o \
$(NLOBJ)/devices/nld_82S16.o \

1
src/lib/netlist/buildVS/netlistlib.vcxproj
View File

@ -123,6 +123,7 @@
<ClCompile Include="..\devices\nld_7497.cpp" />
<ClCompile Include="..\devices\nld_schmitt.cpp" />
<ClCompile Include="..\devices\nld_tms4800.cpp" />
<ClCompile Include="..\devices\nld_4013.cpp" />
<ClCompile Include="..\devices\nld_4020.cpp" />
<ClCompile Include="..\devices\nld_4066.cpp" />
<ClCompile Include="..\devices\nld_4316.cpp" />

6
src/lib/netlist/buildVS/netlistlib.vcxproj.filters
View File

@ -105,6 +105,9 @@
<ClCompile Include="..\devices\nld_82S115.cpp">
<Filter>Source Files</Filter>
</ClCompile>
<ClCompile Include="..\devices\nld_4013.cpp">
<Filter>Source Files</Filter>
</ClCompile>
<ClCompile Include="..\devices\nld_4020.cpp">
<Filter>Source Files</Filter>
</ClCompile>
@ -473,6 +476,9 @@
<ClInclude Include="..\devices\nlid_cmos.h">
<Filter>Header Files</Filter>
</ClInclude>
<ClInclude Include="..\devices\nld_4013.h">
<Filter>Header Files</Filter>
</ClInclude>
<ClInclude Include="..\devices\nld_4020.h">
<Filter>Header Files</Filter>
</ClInclude>

3
src/lib/netlist/devices/net_lib.cpp
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@ -109,6 +109,8 @@ namespace devices
LIB_ENTRY(74107A) // FIXME: implement missing DIP
LIB_ENTRY(74123)
LIB_ENTRY(74123_dip)
LIB_ENTRY(74125)
LIB_ENTRY(74126)
LIB_ENTRY(74153)
LIB_ENTRY(74153_dip)
LIB_ENTRY(74161)
@ -127,6 +129,7 @@ namespace devices
LIB_ENTRY(74193)
LIB_ENTRY(74194)
LIB_ENTRY(74365)
LIB_ENTRY(74377_GATE)
LIB_ENTRY(74393)
LIB_ENTRY(74393_dip)
//ENTRY(74279, TTL_74279, "") // only dip available

2
src/lib/netlist/devices/net_lib.h
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@ -48,6 +48,7 @@
#include "nld_2102A.h"
#include "nld_2716.h"
#include "nld_4006.h"
#include "nld_4013.h"
#include "nld_4020.h"
#include "nld_4066.h"
#include "nld_4316.h"
@ -64,6 +65,7 @@
#include "nld_74193.h"
#include "nld_74194.h"
#include "nld_74365.h"
#include "nld_74377.h"
#include "nld_74393.h"
#include "nld_7448.h"
#include "nld_7450.h"

143
src/lib/netlist/devices/nld_4013.cpp Normal file
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@ -0,0 +1,143 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
/*
* nld_4013.c
*
*/
#include "nld_4013.h"
#include "netlist/nl_base.h"
#include "nlid_system.h"
#include <array>
namespace netlist
{
namespace devices
{
NETLIB_OBJECT(4013)
{
NETLIB_CONSTRUCTOR(4013)
, m_D(*this, "DATA")
, m_RESET(*this, "RESET")
, m_SET(*this, "SET")
, m_CLK(*this, "CLOCK", NETLIB_DELEGATE(4013, clk))
, m_Q(*this, "Q")
, m_QQ(*this, "QQ")
, m_nextD(*this, "m_nextD", 0)
, m_power_pins(*this)
{
}
private:
NETLIB_RESETI();
NETLIB_UPDATEI();
NETLIB_HANDLERI(clk);
logic_input_t m_D;
logic_input_t m_RESET;
logic_input_t m_SET;
logic_input_t m_CLK;
logic_output_t m_Q;
logic_output_t m_QQ;
state_var<netlist_sig_t> m_nextD;
nld_power_pins m_power_pins;
void newstate_clk(const netlist_sig_t stateQ)
{
static constexpr delay = NLTIME_FROM_NS(150);
m_Q.push(stateQ, delay);
m_QQ.push(!stateQ, delay);
}
void newstate_setreset(const netlist_sig_t stateQ, const netlist_sig_t stateQQ)
{
// Q: 150 ns, QQ: 200 ns
static constexpr const std::array<netlist_time, 2> delay = { NLTIME_FROM_NS(150), NLTIME_FROM_NS(200) };
m_Q.push(stateQ, delay[0]);
m_QQ.push(stateQQ, delay[1]);
}
};
NETLIB_OBJECT(4013_dip)
{
NETLIB_CONSTRUCTOR(4013_dip)
NETLIB_FAMILY("CD4XXX")
, m_A(*this, "A")
, m_B(*this, "B")
{
register_subalias("1", "A.Q");
register_subalias("2", "A.QQ");
register_subalias("3", "A.CLOCK");
register_subalias("4", "A.RESET");
register_subalias("5", "A.DATA");
register_subalias("6", "A.SET");
register_subalias("7", "A.VSS");
register_subalias("8", "B.SET");
register_subalias("9", "B.DATA");
register_subalias("10", "B.RESET");
register_subalias("11", "B.CLOCK");
register_subalias("12", "B.QQ");
register_subalias("13", "B.Q");
register_subalias("14", "A.VDD");
connect("A.VSS", "B.VSS");
connect("A.VDD", "B.VDD");
}
NETLIB_UPDATEI();
NETLIB_RESETI();
private:
NETLIB_SUB(4013) m_A;
NETLIB_SUB(4013) m_B;
};
NETLIB_HANDLER(4013, clk)
{
newstate_clk(m_nextD);
m_CLK.inactivate();
}
NETLIB_UPDATE(4013)
{
const auto set(m_SET());
const auto reset(m_RESET());
if ((set ^ 1) & (reset ^ 1))
{
m_D.activate();
m_nextD = m_D();
m_CLK.activate_lh();
}
else
{
newstate_setreset(set, reset);
m_CLK.inactivate();
m_D.inactivate();
}
}
NETLIB_RESET(4013)
{
m_CLK.set_state(logic_t::STATE_INP_LH);
m_D.set_state(logic_t::STATE_INP_ACTIVE);
m_nextD = 0;
}
NETLIB_RESET(4013_dip)
{
}
NETLIB_UPDATE(4013_dip)
{
}
NETLIB_DEVICE_IMPL(CD4013, "CD4013", "+CLOCK,+DATA,+RESET,+SET,@VDD,@VSS")
NETLIB_DEVICE_IMPL(CD4013_DIP, "CD4013_DIP", "")
} //namespace devices
} // namespace netlist

59
src/lib/netlist/devices/nld_4013.h Normal file
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@ -0,0 +1,59 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
/*
* nld_4013.h
*
* CD4013: Dual Positive-Edge-Triggered D Flip-Flops
* with Set, Reset and Complementary Outputs
*
* +--------------+
* Q1 |1 ++ 14| VDD
* Q1Q |2 13| Q2
* CLOCK1 |3 12| Q2Q
* RESET1 |4 4013 11| CLOCK2
* DATA1 |5 10| RESET2
* SET1 |6 9| DATA2
* VSS |7 8| SET2
* +--------------+
*
* +-----+-----+-----+---++---+-----+
* | SET | RES | CLK | D || Q | QQ |
* +=====+=====+=====+===++===+=====+
* | 1 | 0 | X | X || 1 | 0 |
* | 0 | 1 | X | X || 0 | 1 |
* | 1 | 1 | X | X || 1 | 1 | (*)
* | 0 | 0 | R | 1 || 1 | 0 |
* | 0 | 0 | R | 0 || 0 | 1 |
* | 0 | 0 | 0 | X || Q0| Q0Q |
* +-----+-----+-----+---++---+-----+
*
* (*) This configuration is not stable, i.e. it will not persist
* when either the preset and or clear inputs return to their inactive (high) level
*
* Q0 The output logic level of Q before the indicated input conditions were established
*
* R: 0 -. 1
*
* Naming conventions follow National Semiconductor datasheet
*
* FIXME: Check that (*) is emulated properly
*/
#ifndef NLD_4013_H_
#define NLD_4013_H_
#include "netlist/nl_setup.h"
#define CD4013(name, cCLOCK, cDATA, cRESET, cSET) \
NET_REGISTER_DEV(CD4013, name) \
NET_CONNECT(name, VSS, VSS) \
NET_CONNECT(name, VDD, VDD) \
NET_CONNECT(name, CLK, cCLK) \
NET_CONNECT(name, DATA, cDATA) \
NET_CONNECT(name, SET, cSET) \
NET_CONNECT(name, RESET, cRESET)
#define CD4013_DIP(name) \
NET_REGISTER_DEV(CD4013_DIP, name)
#endif /* NLD_4013_H_ */

122
src/lib/netlist/devices/nld_74125.cpp Normal file
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@ -0,0 +1,122 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
/*
* nld_74125.c
*
*/
#include "nld_74125.h"
#include "nl_base.h"
namespace netlist
{
template <typename T>
struct uptr : public unique_pool_ptr<T>
{
uptr() = default;
using base_type = unique_pool_ptr<T>;
template<typename O, typename... Args, class = typename std::enable_if<
std::is_base_of<core_device_t, O>::value>::type>
uptr(O &owner, const pstring &name, Args&&... args)
: unique_pool_ptr<T>(static_cast<core_device_t &>(owner).state().make_object<T>(owner, name, std::forward<Args>(args)...))
{ }
template<typename O, typename... Args>
uptr(typename std::enable_if<
std::is_base_of<netlist_state_t, O>::value, O>::type &owner, const pstring &name, Args&&... args)
: unique_pool_ptr<T>(static_cast<netlist_state_t>(owner).make_object<T>(owner, name, std::forward<Args>(args)...))
{ }
C14CONSTEXPR auto operator ()() noexcept -> decltype((*unique_pool_ptr<T>::get())()) { return (*this->get())(); }
constexpr auto operator ()() const noexcept -> const decltype((*unique_pool_ptr<T>::get())()) { return (*this->get())(); }
};
namespace devices
{
template <netlist_sig_t INVERT_G>
NETLIB_OBJECT(74125_base)
{
NETLIB_CONSTRUCTOR(74125_base)
, m_A(*this, "A", NETLIB_DELEGATE(74125_base, A))
, m_G(*this, "G", NETLIB_DELEGATE(74125_base, G))
, m_Y(*this, "Y", NLTIME_FROM_NS(11), NLTIME_FROM_NS(13))
, m_power_pins(*this)
{
}
private:
NETLIB_RESETI()
{
}
NETLIB_UPDATEI()
{
// this one is only called during startup. Ensure all outputs
// are in a consistent state.
m_Y.set_tristate(m_G() ^ INVERT_G);
m_Y.push(m_A(), m_A() ? NLTIME_FROM_NS(8) : NLTIME_FROM_NS(12));
}
NETLIB_HANDLERI(A)
{
m_Y.push(m_A(), m_A() ? NLTIME_FROM_NS(8) : NLTIME_FROM_NS(12));
}
NETLIB_HANDLERI(G)
{
m_Y.set_tristate(m_G() ^ INVERT_G);
}
logic_input_t m_A;
uptr<logic_input_t> m_G;
tristate_output_t m_Y;
nld_power_pins m_power_pins;
};
#if 0
template <bool ASYNC>
NETLIB_OBJECT(74125_dip_base)
{
NETLIB_CONSTRUCTOR(74125_dip_base)
, A(*this, "A")
{
this->register_subalias("1", "A.CLRQ");
this->register_subalias("2", "A.CLK");
this->register_subalias("3", "A.A");
this->register_subalias("4", "A.B");
this->register_subalias("5", "A.C");
this->register_subalias("6", "A.D");
this->register_subalias("7", "A.ENP");
this->register_subalias("8", "A.GND");
this->register_subalias("9", "A.LOADQ");
this->register_subalias("10", "A.ENT");
this->register_subalias("11", "A.QD");
this->register_subalias("12", "A.QC");
this->register_subalias("13", "A.QB");
this->register_subalias("14", "A.QA");
this->register_subalias("15", "A.RC");
this->register_subalias("16", "A.VCC");
}
private:
NETLIB_SUB(74125_base)<ASYNC> A;
};
using NETLIB_NAME(74163) = NETLIB_NAME(74125_base)<false>;
using NETLIB_NAME(74125_dip) = NETLIB_NAME(74125_dip_base)<true>;
using NETLIB_NAME(74163_dip) = NETLIB_NAME(74125_dip_base)<false>;
NETLIB_DEVICE_IMPL(74125_dip, "TTL_74125_DIP", "")
NETLIB_DEVICE_IMPL(74163, "TTL_74163", "+CLK,+ENP,+ENT,+CLRQ,+LOADQ,+A,+B,+C,+D,@VCC,@GND")
NETLIB_DEVICE_IMPL(74163_dip, "TTL_74163_DIP", "")
#endif
using NETLIB_NAME(74125) = NETLIB_NAME(74125_base)<1>;
using NETLIB_NAME(74126) = NETLIB_NAME(74125_base)<0>;
NETLIB_DEVICE_IMPL(74125, "TTL_74125", "")
NETLIB_DEVICE_IMPL(74126, "TTL_74126", "")
} //namespace devices
} // namespace netlist

92
src/lib/netlist/devices/nld_74125.h Normal file
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@ -0,0 +1,92 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
/*
* nld_74125.h
*
* DM74125: Synchronous 4-Bit Counters
*
* +--------------+
* /CLEAR |1 ++ 16| VCC
* CLOCK |2 15| RC (Ripple Carry)
* A |3 14| QA
* B |4 74125 13| QB
* C |5 12| QC
* D |6 11| QD
* Enable P |7 10| Enable T
* GND |8 9| /LOAD
* +--------------+
*
* Counter Sequence
*
* +-------++----+----+----+----+----+
* | COUNT || QD | QC | QB | QA | RC |
* +=======++====+====+====+====+====+
* | 0 || 0 | 0 | 0 | 0 | 0 |
* | 1 || 0 | 0 | 0 | 1 | 0 |
* | 2 || 0 | 0 | 1 | 0 | 0 |
* | 3 || 0 | 0 | 1 | 1 | 0 |
* | 4 || 0 | 1 | 0 | 0 | 0 |
* | 5 || 0 | 1 | 0 | 1 | 0 |
* | 6 || 0 | 1 | 1 | 0 | 0 |
* | 7 || 0 | 1 | 1 | 1 | 0 |
* | 8 || 1 | 0 | 0 | 0 | 0 |
* | 9 || 1 | 0 | 0 | 1 | 0 |
* | 10 || 1 | 0 | 1 | 0 | 0 |
* | 11 || 1 | 0 | 1 | 1 | 0 |
* | 12 || 1 | 1 | 0 | 0 | 0 |
* | 13 || 1 | 1 | 0 | 1 | 0 |
* | 14 || 1 | 1 | 1 | 0 | 0 |
* | 15 || 1 | 1 | 1 | 1 | 1 |
* +-------++----+----+----+----+----+
*
* Reset count function: Please refer to
* National Semiconductor datasheet (timing diagram)
*
* Naming conventions follow National Semiconductor datasheet
*
* TODO: DM74161 is compatible to DM74125 (both asynchronous clear)
* DM74163 has asynchronous clear (on L to H transition of clock)
*/
#ifndef NLD_74125_H_
#define NLD_74125_H_
#include "netlist/nl_setup.h"
#if 0
#define TTL_74125(name, cCLK, cENP, cENT, cCLRQ, cLOADQ, cA, cB, cC, cD) \
NET_REGISTER_DEV(TTL_74125, name) \
NET_CONNECT(name, GND, GND) \
NET_CONNECT(name, VCC, VCC) \
NET_CONNECT(name, CLK, cCLK) \
NET_CONNECT(name, ENP, cENP) \
NET_CONNECT(name, ENT, cENT) \
NET_CONNECT(name, CLRQ, cCLRQ) \
NET_CONNECT(name, LOADQ, cLOADQ) \
NET_CONNECT(name, A, cA) \
NET_CONNECT(name, B, cB) \
NET_CONNECT(name, C, cC) \
NET_CONNECT(name, D, cD)
#define TTL_74163(name, cCLK, cENP, cENT, cCLRQ, cLOADQ, cA, cB, cC, cD) \
NET_REGISTER_DEV(TTL_74163, name) \
NET_CONNECT(name, GND, GND) \
NET_CONNECT(name, VCC, VCC) \
NET_CONNECT(name, CLK, cCLK) \
NET_CONNECT(name, ENP, cENP) \
NET_CONNECT(name, ENT, cENT) \
NET_CONNECT(name, CLRQ, cCLRQ) \
NET_CONNECT(name, LOADQ, cLOADQ) \
NET_CONNECT(name, A, cA) \
NET_CONNECT(name, B, cB) \
NET_CONNECT(name, C, cC) \
NET_CONNECT(name, D, cD)
#define TTL_74125_DIP(name) \
NET_REGISTER_DEV(TTL_74125_DIP, name)
#define TTL_74163_DIP(name) \
NET_REGISTER_DEV(TTL_74163_DIP, name)
#endif
#endif /* NLD_74125_H_ */

62
src/lib/netlist/devices/nld_74377.cpp Normal file
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@ -0,0 +1,62 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
/*
* nld_74377.c
*
*/
#include "nld_74377.h"
#include "netlist/nl_base.h"
namespace netlist
{
namespace devices
{
constexpr const std::array<netlist_time, 2> delay = { NLTIME_FROM_NS(25), NLTIME_FROM_NS(25) };
NETLIB_OBJECT(74377_GATE)
{
NETLIB_CONSTRUCTOR(74377_GATE)
, m_E(*this, "E")
, m_D(*this, "D")
, m_CP(*this, "CP")
, m_Q(*this, "Q")
, m_QQ(*this, "QQ")
, m_cp(*this, "m_cp", 0)
, m_power_pins(*this)
{
}
NETLIB_RESETI()
{
}
NETLIB_UPDATEI()
{
netlist_sig_t last_cp = m_cp;
m_cp = m_CP();
if (!m_E() && !last_cp && m_cp)
{
netlist_sig_t d = m_D();
m_Q.push(d, delay[d]);
m_QQ.push(d ^ 1, delay[d ^ 1]);
}
}
private:
logic_input_t m_E;
logic_input_t m_D;
logic_input_t m_CP;
logic_output_t m_Q;
logic_output_t m_QQ;
state_var_sig m_cp;
nld_power_pins m_power_pins;
};
NETLIB_DEVICE_IMPL(74377_GATE, "TTL_74377_GATE", "")
} //namespace devices
} // namespace netlist

61
src/lib/netlist/devices/nld_74377.h Normal file
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@ -0,0 +1,61 @@
// license:GPL-2.0+
// copyright-holders:Couriersud,Aaron Giles
/*
* nld_74377.h
*
* DM74377: Octal D Flip-Flop With Enable
*
* +--------------+
* /E |1 ++ 20| VCC
* Q0 |2 19| Q7
* D0 |3 18| D7
* D1 |4 74377 17| D6
* Q1 |5 16| Q6
* Q2 |6 15| Q5
* D2 |7 14| D5
* D3 |8 13| D4
* Q3 |9 12| Q4
* GND |10 11| CP
* +--------------+
*
* DM74378: Hex D Flip-Flop With Enable
*
* +--------------+
* /E |1 ++ 16| VCC
* Q0 |2 15| Q5
* D0 |3 14| D5
* D1 |4 74378 13| D4
* Q1 |5 12| Q4
* D2 |6 11| D3
* Q2 |7 10| Q3
* GND |8 9| CP
* +--------------+
*
* DM74379: 4-bit D Flip-Flop With Enable
*
* +--------------+
* /E |1 ++ 16| VCC
* Q0 |2 15| Q3
* /Q0 |3 14| /Q3
* D0 |4 74379 13| D3
* D1 |5 12| D2
* /Q1 |6 11| /Q2
* Q1 |7 10| Q2
* GND |8 9| CP
* +--------------+
*
* Naming conventions follow Motorola datasheet
*
*/
#ifndef NLD_74377_H_
#define NLD_74377_H_
#include "netlist/nl_setup.h"
#define TTL_74377_GATE(name) \
NET_REGISTER_DEV(TTL_74377_GATE, name)
#endif /* NLD_74377_H_ */

18
src/lib/netlist/devices/nld_devinc.h
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@ -426,6 +426,12 @@
#define TTL_74365(name, pG1Q, pG2Q, pA1, pA2, pA3, pA4, pA5, pA6) \
NET_REGISTER_DEVEXT(TTL_74365, name, pG1Q, pG2Q, pA1, pA2, pA3, pA4, pA5, pA6)
// ---------------------------------------------------------------------
// Source: src/lib/netlist/devices/nld_74377.cpp
// ---------------------------------------------------------------------
#define TTL_74377_GATE(name) \
NET_REGISTER_DEVEXT(TTL_74377_GATE, name)
// ---------------------------------------------------------------------
// Source: src/lib/netlist/devices/nld_74393.cpp
// ---------------------------------------------------------------------
@ -879,6 +885,15 @@
#define TTL_74279_DIP(name) \
NET_REGISTER_DEVEXT(TTL_74279_DIP, name)
#define TTL_74377_DIP(name) \
NET_REGISTER_DEVEXT(TTL_74377_DIP, name)
#define TTL_74378_DIP(name) \
NET_REGISTER_DEVEXT(TTL_74378_DIP, name)
#define TTL_74379_DIP(name) \
NET_REGISTER_DEVEXT(TTL_74379_DIP, name)
#define DM9312_DIP(name) \
NET_REGISTER_DEVEXT(DM9312_DIP, name)
@ -891,6 +906,9 @@
#define CD4070_GATE(name) \
NET_REGISTER_DEVEXT(CD4070_GATE, name)
#define CD4069_GATE(name) \
NET_REGISTER_DEVEXT(CD4069_GATE, name)
#define CD4001_DIP(name) \
NET_REGISTER_DEVEXT(CD4001_DIP, name)

35
src/lib/netlist/devices/nlid_proxy.cpp
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@ -120,7 +120,7 @@ namespace netlist
, m_I(*this, "I")
, m_RP(*this, "RP")
, m_RN(*this, "RN")
, m_last_state(*this, "m_last_var", -1)
, m_last_state(*this, "m_last_var", terminal_t::OUT_TRISTATE())
{
register_subalias("Q", m_RN.P());
@ -144,7 +144,7 @@ namespace netlist
void nld_d_to_a_proxy::reset()
{
//m_Q.initial(0.0);
m_last_state = -1;
m_last_state = terminal_t::OUT_TRISTATE();
m_RN.reset();
m_RP.reset();
m_RN.set_G_V_I(plib::reciprocal(logic_family()->R_low()),
@ -156,27 +156,38 @@ namespace netlist
NETLIB_UPDATE(d_to_a_proxy)
{
const auto state = static_cast<int>(m_I());
const auto state = m_I();
if (state != m_last_state)
{
// RN, RP are connected ...
m_RN.change_state([this, &state]()
{
if (state)
{
m_RN.set_G_V_I(G_OFF,
nlconst::zero(),
nlconst::zero());
m_RP.set_G_V_I(plib::reciprocal(logic_family()->R_high()),
logic_family()->high_offset_V(), nlconst::zero());
}
else
switch (state)
{
case 0:
m_RN.set_G_V_I(plib::reciprocal(logic_family()->R_low()),
logic_family()->low_offset_V(), nlconst::zero());
m_RP.set_G_V_I(G_OFF,
nlconst::zero(),
nlconst::zero());
break;
case 1:
m_RN.set_G_V_I(G_OFF,
nlconst::zero(),
nlconst::zero());
m_RP.set_G_V_I(plib::reciprocal(logic_family()->R_high()),
logic_family()->high_offset_V(), nlconst::zero());
break;
case terminal_t::OUT_TRISTATE():
m_RN.set_G_V_I(G_OFF,
nlconst::zero(),
nlconst::zero());
m_RP.set_G_V_I(G_OFF,
nlconst::zero(),
nlconst::zero());
break;
default:
printf("this should never happen!");
}
});
m_last_state = state;

2
src/lib/netlist/devices/nlid_proxy.h
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@ -118,7 +118,7 @@ namespace devices
logic_input_t m_I;
analog::NETLIB_NAME(twoterm) m_RP;
analog::NETLIB_NAME(twoterm) m_RN;
state_var<int> m_last_state;
state_var<netlist_sig_t> m_last_state;
};
} // namespace devices

40
src/lib/netlist/examples/74125.cpp Normal file
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@ -0,0 +1,40 @@
// license:CC0
// copyright-holders:Couriersud
/*
* 74125.cpp
*
*/
//! [74125_example]
#include "netlist/devices/net_lib.h"
// ./nltool -c run -l RL.1 src/lib/netlist/examples/74125.cpp
// RL.1 : Output
NETLIST_START(main)
SOLVER(Solver, 48000) // could be 1 in this example
ANALOG_INPUT(VCC, 5.0)
TTL_74125(X1)
TTL_74126(X2)
CLOCK(C1, 100)
CLOCK(C2, 300)
CLOCK(C3, 5)
RES(RL, 1000)
NET_C(C1.Q, X1.A)
NET_C(C2.Q, X2.A)
NET_C(C3.Q, X1.G, X2.G)
NET_C(X1.Y, X2.Y, RL.1)
NET_C(GND, RL.2, C1.GND, C2.GND, C3.GND, X1.GND, X2.GND)
NET_C(VCC, C1.VCC, C2.VCC, C3.VCC, X1.VCC, X2.VCC)
NETLIST_END()
//! [74125_example]

74
src/lib/netlist/macro/nlm_cd4xxx.cpp
View File

@ -7,13 +7,13 @@
* CD4001BC: Quad 2-Input NOR Buffered B Series Gate
*
* +--------------+
* A1 |1 ++ 14| VCC
* A1 |1 ++ 14| VDD
* B1 |2 13| A6
* A2 |3 12| Y6
* Y2 |4 4001 11| A5
* A3 |5 10| Y5
* Y3 |6 9| A4
* GND |7 8| Y4
* VSS |7 8| Y4
* +--------------+
*
*/
@ -24,16 +24,16 @@ static NETLIST_START(CD4001_DIP)
CD4001_GATE(s3)
CD4001_GATE(s4)
NET_C(s1.VCC, s2.VCC, s3.VCC, s4.VCC)
NET_C(s1.GND, s2.GND, s3.GND, s4.GND)
NET_C(s1.VDD, s2.VDD, s3.VDD, s4.VDD)
NET_C(s1.VSS, s2.VSS, s3.VSS, s4.VSS)
DIPPINS( /* +--------------+ */
s1.A, /* A1 |1 ++ 14| VDD */ s1.VCC,
s1.A, /* A1 |1 ++ 14| VDD */ s1.VDD,
s1.B, /* B1 |2 13| A6 */ s4.B,
s1.Q, /* A2 |3 12| Y6 */ s4.A,
s2.Q, /* Y2 |4 4001 11| A5 */ s4.Q,
s2.A, /* A3 |5 10| Y5 */ s3.Q,
s2.B, /* Y3 |6 9| A4 */ s3.B,
s1.GND, /* VSS |7 8| Y4 */ s3.A
s1.VSS, /* VSS |7 8| Y4 */ s3.A
/* +--------------+ */
)
@ -149,7 +149,45 @@ static NETLIST_START(CD4016_DIP)
NETLIST_END()
/*
* DM7486: Quad 2-Input Exclusive-OR Gates
* CD4069: Hex Inverter
* _
* Y = A
* +---++---+
* | A || Y |
* +===++===+
* | 0 || 1 |
* | 1 || 0 |
* +---++---+
*
* Naming conventions follow National Semiconductor datasheet
*
*/
static NETLIST_START(CD4069_DIP)
CD4069_GATE(A)
CD4069_GATE(B)
CD4069_GATE(C)
CD4069_GATE(D)
CD4069_GATE(E)
CD4069_GATE(F)
NET_C(A.VDD, B.VDD, C.VDD, D.VDD, E.VDD, E.VDD)
NET_C(A.VSS, B.VSS, C.VSS, D.VSS, E.VSS, F.VSS)
DIPPINS( /* +--------------+ */
A.A, /* A1 |1 ++ 14| VDD */ A.VDD,
A.Q, /* Y1 |2 13| A6 */ F.A,
B.A, /* A2 |3 12| Y6 */ F.Q,
B.Q, /* Y2 |4 4069 11| A5 */ E.A,
C.A, /* A3 |5 10| Y5 */ E.Q,
C.Q, /* Y3 |6 9| A4 */ D.A,
A.VSS,/* VSS |7 8| Y4 */ D.Q
/* +--------------+ */
)
NETLIST_END()
/*
* CD4070: Quad 2-Input Exclusive-OR Gates
*
* Y = A+B
* +---+---++---+
@ -161,8 +199,6 @@ NETLIST_END()
* | 1 | 1 || 0 |
* +---+---++---+
*
* Naming conventions follow National Semiconductor datasheet
*
*/
static NETLIST_START(CD4070_DIP)
@ -171,17 +207,17 @@ static NETLIST_START(CD4070_DIP)
CD4070_GATE(C)
CD4070_GATE(D)
NET_C(A.VCC, B.VCC, C.VCC, D.VCC)
NET_C(A.GND, B.GND, C.GND, D.GND)
NET_C(A.VDD, B.VDD, C.VDD, D.VDD)
NET_C(A.VSS, B.VSS, C.VSS, D.VSS)
DIPPINS( /* +--------------+ */
A.A, /* A1 |1 ++ 14| VCC */ A.VCC,
A.A, /* A1 |1 ++ 14| VDD */ A.VDD,
A.B, /* B1 |2 13| B4 */ D.B,
A.Q, /* Y1 |3 12| A4 */ D.A,
B.Q, /* Y2 |4 7486 11| Y4 */ D.Q,
B.Q, /* Y2 |4 4070 11| Y4 */ D.Q,
B.A, /* A2 |5 10| Y3 */ C.Q,
B.B, /* B2 |6 9| B3 */ C.B,
A.GND,/* GND |7 8| A3 */ C.A
A.VSS,/* VSS |7 8| A3 */ C.A
/* +--------------+ */
)
NETLIST_END()
@ -220,12 +256,19 @@ NETLIST_START(CD4XXX_lib)
TRUTHTABLE_START(CD4001_GATE, 2, 1, "")
TT_HEAD("A , B | Q ")
TT_LINE("0,0|1|85")
TT_LINE("0,0|1|110")
TT_LINE("X,1|0|120")
TT_LINE("1,X|0|120")
TT_FAMILY("CD4XXX")
TRUTHTABLE_END()
TRUTHTABLE_START(CD4069_GATE, 1, 1, "")
TT_HEAD("A|Q ")
TT_LINE("0|1|55")
TT_LINE("1|0|55")
TT_FAMILY("CD4XXX")
TRUTHTABLE_END()
TRUTHTABLE_START(CD4070_GATE, 2, 1, "")
TT_HEAD("A,B|Q ")
TT_LINE("0,0|0|15")
@ -236,6 +279,7 @@ NETLIST_START(CD4XXX_lib)
TRUTHTABLE_END()
LOCAL_LIB_ENTRY(CD4001_DIP)
LOCAL_LIB_ENTRY(CD4069_DIP)
LOCAL_LIB_ENTRY(CD4070_DIP)
/* DIP ONLY */

6
src/lib/netlist/macro/nlm_cd4xxx.h
View File

@ -33,6 +33,12 @@
#define CD4001_DIP(name) \
NET_REGISTER_DEV(CD4001_DIP, name)
#define CD4069_GATE(name) \
NET_REGISTER_DEV(CD4069_GATE, name)
#define CD4069_DIP(name) \
NET_REGISTER_DEV(CD4069_DIP, name)
#define CD4070_GATE(name) \
NET_REGISTER_DEV(CD4070_GATE, name)

94
src/lib/netlist/macro/nlm_ttl74xx.cpp
View File

@ -296,7 +296,7 @@ static NETLIST_START(TTL_7414_DIP)
NET_C(A.VCC, B.VCC, C.VCC, D.VCC, E.VCC, F.VCC)
DIPPINS( /* +--------------+ */
A.A, /* A1 |1 ++ 14| VCC */ VCC.I,
A.A, /* A1 |1 ++ 14| VCC */ A.VCC,
A.Q, /* Y1 |2 13| A6 */ F.A,
B.A, /* A2 |3 12| Y6 */ F.Q,
B.Q, /* Y2 |4 7414 11| A5 */ E.A,
@ -319,7 +319,7 @@ static NETLIST_START(TTL_74LS14_DIP)
NET_C(A.VCC, B.VCC, C.VCC, D.VCC, E.VCC, F.VCC)
DIPPINS( /* +--------------+ */
A.A, /* A1 |1 ++ 14| VCC */ VCC.I,
A.A, /* A1 |1 ++ 14| VCC */ A.VCC,
A.Q, /* Y1 |2 13| A6 */ F.A,
B.A, /* A2 |3 12| Y6 */ F.Q,
B.Q, /* Y2 |4 74LS14 11| A5 */ E.A,
@ -828,6 +828,93 @@ static NETLIST_START(TTL_74279_DIP)
)
NETLIST_END()
/*
* DM74377: Octal D Flip-Flop With Enable
* DM74378: Hex D Flip-Flop With Enable
* DM74379: 4-bit D Flip-Flop With Enable
*
*/
static NETLIST_START(TTL_74377_DIP)
TTL_74377_GATE(A)
TTL_74377_GATE(B)
TTL_74377_GATE(C)
TTL_74377_GATE(D)
TTL_74377_GATE(E)
TTL_74377_GATE(F)
TTL_74377_GATE(G)
TTL_74377_GATE(H)
NET_C(A.VCC, B.VCC, C.VCC, D.VCC, E.VCC, F.VCC, G.VCC, H.VCC)
NET_C(A.GND, B.GND, C.GND, D.GND, E.GND, F.GND, G.GND, H.GND)
NET_C(A.CP, B.CP, C.CP, D.CP, E.CP, F.CP, G.CP, H.CP)
NET_C(A.E, B.E, C.E, D.E, E.E, F.E, G.E, H.E)
DIPPINS( /* +--------------+ */
A.E, /* /E |1 ++ 20| VCC */ A.VCC,
A.Q, /* Q0 |2 19| Q7 */ H.Q,
A.D, /* D0 |3 18| D7 */ H.D,
B.D, /* D1 |4 74377 17| D6 */ G.D,
B.Q, /* Q1 |5 16| Q6 */ G.Q,
C.Q, /* Q2 |6 15| Q5 */ F.Q,
C.D, /* D2 |7 14| D5 */ F.D,
D.D, /* D3 |8 13| D4 */ E.D,
D.Q, /* Q3 |9 12| Q4 */ E.D,
A.GND,/* GND |10 11| CP */ A.CP
/* +--------------+ */
)
NETLIST_END()
static NETLIST_START(TTL_74378_DIP)
TTL_74377_GATE(A)
TTL_74377_GATE(B)
TTL_74377_GATE(C)
TTL_74377_GATE(D)
TTL_74377_GATE(E)
TTL_74377_GATE(F)
NET_C(A.VCC, B.VCC, C.VCC, D.VCC, E.VCC, F.VCC)
NET_C(A.GND, B.GND, C.GND, D.GND, E.GND, F.GND)
NET_C(A.CP, B.CP, C.CP, D.CP, E.CP, F.CP)
NET_C(A.E, B.E, C.E, D.E, E.E, F.E)
DIPPINS( /* +--------------+ */
A.E, /* /E |1 ++ 16| VCC */ A.VCC,
A.Q, /* Q0 |2 15| Q5 */ F.Q,
A.D, /* D0 |3 14| D5 */ F.D,
B.D, /* D1 |4 74378 13| D4 */ E.D,
B.Q, /* Q1 |5 12| Q4 */ E.Q,
C.D, /* D2 |6 11| D3 */ D.D,
C.Q, /* Q2 |7 10| Q3 */ D.Q,
A.GND,/* GND |8 9| CP */ A.CP
/* +--------------+ */
)
NETLIST_END()
static NETLIST_START(TTL_74379_DIP)
TTL_74377_GATE(A)
TTL_74377_GATE(B)
TTL_74377_GATE(C)
TTL_74377_GATE(D)
NET_C(A.VCC, B.VCC, C.VCC, D.VCC)
NET_C(A.GND, B.GND, C.GND, D.GND)
NET_C(A.CP, B.CP, C.CP, D.CP)
NET_C(A.E, B.E, C.E, D.E)
DIPPINS( /* +--------------+ */
A.E, /* /E |1 ++ 16| VCC */ A.VCC,
A.Q, /* Q0 |2 15| Q3 */ D.Q,
A.QQ, /* /Q0 |3 14| /Q3 */ D.QQ,
A.D, /* D0 |4 74379 13| D3 */ D.D,
B.D, /* D1 |5 12| D2 */ C.D,
B.QQ, /* /Q1 |6 11| /Q2 */ C.QQ,
B.Q, /* Q1 |7 10| Q2 */ C.Q,
A.GND,/* GND |8 9| CP */ A.CP
/* +--------------+ */
)
NETLIST_END()
/*
* DM9312: One of Eight Line Data Selectors/Multiplexers
*
@ -1434,5 +1521,8 @@ NETLIST_START(TTL74XX_lib)
LOCAL_LIB_ENTRY(TTL_74156_DIP)
LOCAL_LIB_ENTRY(TTL_74260_DIP)
LOCAL_LIB_ENTRY(TTL_74279_DIP)
LOCAL_LIB_ENTRY(TTL_74377_DIP)
LOCAL_LIB_ENTRY(TTL_74378_DIP)
LOCAL_LIB_ENTRY(TTL_74379_DIP)
LOCAL_LIB_ENTRY(DM9312_DIP)
NETLIST_END()

9
src/lib/netlist/macro/nlm_ttl74xx.h
View File

@ -293,6 +293,15 @@
#define TTL_74279_DIP(name) \
NET_REGISTER_DEV(TTL_74279_DIP, name)
#define TTL_74377_DIP(name) \
NET_REGISTER_DEV(TTL_74377_DIP, name)
#define TTL_74378_DIP(name) \
NET_REGISTER_DEV(TTL_74378_DIP, name)
#define TTL_74379_DIP(name) \
NET_REGISTER_DEV(TTL_74379_DIP, name)
#define DM9312(name, cA, cB, cC, cSTROBE, cD0, cD1, cD2, cD3, cD4, cD5, cD6, cD7) \
NET_REGISTER_DEV(DM9312, name) \
NET_CONNECT(name, VCC, VCC) \

61
src/lib/netlist/nl_base.cpp
View File

@ -194,7 +194,10 @@ namespace netlist
void netlist_state_t::compile_defines(std::vector<std::pair<pstring, pstring>> &defs)
{
#define ENTRY(x) if (pstring(#x) != PSTRINGIFY(x)) defs.emplace_back(std::pair<pstring, pstring>(#x, PSTRINGIFY(x)));
#define ENTRY(x) if (pstring(#x) != PSTRINGIFY(x)) \
defs.emplace_back(std::pair<pstring, pstring>(#x, PSTRINGIFY(x))); \
else defs.emplace_back(std::pair<pstring, pstring>(#x, "<NOT DEFINED>"));
#define ENTRY_EX(x) defs.emplace_back(std::pair<pstring, pstring>(#x, plib::pfmt("{}")(x)));
ENTRY(NL_VERSION_MAJOR)
ENTRY(NL_VERSION_MINOR)
ENTRY(NL_VERSION_PATCHLEVEL)
@ -242,6 +245,15 @@ namespace netlist
ENTRY(__unix__)
ENTRY(__linux__)
ENTRY_EX(sizeof(base_device_t))
ENTRY_EX(sizeof(device_t))
ENTRY_EX(sizeof(logic_input_t))
ENTRY_EX(sizeof(logic_output_t))
ENTRY_EX(sizeof(param_model_t))
ENTRY_EX(sizeof(param_logic_t))
ENTRY_EX(sizeof(state_var<int>))
ENTRY_EX(sizeof(pstring))
#undef ENTRY
}
@ -275,6 +287,8 @@ namespace netlist
void netlist_state_t::reset()
{
m_setup = nullptr;
// Reset all nets once !
log().verbose("Call reset on all nets:");
for (auto & n : nets())
@ -649,41 +663,6 @@ namespace netlist
}
}
void detail::net_t::add_terminal(detail::core_terminal_t &terminal) noexcept(false)
{
for (auto &t : core_terms())
if (t == &terminal)
{
state().log().fatal(MF_NET_1_DUPLICATE_TERMINAL_2(name(), t->name()));
throw nl_exception(MF_NET_1_DUPLICATE_TERMINAL_2(name(), t->name()));
}
terminal.set_net(this);
core_terms().push_back(&terminal);
}
void detail::net_t::remove_terminal(detail::core_terminal_t &terminal) noexcept(false)
{
if (plib::container::contains(core_terms(), &terminal))
{
terminal.set_net(nullptr);
plib::container::remove(core_terms(), &terminal);
}
else
{
state().log().fatal(MF_REMOVE_TERMINAL_1_FROM_NET_2(terminal.name(), this->name()));
throw nl_exception(MF_REMOVE_TERMINAL_1_FROM_NET_2(terminal.name(), this->name()));
}
}
void detail::net_t::move_connections(detail::net_t &dest_net)
{
for (auto &ct : core_terms())
dest_net.add_terminal(*ct);
core_terms().clear();
}
// ----------------------------------------------------------------------------------------
// logic_net_t
// ----------------------------------------------------------------------------------------
@ -868,13 +847,13 @@ namespace netlist
param_str_t::param_str_t(core_device_t &device, const pstring &name, const pstring &val)
: param_t(&device, name)
{
m_param = device.state().setup().get_initial_param_val(this->name(),val);
m_param = plib::make_unique<pstring>(device.state().setup().get_initial_param_val(this->name(),val));
}
param_str_t::param_str_t(netlist_state_t &state, const pstring &name, const pstring &val)
: param_t(nullptr, name)
{
m_param = state.setup().get_initial_param_val(this->name(),val);
m_param = plib::make_unique<pstring>(state.setup().get_initial_param_val(this->name(),val));
}
void param_str_t::changed() noexcept
@ -893,18 +872,18 @@ namespace netlist
pstring param_model_t::type()
{
auto mod = state().parser().models().get_model(str());
auto mod = state().setup().models().get_model(str());
return mod.type();
}
pstring param_model_t::value_str(const pstring &entity)
{
return state().parser().models().get_model(str()).value_str(entity);
return state().setup().models().get_model(str()).value_str(entity);
}
nl_fptype param_model_t::value(const pstring &entity)
{
return state().parser().models().get_model(str()).value(entity);
return state().setup().models().get_model(str()).value(entity);
}

64
src/lib/netlist/nl_base.h
View File

@ -627,12 +627,17 @@ namespace netlist
/// Going forward setting this to 8 will allow 8-bit signal
/// busses to be used in netlist, e.g. for more complex memory
/// arrangements.
static constexpr const unsigned int INP_BITS = 1;
/// Mimimum value is 2 here to support tristate output on proxies.
static constexpr const unsigned int INP_BITS = 2;
static constexpr const unsigned int INP_MASK = (1 << INP_BITS) - 1;
static constexpr const unsigned int INP_HL_SHIFT = 0;
static constexpr const unsigned int INP_LH_SHIFT = INP_BITS;
static constexpr netlist_sig_t OUT_TRISTATE() { return INP_MASK; }
static_assert(INP_BITS * 2 <= sizeof(netlist_sig_t) * 8, "netlist_sig_t size not sufficient");
enum state_e {
STATE_INP_PASSIVE = 0,
STATE_INP_HL = (INP_MASK << INP_HL_SHIFT),
@ -747,14 +752,10 @@ namespace netlist
// setup stuff
void add_terminal(core_terminal_t &terminal) noexcept(false);
void remove_terminal(core_terminal_t &terminal) noexcept(false);
bool is_logic() const noexcept;
bool is_analog() const noexcept;
void rebuild_list(); // rebuild m_list after a load
void move_connections(net_t &dest_net);
std::vector<core_terminal_t *> &core_terms() noexcept { return m_core_terms; }
@ -1018,6 +1019,47 @@ namespace netlist
logic_net_t m_my_net;
};
// -----------------------------------------------------------------------------
// tristate_output_t
// -----------------------------------------------------------------------------
class tristate_output_t : public logic_output_t
{
public:
tristate_output_t(device_t &dev, const pstring &aname,
netlist_time ts_off_on, netlist_time ts_on_off)
: logic_output_t(dev, aname)
, m_last_logic(dev, name() + "." + "m_last_logic", 2) // force change
, m_tristate(dev, name() + "." + "m_tristate", 2) // force change
, m_ts_off_on(ts_off_on)
, m_ts_on_off(ts_on_off)
{}
void push(netlist_sig_t newQ, netlist_time delay) noexcept
{
if (!m_tristate)
logic_output_t::push(newQ, delay);
m_last_logic = newQ;
}
void set_tristate(bool v) noexcept
{
if (v != m_tristate)
{
logic_output_t::push(v ? OUT_TRISTATE() : m_last_logic, v ? m_ts_off_on : m_ts_on_off);
m_tristate = v;
}
}
private:
using logic_output_t::initial;
using logic_output_t::set_Q_time;
state_var<netlist_sig_t> m_last_logic;
state_var<netlist_sig_t> m_tristate;
const netlist_time m_ts_off_on;
const netlist_time m_ts_on_off;
};
// -----------------------------------------------------------------------------
// analog_output_t
// -----------------------------------------------------------------------------
@ -1161,22 +1203,22 @@ namespace netlist
const pstring &operator()() const noexcept { return str(); }
void set(const pstring &param)
{
if (m_param != param)
if (*m_param != param)
{
m_param = param;
*m_param = param;
changed();
update_param();
}
}
pstring valstr() const override
{
return m_param;
return *m_param;
}
protected:
virtual void changed() noexcept;
const pstring &str() const noexcept { return m_param; }
const pstring &str() const noexcept { return *m_param; }
private:
pstring m_param;
plib::unique_ptr<pstring> m_param;
};
// -----------------------------------------------------------------------------
@ -2021,6 +2063,8 @@ namespace netlist
inline void detail::net_t::push_to_queue(netlist_time delay) noexcept
{
// FIXME: checking for has_connection doesn't have any noticable effect
// on performance.
if (has_connections())
{
m_next_scheduled_time = exec().time() + delay;

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