mirror of
https://github.com/holub/mame
synced 2025-05-23 22:20:01 +03:00
pci: A little more, reaches an unemulated pslldq at fd228 [O. Galibert]
This commit is contained in:
Olivier Galibert
parent
6adba2caa0
commit
a6ce93036e
@ -29,10 +29,21 @@ DEVICE_ADDRESS_MAP_START(config_map, 32, i6300esb_lpc_device)
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AM_RANGE(0xe4, 0xe7) AM_READWRITE16(gen1_dec_r, gen1_dec_w, 0x0000ffff)
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AM_RANGE(0xe4, 0xe7) AM_READWRITE16(lpc_en_r, lpc_en_w, 0xffff0000)
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AM_RANGE(0xe8, 0xeb) AM_READWRITE (fwh_sel1_r, fwh_sel1_w)
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AM_RANGE(0xfc, 0xff) AM_READWRITE (unk_fc_r, unk_fc_w)
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AM_INHERIT_FROM(pci_device::config_map)
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ADDRESS_MAP_END
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DEVICE_ADDRESS_MAP_START(internal_io_map, 32, i6300esb_lpc_device)
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if(lpc_en & 0x2000) {
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AM_RANGE(0x004c, 0x004f) AM_READWRITE8(siu_config_port_r, siu_config_port_w, 0x00ff0000)
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AM_RANGE(0x004c, 0x004f) AM_READWRITE8(siu_data_port_r, siu_data_port_w, 0xff000000)
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}
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AM_RANGE(0x80, 0x83) AM_WRITE8( nop_w, 0x000000ff) // POST/non-existing, used for delays by the bios/os
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AM_RANGE(0xec, 0xef) AM_WRITE8( nop_w, 0x0000ff00) // Non-existing, used for delays by the bios/os
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ADDRESS_MAP_END
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i6300esb_lpc_device::i6300esb_lpc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: pci_device(mconfig, I6300ESB_LPC, "i6300ESB southbridge ISA/LPC bridge", tag, owner, clock, "i6300esb_lpc", __FILE__)
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@ -47,10 +58,20 @@ void i6300esb_lpc_device::device_start()
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void i6300esb_lpc_device::device_reset()
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{
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pci_device::device_reset();
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siu_config_port = 0;
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siu_config_state = 0;
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}
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void i6300esb_lpc_device::reset_all_mappings()
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{
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gpio_base = 0;
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gpio_cntl = 0x00;
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lpc_if_com_range = 0x00;
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lpc_if_fdd_lpt_range = 0x00;
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lpc_if_sound_range = 0x00;
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fwh_dec_en1 = 0xff;
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gen1_dec = 0x0000;
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lpc_en = 0x0000;
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lpc_en = 0x2000;
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fwh_sel1 = 0x00112233;
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}
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@ -77,6 +98,50 @@ WRITE8_MEMBER (i6300esb_lpc_device::gpio_cntl_w)
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logerror("%s: gpio_cntl = %02x\n", tag(), gpio_cntl);
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}
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READ8_MEMBER (i6300esb_lpc_device::lpc_if_com_range_r)
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{
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return lpc_if_com_range;
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}
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WRITE8_MEMBER (i6300esb_lpc_device::lpc_if_com_range_w)
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{
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COMBINE_DATA(&lpc_if_com_range);
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logerror("%s: lpc_if_com_range = %02x\n", tag(), lpc_if_com_range);
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}
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READ8_MEMBER (i6300esb_lpc_device::lpc_if_fdd_lpt_range_r)
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{
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return lpc_if_fdd_lpt_range;
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}
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WRITE8_MEMBER (i6300esb_lpc_device::lpc_if_fdd_lpt_range_w)
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{
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COMBINE_DATA(&lpc_if_fdd_lpt_range);
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logerror("%s: lpc_if_fdd_lpt_range = %02x\n", tag(), lpc_if_fdd_lpt_range);
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}
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READ8_MEMBER (i6300esb_lpc_device::lpc_if_sound_range_r)
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{
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return lpc_if_sound_range;
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}
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WRITE8_MEMBER (i6300esb_lpc_device::lpc_if_sound_range_w)
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{
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COMBINE_DATA(&lpc_if_sound_range);
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logerror("%s: lpc_if_sound_range = %02x\n", tag(), lpc_if_sound_range);
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}
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READ8_MEMBER (i6300esb_lpc_device::fwh_dec_en1_r)
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{
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return fwh_dec_en1;
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}
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WRITE8_MEMBER (i6300esb_lpc_device::fwh_dec_en1_w)
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{
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fwh_dec_en1 = data | 0x80;
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logerror("%s: fwh_dec_en1 = %02x\n", tag(), fwh_dec_en1);
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}
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READ16_MEMBER (i6300esb_lpc_device::gen1_dec_r)
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{
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return gen1_dec;
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@ -110,10 +175,110 @@ WRITE32_MEMBER(i6300esb_lpc_device::fwh_sel1_w)
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logerror("%s: fwh_sel1 = %08x\n", tag(), fwh_sel1);
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}
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READ32_MEMBER (i6300esb_lpc_device::unk_fc_r)
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{
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logerror("%s: read undocumented config reg fc\n", tag());
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return 0;
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}
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WRITE32_MEMBER(i6300esb_lpc_device::unk_fc_w)
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{
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logerror("%s: write undocumented config reg fc (%08x)\n", tag(), data);
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}
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READ8_MEMBER (i6300esb_lpc_device::siu_config_port_r)
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{
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return siu_config_port;
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}
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WRITE8_MEMBER (i6300esb_lpc_device::siu_config_port_w)
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{
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siu_config_port = data;
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switch(siu_config_state) {
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case 0:
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siu_config_state = data == 0x80 ? 1 : 0;
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break;
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case 1:
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siu_config_state = data == 0x86 ? 2 : data == 0x80 ? 1 : 0;
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if(siu_config_state == 2)
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logerror("%s: siu configuration active\n", tag());
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break;
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case 2:
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siu_config_state = data == 0x68 ? 3 : 2;
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break;
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case 3:
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siu_config_state = data == 0x08 ? 0 : data == 0x68 ? 3 : 2;
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if(!siu_config_state)
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logerror("%s: siu configuration disabled\n", tag());
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break;
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}
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}
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READ8_MEMBER (i6300esb_lpc_device::siu_data_port_r)
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{
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logerror("%s: siu config read port %02x\n", tag(), siu_config_port);
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return 0xff;
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}
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WRITE8_MEMBER (i6300esb_lpc_device::siu_data_port_w)
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{
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if(siu_config_state < 2) {
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logerror("%s: siu config write port with config disabled (port=%02x, data=%02x)\n", tag(), siu_config_port, data);
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return;
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}
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logerror("%s: siu config write port %02x, %02x\n", tag(), siu_config_port, data);
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}
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WRITE8_MEMBER (i6300esb_lpc_device::nop_w)
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{
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}
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void i6300esb_lpc_device::map_bios(address_space *memory_space, UINT32 start, UINT32 end, int idsel)
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{
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// Ignore idsel, a16 inversion for now
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UINT32 mask = m_region->bytes() - 1;
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memory_space->install_rom(start, end, m_region->base() + (start & mask));
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}
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void i6300esb_lpc_device::map_extra(UINT64 memory_window_start, UINT64 memory_window_end, UINT64 memory_offset, address_space *memory_space,
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UINT64 io_window_start, UINT64 io_window_end, UINT64 io_offset, address_space *io_space)
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{
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memory_space->install_rom(0xfff00000, 0xffffffff, m_region->base());
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memory_space->install_rom(0x000f0000, 0x000fffff, m_region->base()+0xf0000);
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if(fwh_dec_en1 & 0x80) {
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map_bios(memory_space, 0xfff80000, 0xffffffff, 7);
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map_bios(memory_space, 0xffb80000, 0xffbfffff, 7);
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map_bios(memory_space, 0x000e0000, 0x000fffff, 7);
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}
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if(fwh_dec_en1 & 0x40) {
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map_bios(memory_space, 0xfff00000, 0xfff7ffff, 6);
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map_bios(memory_space, 0xffb00000, 0xffb7ffff, 6);
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}
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if(fwh_dec_en1 & 0x20) {
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map_bios(memory_space, 0xffe80000, 0xffefffff, 5);
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map_bios(memory_space, 0xffa80000, 0xffafffff, 5);
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}
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if(fwh_dec_en1 & 0x10) {
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map_bios(memory_space, 0xffe00000, 0xffe7ffff, 4);
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map_bios(memory_space, 0xffa00000, 0xffa7ffff, 4);
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}
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if(fwh_dec_en1 & 0x08) {
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map_bios(memory_space, 0xffd80000, 0xffdfffff, 3);
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map_bios(memory_space, 0xff980000, 0xff9fffff, 3);
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}
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if(fwh_dec_en1 & 0x04) {
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map_bios(memory_space, 0xffd00000, 0xffd7ffff, 2);
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map_bios(memory_space, 0xff900000, 0xff97ffff, 2);
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}
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if(fwh_dec_en1 & 0x02) {
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map_bios(memory_space, 0xffc80000, 0xffcfffff, 1);
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map_bios(memory_space, 0xff880000, 0xff8fffff, 1);
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}
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if(fwh_dec_en1 & 0x01) {
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map_bios(memory_space, 0xffc00000, 0xffc7ffff, 0);
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map_bios(memory_space, 0xff800000, 0xff87ffff, 0);
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}
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io_space->install_device(0, 0xffff, *this, &i6300esb_lpc_device::internal_io_map);
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}
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@ -15,31 +15,59 @@ class i6300esb_lpc_device : public pci_device {
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public:
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i6300esb_lpc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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virtual void reset_all_mappings();
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virtual void map_extra(UINT64 memory_window_start, UINT64 memory_window_end, UINT64 memory_offset, address_space *memory_space,
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UINT64 io_window_start, UINT64 io_window_end, UINT64 io_offset, address_space *io_space);
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virtual DECLARE_ADDRESS_MAP(config_map, 32);
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protected:
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virtual void device_start();
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virtual void device_reset();
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private:
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DECLARE_ADDRESS_MAP(internal_io_map, 32);
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UINT32 gpio_base, fwh_sel1;
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UINT16 gen1_dec, lpc_en;
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UINT8 gpio_cntl;
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UINT8 gpio_cntl, lpc_if_com_range, lpc_if_fdd_lpt_range, lpc_if_sound_range, fwh_dec_en1, siu_config_port;
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int siu_config_state;
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DECLARE_READ32_MEMBER (gpio_base_r); // 58
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DECLARE_WRITE8_MEMBER (nop_w);
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// configuration space registers
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DECLARE_READ32_MEMBER (gpio_base_r); // 58
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DECLARE_WRITE32_MEMBER(gpio_base_w);
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DECLARE_READ8_MEMBER (gpio_cntl_r); // 5c
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DECLARE_READ8_MEMBER (gpio_cntl_r); // 5c
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DECLARE_WRITE8_MEMBER (gpio_cntl_w);
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DECLARE_READ16_MEMBER (gen1_dec_r); // e4
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DECLARE_READ8_MEMBER (lpc_if_com_range_r); // e0
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DECLARE_WRITE8_MEMBER (lpc_if_com_range_w);
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DECLARE_READ8_MEMBER (lpc_if_fdd_lpt_range_r); // e1
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DECLARE_WRITE8_MEMBER (lpc_if_fdd_lpt_range_w);
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DECLARE_READ8_MEMBER (lpc_if_sound_range_r); // e2
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DECLARE_WRITE8_MEMBER (lpc_if_sound_range_w);
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DECLARE_READ8_MEMBER (fwh_dec_en1_r); // e3
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DECLARE_WRITE8_MEMBER (fwh_dec_en1_w);
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DECLARE_READ16_MEMBER (gen1_dec_r); // e4
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DECLARE_WRITE16_MEMBER(gen1_dec_w);
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DECLARE_READ16_MEMBER (lpc_en_r); // e6
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DECLARE_READ16_MEMBER (lpc_en_r); // e6
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DECLARE_WRITE16_MEMBER(lpc_en_w);
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DECLARE_READ32_MEMBER (fwh_sel1_r); // e8
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DECLARE_READ32_MEMBER (fwh_sel1_r); // e8
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DECLARE_WRITE32_MEMBER(fwh_sel1_w);
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DECLARE_READ32_MEMBER (unk_fc_r); // fc
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DECLARE_WRITE32_MEMBER(unk_fc_w);
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// i/o space registers
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DECLARE_READ8_MEMBER (siu_config_port_r); // 4e
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DECLARE_WRITE8_MEMBER (siu_config_port_w);
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DECLARE_READ8_MEMBER (siu_data_port_r); // 4f
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DECLARE_WRITE8_MEMBER (siu_data_port_w);
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void map_bios(address_space *memory_space, UINT32 start, UINT32 end, int idsel);
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};
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class i6300esb_watchdog_device : public pci_device {
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@ -4,6 +4,17 @@ const device_type PCI_ROOT = &device_creator<pci_root_device>;
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const device_type PCI_BRIDGE = &device_creator<pci_bridge_device>;
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DEVICE_ADDRESS_MAP_START(config_map, 32, pci_device)
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AM_RANGE(0x00, 0x03) AM_READ16(vendor_r, 0x0000ffff)
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AM_RANGE(0x00, 0x03) AM_READ16(device_r, 0xffff0000)
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AM_RANGE(0x08, 0x0b) AM_READ (class_rev_r)
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AM_RANGE(0x0c, 0x0f) AM_READ8 (cache_line_size_r, 0x000000ff)
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AM_RANGE(0x0c, 0x0f) AM_READ8 (latency_timer_r, 0x0000ff00)
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AM_RANGE(0x0c, 0x0f) AM_READ8 (header_type_r, 0x00ff0000)
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AM_RANGE(0x0c, 0x0f) AM_READ8 (bist_r, 0xff000000)
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AM_RANGE(0x2c, 0x2f) AM_READ16(subvendor_r, 0x0000ffff)
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AM_RANGE(0x2c, 0x2f) AM_READ16(subsystem_r, 0xffff0000)
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ADDRESS_MAP_END
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pci_device::pci_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source)
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@ -12,15 +23,15 @@ pci_device::pci_device(const machine_config &mconfig, device_type type, const ch
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main_id = 0xffffffff;
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revision = 0x00;
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pclass = 0xffffff;
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subdevice_id = 0xffffffff;
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subsystem_id = 0xffffffff;
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}
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void pci_device::set_ids(UINT32 _main_id, UINT8 _revision, UINT32 _pclass, UINT32 _subdevice_id)
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void pci_device::set_ids(UINT32 _main_id, UINT8 _revision, UINT32 _pclass, UINT32 _subsystem_id)
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{
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main_id = _main_id;
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revision = _revision;
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pclass = _pclass;
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subdevice_id = _subdevice_id;
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subsystem_id = _subsystem_id;
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}
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void pci_device::device_start()
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@ -31,6 +42,51 @@ void pci_device::device_reset()
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{
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}
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READ16_MEMBER(pci_device::vendor_r)
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{
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return main_id >> 16;
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}
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READ16_MEMBER(pci_device::device_r)
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{
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return main_id;
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}
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READ32_MEMBER(pci_device::class_rev_r)
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{
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return (pclass << 8) | revision;
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}
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READ8_MEMBER(pci_device::cache_line_size_r)
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{
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return 0x00;
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}
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READ8_MEMBER(pci_device::latency_timer_r)
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{
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return 0x00;
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}
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READ8_MEMBER(pci_device::header_type_r)
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{
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return 0x00;
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}
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READ8_MEMBER(pci_device::bist_r)
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{
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return 0x00;
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}
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READ16_MEMBER(pci_device::subvendor_r)
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{
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return subsystem_id >> 16;
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}
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READ16_MEMBER(pci_device::subsystem_r)
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{
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return subsystem_id;
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}
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void pci_device::scan_sub_devices(pci_device **devices, dynamic_array<pci_device *> &all, dynamic_array<pci_device *> &bridges, device_t *root)
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{
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}
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@ -92,6 +148,11 @@ pci_bridge_device::pci_bridge_device(const machine_config &mconfig, device_type
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{
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}
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READ8_MEMBER(pci_bridge_device::header_type_r)
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{
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return 0x01;
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}
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const address_space_config *pci_bridge_device::memory_space_config(address_spacenum spacenum) const
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{
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return spacenum == AS_PROGRAM ? &configure_space_config : NULL;
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@ -110,8 +171,6 @@ void pci_bridge_device::device_start()
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sub_devices[i] = NULL;
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for(device_t *d = bus_root()->first_subdevice(); d != NULL; d = d->next()) {
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if(d == this)
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continue;
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const char *t = d->tag();
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int l = strlen(t);
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if(l <= 4 || t[l-5] != ':' || t[l-2] != '.')
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@ -123,9 +182,11 @@ void pci_bridge_device::device_start()
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for(int i=0; i<32*8; i++)
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if(sub_devices[i]) {
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all_devices.append(sub_devices[i]);
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pci_bridge_device *bridge = dynamic_cast<pci_bridge_device *>(sub_devices[i]);
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if(bridge)
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||||
all_bridges.append(bridge);
|
||||
if(sub_devices[i] != this) {
|
||||
pci_bridge_device *bridge = dynamic_cast<pci_bridge_device *>(sub_devices[i]);
|
||||
if(bridge)
|
||||
all_bridges.append(bridge);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -138,7 +199,8 @@ void pci_bridge_device::device_reset()
|
||||
void pci_bridge_device::reset_all_mappings()
|
||||
{
|
||||
for(int i=0; i != all_devices.count(); i++)
|
||||
all_devices[i]->reset_all_mappings();
|
||||
if(all_devices[i] != this)
|
||||
all_devices[i]->reset_all_mappings();
|
||||
}
|
||||
|
||||
|
||||
@ -146,8 +208,9 @@ void pci_bridge_device::map_device(UINT64 memory_window_start, UINT64 memory_win
|
||||
UINT64 io_window_start, UINT64 io_window_end, UINT64 io_offset, address_space *io_space)
|
||||
{
|
||||
for(int i = all_devices.count()-1; i>=0; i--)
|
||||
all_devices[i]->map_device(memory_window_start, memory_window_end, memory_offset, memory_space,
|
||||
io_window_start, io_window_end, io_offset, io_space);
|
||||
if(all_devices[i] != this)
|
||||
all_devices[i]->map_device(memory_window_start, memory_window_end, memory_offset, memory_space,
|
||||
io_window_start, io_window_end, io_offset, io_space);
|
||||
|
||||
map_extra(memory_window_start, memory_window_end, memory_offset, memory_space,
|
||||
io_window_start, io_window_end, io_offset, io_space);
|
||||
@ -208,8 +271,7 @@ void pci_host_device::device_start()
|
||||
void pci_host_device::device_reset()
|
||||
{
|
||||
pci_bridge_device::device_reset();
|
||||
for(int i=0; i != all_devices.count(); i++)
|
||||
all_devices[i]->reset_all_mappings();
|
||||
reset_all_mappings();
|
||||
regenerate_mapping();
|
||||
|
||||
config_address = 0;
|
||||
@ -217,6 +279,7 @@ void pci_host_device::device_reset()
|
||||
|
||||
void pci_host_device::regenerate_mapping()
|
||||
{
|
||||
logerror("Regenerating mapping\n");
|
||||
memory_space->unmap_readwrite(memory_window_start, memory_window_end);
|
||||
io_space->unmap_readwrite(io_window_start, io_window_end);
|
||||
|
||||
@ -224,12 +287,6 @@ void pci_host_device::regenerate_mapping()
|
||||
io_window_start, io_window_end, io_offset, io_space);
|
||||
}
|
||||
|
||||
void pci_host_device::regenerate_config_mapping()
|
||||
{
|
||||
pci_bridge_device::regenerate_config_mapping();
|
||||
map_config(0, &space(AS_PROGRAM));
|
||||
}
|
||||
|
||||
READ32_MEMBER(pci_host_device::config_address_r)
|
||||
{
|
||||
return config_address;
|
||||
|
||||
@ -6,15 +6,15 @@
|
||||
#define MCFG_PCI_ROOT_ADD(_tag) \
|
||||
MCFG_DEVICE_ADD(_tag, PCI_ROOT, 0)
|
||||
|
||||
#define MCFG_PCI_DEVICE_ADD(_tag, _type, _main_id, _revision, _pclass, _subdevice_id) \
|
||||
#define MCFG_PCI_DEVICE_ADD(_tag, _type, _main_id, _revision, _pclass, _subsystem_id) \
|
||||
MCFG_DEVICE_ADD(_tag, _type, 0) \
|
||||
downcast<pci_device *>(device)->set_ids(_main_id, _revision, _pclass, _subdevice_id);
|
||||
downcast<pci_device *>(device)->set_ids(_main_id, _revision, _pclass, _subsystem_id);
|
||||
|
||||
#define MCFG_AGP_DEVICE_ADD(_tag, _type, _main_id, _revision, _subdevice_id) \
|
||||
MCFG_PCI_DEVICE_ADD(_tag, _type, _main_id, _revision, 0x030000, _subdevice_id)
|
||||
#define MCFG_AGP_DEVICE_ADD(_tag, _type, _main_id, _revision, _subsystem_id) \
|
||||
MCFG_PCI_DEVICE_ADD(_tag, _type, _main_id, _revision, 0x030000, _subsystem_id)
|
||||
|
||||
#define MCFG_PCI_HOST_ADD(_tag, _type, _main_id, _revision, _subdevice_id) \
|
||||
MCFG_PCI_DEVICE_ADD(_tag, _type, _main_id, _revision, 0x060000, _subdevice_id)
|
||||
#define MCFG_PCI_HOST_ADD(_tag, _type, _main_id, _revision, _subsystem_id) \
|
||||
MCFG_PCI_DEVICE_ADD(_tag, _type, _main_id, _revision, 0x060000, _subsystem_id)
|
||||
|
||||
#define MCFG_PCI_BRIDGE_ADD(_tag, _main_id, _revision) \
|
||||
MCFG_PCI_DEVICE_ADD(_tag, PCI_BRIDGE, _main_id, _revision, 0x060400, 0x00000000)
|
||||
@ -26,7 +26,7 @@ class pci_device : public device_t {
|
||||
public:
|
||||
pci_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source);
|
||||
|
||||
void set_ids(UINT32 main_id, UINT8 revision, UINT32 pclass, UINT32 subdevice_id);
|
||||
void set_ids(UINT32 main_id, UINT8 revision, UINT32 pclass, UINT32 subsystem_id);
|
||||
|
||||
virtual void reset_all_mappings();
|
||||
virtual void map_device(UINT64 memory_window_start, UINT64 memory_window_end, UINT64 memory_offset, address_space *memory_space,
|
||||
@ -38,6 +38,16 @@ public:
|
||||
|
||||
virtual DECLARE_ADDRESS_MAP(config_map, 32);
|
||||
|
||||
DECLARE_READ16_MEMBER(vendor_r);
|
||||
DECLARE_READ16_MEMBER(device_r);
|
||||
DECLARE_READ32_MEMBER(class_rev_r);
|
||||
virtual DECLARE_READ8_MEMBER(cache_line_size_r);
|
||||
virtual DECLARE_READ8_MEMBER(latency_timer_r);
|
||||
virtual DECLARE_READ8_MEMBER(header_type_r);
|
||||
virtual DECLARE_READ8_MEMBER(bist_r);
|
||||
DECLARE_READ16_MEMBER(subvendor_r);
|
||||
DECLARE_READ16_MEMBER(subsystem_r);
|
||||
|
||||
protected:
|
||||
enum {
|
||||
M_MEM = 0,
|
||||
@ -47,7 +57,7 @@ protected:
|
||||
M_PREF = 8
|
||||
};
|
||||
|
||||
UINT32 main_id, subdevice_id;
|
||||
UINT32 main_id, subsystem_id;
|
||||
UINT32 pclass;
|
||||
UINT8 revision;
|
||||
|
||||
@ -81,6 +91,8 @@ public:
|
||||
UINT64 io_window_start, UINT64 io_window_end, UINT64 io_offset, address_space *io_space);
|
||||
virtual void reset_all_mappings();
|
||||
|
||||
virtual DECLARE_READ8_MEMBER(header_type_r);
|
||||
|
||||
protected:
|
||||
pci_device *sub_devices[32*8];
|
||||
dynamic_array<pci_device *> all_devices;
|
||||
@ -134,7 +146,6 @@ protected:
|
||||
void config_write(UINT8 bus, UINT8 device, UINT16 reg, UINT32 data, UINT32 mem_mask);
|
||||
|
||||
void regenerate_mapping();
|
||||
virtual void regenerate_config_mapping();
|
||||
};
|
||||
|
||||
class pci_root_device : public device_t {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user