From a70f95ea21f718c96c875c3f9b98fed776fe7f84 Mon Sep 17 00:00:00 2001 From: Wilbert Pol Date: Sat, 3 Aug 2013 19:51:36 +0000 Subject: [PATCH] i860.c: Modernized cpu core. (nw) --- src/emu/cpu/i860/i860.c | 541 +++++------- src/emu/cpu/i860/i860.h | 225 +++-- src/emu/cpu/i860/i860dec.c | 1705 ++++++++++++++++++------------------ src/mame/drivers/vcombat.c | 30 +- 4 files changed, 1223 insertions(+), 1278 deletions(-) diff --git a/src/emu/cpu/i860/i860.c b/src/emu/cpu/i860/i860.c index 0eb956b9b4b..0ea1be31177 100644 --- a/src/emu/cpu/i860/i860.c +++ b/src/emu/cpu/i860/i860.c @@ -22,349 +22,220 @@ TODO: Separate out i860XR and i860XP (make different types, etc). #include "debugger.h" #include "i860.h" -/************************************************************************** - * Functions specified by GET_INFO - **************************************************************************/ -static CPU_INIT( i860 ) +/* Control register numbers. */ +enum { + CR_FIR = 0, + CR_PSR = 1, + CR_DIRBASE = 2, + CR_DB = 3, + CR_FSR = 4, + CR_EPSR = 5 +}; + + +const device_type I860 = &device_creator; + + +i860_cpu_device::i860_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : cpu_device(mconfig, I860, "i860XR", tag, owner, clock, "i860xr", __FILE__) + , m_program_config("program", ENDIANNESS_LITTLE, 64, 32, 0) { - i860_state_t *cpustate = get_safe_token(device); - cpustate->device = device; - cpustate->program = &device->space(AS_PROGRAM); - reset_i860(cpustate); - i860_set_pin(device, DEC_PIN_BUS_HOLD, 0); - i860_set_pin(device, DEC_PIN_RESET, 0); - cpustate->single_stepping = 0; - - device->save_item(NAME(cpustate->iregs)); - device->save_item(NAME(cpustate->cregs)); - device->save_item(NAME(cpustate->frg)); - device->save_item(NAME(cpustate->pc)); -} - -static CPU_RESET( i860 ) -{ - i860_state_t *cpustate = get_safe_token(device); - reset_i860(cpustate); } -extern CPU_DISASSEMBLE( i860 ); +void i860_cpu_device::device_start() +{ + m_program = &space(AS_PROGRAM); + reset_i860(); + i860_set_pin(DEC_PIN_BUS_HOLD, 0); + i860_set_pin(DEC_PIN_RESET, 0); + m_single_stepping = 0; + + save_item(NAME(m_iregs)); + save_item(NAME(m_cregs)); + save_item(NAME(m_frg)); + save_item(NAME(m_pc)); + + state_add( I860_PC, "PC", m_pc).formatstr("%08X"); + state_add( I860_FIR, "FIR", m_cregs[CR_FIR]).formatstr("%08X"); + state_add( I860_PSR, "PSR", m_cregs[CR_PSR]).formatstr("%08X"); + state_add( I860_DIRBASE, "DIRBASE", m_cregs[CR_DIRBASE]).formatstr("%08X"); + state_add( I860_DB, "DB", m_cregs[CR_DB]).formatstr("%08X"); + state_add( I860_FSR, "FSR", m_cregs[CR_FSR]).formatstr("%08X"); + state_add( I860_EPSR, "EPSR", m_cregs[CR_EPSR]).formatstr("%08X"); + state_add( I860_R0, "R0", m_iregs[0]).formatstr("%08X"); + state_add( I860_R1, "R1", m_iregs[1]).formatstr("%08X"); + state_add( I860_R2, "R2", m_iregs[2]).formatstr("%08X"); + state_add( I860_R3, "R3", m_iregs[3]).formatstr("%08X"); + state_add( I860_R4, "R4", m_iregs[4]).formatstr("%08X"); + state_add( I860_R5, "R5", m_iregs[5]).formatstr("%08X"); + state_add( I860_R6, "R6", m_iregs[6]).formatstr("%08X"); + state_add( I860_R7, "R7", m_iregs[7]).formatstr("%08X"); + state_add( I860_R8, "R8", m_iregs[8]).formatstr("%08X"); + state_add( I860_R9, "R9", m_iregs[9]).formatstr("%08X"); + state_add( I860_R10, "R10", m_iregs[10]).formatstr("%08X"); + state_add( I860_R11, "R11", m_iregs[11]).formatstr("%08X"); + state_add( I860_R12, "R12", m_iregs[12]).formatstr("%08X"); + state_add( I860_R13, "R13", m_iregs[13]).formatstr("%08X"); + state_add( I860_R14, "R14", m_iregs[14]).formatstr("%08X"); + state_add( I860_R15, "R15", m_iregs[15]).formatstr("%08X"); + state_add( I860_R16, "R16", m_iregs[16]).formatstr("%08X"); + state_add( I860_R17, "R17", m_iregs[17]).formatstr("%08X"); + state_add( I860_R18, "R18", m_iregs[18]).formatstr("%08X"); + state_add( I860_R19, "R19", m_iregs[19]).formatstr("%08X"); + state_add( I860_R20, "R20", m_iregs[20]).formatstr("%08X"); + state_add( I860_R21, "R21", m_iregs[21]).formatstr("%08X"); + state_add( I860_R22, "R22", m_iregs[22]).formatstr("%08X"); + state_add( I860_R23, "R23", m_iregs[23]).formatstr("%08X"); + state_add( I860_R24, "R24", m_iregs[24]).formatstr("%08X"); + state_add( I860_R25, "R25", m_iregs[25]).formatstr("%08X"); + state_add( I860_R26, "R26", m_iregs[26]).formatstr("%08X"); + state_add( I860_R27, "R27", m_iregs[27]).formatstr("%08X"); + state_add( I860_R28, "R28", m_iregs[28]).formatstr("%08X"); + state_add( I860_R29, "R29", m_iregs[29]).formatstr("%08X"); + state_add( I860_R30, "R30", m_iregs[30]).formatstr("%08X"); + state_add( I860_R31, "R31", m_iregs[31]).formatstr("%08X"); + + state_add( I860_F0, "F0", m_freg[0]).callimport().callexport().formatstr("%08X"); + state_add( I860_F1, "F1", m_freg[1]).callimport().callexport().formatstr("%08X"); + state_add( I860_F2, "F2", m_freg[2]).callimport().callexport().formatstr("%08X"); + state_add( I860_F3, "F3", m_freg[3]).callimport().callexport().formatstr("%08X"); + state_add( I860_F4, "F4", m_freg[4]).callimport().callexport().formatstr("%08X"); + state_add( I860_F5, "F5", m_freg[5]).callimport().callexport().formatstr("%08X"); + state_add( I860_F6, "F6", m_freg[6]).callimport().callexport().formatstr("%08X"); + state_add( I860_F7, "F7", m_freg[7]).callimport().callexport().formatstr("%08X"); + state_add( I860_F8, "F8", m_freg[8]).callimport().callexport().formatstr("%08X"); + state_add( I860_F9, "F9", m_freg[9]).callimport().callexport().formatstr("%08X"); + state_add( I860_F10, "F10", m_freg[10]).callimport().callexport().formatstr("%08X"); + state_add( I860_F11, "F11", m_freg[11]).callimport().callexport().formatstr("%08X"); + state_add( I860_F12, "F12", m_freg[12]).callimport().callexport().formatstr("%08X"); + state_add( I860_F13, "F13", m_freg[13]).callimport().callexport().formatstr("%08X"); + state_add( I860_F14, "F14", m_freg[14]).callimport().callexport().formatstr("%08X"); + state_add( I860_F15, "F15", m_freg[15]).callimport().callexport().formatstr("%08X"); + state_add( I860_F16, "F16", m_freg[16]).callimport().callexport().formatstr("%08X"); + state_add( I860_F17, "F17", m_freg[17]).callimport().callexport().formatstr("%08X"); + state_add( I860_F18, "F18", m_freg[18]).callimport().callexport().formatstr("%08X"); + state_add( I860_F19, "F19", m_freg[19]).callimport().callexport().formatstr("%08X"); + state_add( I860_F20, "F20", m_freg[20]).callimport().callexport().formatstr("%08X"); + state_add( I860_F21, "F21", m_freg[21]).callimport().callexport().formatstr("%08X"); + state_add( I860_F22, "F22", m_freg[22]).callimport().callexport().formatstr("%08X"); + state_add( I860_F23, "F23", m_freg[23]).callimport().callexport().formatstr("%08X"); + state_add( I860_F24, "F24", m_freg[24]).callimport().callexport().formatstr("%08X"); + state_add( I860_F25, "F25", m_freg[25]).callimport().callexport().formatstr("%08X"); + state_add( I860_F26, "F26", m_freg[26]).callimport().callexport().formatstr("%08X"); + state_add( I860_F27, "F27", m_freg[27]).callimport().callexport().formatstr("%08X"); + state_add( I860_F28, "F28", m_freg[28]).callimport().callexport().formatstr("%08X"); + state_add( I860_F29, "F29", m_freg[29]).callimport().callexport().formatstr("%08X"); + state_add( I860_F30, "F30", m_freg[30]).callimport().callexport().formatstr("%08X"); + state_add( I860_F31, "F31", m_freg[31]).callimport().callexport().formatstr("%08X"); + + state_add(STATE_GENPC, "curpc", m_pc).noshow(); + + m_icountptr = &m_icount; +} + + +void i860_cpu_device::state_import(const device_state_entry &entry) +{ +#define I860_SET_INFO_F(fnum) m_frg[0+(4*fnum)] = (m_freg[fnum] & 0x000000ff); \ + m_frg[1+(4*fnum)] = (m_freg[fnum] & 0x0000ff00) >> 8; \ + m_frg[2+(4*fnum)] = (m_freg[fnum] & 0x00ff0000) >> 16; \ + m_frg[3+(4*fnum)] = (m_freg[fnum] & 0xff000000) >> 24; + + switch (entry.index()) + { + case I860_F0: I860_SET_INFO_F(0); break; + case I860_F1: I860_SET_INFO_F(1); break; + case I860_F2: I860_SET_INFO_F(2); break; + case I860_F3: I860_SET_INFO_F(3); break; + case I860_F4: I860_SET_INFO_F(4); break; + case I860_F5: I860_SET_INFO_F(5); break; + case I860_F6: I860_SET_INFO_F(6); break; + case I860_F7: I860_SET_INFO_F(7); break; + case I860_F8: I860_SET_INFO_F(8); break; + case I860_F9: I860_SET_INFO_F(9); break; + case I860_F10: I860_SET_INFO_F(10); break; + case I860_F11: I860_SET_INFO_F(11); break; + case I860_F12: I860_SET_INFO_F(12); break; + case I860_F13: I860_SET_INFO_F(13); break; + case I860_F14: I860_SET_INFO_F(14); break; + case I860_F15: I860_SET_INFO_F(15); break; + case I860_F16: I860_SET_INFO_F(16); break; + case I860_F17: I860_SET_INFO_F(17); break; + case I860_F18: I860_SET_INFO_F(18); break; + case I860_F19: I860_SET_INFO_F(19); break; + case I860_F20: I860_SET_INFO_F(20); break; + case I860_F21: I860_SET_INFO_F(21); break; + case I860_F22: I860_SET_INFO_F(22); break; + case I860_F23: I860_SET_INFO_F(23); break; + case I860_F24: I860_SET_INFO_F(24); break; + case I860_F25: I860_SET_INFO_F(25); break; + case I860_F26: I860_SET_INFO_F(26); break; + case I860_F27: I860_SET_INFO_F(27); break; + case I860_F28: I860_SET_INFO_F(28); break; + case I860_F29: I860_SET_INFO_F(29); break; + case I860_F30: I860_SET_INFO_F(30); break; + case I860_F31: I860_SET_INFO_F(31); break; + } +} + +void i860_cpu_device::state_export(const device_state_entry &entry) +{ +#define I860_GET_INFO_F(fnum) m_freg[fnum] = m_frg[0+(4*fnum)] | ( m_frg[1+(4*fnum)] << 8 ) | ( m_frg[2+(4*fnum)] << 16 ) | ( m_frg[3+(4*fnum)] << 24) + + switch (entry.index()) + { + case I860_F0: I860_GET_INFO_F(0); break; + case I860_F1: I860_GET_INFO_F(1); break; + case I860_F2: I860_GET_INFO_F(2); break; + case I860_F3: I860_GET_INFO_F(3); break; + case I860_F4: I860_GET_INFO_F(4); break; + case I860_F5: I860_GET_INFO_F(5); break; + case I860_F6: I860_GET_INFO_F(6); break; + case I860_F7: I860_GET_INFO_F(7); break; + case I860_F8: I860_GET_INFO_F(8); break; + case I860_F9: I860_GET_INFO_F(9); break; + case I860_F10: I860_GET_INFO_F(10); break; + case I860_F11: I860_GET_INFO_F(11); break; + case I860_F12: I860_GET_INFO_F(12); break; + case I860_F13: I860_GET_INFO_F(13); break; + case I860_F14: I860_GET_INFO_F(14); break; + case I860_F15: I860_GET_INFO_F(15); break; + case I860_F16: I860_GET_INFO_F(16); break; + case I860_F17: I860_GET_INFO_F(17); break; + case I860_F18: I860_GET_INFO_F(18); break; + case I860_F19: I860_GET_INFO_F(19); break; + case I860_F20: I860_GET_INFO_F(20); break; + case I860_F21: I860_GET_INFO_F(21); break; + case I860_F22: I860_GET_INFO_F(22); break; + case I860_F23: I860_GET_INFO_F(23); break; + case I860_F24: I860_GET_INFO_F(24); break; + case I860_F25: I860_GET_INFO_F(25); break; + case I860_F26: I860_GET_INFO_F(26); break; + case I860_F27: I860_GET_INFO_F(27); break; + case I860_F28: I860_GET_INFO_F(28); break; + case I860_F29: I860_GET_INFO_F(29); break; + case I860_F30: I860_GET_INFO_F(30); break; + case I860_F31: I860_GET_INFO_F(31); break; + } +} + +void i860_cpu_device::device_reset() +{ + reset_i860(); +} + + +offs_t i860_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) +{ + extern CPU_DISASSEMBLE( i860 ); + return CPU_DISASSEMBLE_NAME(i860)(this, buffer, pc, oprom, opram, options); +} + /************************************************************************** * The actual decode and execute code. **************************************************************************/ #include "i860dec.c" - -/************************************************************************** - * Generic set_info/get_info - **************************************************************************/ - -#define CPU_SET_INFO_F(fnum) cpustate->frg[0+(4*fnum)] = (info->i & 0x000000ff); \ - cpustate->frg[1+(4*fnum)] = (info->i & 0x0000ff00) >> 8; \ - cpustate->frg[2+(4*fnum)] = (info->i & 0x00ff0000) >> 16; \ - cpustate->frg[3+(4*fnum)] = (info->i & 0xff000000) >> 24; - -static CPU_SET_INFO( i860 ) -{ - i860_state_t *cpustate = get_safe_token(device); - - switch(state) - { - case CPUINFO_INT_PC: - case CPUINFO_INT_REGISTER + I860_PC: cpustate->pc = info->i & 0xffffffff; break; - - case CPUINFO_INT_REGISTER + I860_FIR: cpustate->cregs[CR_FIR] = info->i & 0xffffffff; break; - case CPUINFO_INT_REGISTER + I860_PSR: cpustate->cregs[CR_PSR] = info->i & 0xffffffff; break; - case CPUINFO_INT_REGISTER + I860_DIRBASE: cpustate->cregs[CR_DIRBASE] = info->i & 0xffffffff; break; - case CPUINFO_INT_REGISTER + I860_DB: cpustate->cregs[CR_DB] = info->i & 0xffffffff; break; - case CPUINFO_INT_REGISTER + I860_FSR: cpustate->cregs[CR_FSR] = info->i & 0xffffffff; break; - case CPUINFO_INT_REGISTER + I860_EPSR: cpustate->cregs[CR_EPSR] = info->i & 0xffffffff; break; - - case CPUINFO_INT_REGISTER + I860_R0: cpustate->iregs[0] = info->i & 0xffffffff; break; - case CPUINFO_INT_REGISTER + I860_R1: cpustate->iregs[1] = info->i & 0xffffffff; break; - case CPUINFO_INT_REGISTER + I860_R2: cpustate->iregs[2] = info->i & 0xffffffff; break; - case CPUINFO_INT_REGISTER + I860_R3: cpustate->iregs[3] = info->i & 0xffffffff; break; - case CPUINFO_INT_REGISTER + I860_R4: cpustate->iregs[4] = info->i & 0xffffffff; break; - case CPUINFO_INT_REGISTER + I860_R5: cpustate->iregs[5] = info->i & 0xffffffff; break; - case CPUINFO_INT_REGISTER + I860_R6: cpustate->iregs[6] = info->i & 0xffffffff; break; - case CPUINFO_INT_REGISTER + I860_R7: cpustate->iregs[7] = info->i & 0xffffffff; break; - case CPUINFO_INT_REGISTER + I860_R8: cpustate->iregs[8] = info->i & 0xffffffff; break; - case CPUINFO_INT_REGISTER + I860_R9: cpustate->iregs[9] = info->i & 0xffffffff; break; - case CPUINFO_INT_REGISTER + I860_R10: cpustate->iregs[10] = info->i & 0xffffffff; break; - case CPUINFO_INT_REGISTER + I860_R11: cpustate->iregs[11] = info->i & 0xffffffff; break; - case CPUINFO_INT_REGISTER + I860_R12: cpustate->iregs[12] = info->i & 0xffffffff; break; - case CPUINFO_INT_REGISTER + I860_R13: cpustate->iregs[13] = info->i & 0xffffffff; break; - case CPUINFO_INT_REGISTER + I860_R14: cpustate->iregs[14] = info->i & 0xffffffff; break; - case CPUINFO_INT_REGISTER + I860_R15: cpustate->iregs[15] = info->i & 0xffffffff; break; - case CPUINFO_INT_REGISTER + I860_R16: cpustate->iregs[16] = info->i & 0xffffffff; break; - case CPUINFO_INT_REGISTER + I860_R17: cpustate->iregs[17] = info->i & 0xffffffff; break; - case CPUINFO_INT_REGISTER + I860_R18: cpustate->iregs[18] = info->i & 0xffffffff; break; - case CPUINFO_INT_REGISTER + I860_R19: cpustate->iregs[19] = info->i & 0xffffffff; break; - case CPUINFO_INT_REGISTER + I860_R20: cpustate->iregs[20] = info->i & 0xffffffff; break; - case CPUINFO_INT_REGISTER + I860_R21: cpustate->iregs[21] = info->i & 0xffffffff; break; - case CPUINFO_INT_REGISTER + I860_R22: cpustate->iregs[22] = info->i & 0xffffffff; break; - case CPUINFO_INT_REGISTER + I860_R23: cpustate->iregs[23] = info->i & 0xffffffff; break; - case CPUINFO_INT_REGISTER + I860_R24: cpustate->iregs[24] = info->i & 0xffffffff; break; - case CPUINFO_INT_REGISTER + I860_R25: cpustate->iregs[25] = info->i & 0xffffffff; break; - case CPUINFO_INT_REGISTER + I860_R26: cpustate->iregs[26] = info->i & 0xffffffff; break; - case CPUINFO_INT_REGISTER + I860_R27: cpustate->iregs[27] = info->i & 0xffffffff; break; - case CPUINFO_INT_REGISTER + I860_R28: cpustate->iregs[28] = info->i & 0xffffffff; break; - case CPUINFO_INT_REGISTER + I860_R29: cpustate->iregs[29] = info->i & 0xffffffff; break; - case CPUINFO_INT_REGISTER + I860_R30: cpustate->iregs[30] = info->i & 0xffffffff; break; - case CPUINFO_INT_REGISTER + I860_R31: cpustate->iregs[31] = info->i & 0xffffffff; break; - - case CPUINFO_INT_REGISTER + I860_F0: CPU_SET_INFO_F(0); break; - case CPUINFO_INT_REGISTER + I860_F1: CPU_SET_INFO_F(1); break; - case CPUINFO_INT_REGISTER + I860_F2: CPU_SET_INFO_F(2); break; - case CPUINFO_INT_REGISTER + I860_F3: CPU_SET_INFO_F(3); break; - case CPUINFO_INT_REGISTER + I860_F4: CPU_SET_INFO_F(4); break; - case CPUINFO_INT_REGISTER + I860_F5: CPU_SET_INFO_F(5); break; - case CPUINFO_INT_REGISTER + I860_F6: CPU_SET_INFO_F(6); break; - case CPUINFO_INT_REGISTER + I860_F7: CPU_SET_INFO_F(7); break; - case CPUINFO_INT_REGISTER + I860_F8: CPU_SET_INFO_F(8); break; - case CPUINFO_INT_REGISTER + I860_F9: CPU_SET_INFO_F(9); break; - case CPUINFO_INT_REGISTER + I860_F10: CPU_SET_INFO_F(10); break; - case CPUINFO_INT_REGISTER + I860_F11: CPU_SET_INFO_F(11); break; - case CPUINFO_INT_REGISTER + I860_F12: CPU_SET_INFO_F(12); break; - case CPUINFO_INT_REGISTER + I860_F13: CPU_SET_INFO_F(13); break; - case CPUINFO_INT_REGISTER + I860_F14: CPU_SET_INFO_F(14); break; - case CPUINFO_INT_REGISTER + I860_F15: CPU_SET_INFO_F(15); break; - case CPUINFO_INT_REGISTER + I860_F16: CPU_SET_INFO_F(16); break; - case CPUINFO_INT_REGISTER + I860_F17: CPU_SET_INFO_F(17); break; - case CPUINFO_INT_REGISTER + I860_F18: CPU_SET_INFO_F(18); break; - case CPUINFO_INT_REGISTER + I860_F19: CPU_SET_INFO_F(19); break; - case CPUINFO_INT_REGISTER + I860_F20: CPU_SET_INFO_F(20); break; - case CPUINFO_INT_REGISTER + I860_F21: CPU_SET_INFO_F(21); break; - case CPUINFO_INT_REGISTER + I860_F22: CPU_SET_INFO_F(22); break; - case CPUINFO_INT_REGISTER + I860_F23: CPU_SET_INFO_F(23); break; - case CPUINFO_INT_REGISTER + I860_F24: CPU_SET_INFO_F(24); break; - case CPUINFO_INT_REGISTER + I860_F25: CPU_SET_INFO_F(25); break; - case CPUINFO_INT_REGISTER + I860_F26: CPU_SET_INFO_F(26); break; - case CPUINFO_INT_REGISTER + I860_F27: CPU_SET_INFO_F(27); break; - case CPUINFO_INT_REGISTER + I860_F28: CPU_SET_INFO_F(28); break; - case CPUINFO_INT_REGISTER + I860_F29: CPU_SET_INFO_F(29); break; - case CPUINFO_INT_REGISTER + I860_F30: CPU_SET_INFO_F(30); break; - case CPUINFO_INT_REGISTER + I860_F31: CPU_SET_INFO_F(31); break; - } -} - -#define CPU_GET_INFO_INT_F(fnum) (info->i = cpustate->frg[0+(4*fnum)] | \ - cpustate->frg[1+(4*fnum)] << 8 | \ - cpustate->frg[2+(4*fnum)] << 16 | \ - cpustate->frg[3+(4*fnum)] << 24) - -#define CPU_GET_INFO_STR_F(fnum) (sprintf(info->s, "F%d : %08x", fnum, cpustate->frg[0+(4*fnum)] | \ - cpustate->frg[1+(4*fnum)] << 8 | \ - cpustate->frg[2+(4*fnum)] << 16 | \ - cpustate->frg[3+(4*fnum)] << 24)) - -CPU_GET_INFO( i860 ) -{ - i860_state_t *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL; - - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(i860_state_t); break; - case CPUINFO_INT_INPUT_LINES: info->i = 0; break; - case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0x00000000; break; - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break; - case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break; - case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break; - case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 4; break; - case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 4; break; - case CPUINFO_INT_MIN_CYCLES: info->i = 1; break; - case CPUINFO_INT_MAX_CYCLES: info->i = 8; break; - - case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 64; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 32; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break; - - case CPUINFO_INT_PC: - case CPUINFO_INT_REGISTER + I860_PC: info->i = cpustate->pc; break; - case CPUINFO_INT_PREVIOUSPC: info->i = cpustate->ppc; break; - - case CPUINFO_INT_REGISTER + I860_FIR: info->i = cpustate->cregs[CR_FIR]; break; - case CPUINFO_INT_REGISTER + I860_PSR: info->i = cpustate->cregs[CR_PSR]; break; - case CPUINFO_INT_REGISTER + I860_DIRBASE: info->i = cpustate->cregs[CR_DIRBASE]; break; - case CPUINFO_INT_REGISTER + I860_DB: info->i = cpustate->cregs[CR_DB]; break; - case CPUINFO_INT_REGISTER + I860_FSR: info->i = cpustate->cregs[CR_FSR]; break; - case CPUINFO_INT_REGISTER + I860_EPSR: info->i = cpustate->cregs[CR_EPSR]; break; - - case CPUINFO_INT_REGISTER + I860_R0: info->i = cpustate->iregs[0]; break; - case CPUINFO_INT_REGISTER + I860_R1: info->i = cpustate->iregs[1]; break; - case CPUINFO_INT_REGISTER + I860_R2: info->i = cpustate->iregs[2]; break; - case CPUINFO_INT_REGISTER + I860_R3: info->i = cpustate->iregs[3]; break; - case CPUINFO_INT_REGISTER + I860_R4: info->i = cpustate->iregs[4]; break; - case CPUINFO_INT_REGISTER + I860_R5: info->i = cpustate->iregs[5]; break; - case CPUINFO_INT_REGISTER + I860_R6: info->i = cpustate->iregs[6]; break; - case CPUINFO_INT_REGISTER + I860_R7: info->i = cpustate->iregs[7]; break; - case CPUINFO_INT_REGISTER + I860_R8: info->i = cpustate->iregs[8]; break; - case CPUINFO_INT_REGISTER + I860_R9: info->i = cpustate->iregs[9]; break; - case CPUINFO_INT_REGISTER + I860_R10: info->i = cpustate->iregs[10]; break; - case CPUINFO_INT_REGISTER + I860_R11: info->i = cpustate->iregs[11]; break; - case CPUINFO_INT_REGISTER + I860_R12: info->i = cpustate->iregs[12]; break; - case CPUINFO_INT_REGISTER + I860_R13: info->i = cpustate->iregs[13]; break; - case CPUINFO_INT_REGISTER + I860_R14: info->i = cpustate->iregs[14]; break; - case CPUINFO_INT_REGISTER + I860_R15: info->i = cpustate->iregs[15]; break; - case CPUINFO_INT_REGISTER + I860_R16: info->i = cpustate->iregs[16]; break; - case CPUINFO_INT_REGISTER + I860_R17: info->i = cpustate->iregs[17]; break; - case CPUINFO_INT_REGISTER + I860_R18: info->i = cpustate->iregs[18]; break; - case CPUINFO_INT_REGISTER + I860_R19: info->i = cpustate->iregs[19]; break; - case CPUINFO_INT_REGISTER + I860_R20: info->i = cpustate->iregs[20]; break; - case CPUINFO_INT_REGISTER + I860_R21: info->i = cpustate->iregs[21]; break; - case CPUINFO_INT_REGISTER + I860_R22: info->i = cpustate->iregs[22]; break; - case CPUINFO_INT_REGISTER + I860_R23: info->i = cpustate->iregs[23]; break; - case CPUINFO_INT_REGISTER + I860_R24: info->i = cpustate->iregs[24]; break; - case CPUINFO_INT_REGISTER + I860_R25: info->i = cpustate->iregs[25]; break; - case CPUINFO_INT_REGISTER + I860_R26: info->i = cpustate->iregs[26]; break; - case CPUINFO_INT_REGISTER + I860_R27: info->i = cpustate->iregs[27]; break; - case CPUINFO_INT_REGISTER + I860_R28: info->i = cpustate->iregs[28]; break; - case CPUINFO_INT_REGISTER + I860_R29: info->i = cpustate->iregs[29]; break; - case CPUINFO_INT_REGISTER + I860_R30: info->i = cpustate->iregs[30]; break; - case CPUINFO_INT_REGISTER + I860_R31: info->i = cpustate->iregs[31]; break; - - case CPUINFO_INT_REGISTER + I860_F0: CPU_GET_INFO_INT_F(0); break; - case CPUINFO_INT_REGISTER + I860_F1: CPU_GET_INFO_INT_F(1); break; - case CPUINFO_INT_REGISTER + I860_F2: CPU_GET_INFO_INT_F(2); break; - case CPUINFO_INT_REGISTER + I860_F3: CPU_GET_INFO_INT_F(3); break; - case CPUINFO_INT_REGISTER + I860_F4: CPU_GET_INFO_INT_F(4); break; - case CPUINFO_INT_REGISTER + I860_F5: CPU_GET_INFO_INT_F(5); break; - case CPUINFO_INT_REGISTER + I860_F6: CPU_GET_INFO_INT_F(6); break; - case CPUINFO_INT_REGISTER + I860_F7: CPU_GET_INFO_INT_F(7); break; - case CPUINFO_INT_REGISTER + I860_F8: CPU_GET_INFO_INT_F(8); break; - case CPUINFO_INT_REGISTER + I860_F9: CPU_GET_INFO_INT_F(9); break; - case CPUINFO_INT_REGISTER + I860_F10: CPU_GET_INFO_INT_F(10); break; - case CPUINFO_INT_REGISTER + I860_F11: CPU_GET_INFO_INT_F(11); break; - case CPUINFO_INT_REGISTER + I860_F12: CPU_GET_INFO_INT_F(12); break; - case CPUINFO_INT_REGISTER + I860_F13: CPU_GET_INFO_INT_F(13); break; - case CPUINFO_INT_REGISTER + I860_F14: CPU_GET_INFO_INT_F(14); break; - case CPUINFO_INT_REGISTER + I860_F15: CPU_GET_INFO_INT_F(15); break; - case CPUINFO_INT_REGISTER + I860_F16: CPU_GET_INFO_INT_F(16); break; - case CPUINFO_INT_REGISTER + I860_F17: CPU_GET_INFO_INT_F(17); break; - case CPUINFO_INT_REGISTER + I860_F18: CPU_GET_INFO_INT_F(18); break; - case CPUINFO_INT_REGISTER + I860_F19: CPU_GET_INFO_INT_F(19); break; - case CPUINFO_INT_REGISTER + I860_F20: CPU_GET_INFO_INT_F(20); break; - case CPUINFO_INT_REGISTER + I860_F21: CPU_GET_INFO_INT_F(21); break; - case CPUINFO_INT_REGISTER + I860_F22: CPU_GET_INFO_INT_F(22); break; - case CPUINFO_INT_REGISTER + I860_F23: CPU_GET_INFO_INT_F(23); break; - case CPUINFO_INT_REGISTER + I860_F24: CPU_GET_INFO_INT_F(24); break; - case CPUINFO_INT_REGISTER + I860_F25: CPU_GET_INFO_INT_F(25); break; - case CPUINFO_INT_REGISTER + I860_F26: CPU_GET_INFO_INT_F(26); break; - case CPUINFO_INT_REGISTER + I860_F27: CPU_GET_INFO_INT_F(27); break; - case CPUINFO_INT_REGISTER + I860_F28: CPU_GET_INFO_INT_F(28); break; - case CPUINFO_INT_REGISTER + I860_F29: CPU_GET_INFO_INT_F(29); break; - case CPUINFO_INT_REGISTER + I860_F30: CPU_GET_INFO_INT_F(30); break; - case CPUINFO_INT_REGISTER + I860_F31: CPU_GET_INFO_INT_F(31); break; - - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(i860); break; - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(i860); break; - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(i860); break; - case CPUINFO_FCT_EXIT: info->exit = NULL; break; - case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(i860); break; - case CPUINFO_FCT_BURN: info->burn = NULL; break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(i860); break; - case CPUINFO_FCT_DEBUG_INIT: info->debug_init = NULL; break; - case CPUINFO_FCT_TRANSLATE: info->translate = NULL; break; - case CPUINFO_FCT_READ: info->read = NULL; break; - case CPUINFO_FCT_WRITE: info->write = NULL; break; - case CPUINFO_FCT_READOP: info->readop = NULL; break; - case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "i860XR"); break; - case CPUINFO_STR_FAMILY: strcpy(info->s, "Intel i860"); break; - case CPUINFO_STR_VERSION: strcpy(info->s, "0.1"); break; - case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break; - case CPUINFO_STR_CREDITS: strcpy(info->s, "Jason Eckhardt"); break; - - case CPUINFO_STR_FLAGS: - strcpy(info->s, ""); break; - - case CPUINFO_STR_REGISTER + I860_PC: sprintf(info->s, "PC : %08x", cpustate->pc); break; - case CPUINFO_STR_REGISTER + I860_FIR: sprintf(info->s, "FIR : %08x", cpustate->cregs[CR_FIR]); break; - case CPUINFO_STR_REGISTER + I860_PSR: sprintf(info->s, "PSR : %08x", cpustate->cregs[CR_PSR]); break; - case CPUINFO_STR_REGISTER + I860_DIRBASE: sprintf(info->s, "DIRBASE : %08x", cpustate->cregs[CR_DIRBASE]);break; - case CPUINFO_STR_REGISTER + I860_DB: sprintf(info->s, "DB : %08x", cpustate->cregs[CR_DB]); break; - case CPUINFO_STR_REGISTER + I860_FSR: sprintf(info->s, "FSR : %08x", cpustate->cregs[CR_FSR]); break; - case CPUINFO_STR_REGISTER + I860_EPSR: sprintf(info->s, "EPSR : %08x", cpustate->cregs[CR_EPSR]); break; - - case CPUINFO_STR_REGISTER + I860_R0: sprintf(info->s, "R0 : %08x", cpustate->iregs[0]); break; - case CPUINFO_STR_REGISTER + I860_R1: sprintf(info->s, "R1 : %08x", cpustate->iregs[1]); break; - case CPUINFO_STR_REGISTER + I860_R2: sprintf(info->s, "R2 : %08x", cpustate->iregs[2]); break; - case CPUINFO_STR_REGISTER + I860_R3: sprintf(info->s, "R3 : %08x", cpustate->iregs[3]); break; - case CPUINFO_STR_REGISTER + I860_R4: sprintf(info->s, "R4 : %08x", cpustate->iregs[4]); break; - case CPUINFO_STR_REGISTER + I860_R5: sprintf(info->s, "R5 : %08x", cpustate->iregs[5]); break; - case CPUINFO_STR_REGISTER + I860_R6: sprintf(info->s, "R6 : %08x", cpustate->iregs[6]); break; - case CPUINFO_STR_REGISTER + I860_R7: sprintf(info->s, "R7 : %08x", cpustate->iregs[7]); break; - case CPUINFO_STR_REGISTER + I860_R8: sprintf(info->s, "R8 : %08x", cpustate->iregs[8]); break; - case CPUINFO_STR_REGISTER + I860_R9: sprintf(info->s, "R9 : %08x", cpustate->iregs[9]); break; - case CPUINFO_STR_REGISTER + I860_R10: sprintf(info->s, "R10 : %08x", cpustate->iregs[10]); break; - case CPUINFO_STR_REGISTER + I860_R11: sprintf(info->s, "R11 : %08x", cpustate->iregs[11]); break; - case CPUINFO_STR_REGISTER + I860_R12: sprintf(info->s, "R12 : %08x", cpustate->iregs[12]); break; - case CPUINFO_STR_REGISTER + I860_R13: sprintf(info->s, "R13 : %08x", cpustate->iregs[13]); break; - case CPUINFO_STR_REGISTER + I860_R14: sprintf(info->s, "R14 : %08x", cpustate->iregs[14]); break; - case CPUINFO_STR_REGISTER + I860_R15: sprintf(info->s, "R15 : %08x", cpustate->iregs[15]); break; - case CPUINFO_STR_REGISTER + I860_R16: sprintf(info->s, "R16 : %08x", cpustate->iregs[16]); break; - case CPUINFO_STR_REGISTER + I860_R17: sprintf(info->s, "R17 : %08x", cpustate->iregs[17]); break; - case CPUINFO_STR_REGISTER + I860_R18: sprintf(info->s, "R18 : %08x", cpustate->iregs[18]); break; - case CPUINFO_STR_REGISTER + I860_R19: sprintf(info->s, "R19 : %08x", cpustate->iregs[19]); break; - case CPUINFO_STR_REGISTER + I860_R20: sprintf(info->s, "R20 : %08x", cpustate->iregs[20]); break; - case CPUINFO_STR_REGISTER + I860_R21: sprintf(info->s, "R21 : %08x", cpustate->iregs[21]); break; - case CPUINFO_STR_REGISTER + I860_R22: sprintf(info->s, "R22 : %08x", cpustate->iregs[22]); break; - case CPUINFO_STR_REGISTER + I860_R23: sprintf(info->s, "R23 : %08x", cpustate->iregs[23]); break; - case CPUINFO_STR_REGISTER + I860_R24: sprintf(info->s, "R24 : %08x", cpustate->iregs[24]); break; - case CPUINFO_STR_REGISTER + I860_R25: sprintf(info->s, "R25 : %08x", cpustate->iregs[25]); break; - case CPUINFO_STR_REGISTER + I860_R26: sprintf(info->s, "R26 : %08x", cpustate->iregs[26]); break; - case CPUINFO_STR_REGISTER + I860_R27: sprintf(info->s, "R27 : %08x", cpustate->iregs[27]); break; - case CPUINFO_STR_REGISTER + I860_R28: sprintf(info->s, "R28 : %08x", cpustate->iregs[28]); break; - case CPUINFO_STR_REGISTER + I860_R29: sprintf(info->s, "R29 : %08x", cpustate->iregs[29]); break; - case CPUINFO_STR_REGISTER + I860_R30: sprintf(info->s, "R30 : %08x", cpustate->iregs[30]); break; - case CPUINFO_STR_REGISTER + I860_R31: sprintf(info->s, "R31 : %08x", cpustate->iregs[31]); break; - - case CPUINFO_STR_REGISTER + I860_F0: CPU_GET_INFO_STR_F(0); break; - case CPUINFO_STR_REGISTER + I860_F1: CPU_GET_INFO_STR_F(1); break; - case CPUINFO_STR_REGISTER + I860_F2: CPU_GET_INFO_STR_F(2); break; - case CPUINFO_STR_REGISTER + I860_F3: CPU_GET_INFO_STR_F(3); break; - case CPUINFO_STR_REGISTER + I860_F4: CPU_GET_INFO_STR_F(4); break; - case CPUINFO_STR_REGISTER + I860_F5: CPU_GET_INFO_STR_F(5); break; - case CPUINFO_STR_REGISTER + I860_F6: CPU_GET_INFO_STR_F(6); break; - case CPUINFO_STR_REGISTER + I860_F7: CPU_GET_INFO_STR_F(7); break; - case CPUINFO_STR_REGISTER + I860_F8: CPU_GET_INFO_STR_F(8); break; - case CPUINFO_STR_REGISTER + I860_F9: CPU_GET_INFO_STR_F(9); break; - case CPUINFO_STR_REGISTER + I860_F10: CPU_GET_INFO_STR_F(10); break; - case CPUINFO_STR_REGISTER + I860_F11: CPU_GET_INFO_STR_F(11); break; - case CPUINFO_STR_REGISTER + I860_F12: CPU_GET_INFO_STR_F(12); break; - case CPUINFO_STR_REGISTER + I860_F13: CPU_GET_INFO_STR_F(13); break; - case CPUINFO_STR_REGISTER + I860_F14: CPU_GET_INFO_STR_F(14); break; - case CPUINFO_STR_REGISTER + I860_F15: CPU_GET_INFO_STR_F(15); break; - case CPUINFO_STR_REGISTER + I860_F16: CPU_GET_INFO_STR_F(16); break; - case CPUINFO_STR_REGISTER + I860_F17: CPU_GET_INFO_STR_F(17); break; - case CPUINFO_STR_REGISTER + I860_F18: CPU_GET_INFO_STR_F(18); break; - case CPUINFO_STR_REGISTER + I860_F19: CPU_GET_INFO_STR_F(19); break; - case CPUINFO_STR_REGISTER + I860_F20: CPU_GET_INFO_STR_F(20); break; - case CPUINFO_STR_REGISTER + I860_F21: CPU_GET_INFO_STR_F(21); break; - case CPUINFO_STR_REGISTER + I860_F22: CPU_GET_INFO_STR_F(22); break; - case CPUINFO_STR_REGISTER + I860_F23: CPU_GET_INFO_STR_F(23); break; - case CPUINFO_STR_REGISTER + I860_F24: CPU_GET_INFO_STR_F(24); break; - case CPUINFO_STR_REGISTER + I860_F25: CPU_GET_INFO_STR_F(25); break; - case CPUINFO_STR_REGISTER + I860_F26: CPU_GET_INFO_STR_F(26); break; - case CPUINFO_STR_REGISTER + I860_F27: CPU_GET_INFO_STR_F(27); break; - case CPUINFO_STR_REGISTER + I860_F28: CPU_GET_INFO_STR_F(28); break; - case CPUINFO_STR_REGISTER + I860_F29: CPU_GET_INFO_STR_F(29); break; - case CPUINFO_STR_REGISTER + I860_F30: CPU_GET_INFO_STR_F(30); break; - case CPUINFO_STR_REGISTER + I860_F31: CPU_GET_INFO_STR_F(31); break; - } -} - -DEFINE_LEGACY_CPU_DEVICE(I860, i860); diff --git a/src/emu/cpu/i860/i860.h b/src/emu/cpu/i860/i860.h index 6d5578e74f5..dd2a1321be8 100644 --- a/src/emu/cpu/i860/i860.h +++ b/src/emu/cpu/i860/i860.h @@ -46,37 +46,71 @@ enum }; -/* Needed for MAME */ -DECLARE_LEGACY_CPU_DEVICE(I860, i860); +class i860_cpu_device : public cpu_device +{ +public: + // construction/destruction + i860_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); -/*************************************************************************** - STRUCTURES & TYPEDEFS -***************************************************************************/ + /* This is the external interface for asserting an external interrupt + to the i860. */ + void i860_gen_interrupt(); + + /* This is the external interface for asserting/deasserting a pin on + the i860. */ + void i860_set_pin(int, int); + + /* Hard or soft reset. */ + void reset_i860(); + +protected: + // device-level overrides + virtual void device_start(); + virtual void device_reset(); + + // device_execute_interface overrides + virtual UINT32 execute_min_cycles() const { return 1; } + virtual UINT32 execute_max_cycles() const { return 8; } + virtual UINT32 execute_input_lines() const { return 0; } + virtual void execute_run(); + + // device_memory_interface overrides + virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : NULL; } + + // device_state_interface overrides + void state_export(const device_state_entry &entry); + void state_import(const device_state_entry &entry); + + // device_disasm_interface overrides + virtual UINT32 disasm_min_opcode_bytes() const { return 4; } + virtual UINT32 disasm_max_opcode_bytes() const { return 4; } + virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options); + +private: + address_space_config m_program_config; -/* i860 state. */ -struct i860_state_t { /* Integer registers (32 x 32-bits). */ - UINT32 iregs[32]; + UINT32 m_iregs[32]; /* Floating point registers (32 x 32-bits, 16 x 64 bits, or 8 x 128 bits). When referenced as pairs or quads, the higher numbered registers are the upper bits. E.g., double precision f0 is f1:f0. */ - UINT8 frg[32 * 4]; + UINT8 m_frg[32 * 4]; /* Control registers (6 x 32-bits). */ - UINT32 cregs[6]; + UINT32 m_cregs[6]; /* Program counter (1 x 32-bits). Reset starts at pc=0xffffff00. */ - UINT32 pc; + UINT32 m_pc; /* Special registers (4 x 64-bits). */ union { float s; double d; - } KR, KI, T; - UINT64 merge; + } m_KR, m_KI, m_T; + UINT64 m_merge; /* The adder pipeline, always 3 stages. */ struct @@ -92,7 +126,7 @@ struct i860_state_t { /* Adder result precision (1 = dbl, 0 = sgl). */ char arp; } stat; - } A[3]; + } m_A[3]; /* The multiplier pipeline. 3 stages for single precision, 2 stages for double precision, and confusing for mixed precision. */ @@ -108,7 +142,7 @@ struct i860_state_t { /* Multiplier result precision (1 = dbl, 0 = sgl). */ char mrp; } stat; - } M[3]; + } m_M[3]; /* The load pipeline, always 3 stages. */ struct { @@ -123,7 +157,7 @@ struct i860_state_t { /* Load result precision (1 = dbl, 0 = sgl). */ char lrp; } stat; - } L[3]; + } m_L[3]; /* The graphics/integer pipeline, always 1 stage. */ struct { @@ -138,65 +172,141 @@ struct i860_state_t { /* Integer/graphics result precision (1 = dbl, 0 = sgl). */ char irp; } stat; - } G; + } m_G; /* Pins. */ - int pin_bus_hold; - int pin_reset; + int m_pin_bus_hold; + int m_pin_reset; /* * Other emulator state. */ - int exiting_readmem; - int exiting_ifetch; + int m_exiting_readmem; + int m_exiting_ifetch; /* Indicate a control-flow instruction, so we know the PC is updated. */ - int pc_updated; + int m_pc_updated; /* Indicate an instruction just generated a trap, so we know the PC needs to go to the trap address. */ - int pending_trap; + int m_pending_trap; /* This is 1 if the next fir load gets the trap address, otherwise it is 0 to get the ld.c address. This is set to 1 only when a non-reset trap occurs. */ - int fir_gets_trap_addr; + int m_fir_gets_trap_addr; /* Single stepping flag for internal use. */ - int single_stepping; + int m_single_stepping; /* * MAME-specific stuff. */ - legacy_cpu_device *device; - address_space *program; - UINT32 ppc; - int icount; + address_space *m_program; + UINT32 m_ppc; + int m_icount; + // For debugger + UINT32 m_freg[32]; + void writememi_emu (UINT32 addr, int size, UINT32 data); + void fp_readmem_emu (UINT32 addr, int size, UINT8 *dest); + void fp_writemem_emu (UINT32 addr, int size, UINT8 *data, UINT32 wmask); + void dump_pipe (int type); + void dump_state (); + void unrecog_opcode (UINT32 pc, UINT32 insn); + void insn_ld_ctrl (UINT32 insn); + void insn_st_ctrl (UINT32 insn); + void insn_ldx (UINT32 insn); + void insn_stx (UINT32 insn); + void insn_fsty (UINT32 insn); + void insn_fldy (UINT32 insn); + void insn_pstd (UINT32 insn); + void insn_ixfr (UINT32 insn); + void insn_addu (UINT32 insn); + void insn_addu_imm (UINT32 insn); + void insn_adds (UINT32 insn); + void insn_adds_imm (UINT32 insn); + void insn_subu (UINT32 insn); + void insn_subu_imm (UINT32 insn); + void insn_subs (UINT32 insn); + void insn_subs_imm (UINT32 insn); + void insn_shl (UINT32 insn); + void insn_shl_imm (UINT32 insn); + void insn_shr (UINT32 insn); + void insn_shr_imm (UINT32 insn); + void insn_shra (UINT32 insn); + void insn_shra_imm (UINT32 insn); + void insn_shrd (UINT32 insn); + void insn_and (UINT32 insn); + void insn_and_imm (UINT32 insn); + void insn_andh_imm (UINT32 insn); + void insn_andnot (UINT32 insn); + void insn_andnot_imm (UINT32 insn); + void insn_andnoth_imm (UINT32 insn); + void insn_or (UINT32 insn); + void insn_or_imm (UINT32 insn); + void insn_orh_imm (UINT32 insn); + void insn_xor (UINT32 insn); + void insn_xor_imm (UINT32 insn); + void insn_xorh_imm (UINT32 insn); + void insn_trap (UINT32 insn); + void insn_intovr (UINT32 insn); + void insn_bte (UINT32 insn); + void insn_bte_imm (UINT32 insn); + void insn_btne (UINT32 insn); + void insn_btne_imm (UINT32 insn); + void insn_bc (UINT32 insn); + void insn_bnc (UINT32 insn); + void insn_bct (UINT32 insn); + void insn_bnct (UINT32 insn); + void insn_call (UINT32 insn); + void insn_br (UINT32 insn); + void insn_bri (UINT32 insn); + void insn_calli (UINT32 insn); + void insn_bla (UINT32 insn); + void insn_flush (UINT32 insn); + void insn_fmul (UINT32 insn); + void insn_fmlow (UINT32 insn); + void insn_fadd_sub (UINT32 insn); + void insn_dualop (UINT32 insn); + void insn_frcp (UINT32 insn); + void insn_frsqr (UINT32 insn); + void insn_fxfr (UINT32 insn); + void insn_ftrunc (UINT32 insn); + void insn_famov (UINT32 insn); + void insn_fiadd_sub (UINT32 insn); + void insn_fcmp (UINT32 insn); + void insn_fzchk (UINT32 insn); + void insn_form (UINT32 insn); + void insn_faddp (UINT32 insn); + void insn_faddz (UINT32 insn); + void decode_exec (UINT32 insn, UINT32 non_shadow); + void disasm (UINT32 addr, int len); + void dbg_db (UINT32 addr, int len); + float get_fregval_s (int fr); + double get_fregval_d (int fr); + void set_fregval_s (int fr, float s); + void set_fregval_d (int fr, double d); + int has_delay_slot(UINT32 insn); + UINT32 ifetch (UINT32 pc); + UINT32 get_address_translation (UINT32 vaddr, int is_dataref, int is_write); + UINT32 readmemi_emu (UINT32 addr, int size); + float get_fval_from_optype_s (UINT32 insn, int optype); + double get_fval_from_optype_d (UINT32 insn, int optype); + + typedef void (i860_cpu_device::*insn_func)(UINT32); + struct decode_tbl_t + { + /* Execute function for this opcode. */ + insn_func insn_exec; + /* Flags for this opcode. */ + char flags; + }; + static const decode_tbl_t decode_tbl[64]; + static const decode_tbl_t core_esc_decode_tbl[8]; + static const decode_tbl_t fp_decode_tbl[128]; }; -INLINE i860_state_t *get_safe_token(device_t *device) -{ - assert(device != NULL); - assert(device->type() == I860); - return (i860_state_t *)downcast(device)->token(); -} - - -/*************************************************************************** - PUBLIC FUNCTIONS -***************************************************************************/ - -/* This is the external interface for asserting an external interrupt - to the i860. */ -extern void i860_gen_interrupt(i860_state_t*); - -/* This is the external interface for asserting/deasserting a pin on - the i860. */ -extern void i860_set_pin(device_t *, int, int); - -/* Hard or soft reset. */ -extern void reset_i860(i860_state_t*); /* i860 pins. */ enum { @@ -205,18 +315,7 @@ enum { }; -/* TODO: THESE WILL BE REPLACED BY MAME FUNCTIONS -#define BYTE_REV32(t) \ - do { \ - (t) = ((UINT32)(t) >> 16) | ((UINT32)(t) << 16); \ - (t) = (((UINT32)(t) >> 8) & 0x00ff00ff) | (((UINT32)(t) << 8) & 0xff00ff00); \ - } while (0); +extern const device_type I860; -#define BYTE_REV16(t) \ - do { \ - (t) = (((UINT16)(t) >> 8) & 0x00ff) | (((UINT16)(t) << 8) & 0xff00); \ - } while (0); -#endif -*/ #endif /* __I860_H__ */ diff --git a/src/emu/cpu/i860/i860dec.c b/src/emu/cpu/i860/i860dec.c index b09ce21a138..286e4a9f893 100644 --- a/src/emu/cpu/i860/i860dec.c +++ b/src/emu/cpu/i860/i860dec.c @@ -52,22 +52,6 @@ #define TRACE_UNALIGNED_MEM - -#define i860s i860_state_t - - -/* Prototypes. */ -static void decode_exec (i860s *, UINT32, UINT32); -static UINT32 get_address_translation (i860s *, UINT32, int, int); -static UINT32 readmemi_emu (i860s *cpustate, UINT32, int); - -//static void debugger (i860s *cpustate); -//static void disasm (i860s *cpustate, UINT32, int); -//static void dump_state (i860s *cpustate); - - - - /* Defines for pending_trap. */ enum { TRAP_NORMAL = 0x01, @@ -76,32 +60,45 @@ enum { }; +/* TODO: THESE WILL BE REPLACED BY MAME FUNCTIONS +#define BYTE_REV32(t) \ + do { \ + (t) = ((UINT32)(t) >> 16) | ((UINT32)(t) << 16); \ + (t) = (((UINT32)(t) >> 8) & 0x00ff00ff) | (((UINT32)(t) << 8) & 0xff00ff00); \ + } while (0); + +#define BYTE_REV16(t) \ + do { \ + (t) = (((UINT16)(t) >> 8) & 0x00ff) | (((UINT16)(t) << 8) & 0xff00); \ + } while (0); +#endif +*/ /* Get/set general register value -- watch for r0 on writes. */ -#define get_iregval(gr) (cpustate->iregs[(gr)]) -#define set_iregval(gr, val) (cpustate->iregs[(gr)] = ((gr) == 0 ? 0 : (val))) +#define get_iregval(gr) (m_iregs[(gr)]) +#define set_iregval(gr, val) (m_iregs[(gr)] = ((gr) == 0 ? 0 : (val))) -INLINE float get_fregval_s (i860s *cpustate, int fr) +float i860_cpu_device::get_fregval_s (int fr) { float f; UINT32 x; UINT8 *tp; fr = 31 - fr; - tp = (UINT8 *)(&cpustate->frg[fr * 4]); + tp = (UINT8 *)(&m_frg[fr * 4]); x = ((UINT32)tp[0] << 24) | ((UINT32)tp[1] << 16) | ((UINT32)tp[2] << 8) | ((UINT32)tp[3]); f = *(float *)(&x); return f; } -INLINE double get_fregval_d (i860s *cpustate, int fr) +double i860_cpu_device::get_fregval_d (int fr) { double d; UINT64 x; UINT8 *tp; fr = 31 - (fr + 1); - tp = (UINT8 *)(&cpustate->frg[fr * 4]); + tp = (UINT8 *)(&m_frg[fr * 4]); x = ((UINT64)tp[0] << 56) | ((UINT64)tp[1] << 48) | ((UINT64)tp[2] << 40) | ((UINT64)tp[3] << 32) | ((UINT64)tp[4] << 24) | ((UINT64)tp[5] << 16) | @@ -110,13 +107,13 @@ INLINE double get_fregval_d (i860s *cpustate, int fr) return d; } -INLINE void set_fregval_s (i860s *cpustate, int fr, float s) +void i860_cpu_device::set_fregval_s (int fr, float s) { UINT8 *f = (UINT8 *)&s; UINT8 *tp; int newfr = 31 - fr; float jj = s; - tp = (UINT8 *)(&cpustate->frg[newfr * 4]); + tp = (UINT8 *)(&m_frg[newfr * 4]); f = (UINT8 *)(&jj); if (fr == 0 || fr == 1) @@ -133,13 +130,13 @@ INLINE void set_fregval_s (i860s *cpustate, int fr, float s) } } -INLINE void set_fregval_d (i860s *cpustate, int fr, double d) +void i860_cpu_device::set_fregval_d (int fr, double d) { UINT8 *f = (UINT8 *)&d; UINT8 *tp; int newfr = 31 - (fr + 1); double jj = d; - tp = (UINT8 *)(&cpustate->frg[newfr * 4]); + tp = (UINT8 *)(&m_frg[newfr * 4]); f = (UINT8 *)(&jj); @@ -174,16 +171,6 @@ INLINE void set_fregval_d (i860s *cpustate, int fr, double d) /* 16-bit immediate. */ #define get_imm16(insn) ((insn) & 0xffff) -/* Control register numbers. */ -enum { - CR_FIR = 0, - CR_PSR = 1, - CR_DIRBASE = 2, - CR_DB = 3, - CR_FSR = 4, - CR_EPSR = 5 -}; - /* A mask for all the trap bits of the PSR (FT, DAT, IAT, IN, IT, or bits [12..8]). */ #define PSR_ALL_TRAP_BITS_MASK 0x00001f00 @@ -193,111 +180,110 @@ enum { /* PSR: BR flag (PSR[0]): set/get. */ -#define GET_PSR_BR() ((cpustate->cregs[CR_PSR] >> 0) & 1) -#define SET_PSR_BR(val) (cpustate->cregs[CR_PSR] = (cpustate->cregs[CR_PSR] & ~(1 << 0)) | (((val) & 1) << 0)) +#define GET_PSR_BR() ((m_cregs[CR_PSR] >> 0) & 1) +#define SET_PSR_BR(val) (m_cregs[CR_PSR] = (m_cregs[CR_PSR] & ~(1 << 0)) | (((val) & 1) << 0)) /* PSR: BW flag (PSR[1]): set/get. */ -#define GET_PSR_BW() ((cpustate->cregs[CR_PSR] >> 1) & 1) -#define SET_PSR_BW(val) (cpustate->cregs[CR_PSR] = (cpustate->cregs[CR_PSR] & ~(1 << 1)) | (((val) & 1) << 1)) +#define GET_PSR_BW() ((m_cregs[CR_PSR] >> 1) & 1) +#define SET_PSR_BW(val) (m_cregs[CR_PSR] = (m_cregs[CR_PSR] & ~(1 << 1)) | (((val) & 1) << 1)) /* PSR: Shift count (PSR[21..17]): set/get. */ -#define GET_PSR_SC() ((cpustate->cregs[CR_PSR] >> 17) & 0x1f) -#define SET_PSR_SC(val) (cpustate->cregs[CR_PSR] = (cpustate->cregs[CR_PSR] & ~0x003e0000) | (((val) & 0x1f) << 17)) +#define GET_PSR_SC() ((m_cregs[CR_PSR] >> 17) & 0x1f) +#define SET_PSR_SC(val) (m_cregs[CR_PSR] = (m_cregs[CR_PSR] & ~0x003e0000) | (((val) & 0x1f) << 17)) /* PSR: CC flag (PSR[2]): set/get. */ -#define GET_PSR_CC() ((cpustate->cregs[CR_PSR] >> 2) & 1) -#define SET_PSR_CC(val) (cpustate->cregs[CR_PSR] = (cpustate->cregs[CR_PSR] & ~(1 << 2)) | (((val) & 1) << 2)) +#define GET_PSR_CC() ((m_cregs[CR_PSR] >> 2) & 1) +#define SET_PSR_CC(val) (m_cregs[CR_PSR] = (m_cregs[CR_PSR] & ~(1 << 2)) | (((val) & 1) << 2)) /* PSR: IT flag (PSR[8]): set/get. */ -#define GET_PSR_IT() ((cpustate->cregs[CR_PSR] >> 8) & 1) -#define SET_PSR_IT(val) (cpustate->cregs[CR_PSR] = (cpustate->cregs[CR_PSR] & ~(1 << 8)) | (((val) & 1) << 8)) +#define GET_PSR_IT() ((m_cregs[CR_PSR] >> 8) & 1) +#define SET_PSR_IT(val) (m_cregs[CR_PSR] = (m_cregs[CR_PSR] & ~(1 << 8)) | (((val) & 1) << 8)) /* PSR: IN flag (PSR[9]): set/get. */ -#define GET_PSR_IN() ((cpustate->cregs[CR_PSR] >> 9) & 1) -#define SET_PSR_IN(val) (cpustate->cregs[CR_PSR] = (cpustate->cregs[CR_PSR] & ~(1 << 9)) | (((val) & 1) << 9)) +#define GET_PSR_IN() ((m_cregs[CR_PSR] >> 9) & 1) +#define SET_PSR_IN(val) (m_cregs[CR_PSR] = (m_cregs[CR_PSR] & ~(1 << 9)) | (((val) & 1) << 9)) /* PSR: IAT flag (PSR[10]): set/get. */ -#define GET_PSR_IAT() ((cpustate->cregs[CR_PSR] >> 10) & 1) -#define SET_PSR_IAT(val) (cpustate->cregs[CR_PSR] = (cpustate->cregs[CR_PSR] & ~(1 << 10)) | (((val) & 1) << 10)) +#define GET_PSR_IAT() ((m_cregs[CR_PSR] >> 10) & 1) +#define SET_PSR_IAT(val) (m_cregs[CR_PSR] = (m_cregs[CR_PSR] & ~(1 << 10)) | (((val) & 1) << 10)) /* PSR: DAT flag (PSR[11]): set/get. */ -#define GET_PSR_DAT() ((cpustate->cregs[CR_PSR] >> 11) & 1) -#define SET_PSR_DAT(val) (cpustate->cregs[CR_PSR] = (cpustate->cregs[CR_PSR] & ~(1 << 11)) | (((val) & 1) << 11)) +#define GET_PSR_DAT() ((m_cregs[CR_PSR] >> 11) & 1) +#define SET_PSR_DAT(val) (m_cregs[CR_PSR] = (m_cregs[CR_PSR] & ~(1 << 11)) | (((val) & 1) << 11)) /* PSR: FT flag (PSR[12]): set/get. */ -#define GET_PSR_FT() ((cpustate->cregs[CR_PSR] >> 12) & 1) -#define SET_PSR_FT(val) (cpustate->cregs[CR_PSR] = (cpustate->cregs[CR_PSR] & ~(1 << 12)) | (((val) & 1) << 12)) +#define GET_PSR_FT() ((m_cregs[CR_PSR] >> 12) & 1) +#define SET_PSR_FT(val) (m_cregs[CR_PSR] = (m_cregs[CR_PSR] & ~(1 << 12)) | (((val) & 1) << 12)) /* PSR: DS flag (PSR[13]): set/get. */ -#define GET_PSR_DS() ((cpustate->cregs[CR_PSR] >> 13) & 1) -#define SET_PSR_DS(val) (cpustate->cregs[CR_PSR] = (cpustate->cregs[CR_PSR] & ~(1 << 13)) | (((val) & 1) << 13)) +#define GET_PSR_DS() ((m_cregs[CR_PSR] >> 13) & 1) +#define SET_PSR_DS(val) (m_cregs[CR_PSR] = (m_cregs[CR_PSR] & ~(1 << 13)) | (((val) & 1) << 13)) /* PSR: DIM flag (PSR[14]): set/get. */ -#define GET_PSR_DIM() ((cpustate->cregs[CR_PSR] >> 14) & 1) -#define SET_PSR_DIM(val) (cpustate->cregs[CR_PSR] = (cpustate->cregs[CR_PSR] & ~(1 << 14)) | (((val) & 1) << 14)) +#define GET_PSR_DIM() ((m_cregs[CR_PSR] >> 14) & 1) +#define SET_PSR_DIM(val) (m_cregs[CR_PSR] = (m_cregs[CR_PSR] & ~(1 << 14)) | (((val) & 1) << 14)) /* PSR: LCC (PSR[3]): set/get. */ -#define GET_PSR_LCC() ((cpustate->cregs[CR_PSR] >> 3) & 1) -#define SET_PSR_LCC(val) (cpustate->cregs[CR_PSR] = (cpustate->cregs[CR_PSR] & ~(1 << 3)) | (((val) & 1) << 3)) +#define GET_PSR_LCC() ((m_cregs[CR_PSR] >> 3) & 1) +#define SET_PSR_LCC(val) (m_cregs[CR_PSR] = (m_cregs[CR_PSR] & ~(1 << 3)) | (((val) & 1) << 3)) /* PSR: IM (PSR[4]): set/get. */ -#define GET_PSR_IM() ((cpustate->cregs[CR_PSR] >> 4) & 1) -#define SET_PSR_IM(val) (cpustate->cregs[CR_PSR] = (cpustate->cregs[CR_PSR] & ~(1 << 4)) | (((val) & 1) << 4)) +#define GET_PSR_IM() ((m_cregs[CR_PSR] >> 4) & 1) +#define SET_PSR_IM(val) (m_cregs[CR_PSR] = (m_cregs[CR_PSR] & ~(1 << 4)) | (((val) & 1) << 4)) /* PSR: PIM (PSR[5]): set/get. */ -#define GET_PSR_PIM() ((cpustate->cregs[CR_PSR] >> 5) & 1) -#define SET_PSR_PIM(val) (cpustate->cregs[CR_PSR] = (cpustate->cregs[CR_PSR] & ~(1 << 5)) | (((val) & 1) << 5)) +#define GET_PSR_PIM() ((m_cregs[CR_PSR] >> 5) & 1) +#define SET_PSR_PIM(val) (m_cregs[CR_PSR] = (m_cregs[CR_PSR] & ~(1 << 5)) | (((val) & 1) << 5)) /* PSR: U (PSR[6]): set/get. */ -#define GET_PSR_U() ((cpustate->cregs[CR_PSR] >> 6) & 1) -#define SET_PSR_U(val) (cpustate->cregs[CR_PSR] = (cpustate->cregs[CR_PSR] & ~(1 << 6)) | (((val) & 1) << 6)) +#define GET_PSR_U() ((m_cregs[CR_PSR] >> 6) & 1) +#define SET_PSR_U(val) (m_cregs[CR_PSR] = (m_cregs[CR_PSR] & ~(1 << 6)) | (((val) & 1) << 6)) /* PSR: PU (PSR[7]): set/get. */ -#define GET_PSR_PU() ((cpustate->cregs[CR_PSR] >> 7) & 1) -#define SET_PSR_PU(val) (cpustate->cregs[CR_PSR] = (cpustate->cregs[CR_PSR] & ~(1 << 7)) | (((val) & 1) << 7)) +#define GET_PSR_PU() ((m_cregs[CR_PSR] >> 7) & 1) +#define SET_PSR_PU(val) (m_cregs[CR_PSR] = (m_cregs[CR_PSR] & ~(1 << 7)) | (((val) & 1) << 7)) /* PSR: Pixel size (PSR[23..22]): set/get. */ -#define GET_PSR_PS() ((cpustate->cregs[CR_PSR] >> 22) & 0x3) -#define SET_PSR_PS(val) (cpustate->cregs[CR_PSR] = (cpustate->cregs[CR_PSR] & ~0x00c00000) | (((val) & 0x3) << 22)) +#define GET_PSR_PS() ((m_cregs[CR_PSR] >> 22) & 0x3) +#define SET_PSR_PS(val) (m_cregs[CR_PSR] = (m_cregs[CR_PSR] & ~0x00c00000) | (((val) & 0x3) << 22)) /* PSR: Pixel mask (PSR[31..24]): set/get. */ -#define GET_PSR_PM() ((cpustate->cregs[CR_PSR] >> 24) & 0xff) -#define SET_PSR_PM(val) (cpustate->cregs[CR_PSR] = (cpustate->cregs[CR_PSR] & ~0xff000000) | (((val) & 0xff) << 24)) +#define GET_PSR_PM() ((m_cregs[CR_PSR] >> 24) & 0xff) +#define SET_PSR_PM(val) (m_cregs[CR_PSR] = (m_cregs[CR_PSR] & ~0xff000000) | (((val) & 0xff) << 24)) /* EPSR: WP bit (EPSR[14]): set/get. */ -#define GET_EPSR_WP() ((cpustate->cregs[CR_EPSR] >> 14) & 1) -#define SET_EPSR_WP(val) (cpustate->cregs[CR_EPSR] = (cpustate->cregs[CR_EPSR] & ~(1 << 14)) | (((val) & 1) << 14)) +#define GET_EPSR_WP() ((m_cregs[CR_EPSR] >> 14) & 1) +#define SET_EPSR_WP(val) (m_cregs[CR_EPSR] = (m_cregs[CR_EPSR] & ~(1 << 14)) | (((val) & 1) << 14)) /* EPSR: INT bit (EPSR[17]): set/get. */ -#define GET_EPSR_INT() ((cpustate->cregs[CR_EPSR] >> 17) & 1) -#define SET_EPSR_INT(val) (cpustate->cregs[CR_EPSR] = (cpustate->cregs[CR_EPSR] & ~(1 << 17)) | (((val) & 1) << 17)) +#define GET_EPSR_INT() ((m_cregs[CR_EPSR] >> 17) & 1) +#define SET_EPSR_INT(val) (m_cregs[CR_EPSR] = (m_cregs[CR_EPSR] & ~(1 << 17)) | (((val) & 1) << 17)) /* EPSR: OF flag (EPSR[24]): set/get. */ -#define GET_EPSR_OF() ((cpustate->cregs[CR_EPSR] >> 24) & 1) -#define SET_EPSR_OF(val) (cpustate->cregs[CR_EPSR] = (cpustate->cregs[CR_EPSR] & ~(1 << 24)) | (((val) & 1) << 24)) +#define GET_EPSR_OF() ((m_cregs[CR_EPSR] >> 24) & 1) +#define SET_EPSR_OF(val) (m_cregs[CR_EPSR] = (m_cregs[CR_EPSR] & ~(1 << 24)) | (((val) & 1) << 24)) /* EPSR: BE flag (EPSR[23]): set/get. */ -#define GET_EPSR_BE() ((cpustate->cregs[CR_EPSR] >> 23) & 1) -#define SET_EPSR_BE(val) (cpustate->cregs[CR_EPSR] = (cpustate->cregs[CR_EPSR] & ~(1 << 23)) | (((val) & 1) << 23)) +#define GET_EPSR_BE() ((m_cregs[CR_EPSR] >> 23) & 1) +#define SET_EPSR_BE(val) (m_cregs[CR_EPSR] = (m_cregs[CR_EPSR] & ~(1 << 23)) | (((val) & 1) << 23)) /* DIRBASE: ATE bit (DIRBASE[0]): get. */ -#define GET_DIRBASE_ATE() (cpustate->cregs[CR_DIRBASE] & 1) +#define GET_DIRBASE_ATE() (m_cregs[CR_DIRBASE] & 1) /* DIRBASE: CS8 bit (DIRBASE[7]): get. */ -#define GET_DIRBASE_CS8() ((cpustate->cregs[CR_DIRBASE] >> 7) & 1) +#define GET_DIRBASE_CS8() ((m_cregs[CR_DIRBASE] >> 7) & 1) /* FSR: FTE bit (FSR[5]): set/get. */ -#define GET_FSR_FTE() ((cpustate->cregs[CR_FSR] >> 5) & 1) -#define SET_FSR_FTE(val) (cpustate->cregs[CR_FSR] = (cpustate->cregs[CR_FSR] & ~(1 << 5)) | (((val) & 1) << 5)) +#define GET_FSR_FTE() ((m_cregs[CR_FSR] >> 5) & 1) +#define SET_FSR_FTE(val) (m_cregs[CR_FSR] = (m_cregs[CR_FSR] & ~(1 << 5)) | (((val) & 1) << 5)) /* FSR: SE bit (FSR[8]): set/get. */ -#define GET_FSR_SE() ((cpustate->cregs[CR_FSR] >> 8) & 1) -#define SET_FSR_SE(val) (cpustate->cregs[CR_FSR] = (cpustate->cregs[CR_FSR] & ~(1 << 8)) | (((val) & 1) << 8)) +#define GET_FSR_SE() ((m_cregs[CR_FSR] >> 8) & 1) +#define SET_FSR_SE(val) (m_cregs[CR_FSR] = (m_cregs[CR_FSR] & ~(1 << 8)) | (((val) & 1) << 8)) -/* -static int has_delay_slot(UINT32 insn) +int i860_cpu_device::has_delay_slot(UINT32 insn) { int opc = (insn >> 26) & 0x3f; if (opc == 0x10 || opc == 0x1a || opc == 0x1b || opc == 0x1d || @@ -305,17 +291,15 @@ static int has_delay_slot(UINT32 insn) return 1; return 0; } -*/ /* This is the external interface for asserting/deasserting pins on the i860. */ -void i860_set_pin (device_t *device, int pin, int val) +void i860_cpu_device::i860_set_pin (int pin, int val) { - i860s *cpustate = get_safe_token(device); if (pin == DEC_PIN_BUS_HOLD) - cpustate->pin_bus_hold = val; + m_pin_bus_hold = val; else if (pin == DEC_PIN_RESET) - cpustate->pin_reset = val; + m_pin_reset = val; else assert (0); } @@ -323,7 +307,7 @@ void i860_set_pin (device_t *device, int pin, int val) /* This is the external interface for indicating an external interrupt to the i860. */ -void i860_gen_interrupt (i860s *cpustate) +void i860_cpu_device::i860_gen_interrupt() { /* If interrupts are enabled, then set PSR.IN and prepare for trap. Otherwise, the external interrupt is ignored. We also set @@ -332,7 +316,7 @@ void i860_gen_interrupt (i860s *cpustate) { SET_PSR_IN (1); SET_EPSR_INT (1); - cpustate->pending_trap = TRAP_WAS_EXTERNAL; + m_pending_trap = TRAP_WAS_EXTERNAL; } #ifdef TRACE_EXT_INT @@ -348,7 +332,7 @@ void i860_gen_interrupt (i860s *cpustate) /* Fetch instructions from instruction cache. Note: The instruction cache is not implemented for MAME version, this just fetches and returns 1 instruction from memory. */ -static UINT32 ifetch (i860s *cpustate, UINT32 pc) +UINT32 i860_cpu_device::ifetch (UINT32 pc) { UINT32 phys_pc = 0; UINT32 w1 = 0; @@ -356,11 +340,11 @@ static UINT32 ifetch (i860s *cpustate, UINT32 pc) /* If virtual mode, get translation. */ if (GET_DIRBASE_ATE ()) { - phys_pc = get_address_translation (cpustate, pc, 0 /* is_dataref */, 0 /* is_write */); - cpustate->exiting_ifetch = 0; - if (cpustate->pending_trap && (GET_PSR_DAT () || GET_PSR_IAT ())) + phys_pc = get_address_translation (pc, 0 /* is_dataref */, 0 /* is_write */); + m_exiting_ifetch = 0; + if (m_pending_trap && (GET_PSR_DAT () || GET_PSR_IAT ())) { - cpustate->exiting_ifetch = 1; + m_exiting_ifetch = 1; return 0xffeeffee; } } @@ -369,7 +353,7 @@ static UINT32 ifetch (i860s *cpustate, UINT32 pc) /* Since i860 instructions are always stored LSB first (regardless of the BE bit), we need to adjust the instruction below on MSB hosts. */ - w1 = cpustate->program->read_dword(phys_pc); + w1 = m_program->read_dword(phys_pc); #ifdef HOST_MSB BYTE_REV32 (w1); #endif /* HOST_MSB. */ @@ -387,12 +371,12 @@ static UINT32 ifetch (i860s *cpustate, UINT32 pc) Page tables must always be in memory (not cached). So the routine here only accesses memory. */ -static UINT32 get_address_translation (i860s *cpustate, UINT32 vaddr, int is_dataref, int is_write) +UINT32 i860_cpu_device::get_address_translation (UINT32 vaddr, int is_dataref, int is_write) { UINT32 vdir = (vaddr >> 22) & 0x3ff; UINT32 vpage = (vaddr >> 12) & 0x3ff; UINT32 voffset = vaddr & 0xfff; - UINT32 dtb = (cpustate->cregs[CR_DIRBASE]) & 0xfffff000; + UINT32 dtb = (m_cregs[CR_DIRBASE]) & 0xfffff000; UINT32 pg_dir_entry_a = 0; UINT32 pg_dir_entry = 0; UINT32 pg_tbl_entry_a = 0; @@ -407,7 +391,7 @@ static UINT32 get_address_translation (i860s *cpustate, UINT32 vaddr, int is_dat /* Get page directory entry at DTB:DIR:00. */ pg_dir_entry_a = dtb | (vdir << 2); - pg_dir_entry = cpustate->program->read_dword(pg_dir_entry_a); + pg_dir_entry = m_program->read_dword(pg_dir_entry_a); #ifdef HOST_MSB BYTE_REV32 (pg_dir_entry); #endif @@ -420,7 +404,7 @@ static UINT32 get_address_translation (i860s *cpustate, UINT32 vaddr, int is_dat SET_PSR_DAT (1); else SET_PSR_IAT (1); - cpustate->pending_trap = 1; + m_pending_trap = 1; /* Dummy return. */ return 0; @@ -432,7 +416,7 @@ static UINT32 get_address_translation (i860s *cpustate, UINT32 vaddr, int is_dat && (GET_PSR_U () || GET_EPSR_WP ())) /* PSR_U = 1 or EPSR_WP = 1. */ { SET_PSR_DAT (1); - cpustate->pending_trap = 1; + m_pending_trap = 1; /* Dummy return. */ return 0; } @@ -445,7 +429,7 @@ static UINT32 get_address_translation (i860s *cpustate, UINT32 vaddr, int is_dat SET_PSR_DAT (1); else SET_PSR_IAT (1); - cpustate->pending_trap = 1; + m_pending_trap = 1; /* Dummy return. */ return 0; } @@ -455,7 +439,7 @@ static UINT32 get_address_translation (i860s *cpustate, UINT32 vaddr, int is_dat /* Get page table entry at PFA1:PAGE:00. */ pfa1 = pg_dir_entry & 0xfffff000; pg_tbl_entry_a = pfa1 | (vpage << 2); - pg_tbl_entry = cpustate->program->read_dword(pg_tbl_entry_a); + pg_tbl_entry = m_program->read_dword(pg_tbl_entry_a); #ifdef HOST_MSB BYTE_REV32 (pg_tbl_entry); #endif @@ -468,7 +452,7 @@ static UINT32 get_address_translation (i860s *cpustate, UINT32 vaddr, int is_dat SET_PSR_DAT (1); else SET_PSR_IAT (1); - cpustate->pending_trap = 1; + m_pending_trap = 1; /* Dummy return. */ return 0; @@ -480,7 +464,7 @@ static UINT32 get_address_translation (i860s *cpustate, UINT32 vaddr, int is_dat && (GET_PSR_U () || GET_EPSR_WP ())) /* PSR_U = 1 or EPSR_WP = 1. */ { SET_PSR_DAT (1); - cpustate->pending_trap = 1; + m_pending_trap = 1; /* Dummy return. */ return 0; } @@ -493,7 +477,7 @@ static UINT32 get_address_translation (i860s *cpustate, UINT32 vaddr, int is_dat SET_PSR_DAT (1); else SET_PSR_IAT (1); - cpustate->pending_trap = 1; + m_pending_trap = 1; /* Dummy return. */ return 0; } @@ -505,15 +489,15 @@ static UINT32 get_address_translation (i860s *cpustate, UINT32 vaddr, int is_dat BYTE_REV32 (ttpde); BYTE_REV32 (ttpte); #endif - cpustate->program->write_dword(pg_dir_entry_a, ttpde); - cpustate->program->write_dword(pg_tbl_entry_a, ttpte); + m_program->write_dword(pg_dir_entry_a, ttpde); + m_program->write_dword(pg_tbl_entry_a, ttpte); if (is_write && is_dataref && (pg_tbl_entry & 0x40) == 0) { /* fprintf(stderr, "DAT trap on write without dirty bit v0x%08x/p0x%08x\n", vaddr, (pg_tbl_entry & ~0xfff)|voffset); */ SET_PSR_DAT (1); - cpustate->pending_trap = 1; + m_pending_trap = 1; /* Dummy return. */ return 0; } @@ -533,7 +517,7 @@ static UINT32 get_address_translation (i860s *cpustate, UINT32 vaddr, int is_dat /* Read memory emulation. addr = address to read. size = size of read in bytes. */ -static UINT32 readmemi_emu (i860s *cpustate, UINT32 addr, int size) +UINT32 i860_cpu_device::readmemi_emu (UINT32 addr, int size) { #ifdef TRACE_RDWR_MEM fprintf (stderr, "readmemi_emu: (ATE=%d) addr = 0x%08x, size = %d\n", @@ -543,36 +527,36 @@ static UINT32 readmemi_emu (i860s *cpustate, UINT32 addr, int size) /* If virtual mode, do translation. */ if (GET_DIRBASE_ATE ()) { - UINT32 phys = get_address_translation (cpustate, addr, 1 /* is_dataref */, 0 /* is_write */); - if (cpustate->pending_trap && (GET_PSR_IAT () || GET_PSR_DAT ())) + UINT32 phys = get_address_translation (addr, 1 /* is_dataref */, 0 /* is_write */); + if (m_pending_trap && (GET_PSR_IAT () || GET_PSR_DAT ())) { #ifdef TRACE_PAGE_FAULT fprintf (stderr, "0x%08x: ## Page fault (readmemi_emu).\n", - cpustate->pc); + m_pc); #endif - cpustate->exiting_readmem = 1; + m_exiting_readmem = 1; return 0; } addr = phys; } /* First check for match to db register (before read). */ - if (((addr & ~(size - 1)) == cpustate->cregs[CR_DB]) && GET_PSR_BR ()) + if (((addr & ~(size - 1)) == m_cregs[CR_DB]) && GET_PSR_BR ()) { SET_PSR_DAT (1); - cpustate->pending_trap = 1; + m_pending_trap = 1; return 0; } /* Now do the actual read. */ if (size == 1) { - UINT32 ret = cpustate->program->read_byte(addr); + UINT32 ret = m_program->read_byte(addr); return ret & 0xff; } else if (size == 2) { - UINT32 ret = cpustate->program->read_word(addr); + UINT32 ret = m_program->read_word(addr); #ifdef HOST_MSB BYTE_REV16 (ret); #endif @@ -580,7 +564,7 @@ static UINT32 readmemi_emu (i860s *cpustate, UINT32 addr, int size) } else if (size == 4) { - UINT32 ret = cpustate->program->read_dword(addr); + UINT32 ret = m_program->read_dword(addr); #ifdef HOST_MSB BYTE_REV32 (ret); #endif @@ -597,7 +581,7 @@ static UINT32 readmemi_emu (i860s *cpustate, UINT32 addr, int size) addr = address to write. size = size of write in bytes. data = data to write. */ -static void writememi_emu (i860s *cpustate, UINT32 addr, int size, UINT32 data) +void i860_cpu_device::writememi_emu (UINT32 addr, int size, UINT32 data) { #ifdef TRACE_RDWR_MEM fprintf (stderr, "writememi_emu: (ATE=%d) addr = 0x%08x, size = %d, data = 0x%08x\n", @@ -607,43 +591,43 @@ static void writememi_emu (i860s *cpustate, UINT32 addr, int size, UINT32 data) /* If virtual mode, do translation. */ if (GET_DIRBASE_ATE ()) { - UINT32 phys = get_address_translation (cpustate, addr, 1 /* is_dataref */, 1 /* is_write */); - if (cpustate->pending_trap && (GET_PSR_IAT () || GET_PSR_DAT ())) + UINT32 phys = get_address_translation (addr, 1 /* is_dataref */, 1 /* is_write */); + if (m_pending_trap && (GET_PSR_IAT () || GET_PSR_DAT ())) { #ifdef TRACE_PAGE_FAULT fprintf (stderr, "0x%08x: ## Page fault (writememi_emu).\n", - cpustate->pc); + m_pc); #endif - cpustate->exiting_readmem = 2; + m_exiting_readmem = 2; return; } addr = phys; } /* First check for match to db register (before write). */ - if (((addr & ~(size - 1)) == cpustate->cregs[CR_DB]) && GET_PSR_BW ()) + if (((addr & ~(size - 1)) == m_cregs[CR_DB]) && GET_PSR_BW ()) { SET_PSR_DAT (1); - cpustate->pending_trap = 1; + m_pending_trap = 1; return; } /* Now do the actual write. */ if (size == 1) - cpustate->program->write_byte(addr, data); + m_program->write_byte(addr, data); else if (size == 2) { #ifdef HOST_MSB BYTE_REV16 (data); #endif - cpustate->program->write_word(addr, data); + m_program->write_word(addr, data); } else if (size == 4) { #ifdef HOST_MSB BYTE_REV32 (data); #endif - cpustate->program->write_dword(addr, data); + m_program->write_dword(addr, data); } else assert (0); @@ -654,7 +638,7 @@ static void writememi_emu (i860s *cpustate, UINT32 addr, int size, UINT32 data) addr = address to read. size = size of read in bytes. dest = memory to put read data. */ -static void fp_readmem_emu (i860s *cpustate, UINT32 addr, int size, UINT8 *dest) +void i860_cpu_device::fp_readmem_emu (UINT32 addr, int size, UINT8 *dest) { #ifdef TRACE_RDWR_MEM fprintf (stderr, "fp_readmem_emu: (ATE=%d) addr = 0x%08x, size = %d\n", @@ -666,51 +650,51 @@ static void fp_readmem_emu (i860s *cpustate, UINT32 addr, int size, UINT8 *dest) /* If virtual mode, do translation. */ if (GET_DIRBASE_ATE ()) { - UINT32 phys = get_address_translation (cpustate, addr, 1 /* is_dataref */, 0 /* is_write */); - if (cpustate->pending_trap && (GET_PSR_IAT () || GET_PSR_DAT ())) + UINT32 phys = get_address_translation (addr, 1 /* is_dataref */, 0 /* is_write */); + if (m_pending_trap && (GET_PSR_IAT () || GET_PSR_DAT ())) { #ifdef TRACE_PAGE_FAULT fprintf (stderr, "0x%08x: ## Page fault (fp_readmem_emu).\n", - cpustate->pc); + m_pc); #endif - cpustate->exiting_readmem = 3; + m_exiting_readmem = 3; return; } addr = phys; } /* First check for match to db register (before read). */ - if (((addr & ~(size - 1)) == cpustate->cregs[CR_DB]) && GET_PSR_BR ()) + if (((addr & ~(size - 1)) == m_cregs[CR_DB]) && GET_PSR_BR ()) { SET_PSR_DAT (1); - cpustate->pending_trap = 1; + m_pending_trap = 1; return; } if (size == 4) { - dest[0] = cpustate->program->read_byte(addr+3); - dest[1] = cpustate->program->read_byte(addr+2); - dest[2] = cpustate->program->read_byte(addr+1); - dest[3] = cpustate->program->read_byte(addr+0); + dest[0] = m_program->read_byte(addr+3); + dest[1] = m_program->read_byte(addr+2); + dest[2] = m_program->read_byte(addr+1); + dest[3] = m_program->read_byte(addr+0); } else if (size == 8) { - dest[0] = cpustate->program->read_byte(addr+7); - dest[1] = cpustate->program->read_byte(addr+6); - dest[2] = cpustate->program->read_byte(addr+5); - dest[3] = cpustate->program->read_byte(addr+4); - dest[4] = cpustate->program->read_byte(addr+3); - dest[5] = cpustate->program->read_byte(addr+2); - dest[6] = cpustate->program->read_byte(addr+1); - dest[7] = cpustate->program->read_byte(addr+0); + dest[0] = m_program->read_byte(addr+7); + dest[1] = m_program->read_byte(addr+6); + dest[2] = m_program->read_byte(addr+5); + dest[3] = m_program->read_byte(addr+4); + dest[4] = m_program->read_byte(addr+3); + dest[5] = m_program->read_byte(addr+2); + dest[6] = m_program->read_byte(addr+1); + dest[7] = m_program->read_byte(addr+0); } else if (size == 16) { int i; for (i = 0; i < 16; i++) { - dest[i] = cpustate->program->read_byte(addr+15-i); + dest[i] = m_program->read_byte(addr+15-i); } } } @@ -721,7 +705,7 @@ static void fp_readmem_emu (i860s *cpustate, UINT32 addr, int size, UINT8 *dest) size = size of read in bytes. data = pointer to the data. wmask = bit mask of bytes to write (only for pst.d). */ -static void fp_writemem_emu (i860s *cpustate, UINT32 addr, int size, UINT8 *data, UINT32 wmask) +void i860_cpu_device::fp_writemem_emu (UINT32 addr, int size, UINT8 *data, UINT32 wmask) { #ifdef TRACE_RDWR_MEM fprintf (stderr, "fp_writemem_emu: (ATE=%d) addr = 0x%08x, size = %d\n", @@ -733,37 +717,37 @@ static void fp_writemem_emu (i860s *cpustate, UINT32 addr, int size, UINT8 *data /* If virtual mode, do translation. */ if (GET_DIRBASE_ATE ()) { - UINT32 phys = get_address_translation (cpustate, addr, 1 /* is_dataref */, 1 /* is_write */); - if (cpustate->pending_trap && GET_PSR_DAT ()) + UINT32 phys = get_address_translation (addr, 1 /* is_dataref */, 1 /* is_write */); + if (m_pending_trap && GET_PSR_DAT ()) { #ifdef TRACE_PAGE_FAULT fprintf (stderr, "0x%08x: ## Page fault (fp_writememi_emu).\n", - cpustate->pc); + m_pc); #endif - cpustate->exiting_readmem = 4; + m_exiting_readmem = 4; return; } addr = phys; } /* First check for match to db register (before read). */ - if (((addr & ~(size - 1)) == cpustate->cregs[CR_DB]) && GET_PSR_BW ()) + if (((addr & ~(size - 1)) == m_cregs[CR_DB]) && GET_PSR_BW ()) { SET_PSR_DAT (1); - cpustate->pending_trap = 1; + m_pending_trap = 1; return; } if (size == 4) { #if 1 - cpustate->program->write_byte(addr+3, data[0]); - cpustate->program->write_byte(addr+2, data[1]); - cpustate->program->write_byte(addr+1, data[2]); - cpustate->program->write_byte(addr+0, data[3]); + m_program->write_byte(addr+3, data[0]); + m_program->write_byte(addr+2, data[1]); + m_program->write_byte(addr+1, data[2]); + m_program->write_byte(addr+0, data[3]); #else UINT32 ddd = (data[3]) | (data[2] << 8) | (data[1] << 16) |(data[0] << 24); - cpustate->program->write_dword(addr+0, ddd); + m_program->write_dword(addr+0, ddd); #endif } else if (size == 8) @@ -771,25 +755,25 @@ static void fp_writemem_emu (i860s *cpustate, UINT32 addr, int size, UINT8 *data /* Special: watch for wmask != 0xff, which means we're doing pst.d. */ if (wmask == 0xff) { - cpustate->program->write_byte(addr+7, data[0]); - cpustate->program->write_byte(addr+6, data[1]); - cpustate->program->write_byte(addr+5, data[2]); - cpustate->program->write_byte(addr+4, data[3]); - cpustate->program->write_byte(addr+3, data[4]); - cpustate->program->write_byte(addr+2, data[5]); - cpustate->program->write_byte(addr+1, data[6]); - cpustate->program->write_byte(addr+0, data[7]); + m_program->write_byte(addr+7, data[0]); + m_program->write_byte(addr+6, data[1]); + m_program->write_byte(addr+5, data[2]); + m_program->write_byte(addr+4, data[3]); + m_program->write_byte(addr+3, data[4]); + m_program->write_byte(addr+2, data[5]); + m_program->write_byte(addr+1, data[6]); + m_program->write_byte(addr+0, data[7]); } else { - if (wmask & 0x80) cpustate->program->write_byte(addr+7, data[0]); - if (wmask & 0x40) cpustate->program->write_byte(addr+6, data[1]); - if (wmask & 0x20) cpustate->program->write_byte(addr+5, data[2]); - if (wmask & 0x10) cpustate->program->write_byte(addr+4, data[3]); - if (wmask & 0x08) cpustate->program->write_byte(addr+3, data[4]); - if (wmask & 0x04) cpustate->program->write_byte(addr+2, data[5]); - if (wmask & 0x02) cpustate->program->write_byte(addr+1, data[6]); - if (wmask & 0x01) cpustate->program->write_byte(addr+0, data[7]); + if (wmask & 0x80) m_program->write_byte(addr+7, data[0]); + if (wmask & 0x40) m_program->write_byte(addr+6, data[1]); + if (wmask & 0x20) m_program->write_byte(addr+5, data[2]); + if (wmask & 0x10) m_program->write_byte(addr+4, data[3]); + if (wmask & 0x08) m_program->write_byte(addr+3, data[4]); + if (wmask & 0x04) m_program->write_byte(addr+2, data[5]); + if (wmask & 0x02) m_program->write_byte(addr+1, data[6]); + if (wmask & 0x01) m_program->write_byte(addr+0, data[7]); } } else if (size == 16) @@ -797,7 +781,7 @@ static void fp_writemem_emu (i860s *cpustate, UINT32 addr, int size, UINT8 *data int i; for (i = 0; i < 16; i++) { - cpustate->program->write_byte(addr+15-i, data[i]); + m_program->write_byte(addr+15-i, data[i]); } } @@ -807,7 +791,7 @@ static void fp_writemem_emu (i860s *cpustate, UINT32 addr, int size, UINT8 *data #if 0 /* Do a pipeline dump. type: 0 (all), 1 (add), 2 (mul), 3 (load), 4 (graphics). */ -static void dump_pipe (i860s *cpustate, int type) +void i860_cpu_device::dump_pipe (int type) { int i = 0; @@ -818,12 +802,12 @@ static void dump_pipe (i860s *cpustate, int type) fprintf (stderr, " A: "); for (i = 0; i < 3; i++) { - if (cpustate->A[i].stat.arp) + if (m_A[i].stat.arp) fprintf (stderr, "[%dd] 0x%016llx ", i + 1, - *(UINT64 *)(&cpustate->A[i].val.d)); + *(UINT64 *)(&m_A[i].val.d)); else fprintf (stderr, "[%ds] 0x%08x ", i + 1, - *(UINT32 *)(&cpustate->A[i].val.s)); + *(UINT32 *)(&m_A[i].val.s)); } fprintf (stderr, "\n"); } @@ -835,12 +819,12 @@ static void dump_pipe (i860s *cpustate, int type) fprintf (stderr, " M: "); for (i = 0; i < 3; i++) { - if (cpustate->M[i].stat.mrp) + if (m_M[i].stat.mrp) fprintf (stderr, "[%dd] 0x%016llx ", i + 1, - *(UINT64 *)(&cpustate->M[i].val.d)); + *(UINT64 *)(&m_M[i].val.d)); else fprintf (stderr, "[%ds] 0x%08x ", i + 1, - *(UINT32 *)(&cpustate->M[i].val.s)); + *(UINT32 *)(&m_M[i].val.s)); } fprintf (stderr, "\n"); } @@ -851,12 +835,12 @@ static void dump_pipe (i860s *cpustate, int type) fprintf (stderr, " L: "); for (i = 0; i < 3; i++) { - if (cpustate->L[i].stat.lrp) + if (m_L[i].stat.lrp) fprintf (stderr, "[%dd] 0x%016llx ", i + 1, - *(UINT64 *)(&cpustate->L[i].val.d)); + *(UINT64 *)(&m_L[i].val.d)); else fprintf (stderr, "[%ds] 0x%08x ", i + 1, - *(UINT32 *)(&cpustate->L[i].val.s)); + *(UINT32 *)(&m_L[i].val.s)); } fprintf (stderr, "\n"); } @@ -865,18 +849,18 @@ static void dump_pipe (i860s *cpustate, int type) if (type == 0 || type == 4) { fprintf (stderr, " I: "); - if (cpustate->G.stat.irp) + if (m_G.stat.irp) fprintf (stderr, "[1d] 0x%016llx\n", - *(UINT64 *)(&cpustate->G.val.d)); + *(UINT64 *)(&m_G.val.d)); else fprintf (stderr, "[1s] 0x%08x\n", - *(UINT32 *)(&cpustate->G.val.s)); + *(UINT32 *)(&m_G.val.s)); } } /* Do a register/state dump. */ -static void dump_state (i860s *cpustate) +void i860_cpu_device::dump_state (i860s *cpustate) { int rn; @@ -892,7 +876,7 @@ static void dump_state (i860s *cpustate) /* FR's (as 32-bits), 4 per line. */ for (rn = 0; rn < 32; rn++) { - float ff = get_fregval_s (cpustate, rn); + float ff = get_fregval_s (rn); if ((rn % 4) == 0) fprintf (stderr, "\n"); fprintf (stderr, "%%f%-3d: 0x%08x ", rn, *(UINT32 *)&ff); @@ -908,9 +892,9 @@ static void dump_state (i860s *cpustate) fprintf (stderr, "epsr: INT = %d, OF = %d, BE = %d\n", GET_EPSR_INT (), GET_EPSR_OF (), GET_EPSR_BE ()); fprintf (stderr, " fir: 0x%08x dirbase: 0x%08x fsr: 0x%08x\n", - cpustate->cregs[CR_FIR], cpustate->cregs[CR_DIRBASE], - cpustate->cregs[CR_FSR]); - fprintf (stderr, " pc: 0x%08x\n", cpustate->pc); + m_cregs[CR_FIR], m_cregs[CR_DIRBASE], + m_cregs[CR_FSR]); + fprintf (stderr, " pc: 0x%08x\n", m_pc); } #endif @@ -924,14 +908,14 @@ INLINE INT32 sign_ext (UINT32 x, int n) } -static void unrecog_opcode (UINT32 pc, UINT32 insn) +void i860_cpu_device::unrecog_opcode (UINT32 pc, UINT32 insn) { fprintf (stderr, "0x%08x: 0x%08x (unrecognized opcode)\n", pc, insn); } /* Execute "ld.c csrc2,idest" instruction. */ -static void insn_ld_ctrl (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_ld_ctrl (UINT32 insn) { UINT32 csrc2 = get_creg (insn); UINT32 idest = get_idest (insn); @@ -940,7 +924,7 @@ static void insn_ld_ctrl (i860s *cpustate, UINT32 insn) if (csrc2 > 5) { /* Control register not between 0..5. Undefined i860XR behavior. */ - fprintf (stderr, "WARNING: insn_ld_from_ctrl (pc=0x%08x): bad creg in ld.c (ignored)\n", cpustate->pc); + fprintf (stderr, "WARNING: insn_ld_from_ctrl (pc=0x%08x): bad creg in ld.c (ignored)\n", m_pc); return; } #endif @@ -950,22 +934,22 @@ static void insn_ld_ctrl (i860s *cpustate, UINT32 insn) 2. Not first load of fir after a trap = address of the ld.c insn. */ if (csrc2 == CR_FIR) { - if (cpustate->fir_gets_trap_addr) - set_iregval (idest, cpustate->cregs[csrc2]); + if (m_fir_gets_trap_addr) + set_iregval (idest, m_cregs[csrc2]); else { - cpustate->cregs[csrc2] = cpustate->pc; - set_iregval (idest, cpustate->cregs[csrc2]); + m_cregs[csrc2] = m_pc; + set_iregval (idest, m_cregs[csrc2]); } - cpustate->fir_gets_trap_addr = 0; + m_fir_gets_trap_addr = 0; } else - set_iregval (idest, cpustate->cregs[csrc2]); + set_iregval (idest, m_cregs[csrc2]); } /* Execute "st.c isrc1,csrc2" instruction. */ -static void insn_st_ctrl (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_st_ctrl (UINT32 insn) { UINT32 csrc2 = get_creg (insn); UINT32 isrc1 = get_isrc1 (insn); @@ -974,7 +958,7 @@ static void insn_st_ctrl (i860s *cpustate, UINT32 insn) if (csrc2 > 5) { /* Control register not between 0..5. Undefined i860XR behavior. */ - fprintf (stderr, "WARNING: insn_st_to_ctrl (pc=0x%08x): bad creg in st.c (ignored)\n", cpustate->pc); + fprintf (stderr, "WARNING: insn_st_to_ctrl (pc=0x%08x): bad creg in st.c (ignored)\n", m_pc); return; } #endif @@ -993,7 +977,7 @@ static void insn_st_ctrl (i860s *cpustate, UINT32 insn) if (csrc2 == CR_DIRBASE && (get_iregval (isrc1) & 1) && GET_DIRBASE_ATE () == 0) { - fprintf (stderr, "0x%08x: ** ATE going high!\n", cpustate->pc); + fprintf (stderr, "0x%08x: ** ATE going high!\n", m_pc); } /* Update the register -- unless it is fir which cannot be updated. */ @@ -1006,14 +990,14 @@ static void insn_st_ctrl (i860s *cpustate, UINT32 insn) if (GET_PSR_U ()) { enew = get_iregval (isrc1) & ~(0x003e1fff | 0x00c06000); - tmp = cpustate->cregs[CR_EPSR] & (0x003e1fff | 0x00c06000); + tmp = m_cregs[CR_EPSR] & (0x003e1fff | 0x00c06000); } else { enew = get_iregval (isrc1) & ~0x003e1fff; - tmp = cpustate->cregs[CR_EPSR] & 0x003e1fff; + tmp = m_cregs[CR_EPSR] & 0x003e1fff; } - cpustate->cregs[CR_EPSR] = enew | tmp; + m_cregs[CR_EPSR] = enew | tmp; } else if (csrc2 == CR_PSR) { @@ -1021,27 +1005,27 @@ static void insn_st_ctrl (i860s *cpustate, UINT32 insn) if (GET_PSR_U ()) { UINT32 enew = get_iregval (isrc1) & ~PSR_SUPERVISOR_ONLY_MASK; - UINT32 tmp = cpustate->cregs[CR_PSR] & PSR_SUPERVISOR_ONLY_MASK; - cpustate->cregs[CR_PSR] = enew | tmp; + UINT32 tmp = m_cregs[CR_PSR] & PSR_SUPERVISOR_ONLY_MASK; + m_cregs[CR_PSR] = enew | tmp; } else - cpustate->cregs[CR_PSR] = get_iregval (isrc1); + m_cregs[CR_PSR] = get_iregval (isrc1); } else if (csrc2 == CR_FSR) { /* I believe that only 21..17, 8..5, and 3..0 should be updated. */ UINT32 enew = get_iregval (isrc1) & 0x003e01ef; - UINT32 tmp = cpustate->cregs[CR_FSR] & ~0x003e01ef; - cpustate->cregs[CR_FSR] = enew | tmp; + UINT32 tmp = m_cregs[CR_FSR] & ~0x003e01ef; + m_cregs[CR_FSR] = enew | tmp; } else if (csrc2 != CR_FIR) - cpustate->cregs[csrc2] = get_iregval (isrc1); + m_cregs[csrc2] = get_iregval (isrc1); } /* Execute "ld.{s,b,l} isrc1(isrc2),idest" or "ld.{s,b,l} #const(isrc2),idest". */ -static void insn_ldx (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_ldx (UINT32 insn) { UINT32 isrc1 = get_isrc1 (insn); INT32 immsrc1 = sign_ext (get_imm16 (insn), 16); @@ -1073,9 +1057,9 @@ static void insn_ldx (i860s *cpustate, UINT32 insn) if (eff & (size - 1)) { fprintf (stderr, "0x%08x: Unaligned access detected (0x%08x).\n", - cpustate->pc, eff); + m_pc, eff); SET_PSR_DAT (1); - cpustate->pending_trap = 1; + m_pending_trap = 1; return; } #endif @@ -1087,9 +1071,9 @@ static void insn_ldx (i860s *cpustate, UINT32 insn) is the target register). */ if (size < 4) { - UINT32 readval = sign_ext (readmemi_emu (cpustate, eff, size), size * 8); + UINT32 readval = sign_ext (readmemi_emu (eff, size), size * 8); /* Do not update register on page fault. */ - if (cpustate->exiting_readmem) + if (m_exiting_readmem) { return; } @@ -1097,9 +1081,9 @@ static void insn_ldx (i860s *cpustate, UINT32 insn) } else { - UINT32 readval = readmemi_emu (cpustate, eff, size); + UINT32 readval = readmemi_emu (eff, size); /* Do not update register on page fault. */ - if (cpustate->exiting_readmem) + if (m_exiting_readmem) { return; } @@ -1111,7 +1095,7 @@ static void insn_ldx (i860s *cpustate, UINT32 insn) /* Execute "st.x isrc1ni,#const(isrc2)" instruction (there is no (reg + reg form). Store uses the split immediate, not the normal 16-bit immediate as in ld.x. */ -static void insn_stx (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_stx (UINT32 insn) { INT32 immsrc = sign_ext ((((insn >> 5) & 0xf800) | (insn & 0x07ff)), 16); UINT32 isrc1 = get_isrc1 (insn); @@ -1131,8 +1115,8 @@ static void insn_stx (i860s *cpustate, UINT32 insn) eff = (UINT32)(immsrc + (INT32)get_iregval (isrc2)); /* Write data (value of reg isrc1) to memory at eff. */ - writememi_emu (cpustate, eff, size, get_iregval (isrc1)); - if (cpustate->exiting_readmem) + writememi_emu (eff, size, get_iregval (isrc1)); + if (m_exiting_readmem) return; } @@ -1140,7 +1124,7 @@ static void insn_stx (i860s *cpustate, UINT32 insn) /* Execute "fst.y fdest,isrc1(isrc2)", "fst.y fdest,isrc1(isrc2)++", "fst.y fdest,#const(isrc2)" or "fst.y fdest,#const(isrc2)++" instruction. */ -static void insn_fsty (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_fsty (UINT32 insn) { UINT32 isrc1 = get_isrc1 (insn); INT32 immsrc1 = sign_ext (get_imm16 (insn), 16); @@ -1176,9 +1160,9 @@ static void insn_fsty (i860s *cpustate, UINT32 insn) if (eff & (size - 1)) { fprintf (stderr, "0x%08x: Unaligned access detected (0x%08x).\n", - cpustate->pc, eff); + m_pc, eff); SET_PSR_DAT (1); - cpustate->pending_trap = 1; + m_pending_trap = 1; return; } #endif @@ -1192,7 +1176,7 @@ static void insn_fsty (i860s *cpustate, UINT32 insn) if (isrc1 == isrc2) { /* Undefined i860XR behavior. */ - fprintf (stderr, "WARNING: insn_fsty (pc=0x%08x): isrc1 = isrc2 in fst with auto-inc (ignored)\n", cpustate->pc); + fprintf (stderr, "WARNING: insn_fsty (pc=0x%08x): isrc1 = isrc2 in fst with auto-inc (ignored)\n", m_pc); return; } #endif @@ -1200,11 +1184,11 @@ static void insn_fsty (i860s *cpustate, UINT32 insn) /* Write data (value of freg fdest) to memory at eff. */ if (size == 4) - fp_writemem_emu (cpustate, eff, size, (UINT8 *)(&cpustate->frg[4 * (31 - fdest)]), 0xff); + fp_writemem_emu (eff, size, (UINT8 *)(&m_frg[4 * (31 - fdest)]), 0xff); else if (size == 8) - fp_writemem_emu (cpustate, eff, size, (UINT8 *)(&cpustate->frg[4 * (31 - (fdest + 1))]), 0xff); + fp_writemem_emu (eff, size, (UINT8 *)(&m_frg[4 * (31 - (fdest + 1))]), 0xff); else - fp_writemem_emu (cpustate, eff, size, (UINT8 *)(&cpustate->frg[4 * (31 - (fdest + 3))]), 0xff); + fp_writemem_emu (eff, size, (UINT8 *)(&m_frg[4 * (31 - (fdest + 3))]), 0xff); } @@ -1212,7 +1196,7 @@ static void insn_fsty (i860s *cpustate, UINT32 insn) /* Execute "fld.y isrc1(isrc2),fdest", "fld.y isrc1(isrc2)++,idest", "fld.y #const(isrc2),fdest" or "fld.y #const(isrc2)++,idest". Where y = {l,d,q}. Note, there is no pfld.q, though. */ -static void insn_fldy (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_fldy (UINT32 insn) { UINT32 isrc1 = get_isrc1 (insn); INT32 immsrc1 = sign_ext (get_imm16 (insn), 16); @@ -1235,7 +1219,7 @@ static void insn_fldy (i860s *cpustate, UINT32 insn) /* There is no pipelined load quad. */ if (piped && size == 16) { - unrecog_opcode (cpustate->pc, insn); + unrecog_opcode (m_pc, insn); return; } @@ -1261,7 +1245,7 @@ static void insn_fldy (i860s *cpustate, UINT32 insn) if (isrc1 == isrc2) { /* Undefined i860XR behavior. */ - fprintf (stderr, "WARNING: insn_fldy (pc=0x%08x): isrc1 = isrc2 in fst with auto-inc (ignored)\n", cpustate->pc); + fprintf (stderr, "WARNING: insn_fldy (pc=0x%08x): isrc1 = isrc2 in fst with auto-inc (ignored)\n", m_pc); return; } #endif @@ -1271,9 +1255,9 @@ static void insn_fldy (i860s *cpustate, UINT32 insn) if (eff & (size - 1)) { fprintf (stderr, "0x%08x: Unaligned access detected (0x%08x).\n", - cpustate->pc, eff); + m_pc, eff); SET_PSR_DAT (1); - cpustate->pending_trap = 1; + m_pending_trap = 1; return; } #endif @@ -1288,11 +1272,11 @@ static void insn_fldy (i860s *cpustate, UINT32 insn) if (fdest > 1) { if (size == 4) - fp_readmem_emu (cpustate, eff, size, (UINT8 *)&(cpustate->frg[4 * (31 - fdest)])); + fp_readmem_emu (eff, size, (UINT8 *)&(m_frg[4 * (31 - fdest)])); else if (size == 8) - fp_readmem_emu (cpustate, eff, size, (UINT8 *)&(cpustate->frg[4 * (31 - (fdest + 1))])); + fp_readmem_emu (eff, size, (UINT8 *)&(m_frg[4 * (31 - (fdest + 1))])); else if (size == 16) - fp_readmem_emu (cpustate, eff, size, (UINT8 *)&(cpustate->frg[4 * (31 - (fdest + 3))])); + fp_readmem_emu (eff, size, (UINT8 *)&(m_frg[4 * (31 - (fdest + 3))])); } } else @@ -1302,8 +1286,8 @@ static void insn_fldy (i860s *cpustate, UINT32 insn) stay unaffected after a trap so that the instruction can be properly restarted. */ UINT8 bebuf[8]; - fp_readmem_emu (cpustate, eff, size, bebuf); - if (cpustate->pending_trap && cpustate->exiting_readmem) + fp_readmem_emu (eff, size, bebuf); + if (m_pending_trap && m_exiting_readmem) goto ab_op; /* Pipelined version writes fdest with the result from the last @@ -1311,22 +1295,22 @@ static void insn_fldy (i860s *cpustate, UINT32 insn) bit of the stage's result-status bits. */ #if 1 /* FIXME: WIP on FSR update. This may not be correct. */ /* Copy 3rd stage LRP to FSR. */ - if (cpustate->L[1 /* 2 */].stat.lrp) - cpustate->cregs[CR_FSR] |= 0x04000000; + if (m_L[1 /* 2 */].stat.lrp) + m_cregs[CR_FSR] |= 0x04000000; else - cpustate->cregs[CR_FSR] &= ~0x04000000; + m_cregs[CR_FSR] &= ~0x04000000; #endif - if (cpustate->L[2].stat.lrp) /* 3rd (last) stage. */ - set_fregval_d (cpustate, fdest, cpustate->L[2].val.d); + if (m_L[2].stat.lrp) /* 3rd (last) stage. */ + set_fregval_d (fdest, m_L[2].val.d); else - set_fregval_s (cpustate, fdest, cpustate->L[2].val.s); + set_fregval_s (fdest, m_L[2].val.s); /* Now advance pipeline and write loaded data to first stage. */ - cpustate->L[2] = cpustate->L[1]; - cpustate->L[1] = cpustate->L[0]; + m_L[2] = m_L[1]; + m_L[1] = m_L[0]; if (size == 8) { - UINT8 *t = (UINT8 *)&(cpustate->L[0].val.d); + UINT8 *t = (UINT8 *)&(m_L[0].val.d); #ifndef HOST_MSB t[7] = bebuf[0]; t[6] = bebuf[1]; t[5] = bebuf[2]; t[4] = bebuf[3]; t[3] = bebuf[4]; t[2] = bebuf[5]; t[1] = bebuf[6]; t[0] = bebuf[7]; @@ -1334,17 +1318,17 @@ static void insn_fldy (i860s *cpustate, UINT32 insn) t[0] = bebuf[0]; t[1] = bebuf[1]; t[2] = bebuf[2]; t[3] = bebuf[3]; t[4] = bebuf[4]; t[5] = bebuf[5]; t[6] = bebuf[6]; t[7] = bebuf[7]; #endif - cpustate->L[0].stat.lrp = 1; + m_L[0].stat.lrp = 1; } else { - UINT8 *t = (UINT8 *)&(cpustate->L[0].val.s); + UINT8 *t = (UINT8 *)&(m_L[0].val.s); #ifndef HOST_MSB t[3] = bebuf[0]; t[2] = bebuf[1]; t[1] = bebuf[2]; t[0] = bebuf[3]; #else t[0] = bebuf[0]; t[1] = bebuf[1]; t[2] = bebuf[2]; t[3] = bebuf[3]; #endif - cpustate->L[0].stat.lrp = 0; + m_L[0].stat.lrp = 0; } } @@ -1354,7 +1338,7 @@ static void insn_fldy (i860s *cpustate, UINT32 insn) /* Execute "pst.d fdest,#const(isrc2)" or "fst.d fdest,#const(isrc2)++" instruction. */ -static void insn_pstd (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_pstd (UINT32 insn) { INT32 immsrc1 = sign_ext (get_imm16 (insn), 16); UINT32 isrc2 = get_isrc2 (insn); @@ -1382,7 +1366,7 @@ static void insn_pstd (i860s *cpustate, UINT32 insn) if (insn & 0x6) { /* Undefined i860XR behavior. */ - fprintf (stderr, "WARNING: insn_pstd (pc=0x%08x): bad operand size specifier\n", cpustate->pc); + fprintf (stderr, "WARNING: insn_pstd (pc=0x%08x): bad operand size specifier\n", m_pc); } #endif @@ -1396,9 +1380,9 @@ static void insn_pstd (i860s *cpustate, UINT32 insn) if (eff & (8 - 1)) { fprintf (stderr, "0x%08x: Unaligned access detected (0x%08x).\n", - cpustate->pc, eff); + m_pc, eff); SET_PSR_DAT (1); - cpustate->pending_trap = 1; + m_pending_trap = 1; return; } #endif @@ -1448,13 +1432,13 @@ static void insn_pstd (i860s *cpustate, UINT32 insn) } orig_pm <<= 1; } - bebuf = (UINT8 *)(&cpustate->frg[4 * (31 - (fdest + 1))]); - fp_writemem_emu (cpustate, eff, 8, bebuf, wmask); + bebuf = (UINT8 *)(&m_frg[4 * (31 - (fdest + 1))]); + fp_writemem_emu (eff, 8, bebuf, wmask); } /* Execute "ixfr isrc1ni,fdest" instruction. */ -static void insn_ixfr (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_ixfr (UINT32 insn) { UINT32 isrc1 = get_isrc1 (insn); UINT32 fdest = get_fdest (insn); @@ -1462,12 +1446,12 @@ static void insn_ixfr (i860s *cpustate, UINT32 insn) /* This is a bit-pattern transfer, not a conversion. */ iv = get_iregval (isrc1); - set_fregval_s (cpustate, fdest, *(float *)&iv); + set_fregval_s (fdest, *(float *)&iv); } /* Execute "addu isrc1,isrc2,idest". */ -static void insn_addu (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_addu (UINT32 insn) { UINT32 src1val; UINT32 isrc2 = get_isrc2 (insn); @@ -1505,7 +1489,7 @@ static void insn_addu (i860s *cpustate, UINT32 insn) /* Execute "addu #const,isrc2,idest". */ -static void insn_addu_imm (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_addu_imm (UINT32 insn) { UINT32 src1val; UINT32 isrc2 = get_isrc2 (insn); @@ -1543,7 +1527,7 @@ static void insn_addu_imm (i860s *cpustate, UINT32 insn) /* Execute "adds isrc1,isrc2,idest". */ -static void insn_adds (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_adds (UINT32 insn) { UINT32 src1val; UINT32 isrc2 = get_isrc2 (insn); @@ -1583,7 +1567,7 @@ static void insn_adds (i860s *cpustate, UINT32 insn) /* Execute "adds #const,isrc2,idest". */ -static void insn_adds_imm (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_adds_imm (UINT32 insn) { UINT32 src1val; UINT32 isrc2 = get_isrc2 (insn); @@ -1623,7 +1607,7 @@ static void insn_adds_imm (i860s *cpustate, UINT32 insn) /* Execute "subu isrc1,isrc2,idest". */ -static void insn_subu (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_subu (UINT32 insn) { UINT32 src1val; UINT32 isrc2 = get_isrc2 (insn); @@ -1661,7 +1645,7 @@ static void insn_subu (i860s *cpustate, UINT32 insn) /* Execute "subu #const,isrc2,idest". */ -static void insn_subu_imm (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_subu_imm (UINT32 insn) { UINT32 src1val; UINT32 isrc2 = get_isrc2 (insn); @@ -1699,7 +1683,7 @@ static void insn_subu_imm (i860s *cpustate, UINT32 insn) /* Execute "subs isrc1,isrc2,idest". */ -static void insn_subs (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_subs (UINT32 insn) { UINT32 src1val; UINT32 isrc2 = get_isrc2 (insn); @@ -1739,7 +1723,7 @@ static void insn_subs (i860s *cpustate, UINT32 insn) /* Execute "subs #const,isrc2,idest". */ -static void insn_subs_imm (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_subs_imm (UINT32 insn) { UINT32 src1val; UINT32 isrc2 = get_isrc2 (insn); @@ -1779,7 +1763,7 @@ static void insn_subs_imm (i860s *cpustate, UINT32 insn) /* Execute "shl isrc1,isrc2,idest". */ -static void insn_shl (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_shl (UINT32 insn) { UINT32 src1val = 0; UINT32 isrc2 = get_isrc2 (insn); @@ -1791,7 +1775,7 @@ static void insn_shl (i860s *cpustate, UINT32 insn) /* Execute "shl #const,isrc2,idest". */ -static void insn_shl_imm (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_shl_imm (UINT32 insn) { UINT32 src1val = 0; UINT32 isrc2 = get_isrc2 (insn); @@ -1803,7 +1787,7 @@ static void insn_shl_imm (i860s *cpustate, UINT32 insn) /* Execute "shr isrc1,isrc2,idest". */ -static void insn_shr (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_shr (UINT32 insn) { UINT32 src1val = 0; UINT32 isrc2 = get_isrc2 (insn); @@ -1820,7 +1804,7 @@ static void insn_shr (i860s *cpustate, UINT32 insn) /* Execute "shr #const,isrc2,idest". */ -static void insn_shr_imm (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_shr_imm (UINT32 insn) { UINT32 src1val = 0; UINT32 isrc2 = get_isrc2 (insn); @@ -1837,7 +1821,7 @@ static void insn_shr_imm (i860s *cpustate, UINT32 insn) /* Execute "shra isrc1,isrc2,idest". */ -static void insn_shra (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_shra (UINT32 insn) { UINT32 src1val = 0; UINT32 isrc2 = get_isrc2 (insn); @@ -1851,7 +1835,7 @@ static void insn_shra (i860s *cpustate, UINT32 insn) /* Execute "shra #const,isrc2,idest". */ -static void insn_shra_imm (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_shra_imm (UINT32 insn) { UINT32 src1val = 0; UINT32 isrc2 = get_isrc2 (insn); @@ -1865,7 +1849,7 @@ static void insn_shra_imm (i860s *cpustate, UINT32 insn) /* Execute "shrd isrc1ni,isrc2,idest" instruction. */ -static void insn_shrd (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_shrd (UINT32 insn) { UINT32 isrc1 = get_isrc1 (insn); UINT32 isrc2 = get_isrc2 (insn); @@ -1887,7 +1871,7 @@ static void insn_shrd (i860s *cpustate, UINT32 insn) /* Execute "and isrc1,isrc2,idest". */ -static void insn_and (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_and (UINT32 insn) { UINT32 isrc1 = get_isrc1 (insn); UINT32 isrc2 = get_isrc2 (insn); @@ -1908,7 +1892,7 @@ static void insn_and (i860s *cpustate, UINT32 insn) /* Execute "and #const,isrc2,idest". */ -static void insn_and_imm (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_and_imm (UINT32 insn) { UINT32 src1val = 0; UINT32 isrc2 = get_isrc2 (insn); @@ -1930,7 +1914,7 @@ static void insn_and_imm (i860s *cpustate, UINT32 insn) /* Execute "andh #const,isrc2,idest". */ -static void insn_andh_imm (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_andh_imm (UINT32 insn) { UINT32 src1val = 0; UINT32 isrc2 = get_isrc2 (insn); @@ -1952,7 +1936,7 @@ static void insn_andh_imm (i860s *cpustate, UINT32 insn) /* Execute "andnot isrc1,isrc2,idest". */ -static void insn_andnot (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_andnot (UINT32 insn) { UINT32 isrc1 = get_isrc1 (insn); UINT32 isrc2 = get_isrc2 (insn); @@ -1973,7 +1957,7 @@ static void insn_andnot (i860s *cpustate, UINT32 insn) /* Execute "andnot #const,isrc2,idest". */ -static void insn_andnot_imm (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_andnot_imm (UINT32 insn) { UINT32 src1val = 0; UINT32 isrc2 = get_isrc2 (insn); @@ -1995,7 +1979,7 @@ static void insn_andnot_imm (i860s *cpustate, UINT32 insn) /* Execute "andnoth #const,isrc2,idest". */ -static void insn_andnoth_imm (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_andnoth_imm (UINT32 insn) { UINT32 src1val = 0; UINT32 isrc2 = get_isrc2 (insn); @@ -2017,7 +2001,7 @@ static void insn_andnoth_imm (i860s *cpustate, UINT32 insn) /* Execute "or isrc1,isrc2,idest". */ -static void insn_or (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_or (UINT32 insn) { UINT32 isrc1 = get_isrc1 (insn); UINT32 isrc2 = get_isrc2 (insn); @@ -2038,7 +2022,7 @@ static void insn_or (i860s *cpustate, UINT32 insn) /* Execute "or #const,isrc2,idest". */ -static void insn_or_imm (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_or_imm (UINT32 insn) { UINT32 src1val = 0; UINT32 isrc2 = get_isrc2 (insn); @@ -2060,7 +2044,7 @@ static void insn_or_imm (i860s *cpustate, UINT32 insn) /* Execute "orh #const,isrc2,idest". */ -static void insn_orh_imm (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_orh_imm (UINT32 insn) { UINT32 src1val = 0; UINT32 isrc2 = get_isrc2 (insn); @@ -2082,7 +2066,7 @@ static void insn_orh_imm (i860s *cpustate, UINT32 insn) /* Execute "xor isrc1,isrc2,idest". */ -static void insn_xor (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_xor (UINT32 insn) { UINT32 isrc1 = get_isrc1 (insn); UINT32 isrc2 = get_isrc2 (insn); @@ -2103,7 +2087,7 @@ static void insn_xor (i860s *cpustate, UINT32 insn) /* Execute "xor #const,isrc2,idest". */ -static void insn_xor_imm (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_xor_imm (UINT32 insn) { UINT32 src1val = 0; UINT32 isrc2 = get_isrc2 (insn); @@ -2125,7 +2109,7 @@ static void insn_xor_imm (i860s *cpustate, UINT32 insn) /* Execute "xorh #const,isrc2,idest". */ -static void insn_xorh_imm (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_xorh_imm (UINT32 insn) { UINT32 src1val = 0; UINT32 isrc2 = get_isrc2 (insn); @@ -2147,26 +2131,26 @@ static void insn_xorh_imm (i860s *cpustate, UINT32 insn) /* Execute "trap isrc1ni,isrc2,idest" instruction. */ -static void insn_trap (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_trap (UINT32 insn) { SET_PSR_IT (1); - cpustate->pending_trap = 1; + m_pending_trap = 1; } /* Execute "intovr" instruction. */ -static void insn_intovr (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_intovr (UINT32 insn) { if (GET_EPSR_OF ()) { SET_PSR_IT (1); - cpustate->pending_trap = 1; + m_pending_trap = 1; } } /* Execute "bte isrc1,isrc2,sbroff". */ -static void insn_bte (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_bte (UINT32 insn) { UINT32 src1val = 0; UINT32 isrc2 = get_isrc2 (insn); @@ -2178,23 +2162,23 @@ static void insn_bte (i860s *cpustate, UINT32 insn) /* Compute the target address from the sbroff field. */ sbroff = sign_ext ((((insn >> 5) & 0xf800) | (insn & 0x07ff)), 16); - target_addr = (INT32)cpustate->pc + 4 + (sbroff << 2); + target_addr = (INT32)m_pc + 4 + (sbroff << 2); /* Determine comparison result. */ res = (src1val == get_iregval (isrc2)); /* Branch routines always update the PC. */ if (res) - cpustate->pc = target_addr; + m_pc = target_addr; else - cpustate->pc += 4; + m_pc += 4; - cpustate->pc_updated = 1; + m_pc_updated = 1; } /* Execute "bte #const5,isrc2,sbroff". */ -static void insn_bte_imm (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_bte_imm (UINT32 insn) { UINT32 src1val = 0; UINT32 isrc2 = get_isrc2 (insn); @@ -2206,23 +2190,23 @@ static void insn_bte_imm (i860s *cpustate, UINT32 insn) /* Compute the target address from the sbroff field. */ sbroff = sign_ext ((((insn >> 5) & 0xf800) | (insn & 0x07ff)), 16); - target_addr = (INT32)cpustate->pc + 4 + (sbroff << 2); + target_addr = (INT32)m_pc + 4 + (sbroff << 2); /* Determine comparison result. */ res = (src1val == get_iregval (isrc2)); /* Branch routines always update the PC. */ if (res) - cpustate->pc = target_addr; + m_pc = target_addr; else - cpustate->pc += 4; + m_pc += 4; - cpustate->pc_updated = 1; + m_pc_updated = 1; } /* Execute "btne isrc1,isrc2,sbroff". */ -static void insn_btne (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_btne (UINT32 insn) { UINT32 src1val = 0; UINT32 isrc2 = get_isrc2 (insn); @@ -2234,23 +2218,23 @@ static void insn_btne (i860s *cpustate, UINT32 insn) /* Compute the target address from the sbroff field. */ sbroff = sign_ext ((((insn >> 5) & 0xf800) | (insn & 0x07ff)), 16); - target_addr = (INT32)cpustate->pc + 4 + (sbroff << 2); + target_addr = (INT32)m_pc + 4 + (sbroff << 2); /* Determine comparison result. */ res = (src1val != get_iregval (isrc2)); /* Branch routines always update the PC. */ if (res) - cpustate->pc = target_addr; + m_pc = target_addr; else - cpustate->pc += 4; + m_pc += 4; - cpustate->pc_updated = 1; + m_pc_updated = 1; } /* Execute "btne #const5,isrc2,sbroff". */ -static void insn_btne_imm (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_btne_imm (UINT32 insn) { UINT32 src1val = 0; UINT32 isrc2 = get_isrc2 (insn); @@ -2262,23 +2246,23 @@ static void insn_btne_imm (i860s *cpustate, UINT32 insn) /* Compute the target address from the sbroff field. */ sbroff = sign_ext ((((insn >> 5) & 0xf800) | (insn & 0x07ff)), 16); - target_addr = (INT32)cpustate->pc + 4 + (sbroff << 2); + target_addr = (INT32)m_pc + 4 + (sbroff << 2); /* Determine comparison result. */ res = (src1val != get_iregval (isrc2)); /* Branch routines always update the PC. */ if (res) - cpustate->pc = target_addr; + m_pc = target_addr; else - cpustate->pc += 4; + m_pc += 4; - cpustate->pc_updated = 1; + m_pc_updated = 1; } /* Execute "bc lbroff" instruction. */ -static void insn_bc (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_bc (UINT32 insn) { UINT32 target_addr = 0; INT32 lbroff = 0; @@ -2286,23 +2270,23 @@ static void insn_bc (i860s *cpustate, UINT32 insn) /* Compute the target address from the lbroff field. */ lbroff = sign_ext ((insn & 0x03ffffff), 26); - target_addr = (INT32)cpustate->pc + 4 + (lbroff << 2); + target_addr = (INT32)m_pc + 4 + (lbroff << 2); /* Determine comparison result. */ res = (GET_PSR_CC () == 1); /* Branch routines always update the PC. */ if (res) - cpustate->pc = target_addr; + m_pc = target_addr; else - cpustate->pc += 4; + m_pc += 4; - cpustate->pc_updated = 1; + m_pc_updated = 1; } /* Execute "bnc lbroff" instruction. */ -static void insn_bnc (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_bnc (UINT32 insn) { UINT32 target_addr = 0; INT32 lbroff = 0; @@ -2310,7 +2294,7 @@ static void insn_bnc (i860s *cpustate, UINT32 insn) /* Compute the target address from the lbroff field. */ lbroff = sign_ext ((insn & 0x03ffffff), 26); - target_addr = (INT32)cpustate->pc + 4 + (lbroff << 2); + target_addr = (INT32)m_pc + 4 + (lbroff << 2); /* Determine comparison result. */ res = (GET_PSR_CC () == 0); @@ -2318,25 +2302,25 @@ static void insn_bnc (i860s *cpustate, UINT32 insn) /* Branch routines always update the PC, since pc_updated is set in the decode routine. */ if (res) - cpustate->pc = target_addr; + m_pc = target_addr; else - cpustate->pc += 4; + m_pc += 4; - cpustate->pc_updated = 1; + m_pc_updated = 1; } /* Execute "bc.t lbroff" instruction. */ -static void insn_bct (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_bct (UINT32 insn) { UINT32 target_addr = 0; INT32 lbroff = 0; int res = 0; - UINT32 orig_pc = cpustate->pc; + UINT32 orig_pc = m_pc; /* Compute the target address from the lbroff field. */ lbroff = sign_ext ((insn & 0x03ffffff), 26); - target_addr = (INT32)cpustate->pc + 4 + (lbroff << 2); + target_addr = (INT32)m_pc + 4 + (lbroff << 2); /* Determine comparison result. */ res = (GET_PSR_CC () == 1); @@ -2346,12 +2330,12 @@ static void insn_bct (i860s *cpustate, UINT32 insn) if (res) { /* Execute delay slot instruction. */ - cpustate->pc += 4; - decode_exec (cpustate, ifetch (cpustate, orig_pc + 4), 0); - cpustate->pc = orig_pc; - if (cpustate->pending_trap) + m_pc += 4; + decode_exec (ifetch (orig_pc + 4), 0); + m_pc = orig_pc; + if (m_pending_trap) { - cpustate->pending_trap |= TRAP_IN_DELAY_SLOT; + m_pending_trap |= TRAP_IN_DELAY_SLOT; goto ab_op; } } @@ -2359,11 +2343,11 @@ static void insn_bct (i860s *cpustate, UINT32 insn) /* Since this branch is delayed, we must jump 2 instructions if if isn't taken. */ if (res) - cpustate->pc = target_addr; + m_pc = target_addr; else - cpustate->pc += 8; + m_pc += 8; - cpustate->pc_updated = 1; + m_pc_updated = 1; ab_op: ; @@ -2371,16 +2355,16 @@ static void insn_bct (i860s *cpustate, UINT32 insn) /* Execute "bnc.t lbroff" instruction. */ -static void insn_bnct (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_bnct (UINT32 insn) { UINT32 target_addr = 0; INT32 lbroff = 0; int res = 0; - UINT32 orig_pc = cpustate->pc; + UINT32 orig_pc = m_pc; /* Compute the target address from the lbroff field. */ lbroff = sign_ext ((insn & 0x03ffffff), 26); - target_addr = (INT32)cpustate->pc + 4 + (lbroff << 2); + target_addr = (INT32)m_pc + 4 + (lbroff << 2); /* Determine comparison result. */ res = (GET_PSR_CC () == 0); @@ -2390,12 +2374,12 @@ static void insn_bnct (i860s *cpustate, UINT32 insn) if (res) { /* Execute delay slot instruction. */ - cpustate->pc += 4; - decode_exec (cpustate, ifetch (cpustate, orig_pc + 4), 0); - cpustate->pc = orig_pc; - if (cpustate->pending_trap) + m_pc += 4; + decode_exec (ifetch (orig_pc + 4), 0); + m_pc = orig_pc; + if (m_pending_trap) { - cpustate->pending_trap |= TRAP_IN_DELAY_SLOT; + m_pending_trap |= TRAP_IN_DELAY_SLOT; goto ab_op; } } @@ -2403,11 +2387,11 @@ static void insn_bnct (i860s *cpustate, UINT32 insn) /* Since this branch is delayed, we must jump 2 instructions if if isn't taken. */ if (res) - cpustate->pc = target_addr; + m_pc = target_addr; else - cpustate->pc += 8; + m_pc += 8; - cpustate->pc_updated = 1; + m_pc_updated = 1; ab_op: ; @@ -2415,23 +2399,23 @@ static void insn_bnct (i860s *cpustate, UINT32 insn) /* Execute "call lbroff" instruction. */ -static void insn_call (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_call (UINT32 insn) { UINT32 target_addr = 0; INT32 lbroff = 0; - UINT32 orig_pc = cpustate->pc; + UINT32 orig_pc = m_pc; /* Compute the target address from the lbroff field. */ lbroff = sign_ext ((insn & 0x03ffffff), 26); - target_addr = (INT32)cpustate->pc + 4 + (lbroff << 2); + target_addr = (INT32)m_pc + 4 + (lbroff << 2); /* Execute the delay slot instruction. */ - cpustate->pc += 4; - decode_exec (cpustate, ifetch (cpustate, orig_pc + 4), 0); - cpustate->pc = orig_pc; - if (cpustate->pending_trap) + m_pc += 4; + decode_exec (ifetch (orig_pc + 4), 0); + m_pc = orig_pc; + if (m_pending_trap) { - cpustate->pending_trap |= TRAP_IN_DELAY_SLOT; + m_pending_trap |= TRAP_IN_DELAY_SLOT; goto ab_op; } @@ -2439,37 +2423,37 @@ static void insn_call (i860s *cpustate, UINT32 insn) set_iregval (1, orig_pc + 8); /* New target. */ - cpustate->pc = target_addr; - cpustate->pc_updated = 1; + m_pc = target_addr; + m_pc_updated = 1; ab_op:; } /* Execute "br lbroff". */ -static void insn_br (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_br (UINT32 insn) { UINT32 target_addr = 0; INT32 lbroff = 0; - UINT32 orig_pc = cpustate->pc; + UINT32 orig_pc = m_pc; /* Compute the target address from the lbroff field. */ lbroff = sign_ext ((insn & 0x03ffffff), 26); - target_addr = (INT32)cpustate->pc + 4 + (lbroff << 2); + target_addr = (INT32)m_pc + 4 + (lbroff << 2); /* Execute the delay slot instruction. */ - cpustate->pc += 4; - decode_exec (cpustate, ifetch (cpustate, orig_pc + 4), 0); - cpustate->pc = orig_pc; - if (cpustate->pending_trap) + m_pc += 4; + decode_exec (ifetch (orig_pc + 4), 0); + m_pc = orig_pc; + if (m_pending_trap) { - cpustate->pending_trap |= TRAP_IN_DELAY_SLOT; + m_pending_trap |= TRAP_IN_DELAY_SLOT; goto ab_op; } /* New target. */ - cpustate->pc = target_addr; - cpustate->pc_updated = 1; + m_pc = target_addr; + m_pc_updated = 1; ab_op:; } @@ -2478,26 +2462,26 @@ static void insn_br (i860s *cpustate, UINT32 insn) /* Execute "bri isrc1ni" instruction. Note: I didn't merge this code with calli because bri must do a lot of flag manipulation if any trap bits are set. */ -static void insn_bri (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_bri (UINT32 insn) { UINT32 isrc1 = get_isrc1 (insn); - UINT32 orig_pc = cpustate->pc; - UINT32 orig_psr = cpustate->cregs[CR_PSR]; + UINT32 orig_pc = m_pc; + UINT32 orig_psr = m_cregs[CR_PSR]; UINT32 orig_src1_val = get_iregval (isrc1); #if 1 /* TURBO. */ - cpustate->cregs[CR_PSR] &= ~PSR_ALL_TRAP_BITS_MASK; + m_cregs[CR_PSR] &= ~PSR_ALL_TRAP_BITS_MASK; #endif /* Execute the delay slot instruction. */ - cpustate->pc += 4; - decode_exec (cpustate, ifetch (cpustate, orig_pc + 4), 0); - cpustate->pc = orig_pc; + m_pc += 4; + decode_exec (ifetch (orig_pc + 4), 0); + m_pc = orig_pc; /* Delay slot insn caused a trap, abort operation. */ - if (cpustate->pending_trap) + if (m_pending_trap) { - cpustate->pending_trap |= TRAP_IN_DELAY_SLOT; + m_pending_trap |= TRAP_IN_DELAY_SLOT; goto ab_op; } @@ -2512,21 +2496,21 @@ static void insn_bri (i860s *cpustate, UINT32 insn) SET_PSR_U (GET_PSR_PU ()); SET_PSR_IM (GET_PSR_PIM ()); - cpustate->fir_gets_trap_addr = 0; + m_fir_gets_trap_addr = 0; } /* Update PC. */ - cpustate->pc = orig_src1_val; + m_pc = orig_src1_val; - cpustate->pc_updated = 1; + m_pc_updated = 1; ab_op:; } /* Execute "calli isrc1ni" instruction. */ -static void insn_calli (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_calli (UINT32 insn) { UINT32 isrc1 = get_isrc1 (insn); - UINT32 orig_pc = cpustate->pc; + UINT32 orig_pc = m_pc; UINT32 orig_src1_val = get_iregval (isrc1); #ifdef TRACE_UNDEFINED_I860 @@ -2534,41 +2518,41 @@ static void insn_calli (i860s *cpustate, UINT32 insn) if (isrc1 == 1) { /* Src1 must not be r1. */ - fprintf (stderr, "WARNING: insn_calli (pc=0x%08x): isrc1 = r1 on a calli\n", cpustate->pc); + fprintf (stderr, "WARNING: insn_calli (pc=0x%08x): isrc1 = r1 on a calli\n", m_pc); } #endif /* Set return pointer before executing delay slot instruction. */ - set_iregval (1, cpustate->pc + 8); + set_iregval (1, m_pc + 8); /* Execute the delay slot instruction. */ - cpustate->pc += 4; - decode_exec (cpustate, ifetch (cpustate, orig_pc + 4), 0); - cpustate->pc = orig_pc; - if (cpustate->pending_trap) + m_pc += 4; + decode_exec (ifetch (orig_pc + 4), 0); + m_pc = orig_pc; + if (m_pending_trap) { set_iregval (1, orig_src1_val); - cpustate->pending_trap |= TRAP_IN_DELAY_SLOT; + m_pending_trap |= TRAP_IN_DELAY_SLOT; goto ab_op; } /* Set new PC. */ - cpustate->pc = orig_src1_val; - cpustate->pc_updated = 1; + m_pc = orig_src1_val; + m_pc_updated = 1; ab_op:; } /* Execute "bla isrc1ni,isrc2,sbroff" instruction. */ -static void insn_bla (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_bla (UINT32 insn) { UINT32 isrc1 = get_isrc1 (insn); UINT32 isrc2 = get_isrc2 (insn); UINT32 target_addr = 0; INT32 sbroff = 0; int lcc_tmp = 0; - UINT32 orig_pc = cpustate->pc; + UINT32 orig_pc = m_pc; UINT32 orig_isrc2val = get_iregval (isrc2); #ifdef TRACE_UNDEFINED_I860 @@ -2576,14 +2560,14 @@ static void insn_bla (i860s *cpustate, UINT32 insn) if (isrc1 == isrc2) { /* Src1 and src2 the same is undefined i860XR behavior. */ - fprintf (stderr, "WARNING: insn_bla (pc=0x%08x): isrc1 and isrc2 are the same (ignored)\n", cpustate->pc); + fprintf (stderr, "WARNING: insn_bla (pc=0x%08x): isrc1 and isrc2 are the same (ignored)\n", m_pc); return; } #endif /* Compute the target address from the sbroff field. */ sbroff = sign_ext ((((insn >> 5) & 0xf800) | (insn & 0x07ff)), 16); - target_addr = (INT32)cpustate->pc + 4 + (sbroff << 2); + target_addr = (INT32)m_pc + 4 + (sbroff << 2); /* Determine comparison result based on opcode. */ lcc_tmp = ((INT32)get_iregval (isrc2) >= -(INT32)get_iregval (isrc1)); @@ -2591,32 +2575,32 @@ static void insn_bla (i860s *cpustate, UINT32 insn) set_iregval (isrc2, get_iregval (isrc1) + orig_isrc2val); /* Execute the delay slot instruction. */ - cpustate->pc += 4; - decode_exec (cpustate, ifetch (cpustate, orig_pc + 4), 0); - cpustate->pc = orig_pc; - if (cpustate->pending_trap) + m_pc += 4; + decode_exec (ifetch (orig_pc + 4), 0); + m_pc = orig_pc; + if (m_pending_trap) { - cpustate->pending_trap |= TRAP_IN_DELAY_SLOT; + m_pending_trap |= TRAP_IN_DELAY_SLOT; goto ab_op; } if (GET_PSR_LCC ()) - cpustate->pc = target_addr; + m_pc = target_addr; else { /* Since this branch is delayed, we must jump 2 instructions if if isn't taken. */ - cpustate->pc += 8; + m_pc += 8; } SET_PSR_LCC (lcc_tmp); - cpustate->pc_updated = 1; + m_pc_updated = 1; ab_op:; } /* Execute "flush #const(isrc2)" or "flush #const(isrc2)++" instruction. */ -static void insn_flush (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_flush (UINT32 insn) { UINT32 src1val = sign_ext (get_imm16 (insn), 16); UINT32 isrc2 = get_isrc2 (insn); @@ -2654,7 +2638,7 @@ static void insn_flush (i860s *cpustate, UINT32 insn) The pfmul3.dd differs from pfmul.dd in that it treats the pipeline as 3 stages, even though it is a double precision multiply. */ -static void insn_fmul (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_fmul (UINT32 insn) { UINT32 fsrc1 = get_fsrc1 (insn); UINT32 fsrc2 = get_fsrc2 (insn); @@ -2672,14 +2656,14 @@ static void insn_fmul (i860s *cpustate, UINT32 insn) /* Only .dd is valid for pfmul. */ if (is_pfmul3 && (insn & 0x180) != 0x180) { - unrecog_opcode (cpustate->pc, insn); + unrecog_opcode (m_pc, insn); return; } /* Check for invalid .ds combination. */ if ((insn & 0x180) == 0x100) { - unrecog_opcode (cpustate->pc, insn); + unrecog_opcode (m_pc, insn); return; } @@ -2690,18 +2674,18 @@ static void insn_fmul (i860s *cpustate, UINT32 insn) operation. */ if (piped) { - if (cpustate->M[num_stages - 1].stat.mrp) - dbl_last_stage_contents = cpustate->M[num_stages - 1].val.d; + if (m_M[num_stages - 1].stat.mrp) + dbl_last_stage_contents = m_M[num_stages - 1].val.d; else - sgl_last_stage_contents = cpustate->M[num_stages - 1].val.s; + sgl_last_stage_contents = m_M[num_stages - 1].val.s; } /* Do the operation, being careful about source and result precision. */ if (src_prec) { - double v1 = get_fregval_d (cpustate, fsrc1); - double v2 = get_fregval_d (cpustate, fsrc2); + double v1 = get_fregval_d (fsrc1); + double v2 = get_fregval_d (fsrc2); /* For pipelined mul, if fsrc2 is the same as fdest, then the last stage is bypassed to fsrc2 (rather than using the value in fsrc2). @@ -2718,8 +2702,8 @@ static void insn_fmul (i860s *cpustate, UINT32 insn) } else { - float v1 = get_fregval_s (cpustate, fsrc1); - float v2 = get_fregval_s (cpustate, fsrc2); + float v1 = get_fregval_s (fsrc1); + float v2 = get_fregval_s (fsrc2); /* For pipelined mul, if fsrc2 is the same as fdest, then the last stage is bypassed to fsrc2 (rather than using the value in fsrc2). @@ -2744,9 +2728,9 @@ static void insn_fmul (i860s *cpustate, UINT32 insn) /* Scalar version writes the current calculation to the fdest register, with precision specified by the R bit. */ if (res_prec) - set_fregval_d (cpustate, fdest, dbl_tmp_dest); + set_fregval_d (fdest, dbl_tmp_dest); else - set_fregval_s (cpustate, fdest, sgl_tmp_dest); + set_fregval_s (fdest, sgl_tmp_dest); } else { @@ -2754,50 +2738,50 @@ static void insn_fmul (i860s *cpustate, UINT32 insn) stage of the pipeline. */ #if 1 /* FIXME: WIP on FSR update. This may not be correct. */ /* Copy 3rd stage MRP to FSR. */ - if (cpustate->M[num_stages - 2 /* 1 */].stat.mrp) - cpustate->cregs[CR_FSR] |= 0x10000000; + if (m_M[num_stages - 2 /* 1 */].stat.mrp) + m_cregs[CR_FSR] |= 0x10000000; else - cpustate->cregs[CR_FSR] &= ~0x10000000; + m_cregs[CR_FSR] &= ~0x10000000; #endif - if (cpustate->M[num_stages - 1].stat.mrp) - set_fregval_d (cpustate, fdest, dbl_last_stage_contents); + if (m_M[num_stages - 1].stat.mrp) + set_fregval_d (fdest, dbl_last_stage_contents); else - set_fregval_s (cpustate, fdest, sgl_last_stage_contents); + set_fregval_s (fdest, sgl_last_stage_contents); /* Now advance pipeline and write current calculation to first stage. */ if (num_stages == 3) { - cpustate->M[2] = cpustate->M[1]; - cpustate->M[1] = cpustate->M[0]; + m_M[2] = m_M[1]; + m_M[1] = m_M[0]; } else - cpustate->M[1] = cpustate->M[0]; + m_M[1] = m_M[0]; if (res_prec) { - cpustate->M[0].val.d = dbl_tmp_dest; - cpustate->M[0].stat.mrp = 1; + m_M[0].val.d = dbl_tmp_dest; + m_M[0].stat.mrp = 1; } else { - cpustate->M[0].val.s = sgl_tmp_dest; - cpustate->M[0].stat.mrp = 0; + m_M[0].val.s = sgl_tmp_dest; + m_M[0].stat.mrp = 0; } } } /* Execute "fmlow.dd fsrc1,fsrc2,fdest" instruction. */ -static void insn_fmlow (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_fmlow (UINT32 insn) { UINT32 fsrc1 = get_fsrc1 (insn); UINT32 fsrc2 = get_fsrc2 (insn); UINT32 fdest = get_fdest (insn); - double v1 = get_fregval_d (cpustate, fsrc1); - double v2 = get_fregval_d (cpustate, fsrc2); + double v1 = get_fregval_d (fsrc1); + double v2 = get_fregval_d (fsrc2); INT64 i1 = *(UINT64 *)&v1; INT64 i2 = *(UINT64 *)&v2; INT64 tmp = 0; @@ -2805,7 +2789,7 @@ static void insn_fmlow (i860s *cpustate, UINT32 insn) /* Only .dd is valid for fmlow. */ if ((insn & 0x180) != 0x180) { - unrecog_opcode (cpustate->pc, insn); + unrecog_opcode (m_pc, insn); return; } @@ -2818,12 +2802,12 @@ static void insn_fmlow (i860s *cpustate, UINT32 insn) tmp = i1 * i2; tmp &= 0x001fffffffffffffULL; tmp |= (i1 & 0x8000000000000000LL) ^ (i2 & 0x8000000000000000LL); - set_fregval_d (cpustate, fdest, *(double *)&tmp); + set_fregval_d (fdest, *(double *)&tmp); } /* Execute [p]fadd.{ss,sd,dd} fsrc1,fsrc2,fdest (.ds disallowed above). */ -static void insn_fadd_sub (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_fadd_sub (UINT32 insn) { UINT32 fsrc1 = get_fsrc1 (insn); UINT32 fsrc2 = get_fsrc2 (insn); @@ -2840,7 +2824,7 @@ static void insn_fadd_sub (i860s *cpustate, UINT32 insn) /* Check for invalid .ds combination. */ if ((insn & 0x180) == 0x100) { - unrecog_opcode (cpustate->pc, insn); + unrecog_opcode (m_pc, insn); return; } @@ -2850,18 +2834,18 @@ static void insn_fadd_sub (i860s *cpustate, UINT32 insn) for pfadd/pfsub. */ if (piped) { - if (cpustate->A[2].stat.arp) - dbl_last_stage_contents = cpustate->A[2].val.d; + if (m_A[2].stat.arp) + dbl_last_stage_contents = m_A[2].val.d; else - sgl_last_stage_contents = cpustate->A[2].val.s; + sgl_last_stage_contents = m_A[2].val.s; } /* Do the operation, being careful about source and result precision. */ if (src_prec) { - double v1 = get_fregval_d (cpustate, fsrc1); - double v2 = get_fregval_d (cpustate, fsrc2); + double v1 = get_fregval_d (fsrc1); + double v2 = get_fregval_d (fsrc2); /* For pipelined add/sub, if fsrc1 is the same as fdest, then the last stage is bypassed to fsrc1 (rather than using the value in fsrc1). @@ -2878,8 +2862,8 @@ static void insn_fadd_sub (i860s *cpustate, UINT32 insn) } else { - float v1 = get_fregval_s (cpustate, fsrc1); - float v2 = get_fregval_s (cpustate, fsrc2); + float v1 = get_fregval_s (fsrc1); + float v2 = get_fregval_s (fsrc2); /* For pipelined add/sub, if fsrc1 is the same as fdest, then the last stage is bypassed to fsrc1 (rather than using the value in fsrc1). @@ -2903,9 +2887,9 @@ static void insn_fadd_sub (i860s *cpustate, UINT32 insn) /* Scalar version writes the current calculation to the fdest register, with precision specified by the R bit. */ if (res_prec) - set_fregval_d (cpustate, fdest, dbl_tmp_dest); + set_fregval_d (fdest, dbl_tmp_dest); else - set_fregval_s (cpustate, fdest, sgl_tmp_dest); + set_fregval_s (fdest, sgl_tmp_dest); } else { @@ -2914,29 +2898,29 @@ static void insn_fadd_sub (i860s *cpustate, UINT32 insn) bit of the stage's result-status bits. */ #if 1 /* FIXME: WIP on FSR update. This may not be correct. */ /* Copy 3rd stage ARP to FSR. */ - if (cpustate->A[1 /* 2 */].stat.arp) - cpustate->cregs[CR_FSR] |= 0x20000000; + if (m_A[1 /* 2 */].stat.arp) + m_cregs[CR_FSR] |= 0x20000000; else - cpustate->cregs[CR_FSR] &= ~0x20000000; + m_cregs[CR_FSR] &= ~0x20000000; #endif - if (cpustate->A[2].stat.arp) /* 3rd (last) stage. */ - set_fregval_d (cpustate, fdest, dbl_last_stage_contents); + if (m_A[2].stat.arp) /* 3rd (last) stage. */ + set_fregval_d (fdest, dbl_last_stage_contents); else - set_fregval_s (cpustate, fdest, sgl_last_stage_contents); + set_fregval_s (fdest, sgl_last_stage_contents); /* Now advance pipeline and write current calculation to first stage. */ - cpustate->A[2] = cpustate->A[1]; - cpustate->A[1] = cpustate->A[0]; + m_A[2] = m_A[1]; + m_A[1] = m_A[0]; if (res_prec) { - cpustate->A[0].val.d = dbl_tmp_dest; - cpustate->A[0].stat.arp = 1; + m_A[0].val.d = dbl_tmp_dest; + m_A[0].stat.arp = 1; } else { - cpustate->A[0].val.s = sgl_tmp_dest; - cpustate->A[0].stat.arp = 0; + m_A[0].val.s = sgl_tmp_dest; + m_A[0].stat.arp = 0; } } } @@ -2988,7 +2972,7 @@ static const struct /* 1111 */ { OP_SRC1, OP_SRC2, OP_T, OP_APIPE|FLAGM, 0, 0} }; -static float get_fval_from_optype_s (i860s *cpustate, UINT32 insn, int optype) +float i860_cpu_device::get_fval_from_optype_s (UINT32 insn, int optype) { float retval = 0.0; UINT32 fsrc1 = get_fsrc1 (insn); @@ -2998,26 +2982,26 @@ static float get_fval_from_optype_s (i860s *cpustate, UINT32 insn, int optype) switch (optype) { case OP_SRC1: - retval = get_fregval_s (cpustate, fsrc1); + retval = get_fregval_s (fsrc1); break; case OP_SRC2: - retval = get_fregval_s (cpustate, fsrc2); + retval = get_fregval_s (fsrc2); break; case OP_KI: - retval = cpustate->KI.s; + retval = m_KI.s; break; case OP_KR: - retval = cpustate->KR.s; + retval = m_KR.s; break; case OP_T: - retval = cpustate->T.s; + retval = m_T.s; break; case OP_MPIPE: /* Last stage is 3rd stage for single precision input. */ - retval = cpustate->M[2].val.s; + retval = m_M[2].val.s; break; case OP_APIPE: - retval = cpustate->A[2].val.s; + retval = m_A[2].val.s; break; default: assert (0); @@ -3027,7 +3011,7 @@ static float get_fval_from_optype_s (i860s *cpustate, UINT32 insn, int optype) } -static double get_fval_from_optype_d (i860s *cpustate, UINT32 insn, int optype) +double i860_cpu_device::get_fval_from_optype_d (UINT32 insn, int optype) { double retval = 0.0; UINT32 fsrc1 = get_fsrc1 (insn); @@ -3037,26 +3021,26 @@ static double get_fval_from_optype_d (i860s *cpustate, UINT32 insn, int optype) switch (optype) { case OP_SRC1: - retval = get_fregval_d (cpustate, fsrc1); + retval = get_fregval_d (fsrc1); break; case OP_SRC2: - retval = get_fregval_d (cpustate, fsrc2); + retval = get_fregval_d (fsrc2); break; case OP_KI: - retval = cpustate->KI.d; + retval = m_KI.d; break; case OP_KR: - retval = cpustate->KR.d; + retval = m_KR.d; break; case OP_T: - retval = cpustate->T.d; + retval = m_T.d; break; case OP_MPIPE: /* Last stage is 2nd stage for double precision input. */ - retval = cpustate->M[1].val.d; + retval = m_M[1].val.d; break; case OP_APIPE: - retval = cpustate->A[2].val.d; + retval = m_A[2].val.d; break; default: assert (0); @@ -3076,7 +3060,7 @@ static double get_fval_from_optype_d (i860s *cpustate, UINT32 insn, int optype) floating point operations. The S bit denotes the precision of the multiplication source, while the R bit denotes the precision of the addition source as well as precision of all results. */ -static void insn_dualop (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_dualop (UINT32 insn) { UINT32 fsrc1 = get_fsrc1 (insn); UINT32 fsrc2 = get_fsrc2 (insn); @@ -3106,7 +3090,7 @@ static void insn_dualop (i860s *cpustate, UINT32 insn) /* Check for invalid .ds combination. */ if ((insn & 0x180) == 0x100) { - unrecog_opcode (cpustate->pc, insn); + unrecog_opcode (m_pc, insn); return; } @@ -3115,7 +3099,7 @@ static void insn_dualop (i860s *cpustate, UINT32 insn) /* Check for invalid DPC combination 16 for PFMAM. */ if (dpc == 16) { - unrecog_opcode (cpustate->pc, insn); + unrecog_opcode (m_pc, insn); return; } @@ -3132,23 +3116,23 @@ static void insn_dualop (i860s *cpustate, UINT32 insn) whose precision is specified by the MRP bit of the stage's result- status bits. Note for multiply, the number of stages is determined by the source precision of the current operation. */ - if (cpustate->M[num_mul_stages - 1].stat.mrp) - dbl_last_Mstage_contents = cpustate->M[num_mul_stages - 1].val.d; + if (m_M[num_mul_stages - 1].stat.mrp) + dbl_last_Mstage_contents = m_M[num_mul_stages - 1].val.d; else - sgl_last_Mstage_contents = cpustate->M[num_mul_stages - 1].val.s; + sgl_last_Mstage_contents = m_M[num_mul_stages - 1].val.s; /* Similarly, retrieve the last stage of the adder pipe. */ - if (cpustate->A[2].stat.arp) - dbl_last_Astage_contents = cpustate->A[2].val.d; + if (m_A[2].stat.arp) + dbl_last_Astage_contents = m_A[2].val.d; else - sgl_last_Astage_contents = cpustate->A[2].val.s; + sgl_last_Astage_contents = m_A[2].val.s; /* Do the mul operation, being careful about source and result precision. */ if (src_prec) { - double v1 = get_fval_from_optype_d (cpustate, insn, M_unit_op1); - double v2 = get_fval_from_optype_d (cpustate, insn, M_unit_op2); + double v1 = get_fval_from_optype_d (insn, M_unit_op1); + double v2 = get_fval_from_optype_d (insn, M_unit_op2); /* For mul, if fsrc2 is the same as fdest, then the last stage is bypassed to fsrc2 (rather than using the value in fsrc2). @@ -3165,8 +3149,8 @@ static void insn_dualop (i860s *cpustate, UINT32 insn) } else { - float v1 = get_fval_from_optype_s (cpustate, insn, M_unit_op1); - float v2 = get_fval_from_optype_s (cpustate, insn, M_unit_op2); + float v1 = get_fval_from_optype_s (insn, M_unit_op1); + float v2 = get_fval_from_optype_s (insn, M_unit_op2); /* For mul, if fsrc2 is the same as fdest, then the last stage is bypassed to fsrc2 (rather than using the value in fsrc2). @@ -3187,8 +3171,8 @@ static void insn_dualop (i860s *cpustate, UINT32 insn) here. */ if (res_prec) { - double v1 = get_fval_from_optype_d (cpustate, insn, A_unit_op1); - double v2 = get_fval_from_optype_d (cpustate, insn, A_unit_op2); + double v1 = get_fval_from_optype_d (insn, A_unit_op1); + double v2 = get_fval_from_optype_d (insn, A_unit_op2); /* For add/sub, if fsrc1 is the same as fdest, then the last stage is bypassed to fsrc1 (rather than using the value in fsrc1). @@ -3205,8 +3189,8 @@ static void insn_dualop (i860s *cpustate, UINT32 insn) } else { - float v1 = get_fval_from_optype_s (cpustate, insn, A_unit_op1); - float v2 = get_fval_from_optype_s (cpustate, insn, A_unit_op2); + float v1 = get_fval_from_optype_s (insn, A_unit_op1); + float v2 = get_fval_from_optype_s (insn, A_unit_op2); /* For add/sub, if fsrc1 is the same as fdest, then the last stage is bypassed to fsrc1 (rather than using the value in fsrc1). @@ -3226,10 +3210,10 @@ static void insn_dualop (i860s *cpustate, UINT32 insn) if (T_loaded) { /* T is loaded from the result of the last stage of the multiplier. */ - if (cpustate->M[num_mul_stages - 1].stat.mrp) - cpustate->T.d = dbl_last_Mstage_contents; + if (m_M[num_mul_stages - 1].stat.mrp) + m_T.d = dbl_last_Mstage_contents; else - cpustate->T.s = sgl_last_Mstage_contents; + m_T.s = sgl_last_Mstage_contents; } /* If necessary, load KR or KI. */ @@ -3239,16 +3223,16 @@ static void insn_dualop (i860s *cpustate, UINT32 insn) if (M_unit_op1 == OP_KI) { if (src_prec) - cpustate->KI.d = get_fregval_d (cpustate, fsrc1); + m_KI.d = get_fregval_d (fsrc1); else - cpustate->KI.s = get_fregval_s (cpustate, fsrc1); + m_KI.s = get_fregval_s (fsrc1); } else if (M_unit_op1 == OP_KR) { if (src_prec) - cpustate->KR.d = get_fregval_d (cpustate, fsrc1); + m_KR.d = get_fregval_d (fsrc1); else - cpustate->KR.s = get_fregval_s (cpustate, fsrc1); + m_KR.s = get_fregval_s (fsrc1); } else assert (0); @@ -3261,20 +3245,20 @@ static void insn_dualop (i860s *cpustate, UINT32 insn) /* Update fdest with the result from the last stage of the adder pipeline, with precision specified by the ARP bit of the stage's result-status bits. */ - if (cpustate->A[2].stat.arp) - set_fregval_d (cpustate, fdest, dbl_last_Astage_contents); + if (m_A[2].stat.arp) + set_fregval_d (fdest, dbl_last_Astage_contents); else - set_fregval_s (cpustate, fdest, sgl_last_Astage_contents); + set_fregval_s (fdest, sgl_last_Astage_contents); } else { /* Update fdest with the result from the last stage of the multiplier pipeline, with precision specified by the MRP bit of the stage's result-status bits. */ - if (cpustate->M[num_mul_stages - 1].stat.mrp) - set_fregval_d (cpustate, fdest, dbl_last_Mstage_contents); + if (m_M[num_mul_stages - 1].stat.mrp) + set_fregval_d (fdest, dbl_last_Mstage_contents); else - set_fregval_s (cpustate, fdest, sgl_last_Mstage_contents); + set_fregval_s (fdest, sgl_last_Mstage_contents); } /* FIXME: Set result-status bits besides MRP. And copy to fsr from @@ -3282,62 +3266,62 @@ static void insn_dualop (i860s *cpustate, UINT32 insn) /* FIXME: Mixed precision (only weird for pfmul). */ #if 1 /* FIXME: WIP on FSR update. This may not be correct. */ /* Copy 3rd stage MRP to FSR. */ - if (cpustate->M[num_mul_stages - 2 /* 1 */].stat.mrp) - cpustate->cregs[CR_FSR] |= 0x10000000; + if (m_M[num_mul_stages - 2 /* 1 */].stat.mrp) + m_cregs[CR_FSR] |= 0x10000000; else - cpustate->cregs[CR_FSR] &= ~0x10000000; + m_cregs[CR_FSR] &= ~0x10000000; #endif /* Now advance multiplier pipeline and write current calculation to first stage. */ if (num_mul_stages == 3) { - cpustate->M[2] = cpustate->M[1]; - cpustate->M[1] = cpustate->M[0]; + m_M[2] = m_M[1]; + m_M[1] = m_M[0]; } else - cpustate->M[1] = cpustate->M[0]; + m_M[1] = m_M[0]; if (res_prec) { - cpustate->M[0].val.d = dbl_tmp_dest_mul; - cpustate->M[0].stat.mrp = 1; + m_M[0].val.d = dbl_tmp_dest_mul; + m_M[0].stat.mrp = 1; } else { - cpustate->M[0].val.s = sgl_tmp_dest_mul; - cpustate->M[0].stat.mrp = 0; + m_M[0].val.s = sgl_tmp_dest_mul; + m_M[0].stat.mrp = 0; } /* FIXME: Set result-status bits besides ARP. And copy to fsr from last stage. */ #if 1 /* FIXME: WIP on FSR update. This may not be correct. */ /* Copy 3rd stage ARP to FSR. */ - if (cpustate->A[1 /* 2 */].stat.arp) - cpustate->cregs[CR_FSR] |= 0x20000000; + if (m_A[1 /* 2 */].stat.arp) + m_cregs[CR_FSR] |= 0x20000000; else - cpustate->cregs[CR_FSR] &= ~0x20000000; + m_cregs[CR_FSR] &= ~0x20000000; #endif /* Now advance adder pipeline and write current calculation to first stage. */ - cpustate->A[2] = cpustate->A[1]; - cpustate->A[1] = cpustate->A[0]; + m_A[2] = m_A[1]; + m_A[1] = m_A[0]; if (res_prec) { - cpustate->A[0].val.d = dbl_tmp_dest_add; - cpustate->A[0].stat.arp = 1; + m_A[0].val.d = dbl_tmp_dest_add; + m_A[0].stat.arp = 1; } else { - cpustate->A[0].val.s = sgl_tmp_dest_add; - cpustate->A[0].stat.arp = 0; + m_A[0].val.s = sgl_tmp_dest_add; + m_A[0].stat.arp = 0; } } /* Execute frcp.{ss,sd,dd} fsrc2,fdest (.ds disallowed above). */ -static void insn_frcp (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_frcp (UINT32 insn) { UINT32 fsrc2 = get_fsrc2 (insn); UINT32 fdest = get_fdest (insn); @@ -3348,7 +3332,7 @@ static void insn_frcp (i860s *cpustate, UINT32 insn) precision. */ if (src_prec) { - double v = get_fregval_d (cpustate, fsrc2); + double v = get_fregval_d (fsrc2); double res; if (v == (double)0.0) { @@ -3357,7 +3341,7 @@ static void insn_frcp (i860s *cpustate, UINT32 insn) { SET_PSR_FT (1); SET_FSR_SE (1); - cpustate->pending_trap = GET_FSR_FTE (); + m_pending_trap = GET_FSR_FTE (); } /* Set fdest to INF or some other exceptional value here? */ } @@ -3370,14 +3354,14 @@ static void insn_frcp (i860s *cpustate, UINT32 insn) res = (double)1.0/v; *((UINT64 *)&res) &= 0xfffff00000000000ULL; if (res_prec) - set_fregval_d (cpustate, fdest, res); + set_fregval_d (fdest, res); else - set_fregval_s (cpustate, fdest, (float)res); + set_fregval_s (fdest, (float)res); } } else { - float v = get_fregval_s (cpustate, fsrc2); + float v = get_fregval_s (fsrc2); float res; if (v == 0.0) { @@ -3386,7 +3370,7 @@ static void insn_frcp (i860s *cpustate, UINT32 insn) { SET_PSR_FT (1); SET_FSR_SE (1); - cpustate->pending_trap = GET_FSR_FTE (); + m_pending_trap = GET_FSR_FTE (); } /* Set fdest to INF or some other exceptional value here? */ } @@ -3399,16 +3383,16 @@ static void insn_frcp (i860s *cpustate, UINT32 insn) res = (float)1.0/v; *((UINT32 *)&res) &= 0xffff8000; if (res_prec) - set_fregval_d (cpustate, fdest, (double)res); + set_fregval_d (fdest, (double)res); else - set_fregval_s (cpustate, fdest, res); + set_fregval_s (fdest, res); } } } /* Execute frsqr.{ss,sd,dd} fsrc2,fdest (.ds disallowed above). */ -static void insn_frsqr (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_frsqr (UINT32 insn) { UINT32 fsrc2 = get_fsrc2 (insn); UINT32 fdest = get_fdest (insn); @@ -3418,14 +3402,14 @@ static void insn_frsqr (i860s *cpustate, UINT32 insn) /* Check for invalid .ds combination. */ if ((insn & 0x180) == 0x100) { - unrecog_opcode (cpustate->pc, insn); + unrecog_opcode (m_pc, insn); return; } /* Check for invalid .ds combination. */ if ((insn & 0x180) == 0x100) { - unrecog_opcode (cpustate->pc, insn); + unrecog_opcode (m_pc, insn); return; } @@ -3433,7 +3417,7 @@ static void insn_frsqr (i860s *cpustate, UINT32 insn) precision. */ if (src_prec) { - double v = get_fregval_d (cpustate, fsrc2); + double v = get_fregval_d (fsrc2); double res; if (v == 0.0 || v < 0.0) { @@ -3442,7 +3426,7 @@ static void insn_frsqr (i860s *cpustate, UINT32 insn) { SET_PSR_FT (1); SET_FSR_SE (1); - cpustate->pending_trap = GET_FSR_FTE (); + m_pending_trap = GET_FSR_FTE (); } /* Set fdest to INF or some other exceptional value here? */ } @@ -3453,14 +3437,14 @@ static void insn_frsqr (i860s *cpustate, UINT32 insn) res = (double)1.0/sqrt (v); *((UINT64 *)&res) &= 0xfffff00000000000ULL; if (res_prec) - set_fregval_d (cpustate, fdest, res); + set_fregval_d (fdest, res); else - set_fregval_s (cpustate, fdest, (float)res); + set_fregval_s (fdest, (float)res); } } else { - float v = get_fregval_s (cpustate, fsrc2); + float v = get_fregval_s (fsrc2); float res; if (v == 0.0 || v < 0.0) { @@ -3469,7 +3453,7 @@ static void insn_frsqr (i860s *cpustate, UINT32 insn) { SET_PSR_FT (1); SET_FSR_SE (1); - cpustate->pending_trap = GET_FSR_FTE (); + m_pending_trap = GET_FSR_FTE (); } /* Set fdest to INF or some other exceptional value here? */ } @@ -3480,23 +3464,23 @@ static void insn_frsqr (i860s *cpustate, UINT32 insn) res = (float)1.0/sqrt (v); *((UINT32 *)&res) &= 0xffff8000; if (res_prec) - set_fregval_d (cpustate, fdest, (double)res); + set_fregval_d (fdest, (double)res); else - set_fregval_s (cpustate, fdest, res); + set_fregval_s (fdest, res); } } } /* Execute fxfr fsrc1,idest. */ -static void insn_fxfr (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_fxfr (UINT32 insn) { UINT32 fsrc1 = get_fsrc1 (insn); UINT32 idest = get_idest (insn); float fv = 0; /* This is a bit-pattern transfer, not a conversion. */ - fv = get_fregval_s (cpustate, fsrc1); + fv = get_fregval_s (fsrc1); set_iregval (idest, *(UINT32 *)&fv); } @@ -3509,7 +3493,7 @@ static void insn_fxfr (i860s *cpustate, UINT32 insn) results. Inconsistent. Update: The vendor SVR4 assembler does not accept .ss combination, so the latter sentence above appears to be the correct way. */ -static void insn_ftrunc (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_ftrunc (UINT32 insn) { UINT32 fsrc1 = get_fsrc1 (insn); UINT32 fdest = get_fdest (insn); @@ -3520,7 +3504,7 @@ static void insn_ftrunc (i860s *cpustate, UINT32 insn) /* Check for invalid .ds or .ss combinations. */ if ((insn & 0x080) == 0) { - unrecog_opcode (cpustate->pc, insn); + unrecog_opcode (m_pc, insn); return; } @@ -3529,19 +3513,19 @@ static void insn_ftrunc (i860s *cpustate, UINT32 insn) lower 32-bits. */ if (src_prec) { - double v1 = get_fregval_d (cpustate, fsrc1); + double v1 = get_fregval_d (fsrc1); INT32 iv = (INT32)v1; /* We always write a single, since the lower 32-bits of fdest get the result (and the even numbered reg is the lower). */ - set_fregval_s (cpustate, fdest, *(float *)&iv); + set_fregval_s (fdest, *(float *)&iv); } else { - float v1 = get_fregval_s (cpustate, fsrc1); + float v1 = get_fregval_s (fsrc1); INT32 iv = (INT32)v1; /* We always write a single, since the lower 32-bits of fdest get the result (and the even numbered reg is the lower). */ - set_fregval_s (cpustate, fdest, *(float *)&iv); + set_fregval_s (fdest, *(float *)&iv); } /* FIXME: Handle updating of pipestages for pftrunc. */ @@ -3550,15 +3534,15 @@ static void insn_ftrunc (i860s *cpustate, UINT32 insn) { fprintf (stderr, "insn_ftrunc: FIXME: pipelined not functional yet.\n"); if (res_prec) - set_fregval_d (cpustate, fdest, 0.0); + set_fregval_d (fdest, 0.0); else - set_fregval_s (cpustate, fdest, 0.0); + set_fregval_s (fdest, 0.0); } } /* Execute [p]famov.{ss,sd,ds,dd} fsrc1,fdest. */ -static void insn_famov (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_famov (UINT32 insn) { UINT32 fsrc1 = get_fsrc1 (insn); UINT32 fdest = get_fdest (insn); @@ -3572,7 +3556,7 @@ static void insn_famov (i860s *cpustate, UINT32 insn) precision. */ if (src_prec) { - double v1 = get_fregval_d (cpustate, fsrc1); + double v1 = get_fregval_d (fsrc1); if (res_prec) dbl_tmp_dest = v1; else @@ -3580,7 +3564,7 @@ static void insn_famov (i860s *cpustate, UINT32 insn) } else { - float v1 = get_fregval_s (cpustate, fsrc1); + float v1 = get_fregval_s (fsrc1); if (res_prec) dbl_tmp_dest = (double)v1; else @@ -3595,9 +3579,9 @@ static void insn_famov (i860s *cpustate, UINT32 insn) /* Scalar version writes the current calculation to the fdest register, with precision specified by the R bit. */ if (res_prec) - set_fregval_d (cpustate, fdest, dbl_tmp_dest); + set_fregval_d (fdest, dbl_tmp_dest); else - set_fregval_s (cpustate, fdest, sgl_tmp_dest); + set_fregval_s (fdest, sgl_tmp_dest); } else { @@ -3606,36 +3590,36 @@ static void insn_famov (i860s *cpustate, UINT32 insn) bit of the stage's result-status bits. */ #if 1 /* FIXME: WIP on FSR update. This may not be correct. */ /* Copy 3rd stage ARP to FSR. */ - if (cpustate->A[1 /* 2 */].stat.arp) - cpustate->cregs[CR_FSR] |= 0x20000000; + if (m_A[1 /* 2 */].stat.arp) + m_cregs[CR_FSR] |= 0x20000000; else - cpustate->cregs[CR_FSR] &= ~0x20000000; + m_cregs[CR_FSR] &= ~0x20000000; #endif - if (cpustate->A[2].stat.arp) /* 3rd (last) stage. */ - set_fregval_d (cpustate, fdest, cpustate->A[2].val.d); + if (m_A[2].stat.arp) /* 3rd (last) stage. */ + set_fregval_d (fdest, m_A[2].val.d); else - set_fregval_s (cpustate, fdest, cpustate->A[2].val.s); + set_fregval_s (fdest, m_A[2].val.s); /* Now advance pipeline and write current calculation to first stage. */ - cpustate->A[2] = cpustate->A[1]; - cpustate->A[1] = cpustate->A[0]; + m_A[2] = m_A[1]; + m_A[1] = m_A[0]; if (res_prec) { - cpustate->A[0].val.d = dbl_tmp_dest; - cpustate->A[0].stat.arp = 1; + m_A[0].val.d = dbl_tmp_dest; + m_A[0].stat.arp = 1; } else { - cpustate->A[0].val.s = sgl_tmp_dest; - cpustate->A[0].stat.arp = 0; + m_A[0].val.s = sgl_tmp_dest; + m_A[0].stat.arp = 0; } } } /* Execute [p]fiadd/sub.{ss,dd} fsrc1,fsrc2,fdest. */ -static void insn_fiadd_sub (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_fiadd_sub (UINT32 insn) { UINT32 fsrc1 = get_fsrc1 (insn); UINT32 fsrc2 = get_fsrc2 (insn); @@ -3651,7 +3635,7 @@ static void insn_fiadd_sub (i860s *cpustate, UINT32 insn) if ((insn & 0x180) == 0x100 || (insn & 0x180) == 0x080) { - unrecog_opcode (cpustate->pc, insn); + unrecog_opcode (m_pc, insn); return; } @@ -3659,8 +3643,8 @@ static void insn_fiadd_sub (i860s *cpustate, UINT32 insn) precision. */ if (src_prec) { - double v1 = get_fregval_d (cpustate, fsrc1); - double v2 = get_fregval_d (cpustate, fsrc2); + double v1 = get_fregval_d (fsrc1); + double v2 = get_fregval_d (fsrc2); UINT64 iv1 = *(UINT64 *)&v1; UINT64 iv2 = *(UINT64 *)&v2; UINT64 r; @@ -3675,8 +3659,8 @@ static void insn_fiadd_sub (i860s *cpustate, UINT32 insn) } else { - float v1 = get_fregval_s (cpustate, fsrc1); - float v2 = get_fregval_s (cpustate, fsrc2); + float v1 = get_fregval_s (fsrc1); + float v2 = get_fregval_s (fsrc2); UINT64 iv1 = (UINT64)(*(UINT32 *)&v1); UINT64 iv2 = (UINT64)(*(UINT32 *)&v2); UINT32 r; @@ -3697,9 +3681,9 @@ static void insn_fiadd_sub (i860s *cpustate, UINT32 insn) /* Scalar version writes the current calculation to the fdest register, with precision specified by the R bit. */ if (res_prec) - set_fregval_d (cpustate, fdest, dbl_tmp_dest); + set_fregval_d (fdest, dbl_tmp_dest); else - set_fregval_s (cpustate, fdest, sgl_tmp_dest); + set_fregval_s (fdest, sgl_tmp_dest); } else { @@ -3709,25 +3693,25 @@ static void insn_fiadd_sub (i860s *cpustate, UINT32 insn) #if 1 /* FIXME: WIP on FSR update. This may not be correct. */ /* Copy stage IRP to FSR. */ if (res_prec) - cpustate->cregs[CR_FSR] |= 0x08000000; + m_cregs[CR_FSR] |= 0x08000000; else - cpustate->cregs[CR_FSR] &= ~0x08000000; + m_cregs[CR_FSR] &= ~0x08000000; #endif - if (cpustate->G.stat.irp) /* 1st (and last) stage. */ - set_fregval_d (cpustate, fdest, cpustate->G.val.d); + if (m_G.stat.irp) /* 1st (and last) stage. */ + set_fregval_d (fdest, m_G.val.d); else - set_fregval_s (cpustate, fdest, cpustate->G.val.s); + set_fregval_s (fdest, m_G.val.s); /* Now write current calculation to first and only stage. */ if (res_prec) { - cpustate->G.val.d = dbl_tmp_dest; - cpustate->G.stat.irp = 1; + m_G.val.d = dbl_tmp_dest; + m_G.stat.irp = 1; } else { - cpustate->G.val.s = sgl_tmp_dest; - cpustate->G.stat.irp = 0; + m_G.val.s = sgl_tmp_dest; + m_G.stat.irp = 0; } } } @@ -3735,7 +3719,7 @@ static void insn_fiadd_sub (i860s *cpustate, UINT32 insn) /* Execute pf{gt,le,eq}.{ss,dd} fsrc1,fsrc2,fdest. Opcode pfgt has R bit cleared; pfle has R bit set. */ -static void insn_fcmp (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_fcmp (UINT32 insn) { UINT32 fsrc1 = get_fsrc1 (insn); UINT32 fsrc2 = get_fsrc2 (insn); @@ -3757,8 +3741,8 @@ static void insn_fcmp (i860s *cpustate, UINT32 insn) this by just pushing in dbl_ or sgl_tmp_dest which equal 0.0. */ if (src_prec) { - double v1 = get_fregval_d (cpustate, fsrc1); - double v2 = get_fregval_d (cpustate, fsrc2); + double v1 = get_fregval_d (fsrc1); + double v2 = get_fregval_d (fsrc2); if (is_gt) /* gt. */ SET_PSR_CC (v1 > v2 ? 1 : 0); else if (is_le) /* le. */ @@ -3768,8 +3752,8 @@ static void insn_fcmp (i860s *cpustate, UINT32 insn) } else { - float v1 = get_fregval_s (cpustate, fsrc1); - float v2 = get_fregval_s (cpustate, fsrc2); + float v1 = get_fregval_s (fsrc1); + float v2 = get_fregval_s (fsrc2); if (is_gt) /* gt. */ SET_PSR_CC (v1 > v2 ? 1 : 0); else if (is_le) /* le. */ @@ -3785,36 +3769,36 @@ static void insn_fcmp (i860s *cpustate, UINT32 insn) bit of the stage's result-status bits. */ #if 1 /* FIXME: WIP on FSR update. This may not be correct. */ /* Copy 3rd stage ARP to FSR. */ - if (cpustate->A[1 /* 2 */].stat.arp) - cpustate->cregs[CR_FSR] |= 0x20000000; + if (m_A[1 /* 2 */].stat.arp) + m_cregs[CR_FSR] |= 0x20000000; else - cpustate->cregs[CR_FSR] &= ~0x20000000; + m_cregs[CR_FSR] &= ~0x20000000; #endif - if (cpustate->A[2].stat.arp) /* 3rd (last) stage. */ - set_fregval_d (cpustate, fdest, cpustate->A[2].val.d); + if (m_A[2].stat.arp) /* 3rd (last) stage. */ + set_fregval_d (fdest, m_A[2].val.d); else - set_fregval_s (cpustate, fdest, cpustate->A[2].val.s); + set_fregval_s (fdest, m_A[2].val.s); /* Now advance pipeline and write current calculation to first stage. */ - cpustate->A[2] = cpustate->A[1]; - cpustate->A[1] = cpustate->A[0]; + m_A[2] = m_A[1]; + m_A[1] = m_A[0]; if (src_prec) { - cpustate->A[0].val.d = dbl_tmp_dest; - cpustate->A[0].stat.arp = 1; + m_A[0].val.d = dbl_tmp_dest; + m_A[0].stat.arp = 1; } else { - cpustate->A[0].val.s = sgl_tmp_dest; - cpustate->A[0].stat.arp = 0; + m_A[0].val.s = sgl_tmp_dest; + m_A[0].stat.arp = 0; } } /* Execute [p]fzchk{l,s} fsrc1,fsrc2,fdest. The fzchk instructions have S and R bits set. */ -static void insn_fzchk (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_fzchk (UINT32 insn) { UINT32 fsrc1 = get_fsrc1 (insn); UINT32 fsrc2 = get_fsrc2 (insn); @@ -3823,8 +3807,8 @@ static void insn_fzchk (i860s *cpustate, UINT32 insn) int is_fzchks = insn & 8; /* 1 = fzchks, 0 = fzchkl. */ double dbl_tmp_dest = 0.0; int i; - double v1 = get_fregval_d (cpustate, fsrc1); - double v2 = get_fregval_d (cpustate, fsrc2); + double v1 = get_fregval_d (fsrc1); + double v2 = get_fregval_d (fsrc2); UINT64 iv1 = *(UINT64 *)&v1; UINT64 iv2 = *(UINT64 *)&v2; UINT64 r = 0; @@ -3833,7 +3817,7 @@ static void insn_fzchk (i860s *cpustate, UINT32 insn) /* Check for S and R bits set. */ if ((insn & 0x180) != 0x180) { - unrecog_opcode (cpustate->pc, insn); + unrecog_opcode (m_pc, insn); return; } @@ -3881,7 +3865,7 @@ static void insn_fzchk (i860s *cpustate, UINT32 insn) dbl_tmp_dest = *(double *)&r; SET_PSR_PM (pm); - cpustate->merge = 0; + m_merge = 0; /* FIXME: Copy result-status bit IRP to fsr from last stage. */ /* FIXME: Scalar version flows through all stages. */ @@ -3889,46 +3873,46 @@ static void insn_fzchk (i860s *cpustate, UINT32 insn) { /* Scalar version writes the current calculation to the fdest register, always with double precision. */ - set_fregval_d (cpustate, fdest, dbl_tmp_dest); + set_fregval_d (fdest, dbl_tmp_dest); } else { /* Pipelined version writes fdest with the result from the last stage of the pipeline, with precision specified by the IRP bit of the stage's result-status bits. */ - if (cpustate->G.stat.irp) /* 1st (and last) stage. */ - set_fregval_d (cpustate, fdest, cpustate->G.val.d); + if (m_G.stat.irp) /* 1st (and last) stage. */ + set_fregval_d (fdest, m_G.val.d); else - set_fregval_s (cpustate, fdest, cpustate->G.val.s); + set_fregval_s (fdest, m_G.val.s); /* Now write current calculation to first and only stage. */ - cpustate->G.val.d = dbl_tmp_dest; - cpustate->G.stat.irp = 1; + m_G.val.d = dbl_tmp_dest; + m_G.stat.irp = 1; } } /* Execute [p]form.dd fsrc1,fdest. The form.dd instructions have S and R bits set. */ -static void insn_form (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_form (UINT32 insn) { UINT32 fsrc1 = get_fsrc1 (insn); UINT32 fdest = get_fdest (insn); int piped = insn & 0x400; /* 1 = pipelined, 0 = scalar. */ double dbl_tmp_dest = 0.0; - double v1 = get_fregval_d (cpustate, fsrc1); + double v1 = get_fregval_d (fsrc1); UINT64 iv1 = *(UINT64 *)&v1; /* Check for S and R bits set. */ if ((insn & 0x180) != 0x180) { - unrecog_opcode (cpustate->pc, insn); + unrecog_opcode (m_pc, insn); return; } - iv1 |= cpustate->merge; + iv1 |= m_merge; dbl_tmp_dest = *(double *)&iv1; - cpustate->merge = 0; + m_merge = 0; /* FIXME: Copy result-status bit IRP to fsr from last stage. */ /* FIXME: Scalar version flows through all stages. */ @@ -3936,35 +3920,35 @@ static void insn_form (i860s *cpustate, UINT32 insn) { /* Scalar version writes the current calculation to the fdest register, always with double precision. */ - set_fregval_d (cpustate, fdest, dbl_tmp_dest); + set_fregval_d (fdest, dbl_tmp_dest); } else { /* Pipelined version writes fdest with the result from the last stage of the pipeline, with precision specified by the IRP bit of the stage's result-status bits. */ - if (cpustate->G.stat.irp) /* 1st (and last) stage. */ - set_fregval_d (cpustate, fdest, cpustate->G.val.d); + if (m_G.stat.irp) /* 1st (and last) stage. */ + set_fregval_d (fdest, m_G.val.d); else - set_fregval_s (cpustate, fdest, cpustate->G.val.s); + set_fregval_s (fdest, m_G.val.s); /* Now write current calculation to first and only stage. */ - cpustate->G.val.d = dbl_tmp_dest; - cpustate->G.stat.irp = 1; + m_G.val.d = dbl_tmp_dest; + m_G.stat.irp = 1; } } /* Execute [p]faddp fsrc1,fsrc2,fdest. */ -static void insn_faddp (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_faddp (UINT32 insn) { UINT32 fsrc1 = get_fsrc1 (insn); UINT32 fsrc2 = get_fsrc2 (insn); UINT32 fdest = get_fdest (insn); int piped = insn & 0x400; /* 1 = pipelined, 0 = scalar. */ double dbl_tmp_dest = 0.0; - double v1 = get_fregval_d (cpustate, fsrc1); - double v2 = get_fregval_d (cpustate, fsrc2); + double v1 = get_fregval_d (fsrc1); + double v2 = get_fregval_d (fsrc2); UINT64 iv1 = *(UINT64 *)&v1; UINT64 iv2 = *(UINT64 *)&v2; UINT64 r = 0; @@ -3977,18 +3961,18 @@ static void insn_faddp (i860s *cpustate, UINT32 insn) PS: 0 = 8 bits, 1 = 16 bits, 2 = 32-bits. */ if (ps == 0) { - cpustate->merge = ((cpustate->merge >> 8) & ~0xff00ff00ff00ff00ULL); - cpustate->merge |= (r & 0xff00ff00ff00ff00ULL); + m_merge = ((m_merge >> 8) & ~0xff00ff00ff00ff00ULL); + m_merge |= (r & 0xff00ff00ff00ff00ULL); } else if (ps == 1) { - cpustate->merge = ((cpustate->merge >> 6) & ~0xfc00fc00fc00fc00ULL); - cpustate->merge |= (r & 0xfc00fc00fc00fc00ULL); + m_merge = ((m_merge >> 6) & ~0xfc00fc00fc00fc00ULL); + m_merge |= (r & 0xfc00fc00fc00fc00ULL); } else if (ps == 2) { - cpustate->merge = ((cpustate->merge >> 8) & ~0xff000000ff000000ULL); - cpustate->merge |= (r & 0xff000000ff000000ULL); + m_merge = ((m_merge >> 8) & ~0xff000000ff000000ULL); + m_merge |= (r & 0xff000000ff000000ULL); } #ifdef TRACE_UNDEFINED_I860 else @@ -4001,35 +3985,35 @@ static void insn_faddp (i860s *cpustate, UINT32 insn) { /* Scalar version writes the current calculation to the fdest register, always with double precision. */ - set_fregval_d (cpustate, fdest, dbl_tmp_dest); + set_fregval_d (fdest, dbl_tmp_dest); } else { /* Pipelined version writes fdest with the result from the last stage of the pipeline, with precision specified by the IRP bit of the stage's result-status bits. */ - if (cpustate->G.stat.irp) /* 1st (and last) stage. */ - set_fregval_d (cpustate, fdest, cpustate->G.val.d); + if (m_G.stat.irp) /* 1st (and last) stage. */ + set_fregval_d (fdest, m_G.val.d); else - set_fregval_s (cpustate, fdest, cpustate->G.val.s); + set_fregval_s (fdest, m_G.val.s); /* Now write current calculation to first and only stage. */ - cpustate->G.val.d = dbl_tmp_dest; - cpustate->G.stat.irp = 1; + m_G.val.d = dbl_tmp_dest; + m_G.stat.irp = 1; } } /* Execute [p]faddz fsrc1,fsrc2,fdest. */ -static void insn_faddz (i860s *cpustate, UINT32 insn) +void i860_cpu_device::insn_faddz (UINT32 insn) { UINT32 fsrc1 = get_fsrc1 (insn); UINT32 fsrc2 = get_fsrc2 (insn); UINT32 fdest = get_fdest (insn); int piped = insn & 0x400; /* 1 = pipelined, 0 = scalar. */ double dbl_tmp_dest = 0.0; - double v1 = get_fregval_d (cpustate, fsrc1); - double v2 = get_fregval_d (cpustate, fsrc2); + double v1 = get_fregval_d (fsrc1); + double v2 = get_fregval_d (fsrc2); UINT64 iv1 = *(UINT64 *)&v1; UINT64 iv2 = *(UINT64 *)&v2; UINT64 r = 0; @@ -4038,8 +4022,8 @@ static void insn_faddz (i860s *cpustate, UINT32 insn) dbl_tmp_dest = *(double *)&r; /* Update the merge register depending on the pixel size. */ - cpustate->merge = ((cpustate->merge >> 16) & ~0xffff0000ffff0000ULL); - cpustate->merge |= (r & 0xffff0000ffff0000ULL); + m_merge = ((m_merge >> 16) & ~0xffff0000ffff0000ULL); + m_merge |= (r & 0xffff0000ffff0000ULL); /* FIXME: Copy result-status bit IRP to fsr from last stage. */ /* FIXME: Scalar version flows through all stages. */ @@ -4047,21 +4031,21 @@ static void insn_faddz (i860s *cpustate, UINT32 insn) { /* Scalar version writes the current calculation to the fdest register, always with double precision. */ - set_fregval_d (cpustate, fdest, dbl_tmp_dest); + set_fregval_d (fdest, dbl_tmp_dest); } else { /* Pipelined version writes fdest with the result from the last stage of the pipeline, with precision specified by the IRP bit of the stage's result-status bits. */ - if (cpustate->G.stat.irp) /* 1st (and last) stage. */ - set_fregval_d (cpustate, fdest, cpustate->G.val.d); + if (m_G.stat.irp) /* 1st (and last) stage. */ + set_fregval_d (fdest, m_G.val.d); else - set_fregval_s (cpustate, fdest, cpustate->G.val.s); + set_fregval_s (fdest, m_G.val.s); /* Now write current calculation to first and only stage. */ - cpustate->G.val.d = dbl_tmp_dest; - cpustate->G.stat.irp = 1; + m_G.val.d = dbl_tmp_dest; + m_G.stat.irp = 1; } } @@ -4073,94 +4057,85 @@ enum { }; -struct decode_tbl_t { - /* Execute function for this opcode. */ - void (*insn_exec)(i860s *, UINT32); - - /* Flags for this opcode. */ - char flags; -}; - - /* First-level decode table (i.e., for the 6 primary opcode bits). */ -static const decode_tbl_t decode_tbl[64] = { +const i860_cpu_device::decode_tbl_t i860_cpu_device::decode_tbl[64] = { /* A slight bit of decoding for loads and stores is done in the execution routines (operand size and addressing mode), which is why their respective entries are identical. */ - { insn_ldx, DEC_DECODED}, /* ld.b isrc1(isrc2),idest. */ - { insn_ldx, DEC_DECODED}, /* ld.b #const(isrc2),idest. */ - { insn_ixfr, DEC_DECODED}, /* ixfr isrc1ni,fdest. */ - { insn_stx, DEC_DECODED}, /* st.b isrc1ni,#const(isrc2). */ - { insn_ldx, DEC_DECODED}, /* ld.{s,l} isrc1(isrc2),idest. */ - { insn_ldx, DEC_DECODED}, /* ld.{s,l} #const(isrc2),idest. */ + { &i860_cpu_device::insn_ldx, DEC_DECODED}, /* ld.b isrc1(isrc2),idest. */ + { &i860_cpu_device::insn_ldx, DEC_DECODED}, /* ld.b #const(isrc2),idest. */ + { &i860_cpu_device::insn_ixfr, DEC_DECODED}, /* ixfr isrc1ni,fdest. */ + { &i860_cpu_device::insn_stx, DEC_DECODED}, /* st.b isrc1ni,#const(isrc2). */ + { &i860_cpu_device::insn_ldx, DEC_DECODED}, /* ld.{s,l} isrc1(isrc2),idest. */ + { &i860_cpu_device::insn_ldx, DEC_DECODED}, /* ld.{s,l} #const(isrc2),idest. */ { 0, 0}, - { insn_stx, DEC_DECODED}, /* st.{s,l} isrc1ni,#const(isrc2),idest.*/ - { insn_fldy, DEC_DECODED}, /* fld.{l,d,q} isrc1(isrc2)[++],fdest. */ - { insn_fldy, DEC_DECODED}, /* fld.{l,d,q} #const(isrc2)[++],fdest. */ - { insn_fsty, DEC_DECODED}, /* fst.{l,d,q} fdest,isrc1(isrc2)[++] */ - { insn_fsty, DEC_DECODED}, /* fst.{l,d,q} fdest,#const(isrc2)[++] */ - { insn_ld_ctrl, DEC_DECODED}, /* ld.c csrc2,idest. */ - { insn_flush, DEC_DECODED}, /* flush #const(isrc2) (or autoinc). */ - { insn_st_ctrl, DEC_DECODED}, /* st.c isrc1,csrc2. */ - { insn_pstd, DEC_DECODED}, /* pst.d fdest,#const(isrc2)[++]. */ - { insn_bri, DEC_DECODED}, /* bri isrc1ni. */ - { insn_trap, DEC_DECODED}, /* trap isrc1ni,isrc2,idest. */ + { &i860_cpu_device::insn_stx, DEC_DECODED}, /* st.{s,l} isrc1ni,#const(isrc2),idest.*/ + { &i860_cpu_device::insn_fldy, DEC_DECODED}, /* fld.{l,d,q} isrc1(isrc2)[++],fdest. */ + { &i860_cpu_device::insn_fldy, DEC_DECODED}, /* fld.{l,d,q} #const(isrc2)[++],fdest. */ + { &i860_cpu_device::insn_fsty, DEC_DECODED}, /* fst.{l,d,q} fdest,isrc1(isrc2)[++] */ + { &i860_cpu_device::insn_fsty, DEC_DECODED}, /* fst.{l,d,q} fdest,#const(isrc2)[++] */ + { &i860_cpu_device::insn_ld_ctrl, DEC_DECODED}, /* ld.c csrc2,idest. */ + { &i860_cpu_device::insn_flush, DEC_DECODED}, /* flush #const(isrc2) (or autoinc). */ + { &i860_cpu_device::insn_st_ctrl, DEC_DECODED}, /* st.c isrc1,csrc2. */ + { &i860_cpu_device::insn_pstd, DEC_DECODED}, /* pst.d fdest,#const(isrc2)[++]. */ + { &i860_cpu_device::insn_bri, DEC_DECODED}, /* bri isrc1ni. */ + { &i860_cpu_device::insn_trap, DEC_DECODED}, /* trap isrc1ni,isrc2,idest. */ { 0, DEC_MORE}, /* FP ESCAPE FORMAT, more decode. */ { 0, DEC_MORE}, /* CORE ESCAPE FORMAT, more decode. */ - { insn_btne, DEC_DECODED}, /* btne isrc1,isrc2,sbroff. */ - { insn_btne_imm, DEC_DECODED}, /* btne #const,isrc2,sbroff. */ - { insn_bte, DEC_DECODED}, /* bte isrc1,isrc2,sbroff. */ - { insn_bte_imm, DEC_DECODED}, /* bte #const5,isrc2,idest. */ - { insn_fldy, DEC_DECODED}, /* pfld.{l,d,q} isrc1(isrc2)[++],fdest.*/ - { insn_fldy, DEC_DECODED}, /* pfld.{l,d,q} #const(isrc2)[++],fdest.*/ - { insn_br, DEC_DECODED}, /* br lbroff. */ - { insn_call, DEC_DECODED}, /* call lbroff . */ - { insn_bc, DEC_DECODED}, /* bc lbroff. */ - { insn_bct, DEC_DECODED}, /* bc.t lbroff. */ - { insn_bnc, DEC_DECODED}, /* bnc lbroff. */ - { insn_bnct, DEC_DECODED}, /* bnc.t lbroff. */ - { insn_addu, DEC_DECODED}, /* addu isrc1,isrc2,idest. */ - { insn_addu_imm, DEC_DECODED}, /* addu #const,isrc2,idest. */ - { insn_subu, DEC_DECODED}, /* subu isrc1,isrc2,idest. */ - { insn_subu_imm, DEC_DECODED}, /* subu #const,isrc2,idest. */ - { insn_adds, DEC_DECODED}, /* adds isrc1,isrc2,idest. */ - { insn_adds_imm, DEC_DECODED}, /* adds #const,isrc2,idest. */ - { insn_subs, DEC_DECODED}, /* subs isrc1,isrc2,idest. */ - { insn_subs_imm, DEC_DECODED}, /* subs #const,isrc2,idest. */ - { insn_shl, DEC_DECODED}, /* shl isrc1,isrc2,idest. */ - { insn_shl_imm, DEC_DECODED}, /* shl #const,isrc2,idest. */ - { insn_shr, DEC_DECODED}, /* shr isrc1,isrc2,idest. */ - { insn_shr_imm, DEC_DECODED}, /* shr #const,isrc2,idest. */ - { insn_shrd, DEC_DECODED}, /* shrd isrc1ni,isrc2,idest. */ - { insn_bla, DEC_DECODED}, /* bla isrc1ni,isrc2,sbroff. */ - { insn_shra, DEC_DECODED}, /* shra isrc1,isrc2,idest. */ - { insn_shra_imm, DEC_DECODED}, /* shra #const,isrc2,idest. */ - { insn_and, DEC_DECODED}, /* and isrc1,isrc2,idest. */ - { insn_and_imm, DEC_DECODED}, /* and #const,isrc2,idest. */ + { &i860_cpu_device::insn_btne, DEC_DECODED}, /* btne isrc1,isrc2,sbroff. */ + { &i860_cpu_device::insn_btne_imm, DEC_DECODED}, /* btne #const,isrc2,sbroff. */ + { &i860_cpu_device::insn_bte, DEC_DECODED}, /* bte isrc1,isrc2,sbroff. */ + { &i860_cpu_device::insn_bte_imm, DEC_DECODED}, /* bte #const5,isrc2,idest. */ + { &i860_cpu_device::insn_fldy, DEC_DECODED}, /* pfld.{l,d,q} isrc1(isrc2)[++],fdest.*/ + { &i860_cpu_device::insn_fldy, DEC_DECODED}, /* pfld.{l,d,q} #const(isrc2)[++],fdest.*/ + { &i860_cpu_device::insn_br, DEC_DECODED}, /* br lbroff. */ + { &i860_cpu_device::insn_call, DEC_DECODED}, /* call lbroff . */ + { &i860_cpu_device::insn_bc, DEC_DECODED}, /* bc lbroff. */ + { &i860_cpu_device::insn_bct, DEC_DECODED}, /* bc.t lbroff. */ + { &i860_cpu_device::insn_bnc, DEC_DECODED}, /* bnc lbroff. */ + { &i860_cpu_device::insn_bnct, DEC_DECODED}, /* bnc.t lbroff. */ + { &i860_cpu_device::insn_addu, DEC_DECODED}, /* addu isrc1,isrc2,idest. */ + { &i860_cpu_device::insn_addu_imm, DEC_DECODED}, /* addu #const,isrc2,idest. */ + { &i860_cpu_device::insn_subu, DEC_DECODED}, /* subu isrc1,isrc2,idest. */ + { &i860_cpu_device::insn_subu_imm, DEC_DECODED}, /* subu #const,isrc2,idest. */ + { &i860_cpu_device::insn_adds, DEC_DECODED}, /* adds isrc1,isrc2,idest. */ + { &i860_cpu_device::insn_adds_imm, DEC_DECODED}, /* adds #const,isrc2,idest. */ + { &i860_cpu_device::insn_subs, DEC_DECODED}, /* subs isrc1,isrc2,idest. */ + { &i860_cpu_device::insn_subs_imm, DEC_DECODED}, /* subs #const,isrc2,idest. */ + { &i860_cpu_device::insn_shl, DEC_DECODED}, /* shl isrc1,isrc2,idest. */ + { &i860_cpu_device::insn_shl_imm, DEC_DECODED}, /* shl #const,isrc2,idest. */ + { &i860_cpu_device::insn_shr, DEC_DECODED}, /* shr isrc1,isrc2,idest. */ + { &i860_cpu_device::insn_shr_imm, DEC_DECODED}, /* shr #const,isrc2,idest. */ + { &i860_cpu_device::insn_shrd, DEC_DECODED}, /* shrd isrc1ni,isrc2,idest. */ + { &i860_cpu_device::insn_bla, DEC_DECODED}, /* bla isrc1ni,isrc2,sbroff. */ + { &i860_cpu_device::insn_shra, DEC_DECODED}, /* shra isrc1,isrc2,idest. */ + { &i860_cpu_device::insn_shra_imm, DEC_DECODED}, /* shra #const,isrc2,idest. */ + { &i860_cpu_device::insn_and, DEC_DECODED}, /* and isrc1,isrc2,idest. */ + { &i860_cpu_device::insn_and_imm, DEC_DECODED}, /* and #const,isrc2,idest. */ { 0, 0}, - { insn_andh_imm, DEC_DECODED}, /* andh #const,isrc2,idest. */ - { insn_andnot, DEC_DECODED}, /* andnot isrc1,isrc2,idest. */ - { insn_andnot_imm, DEC_DECODED}, /* andnot #const,isrc2,idest. */ + { &i860_cpu_device::insn_andh_imm, DEC_DECODED}, /* andh #const,isrc2,idest. */ + { &i860_cpu_device::insn_andnot, DEC_DECODED}, /* andnot isrc1,isrc2,idest. */ + { &i860_cpu_device::insn_andnot_imm, DEC_DECODED}, /* andnot #const,isrc2,idest. */ { 0, 0}, - { insn_andnoth_imm, DEC_DECODED}, /* andnoth #const,isrc2,idest. */ - { insn_or, DEC_DECODED}, /* or isrc1,isrc2,idest. */ - { insn_or_imm, DEC_DECODED}, /* or #const,isrc2,idest. */ + { &i860_cpu_device::insn_andnoth_imm, DEC_DECODED}, /* andnoth #const,isrc2,idest. */ + { &i860_cpu_device::insn_or, DEC_DECODED}, /* or isrc1,isrc2,idest. */ + { &i860_cpu_device::insn_or_imm, DEC_DECODED}, /* or #const,isrc2,idest. */ { 0, 0}, - { insn_orh_imm, DEC_DECODED}, /* orh #const,isrc2,idest. */ - { insn_xor, DEC_DECODED}, /* xor isrc1,isrc2,idest. */ - { insn_xor_imm, DEC_DECODED}, /* xor #const,isrc2,idest. */ + { &i860_cpu_device::insn_orh_imm, DEC_DECODED}, /* orh #const,isrc2,idest. */ + { &i860_cpu_device::insn_xor, DEC_DECODED}, /* xor isrc1,isrc2,idest. */ + { &i860_cpu_device::insn_xor_imm, DEC_DECODED}, /* xor #const,isrc2,idest. */ { 0, 0}, - { insn_xorh_imm, DEC_DECODED}, /* xorh #const,isrc2,idest. */ + { &i860_cpu_device::insn_xorh_imm, DEC_DECODED}, /* xorh #const,isrc2,idest. */ }; /* Second-level decode table (i.e., for the 3 core escape opcode bits). */ -static const decode_tbl_t core_esc_decode_tbl[8] = { +const i860_cpu_device::decode_tbl_t i860_cpu_device::core_esc_decode_tbl[8] = { { 0, 0}, { 0, 0}, /* lock (FIXME: unimplemented). */ - { insn_calli, DEC_DECODED}, /* calli isrc1ni. */ + { &i860_cpu_device::insn_calli, DEC_DECODED}, /* calli isrc1ni. */ { 0, 0}, - { insn_intovr, DEC_DECODED}, /* intovr. */ + { &i860_cpu_device::insn_intovr, DEC_DECODED}, /* intovr. */ { 0, 0}, { 0, 0}, { 0, 0}, /* unlock (FIXME: unimplemented). */ @@ -4168,49 +4143,49 @@ static const decode_tbl_t core_esc_decode_tbl[8] = { /* Second-level decode table (i.e., for the 7 FP extended opcode bits). */ -static const decode_tbl_t fp_decode_tbl[128] = { +const i860_cpu_device::decode_tbl_t i860_cpu_device::fp_decode_tbl[128] = { /* Floating point instructions. The least significant 7 bits are the (extended) opcode and bits 10:7 are P,D,S,R respectively ([p]ipelined, [d]ual, [s]ource prec., [r]esult prec.). For some operations, I defer decoding the P,S,R bits to the emulation routine for them. */ - { insn_dualop, DEC_DECODED}, /* 0x00 pf[m]am */ - { insn_dualop, DEC_DECODED}, /* 0x01 pf[m]am */ - { insn_dualop, DEC_DECODED}, /* 0x02 pf[m]am */ - { insn_dualop, DEC_DECODED}, /* 0x03 pf[m]am */ - { insn_dualop, DEC_DECODED}, /* 0x04 pf[m]am */ - { insn_dualop, DEC_DECODED}, /* 0x05 pf[m]am */ - { insn_dualop, DEC_DECODED}, /* 0x06 pf[m]am */ - { insn_dualop, DEC_DECODED}, /* 0x07 pf[m]am */ - { insn_dualop, DEC_DECODED}, /* 0x08 pf[m]am */ - { insn_dualop, DEC_DECODED}, /* 0x09 pf[m]am */ - { insn_dualop, DEC_DECODED}, /* 0x0A pf[m]am */ - { insn_dualop, DEC_DECODED}, /* 0x0B pf[m]am */ - { insn_dualop, DEC_DECODED}, /* 0x0C pf[m]am */ - { insn_dualop, DEC_DECODED}, /* 0x0D pf[m]am */ - { insn_dualop, DEC_DECODED}, /* 0x0E pf[m]am */ - { insn_dualop, DEC_DECODED}, /* 0x0F pf[m]am */ - { insn_dualop, DEC_DECODED}, /* 0x10 pf[m]sm */ - { insn_dualop, DEC_DECODED}, /* 0x11 pf[m]sm */ - { insn_dualop, DEC_DECODED}, /* 0x12 pf[m]sm */ - { insn_dualop, DEC_DECODED}, /* 0x13 pf[m]sm */ - { insn_dualop, DEC_DECODED}, /* 0x14 pf[m]sm */ - { insn_dualop, DEC_DECODED}, /* 0x15 pf[m]sm */ - { insn_dualop, DEC_DECODED}, /* 0x16 pf[m]sm */ - { insn_dualop, DEC_DECODED}, /* 0x17 pf[m]sm */ - { insn_dualop, DEC_DECODED}, /* 0x18 pf[m]sm */ - { insn_dualop, DEC_DECODED}, /* 0x19 pf[m]sm */ - { insn_dualop, DEC_DECODED}, /* 0x1A pf[m]sm */ - { insn_dualop, DEC_DECODED}, /* 0x1B pf[m]sm */ - { insn_dualop, DEC_DECODED}, /* 0x1C pf[m]sm */ - { insn_dualop, DEC_DECODED}, /* 0x1D pf[m]sm */ - { insn_dualop, DEC_DECODED}, /* 0x1E pf[m]sm */ - { insn_dualop, DEC_DECODED}, /* 0x1F pf[m]sm */ - { insn_fmul, DEC_DECODED}, /* 0x20 [p]fmul */ - { insn_fmlow, DEC_DECODED}, /* 0x21 fmlow.dd */ - { insn_frcp, DEC_DECODED}, /* 0x22 frcp.{ss,sd,dd} */ - { insn_frsqr, DEC_DECODED}, /* 0x23 frsqr.{ss,sd,dd} */ - { insn_fmul, DEC_DECODED}, /* 0x24 pfmul3.dd */ + { &i860_cpu_device::insn_dualop, DEC_DECODED}, /* 0x00 pf[m]am */ + { &i860_cpu_device::insn_dualop, DEC_DECODED}, /* 0x01 pf[m]am */ + { &i860_cpu_device::insn_dualop, DEC_DECODED}, /* 0x02 pf[m]am */ + { &i860_cpu_device::insn_dualop, DEC_DECODED}, /* 0x03 pf[m]am */ + { &i860_cpu_device::insn_dualop, DEC_DECODED}, /* 0x04 pf[m]am */ + { &i860_cpu_device::insn_dualop, DEC_DECODED}, /* 0x05 pf[m]am */ + { &i860_cpu_device::insn_dualop, DEC_DECODED}, /* 0x06 pf[m]am */ + { &i860_cpu_device::insn_dualop, DEC_DECODED}, /* 0x07 pf[m]am */ + { &i860_cpu_device::insn_dualop, DEC_DECODED}, /* 0x08 pf[m]am */ + { &i860_cpu_device::insn_dualop, DEC_DECODED}, /* 0x09 pf[m]am */ + { &i860_cpu_device::insn_dualop, DEC_DECODED}, /* 0x0A pf[m]am */ + { &i860_cpu_device::insn_dualop, DEC_DECODED}, /* 0x0B pf[m]am */ + { &i860_cpu_device::insn_dualop, DEC_DECODED}, /* 0x0C pf[m]am */ + { &i860_cpu_device::insn_dualop, DEC_DECODED}, /* 0x0D pf[m]am */ + { &i860_cpu_device::insn_dualop, DEC_DECODED}, /* 0x0E pf[m]am */ + { &i860_cpu_device::insn_dualop, DEC_DECODED}, /* 0x0F pf[m]am */ + { &i860_cpu_device::insn_dualop, DEC_DECODED}, /* 0x10 pf[m]sm */ + { &i860_cpu_device::insn_dualop, DEC_DECODED}, /* 0x11 pf[m]sm */ + { &i860_cpu_device::insn_dualop, DEC_DECODED}, /* 0x12 pf[m]sm */ + { &i860_cpu_device::insn_dualop, DEC_DECODED}, /* 0x13 pf[m]sm */ + { &i860_cpu_device::insn_dualop, DEC_DECODED}, /* 0x14 pf[m]sm */ + { &i860_cpu_device::insn_dualop, DEC_DECODED}, /* 0x15 pf[m]sm */ + { &i860_cpu_device::insn_dualop, DEC_DECODED}, /* 0x16 pf[m]sm */ + { &i860_cpu_device::insn_dualop, DEC_DECODED}, /* 0x17 pf[m]sm */ + { &i860_cpu_device::insn_dualop, DEC_DECODED}, /* 0x18 pf[m]sm */ + { &i860_cpu_device::insn_dualop, DEC_DECODED}, /* 0x19 pf[m]sm */ + { &i860_cpu_device::insn_dualop, DEC_DECODED}, /* 0x1A pf[m]sm */ + { &i860_cpu_device::insn_dualop, DEC_DECODED}, /* 0x1B pf[m]sm */ + { &i860_cpu_device::insn_dualop, DEC_DECODED}, /* 0x1C pf[m]sm */ + { &i860_cpu_device::insn_dualop, DEC_DECODED}, /* 0x1D pf[m]sm */ + { &i860_cpu_device::insn_dualop, DEC_DECODED}, /* 0x1E pf[m]sm */ + { &i860_cpu_device::insn_dualop, DEC_DECODED}, /* 0x1F pf[m]sm */ + { &i860_cpu_device::insn_fmul, DEC_DECODED}, /* 0x20 [p]fmul */ + { &i860_cpu_device::insn_fmlow, DEC_DECODED}, /* 0x21 fmlow.dd */ + { &i860_cpu_device::insn_frcp, DEC_DECODED}, /* 0x22 frcp.{ss,sd,dd} */ + { &i860_cpu_device::insn_frsqr, DEC_DECODED}, /* 0x23 frsqr.{ss,sd,dd} */ + { &i860_cpu_device::insn_fmul, DEC_DECODED}, /* 0x24 pfmul3.dd */ { 0, 0}, /* 0x25 */ { 0, 0}, /* 0x26 */ { 0, 0}, /* 0x27 */ @@ -4222,23 +4197,23 @@ static const decode_tbl_t fp_decode_tbl[128] = { { 0, 0}, /* 0x2D */ { 0, 0}, /* 0x2E */ { 0, 0}, /* 0x2F */ - { insn_fadd_sub, DEC_DECODED}, /* 0x30, [p]fadd.{ss,sd,dd} */ - { insn_fadd_sub, DEC_DECODED}, /* 0x31, [p]fsub.{ss,sd,dd} */ + { &i860_cpu_device::insn_fadd_sub, DEC_DECODED}, /* 0x30, [p]fadd.{ss,sd,dd} */ + { &i860_cpu_device::insn_fadd_sub, DEC_DECODED}, /* 0x31, [p]fsub.{ss,sd,dd} */ { 0, 0}, /* 0x32, [p]fix.{ss,sd,dd} FIXME: nyi. */ - { insn_famov, DEC_DECODED}, /* 0x33, [p]famov.{ss,sd,ds,dd} */ - { insn_fcmp, DEC_DECODED}, /* 0x34, pf{gt,le}.{ss,dd} */ - { insn_fcmp, DEC_DECODED}, /* 0x35, pfeq.{ss,dd} */ + { &i860_cpu_device::insn_famov, DEC_DECODED}, /* 0x33, [p]famov.{ss,sd,ds,dd} */ + { &i860_cpu_device::insn_fcmp, DEC_DECODED}, /* 0x34, pf{gt,le}.{ss,dd} */ + { &i860_cpu_device::insn_fcmp, DEC_DECODED}, /* 0x35, pfeq.{ss,dd} */ { 0, 0}, /* 0x36 */ { 0, 0}, /* 0x37 */ { 0, 0}, /* 0x38 */ { 0, 0}, /* 0x39 */ - { insn_ftrunc, DEC_DECODED}, /* 0x3A, [p]ftrunc.{ss,sd,dd} */ + { &i860_cpu_device::insn_ftrunc, DEC_DECODED}, /* 0x3A, [p]ftrunc.{ss,sd,dd} */ { 0, 0}, /* 0x3B */ { 0, 0}, /* 0x3C */ { 0, 0}, /* 0x3D */ { 0, 0}, /* 0x3E */ { 0, 0}, /* 0x3F */ - { insn_fxfr, DEC_DECODED}, /* 0x40, fxfr */ + { &i860_cpu_device::insn_fxfr, DEC_DECODED}, /* 0x40, fxfr */ { 0, 0}, /* 0x41 */ { 0, 0}, /* 0x42 */ { 0, 0}, /* 0x43 */ @@ -4247,29 +4222,29 @@ static const decode_tbl_t fp_decode_tbl[128] = { { 0, 0}, /* 0x46 */ { 0, 0}, /* 0x47 */ { 0, 0}, /* 0x48 */ - { insn_fiadd_sub, DEC_DECODED}, /* 0x49, [p]fiadd.{ss,dd} */ + { &i860_cpu_device::insn_fiadd_sub, DEC_DECODED}, /* 0x49, [p]fiadd.{ss,dd} */ { 0, 0}, /* 0x4A */ { 0, 0}, /* 0x4B */ { 0, 0}, /* 0x4C */ - { insn_fiadd_sub, DEC_DECODED}, /* 0x4D, [p]fisub.{ss,dd} */ + { &i860_cpu_device::insn_fiadd_sub, DEC_DECODED}, /* 0x4D, [p]fisub.{ss,dd} */ { 0, 0}, /* 0x4E */ { 0, 0}, /* 0x4F */ - { insn_faddp, DEC_DECODED}, /* 0x50, [p]faddp */ - { insn_faddz, DEC_DECODED}, /* 0x51, [p]faddz */ + { &i860_cpu_device::insn_faddp, DEC_DECODED}, /* 0x50, [p]faddp */ + { &i860_cpu_device::insn_faddz, DEC_DECODED}, /* 0x51, [p]faddz */ { 0, 0}, /* 0x52 */ { 0, 0}, /* 0x53 */ { 0, 0}, /* 0x54 */ { 0, 0}, /* 0x55 */ { 0, 0}, /* 0x56 */ - { insn_fzchk, DEC_DECODED}, /* 0x57, [p]fzchkl */ + { &i860_cpu_device::insn_fzchk, DEC_DECODED}, /* 0x57, [p]fzchkl */ { 0, 0}, /* 0x58 */ { 0, 0}, /* 0x59 */ - { insn_form, DEC_DECODED}, /* 0x5A, [p]form.dd */ + { &i860_cpu_device::insn_form, DEC_DECODED}, /* 0x5A, [p]form.dd */ { 0, 0}, /* 0x5B */ { 0, 0}, /* 0x5C */ { 0, 0}, /* 0x5D */ { 0, 0}, /* 0x5E */ - { insn_fzchk, DEC_DECODED}, /* 0x5F, [p]fzchks */ + { &i860_cpu_device::insn_fzchk, DEC_DECODED}, /* 0x5F, [p]fzchks */ { 0, 0}, /* 0x60 */ { 0, 0}, /* 0x61 */ { 0, 0}, /* 0x62 */ @@ -4310,13 +4285,13 @@ static const decode_tbl_t fp_decode_tbl[128] = { * insn = instruction at the current PC to execute. * non_shadow = This insn is not in the shadow of a delayed branch). */ -static void decode_exec (i860s *cpustate, UINT32 insn, UINT32 non_shadow) +void i860_cpu_device::decode_exec (UINT32 insn, UINT32 non_shadow) { int upper_6bits = (insn >> 26) & 0x3f; char flags = 0; int unrecognized = 1; - if (cpustate->exiting_ifetch) + if (m_exiting_ifetch) return; if ((upper_6bits == 0x12 || upper_6bits == 0x2c) && insn & 0x0200) @@ -4329,7 +4304,7 @@ static void decode_exec (i860s *cpustate, UINT32 insn, UINT32 non_shadow) flags = decode_tbl[upper_6bits].flags; if (flags & DEC_DECODED) { - decode_tbl[upper_6bits].insn_exec (cpustate, insn); + (this->*decode_tbl[upper_6bits].insn_exec)(insn); unrecognized = 0; } else if (flags & DEC_MORE) @@ -4340,7 +4315,7 @@ static void decode_exec (i860s *cpustate, UINT32 insn, UINT32 non_shadow) char fp_flags = fp_decode_tbl[insn & 0x7f].flags; if (fp_flags & DEC_DECODED) { - fp_decode_tbl[insn & 0x7f].insn_exec (cpustate, insn); + (this->*fp_decode_tbl[insn & 0x7f].insn_exec)(insn); unrecognized = 0; } } @@ -4350,23 +4325,23 @@ static void decode_exec (i860s *cpustate, UINT32 insn, UINT32 non_shadow) char esc_flags = core_esc_decode_tbl[insn & 0x3].flags; if (esc_flags & DEC_DECODED) { - core_esc_decode_tbl[insn & 0x3].insn_exec (cpustate, insn); + (this->*core_esc_decode_tbl[insn & 0x3].insn_exec)(insn); unrecognized = 0; } } } if (unrecognized) - unrecog_opcode (cpustate->pc, insn); + unrecog_opcode (m_pc, insn); /* For now, just treat every instruction as taking the same number of clocks-- a major oversimplification. */ - cpustate->icount -= 9; + m_icount -= 9; } /* Set-up all the default power-on/reset values. */ -void reset_i860 (i860s *cpustate) +void i860_cpu_device::reset_i860 () { int i; /* On power-up/reset, i860 has values: @@ -4388,21 +4363,21 @@ void reset_i860 (i860s *cpustate) try to detect defective i860 software. */ /* PC is at trap address after reset. */ - cpustate->pc = 0xffffff00; + m_pc = 0xffffff00; /* Set grs and frs to undefined/nonsense values, except r0. */ for (i = 0; i < 32; i++) { set_iregval (i, 0x55aa55aa); - set_fregval_s (cpustate, i, 0.0); + set_fregval_s (i, 0.0); } set_iregval (0, 0); - set_fregval_s (cpustate, 0, 0.0); - set_fregval_s (cpustate, 1, 0.0); + set_fregval_s (0, 0.0); + set_fregval_s (1, 0.0); /* Set whole psr to 0. This sets the proper bits to 0 as specified above, and zeroes the undefined bits. */ - cpustate->cregs[CR_PSR] = 0; + m_cregs[CR_PSR] = 0; /* Set most of the epsr bits to 0 (as specified above), leaving undefined as zero as well. Then properly set processor type, @@ -4414,20 +4389,20 @@ void reset_i860 (i860s *cpustate) Proc type: 1 = XR, 2 = XP (XR has 8KB data cache -> DCS = 1). Steppings (XR): 3,4,5,6,7 = (B2, C0, B3, C1, D0 respectively). Steppings (XP): 0, 2, 3, 4 = (A0, B0, B1, B2) (any others?). */ - cpustate->cregs[CR_EPSR] = 0x00040701; + m_cregs[CR_EPSR] = 0x00040701; /* Set DPS, BL, ATE = 0 and the undefined parts also to 0. */ - cpustate->cregs[CR_DIRBASE] = 0x00000000; + m_cregs[CR_DIRBASE] = 0x00000000; /* Set fir, fsr, KR, KI, MERGE, T to undefined. */ - cpustate->cregs[CR_FIR] = 0xaa55aa55; - cpustate->cregs[CR_FSR] = /* 0xaa55aa55; */ 0; - cpustate->KR.d = 0.0; - cpustate->KI.d = 0.0; - cpustate->T.d = 0.0; - cpustate->merge = 0xaa55aa55; + m_cregs[CR_FIR] = 0xaa55aa55; + m_cregs[CR_FSR] = /* 0xaa55aa55; */ 0; + m_KR.d = 0.0; + m_KI.d = 0.0; + m_T.d = 0.0; + m_merge = 0xaa55aa55; - cpustate->fir_gets_trap_addr = 0; + m_fir_gets_trap_addr = 0; } @@ -4437,91 +4412,87 @@ void reset_i860 (i860s *cpustate) /* MAME execution hook for i860 emulator. */ /*=================================================================*/ -#include "emu.h" - -static CPU_EXECUTE( i860 ) +void i860_cpu_device::execute_run() { - i860_state_t *cpustate = get_safe_token(device); - /* Check if the data bus is held by another device, and bail if so. Also check for reset. */ - if (cpustate->pin_reset) - reset_i860 (cpustate); - if (cpustate->pin_bus_hold) + if (m_pin_reset) + reset_i860 (); + if (m_pin_bus_hold) { - cpustate->icount = 0; + m_icount = 0; return; } - cpustate->exiting_readmem = 0; - cpustate->exiting_ifetch = 0; + m_exiting_readmem = 0; + m_exiting_ifetch = 0; /* Decode and execute loop. */ - while (cpustate->icount > 0) + while (m_icount > 0) { - UINT32 savepc = cpustate->pc; - cpustate->pc_updated = 0; - cpustate->pending_trap = 0; + UINT32 savepc = m_pc; + m_pc_updated = 0; + m_pending_trap = 0; #if 1 /* Delete me soon, for debugging VC inter-processor synch. */ - if (cpustate->pc == 0xfffc0370 || - cpustate->pc == 0xfffc03a4) + if (m_pc == 0xfffc0370 || + m_pc == 0xfffc03a4) { - fprintf(stderr, "(%s) 0x%08x: snag 0x20000000\n", cpustate->device->tag(), cpustate->pc); - cpustate->single_stepping = 0; + fprintf(stderr, "(%s) 0x%08x: snag 0x20000000\n", tag(), m_pc); + m_single_stepping = 0; } - else if (cpustate->pc == 0xfffc0384 || - cpustate->pc == 0xfffc03b8) + else if (m_pc == 0xfffc0384 || + m_pc == 0xfffc03b8) { - fprintf(stderr, "(%s) 0x%08x: passed 0x20000000\n", cpustate->device->tag(), cpustate->pc); - cpustate->single_stepping = 0; + fprintf(stderr, "(%s) 0x%08x: passed 0x20000000\n", tag(), m_pc); + m_single_stepping = 0; } #endif - savepc = cpustate->pc; - debugger_instruction_hook(cpustate->device, cpustate->pc); - decode_exec (cpustate, ifetch (cpustate, cpustate->pc), 1); + savepc = m_pc; + debugger_instruction_hook(this, m_pc); + decode_exec (ifetch (m_pc), 1); - cpustate->exiting_ifetch = 0; - cpustate->exiting_readmem = 0; + m_exiting_ifetch = 0; + m_exiting_readmem = 0; - if (cpustate->pending_trap) + if (m_pending_trap) { /* If we need to trap, change PC to trap address. Also set supervisor mode, copy U and IM to their previous versions, clear IM. */ - if ((cpustate->pending_trap & TRAP_WAS_EXTERNAL) || (GET_EPSR_INT () && GET_PSR_IN ())) + if ((m_pending_trap & TRAP_WAS_EXTERNAL) || (GET_EPSR_INT () && GET_PSR_IN ())) { - if (!cpustate->pc_updated) - cpustate->cregs[CR_FIR] = savepc + 4; + if (!m_pc_updated) + m_cregs[CR_FIR] = savepc + 4; else - cpustate->cregs[CR_FIR] = cpustate->pc; + m_cregs[CR_FIR] = m_pc; } - else if (cpustate->pending_trap & TRAP_IN_DELAY_SLOT) + else if (m_pending_trap & TRAP_IN_DELAY_SLOT) { - cpustate->cregs[CR_FIR] = savepc + 4; + m_cregs[CR_FIR] = savepc + 4; } else - cpustate->cregs[CR_FIR] = savepc; + m_cregs[CR_FIR] = savepc; - cpustate->fir_gets_trap_addr = 1; + m_fir_gets_trap_addr = 1; SET_PSR_PU (GET_PSR_U ()); SET_PSR_PIM (GET_PSR_IM ()); SET_PSR_U (0); SET_PSR_IM (0); SET_PSR_DIM (0); SET_PSR_DS (0); - cpustate->pc = 0xffffff00; - cpustate->pending_trap = 0; + m_pc = 0xffffff00; + m_pending_trap = 0; } - else if (!cpustate->pc_updated) + else if (!m_pc_updated) { /* If the PC wasn't updated by a control flow instruction, just bump to next sequential instruction. */ - cpustate->pc += 4; + m_pc += 4; } - /*if (cpustate->single_stepping) + /*if (m_single_stepping) debugger (cpustate); */ } } @@ -4538,7 +4509,7 @@ extern unsigned disasm_i860 (char *buf, unsigned int pc, unsigned int insn); /* Disassemble `len' instructions starting at `addr'. */ -static void disasm (i860s *cpustate, UINT32 addr, int len) +void i860_cpu_device::disasm (UINT32 addr, int len) { UINT32 insn; int j; @@ -4547,12 +4518,12 @@ static void disasm (i860s *cpustate, UINT32 addr, int len) char buf[256]; UINT32 phys_addr = addr; if (GET_DIRBASE_ATE ()) - phys_addr = get_address_translation (cpustate, addr, 1 /* is_dataref */, 0 /* is_write */); + phys_addr = get_address_translation (addr, 1 /* is_dataref */, 0 /* is_write */); /* Note that we print the incoming (possibly virtual) address as the PC rather than the translated address. */ - fprintf (stderr, " (%s) 0x%08x: ", cpustate->device->tag(), addr); - insn = cpustate->program->read_dword(phys_addr); + fprintf (stderr, " (%s) 0x%08x: ", m_device->tag(), addr); + insn = m_program->read_dword(phys_addr); #ifdef HOST_MSB BYTE_REV32 (insn); #endif /* HOST_MSB. */ @@ -4560,7 +4531,7 @@ static void disasm (i860s *cpustate, UINT32 addr, int len) fprintf (stderr, "\n"); addr += 4; #if 1 - if (cpustate->single_stepping == 1 && has_delay_slot (insn)) + if (m_single_stepping == 1 && has_delay_slot (insn)) len += 1; #endif } @@ -4568,7 +4539,7 @@ static void disasm (i860s *cpustate, UINT32 addr, int len) /* Dump `len' bytes starting at `addr'. */ -static void dbg_db (i860s *cpustate, UINT32 addr, int len) +void i860_cpu_device::dbg_db (UINT32 addr, int len) { UINT8 b[16]; int i; @@ -4582,9 +4553,9 @@ static void dbg_db (i860s *cpustate, UINT32 addr, int len) { UINT32 phys_addr = addr; if (GET_DIRBASE_ATE ()) - phys_addr = get_address_translation (cpustate, addr, 1 /* is_dataref */, 0 /* is_write */); + phys_addr = get_address_translation (addr, 1 /* is_dataref */, 0 /* is_write */); - b[i] = cpustate->program->read_byte(phys_addr); + b[i] = m_program->read_byte(phys_addr); fprintf (stderr, "%02x ", b[i]); addr++; } @@ -4606,29 +4577,29 @@ static void dbg_db (i860s *cpustate, UINT32 addr, int len) void debugger (i860s *cpustate) { char buf[256]; - UINT32 curr_disasm = cpustate->pc; + UINT32 curr_disasm = m_pc; UINT32 curr_dumpdb = 0; int c = 0; - if (cpustate->single_stepping > 1 && cpustate->single_stepping != cpustate->pc) + if (m_single_stepping > 1 && m_single_stepping != m_pc) return; buf[0] = 0; /* Always disassemble the upcoming instruction when single-stepping. */ - if (cpustate->single_stepping) + if (m_single_stepping) { - disasm (cpustate, cpustate->pc, 1); + disasm (m_pc, 1); if (has_delay_slot (2)) - disasm (cpustate, cpustate->pc + 4, 1); + disasm (m_pc + 4, 1); } else fprintf (stderr, "\nEmulator: internal debugger started (? for help).\n"); fflush (stdin); - cpustate->single_stepping = 0; - while (!cpustate->single_stepping) + m_single_stepping = 0; + while (!m_single_stepping) { fprintf (stderr, "- "); #if 0 /* Doesn't work on MacOSX BSD flavor. */ @@ -4652,13 +4623,13 @@ void debugger (i860s *cpustate) if (buf[0] == 'g') { if (buf[1] == '0') - sscanf (buf + 1, "%x", &cpustate->single_stepping); + sscanf (buf + 1, "%x", &m_single_stepping); else break; buf[1] = 0; fprintf (stderr, "go until pc = 0x%08x.\n", - cpustate->single_stepping); - cpustate->single_stepping = 0; /* HACK */ + m_single_stepping); + m_single_stepping = 0; /* HACK */ } else if (buf[0] == 'r') dump_state (cpustate); @@ -4666,25 +4637,25 @@ void debugger (i860s *cpustate) { if (buf[1] == '0') sscanf (buf + 1, "%x", &curr_disasm); - disasm (cpustate, curr_disasm, 10); + disasm (curr_disasm, 10); curr_disasm += 10 * 4; buf[1] = 0; } else if (buf[0] == 'p') { if (buf[1] >= '0' && buf[1] <= '4') - dump_pipe (cpustate, buf[1] - 0x30); + dump_pipe (buf[1] - 0x30); buf[1] = 0; } else if (buf[0] == 's') - cpustate->single_stepping = 1; + m_single_stepping = 1; else if (buf[0] == 'l') - ; //cpustate->pc = elf_load(buf + 1); + ; //m_pc = elf_load(buf + 1); else if (buf[0] == 'd' && buf[1] == 'b') { if (buf[2] == '0') sscanf (buf + 2, "%x", &curr_dumpdb); - dbg_db (cpustate, curr_dumpdb, 32); + dbg_db (curr_dumpdb, 32); curr_dumpdb += 32; } else if (buf[0] == 'x' && buf[1] == '0') @@ -4693,13 +4664,13 @@ void debugger (i860s *cpustate) sscanf (buf + 1, "%x", &v); if (GET_DIRBASE_ATE ()) fprintf (stderr, "vma 0x%08x ==> phys 0x%08x\n", v, - get_address_translation (cpustate, v, 1, 0)); + get_address_translation (v, 1, 0)); else fprintf (stderr, "not in virtual address mode.\n"); } else if (buf[0] == 'B') { - ;//cpustate->pc = elf_load("bins/bsd"); + ;//m_pc = elf_load("bins/bsd"); break; } else if (buf[0] == '?') @@ -4711,7 +4682,7 @@ void debugger (i860s *cpustate) } /* Less noise when single-stepping. */ - if (cpustate->single_stepping != 1) + if (m_single_stepping != 1) fprintf (stderr, "Debugger done, continuing emulation.\n"); } diff --git a/src/mame/drivers/vcombat.c b/src/mame/drivers/vcombat.c index 32054b9925f..23eb33c49e7 100644 --- a/src/mame/drivers/vcombat.c +++ b/src/mame/drivers/vcombat.c @@ -101,6 +101,8 @@ public: m_framebuffer_ctrl(*this, "fb_control"), m_maincpu(*this, "maincpu"), m_soundcpu(*this, "soundcpu"), + m_vid_0(*this, "vid_0"), + m_vid_1(*this, "vid_1"), m_dac(*this, "dac") { } UINT16* m_m68k_framebuffer[2]; @@ -133,6 +135,8 @@ public: UINT32 screen_update_vcombat_aux(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect); required_device m_maincpu; required_device m_soundcpu; + required_device m_vid_0; + optional_device m_vid_1; required_device m_dac; }; @@ -228,7 +232,7 @@ READ16_MEMBER(vcombat_state::control_3_r) return (ioport("IN2")->read() << 8); } -static void wiggle_i860_common(device_t *device, UINT16 data) +static void wiggle_i860_common(i860_cpu_device *device, UINT16 data) { int bus_hold = (data & 0x03) == 0x03; int reset = data & 0x10; @@ -238,31 +242,31 @@ static void wiggle_i860_common(device_t *device, UINT16 data) if (bus_hold) { fprintf(stderr, "M0 asserting bus HOLD to i860 %s\n", device->tag()); - i860_set_pin(device, DEC_PIN_BUS_HOLD, 1); + device->i860_set_pin(DEC_PIN_BUS_HOLD, 1); } else { fprintf(stderr, "M0 clearing bus HOLD to i860 %s\n", device->tag()); - i860_set_pin(device, DEC_PIN_BUS_HOLD, 0); + device->i860_set_pin(DEC_PIN_BUS_HOLD, 0); } if (reset) { fprintf(stderr, "M0 asserting RESET to i860 %s\n", device->tag()); - i860_set_pin(device, DEC_PIN_RESET, 1); + device->i860_set_pin(DEC_PIN_RESET, 1); } else - i860_set_pin(device, DEC_PIN_RESET, 0); + device->i860_set_pin(DEC_PIN_RESET, 0); } WRITE16_MEMBER(vcombat_state::wiggle_i860p0_pins_w) { - wiggle_i860_common(machine().device("vid_0"), data); + wiggle_i860_common(m_vid_0, data); } WRITE16_MEMBER(vcombat_state::wiggle_i860p1_pins_w) { - wiggle_i860_common(machine().device("vid_1"), data); + wiggle_i860_common(m_vid_1, data); } READ16_MEMBER(vcombat_state::main_irqiack_r) @@ -415,15 +419,15 @@ ADDRESS_MAP_END MACHINE_RESET_MEMBER(vcombat_state,vcombat) { - i860_set_pin(machine().device("vid_0"), DEC_PIN_BUS_HOLD, 1); - i860_set_pin(machine().device("vid_1"), DEC_PIN_BUS_HOLD, 1); + m_vid_0->i860_set_pin(DEC_PIN_BUS_HOLD, 1); + m_vid_1->i860_set_pin(DEC_PIN_BUS_HOLD, 1); m_crtc_select = 0; } MACHINE_RESET_MEMBER(vcombat_state,shadfgtr) { - i860_set_pin(machine().device("vid_0"), DEC_PIN_BUS_HOLD, 1); + m_vid_0->i860_set_pin(DEC_PIN_BUS_HOLD, 1); m_crtc_select = 0; } @@ -455,10 +459,10 @@ DRIVER_INIT_MEMBER(vcombat_state,vcombat) UINT8 *ROM = memregion("maincpu")->base(); /* The two i860s execute out of RAM */ - address_space &v0space = machine().device("vid_0")->space(AS_PROGRAM); + address_space &v0space = m_vid_0->space(AS_PROGRAM); v0space.set_direct_update_handler(direct_update_delegate(FUNC(vcombat_state::vcombat_vid_0_direct_handler), this)); - address_space &v1space = machine().device("vid_1")->space(AS_PROGRAM); + address_space &v1space = m_vid_1->space(AS_PROGRAM); v1space.set_direct_update_handler(direct_update_delegate(FUNC(vcombat_state::vcombat_vid_1_direct_handler), this)); /* Allocate the 68000 framebuffers */ @@ -502,7 +506,7 @@ DRIVER_INIT_MEMBER(vcombat_state,shadfgtr) m_i860_framebuffer[1][1] = NULL; /* The i860 executes out of RAM */ - address_space &space = machine().device("vid_0")->space(AS_PROGRAM); + address_space &space = m_vid_0->space(AS_PROGRAM); space.set_direct_update_handler(direct_update_delegate(FUNC(vcombat_state::vcombat_vid_0_direct_handler), this)); }