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https://github.com/holub/mame
synced 2025-04-22 16:31:49 +03:00
- Added iack by reading rr2
- z80daisy_iack now returns -1 when no vector found or disabled through the WR9 VIS - Removed z80daisy_reti code to match SCC documentation - Removed defacto reset values where possible and replaced them with documented SCC reset values
This commit is contained in:
Joakim Larsson Edstrom
parent
28eb675b67
commit
a7264b1ce3
@ -56,7 +56,7 @@ DONE (x) (p=partly) NMOS CMOS ESCC EMSCC
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x SWI ack feat N Y Y Y
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higher bps w ext DPLL N 32Mbps 32Mbps 32Mbps
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-- Additional features 85C30 -------------------------------------------
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New WR7 feat N 85C30 Y Y
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x New WR7 feat N 85C30 Y Y
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Improved SDLC N 85C30 Y Y
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Improved reg handl N 85C30 Y Y
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Improved auto feat N 85C30 Y Y
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@ -83,7 +83,7 @@ DONE (x) (p=partly) NMOS CMOS ESCC EMSCC
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#define LOG(x) {}
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#define LOGR(x) {}
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#define LOGSETUP(x) LOGPRINT(x)
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#define LOGINT(x) {}
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#define LOGINT(x) {} LOGPRINT(x)
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#define LOGRCV(x){}
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#if VERBOSE == 2
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#define logerror printf
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@ -298,22 +298,21 @@ that pulls IEO Low. This selectively deactivates parts of the daisy chain regard
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int z80scc_device::z80daisy_irq_state()
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{
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int state = 0;
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int i;
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LOG(("%s %s A:%d%d%d B:%d%d%d ",tag(), FUNCNAME,
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m_int_state[0], m_int_state[1], m_int_state[2],
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m_int_state[3], m_int_state[4], m_int_state[5]));
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// loop over all interrupt sources
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for (i = 0; i < 6; i++)
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for (auto & elem : m_int_state)
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{
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// if we're servicing a request, don't indicate more interrupts
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if (m_int_state[i] & Z80_DAISY_IEO)
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if (elem & Z80_DAISY_IEO)
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{
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state |= Z80_DAISY_IEO;
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break;
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}
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state |= m_int_state[i];
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state |= elem;
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}
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// Last chance to keep the control of the interrupt line
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@ -331,30 +330,31 @@ int z80scc_device::z80daisy_irq_state()
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int z80scc_device::z80daisy_irq_ack()
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{
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int i;
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LOG(("%s %s - needs fixing for SCC\n",tag(), FUNCNAME));
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// loop over all interrupt sources
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for (i = 0; i < 6; i++)
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for (auto & elem : m_int_state)
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{
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// find the first channel with an interrupt requested
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if (m_int_state[i] & Z80_DAISY_INT)
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if (elem & Z80_DAISY_INT)
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{
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// clear interrupt, switch to the IEO state, and update the IRQs
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m_int_state[i] = Z80_DAISY_IEO;
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//m_chanA->m_rr0 &= ~z80scc_channel::RR0_INTERRUPT_PENDING;
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elem = Z80_DAISY_IEO; // Set IUS bit (called IEO in z80 daisy lingo)
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check_interrupts();
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//LOG(("%s %s : Interrupt Acknowledge Vector %02x\n",tag(), FUNCNAME, m_chanB->m_rr2));
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return m_chanB->m_rr2;
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LOGINT((" - Found an INT request, "));
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if (m_wr9 & z80scc_channel::WR9_BIT_VIS)
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{
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LOGINT(("but WR9 D1 set to use autovector, returning -1\n"));
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return -1;
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}
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else
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{
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LOGINT(("returning RR2: %02x\n", m_chanB->m_rr2 ));
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return m_chanB->m_rr2;
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}
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}
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}
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//logerror("z80scc_irq_ack: failed to find an interrupt to ack!\n");
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return m_chanB->m_rr2;
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return -1;
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}
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@ -362,35 +362,14 @@ int z80scc_device::z80daisy_irq_ack()
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// z80daisy_irq_reti - return from interrupt
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//-------------------------------------------------
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/*
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SCC Interrupt Daisy-Chain Operation
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"SCC Interrupt Daisy-Chain Operation
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In the SCC, the IUS bit normally controls the state of the IEO line. The IP bit affects the daisy
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chain only during an Interrupt Acknowledge cycle. Since the IP bit is normally not part of the SCC
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interrupt daisy chain, there is no need to decode the RETI instruction. To allow for control over the
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daisy chain, the SCC has a Disable Lower Chain (DLC) software command (WR9 bit 2) that pulls IEO Low.
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TODO: investigate removal of z80daisy_irq_reti() and rely entirely on rom software to activate IEO as SCC does
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daisy chain, the SCC has a Disable Lower Chain (DLC) software command (WR9 bit 2) that pulls IEO Low."
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*/
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void z80scc_device::z80daisy_irq_reti()
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{
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int i;
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LOG(("%s %s \n",tag(), FUNCNAME));
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// loop over all interrupt sources
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for (i = 0; i < 6; i++)
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{
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// find the first channel with an IEO pending
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if (m_int_state[i] & Z80_DAISY_IEO)
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{
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// clear the IEO state and update the IRQs
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m_int_state[i] &= ~Z80_DAISY_IEO;
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check_interrupts();
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return;
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}
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}
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//logerror("z80scc_irq_reti: failed to find an interrupt to clear IEO on!\n");
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}
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@ -914,12 +893,12 @@ void z80scc_channel::device_reset()
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receive_register_reset();
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transmit_register_reset();
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// Soft/Channel Reset values according to SCC users manual
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// Soft/Channel Reset values (mostly) according to SCC users manual
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m_wr0 = 0x00;
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m_wr1 &= 0x24;
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m_wr3 &= 0x01;
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m_wr4 |= 0x04;
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m_wr5 &= 0x61;
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m_wr4 = 0x04;
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m_wr5 = 0x00;
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if (m_uart->m_variant & (z80scc_device::TYPE_SCC85C30 | SET_ESCC))
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m_wr7 = 0x20;
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// WR9,WR10,WR11 and WR14 has a different hard reset (see z80scc_device::device_reset()) values
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@ -932,24 +911,14 @@ void z80scc_channel::device_reset()
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m_rr0 &= 0xfc;
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m_rr0 |= 0x44;
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m_rr1 &= 0x07;
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m_rr1 |= 0x06;
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m_rr1 |= 0x06; // Required reset value
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m_rr1 |= RR1_ALL_SENT; // It is a don't care in the SCC user manual but drivers hangs without it set
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m_rr3 = 0x00;
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m_rr10 &= 0x40;
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#if 1 // old reset code
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// disable receiver
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m_wr3 &= ~WR3_RX_ENABLE;
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// disable transmitter
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m_wr5 &= ~WR5_TX_ENABLE;
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m_rr0 |= RR0_TX_BUFFER_EMPTY;
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#endif
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// TODO: check dependencies on RR1_ALL_SENT and (re)move this setting
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m_rr1 |= RR1_ALL_SENT; // It is a don't care in the SCC user manual
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// reset external lines TODO: check relation to control bits and reset
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set_rts(1);
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set_dtr(1);
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// reset external lines
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set_rts(m_wr5 & WR5_RTS ? 0 : 1);
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set_dtr(m_wr14 & WR14_DTR_REQ_FUNC ? 0 : (m_wr5 & WR5_DTR ? 0 : 1));
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// reset interrupts
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if (m_index == z80scc_device::CHANNEL_A)
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@ -1283,15 +1252,24 @@ UINT8 z80scc_channel::do_sccreg_rr2()
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// If we are chan B we have to modify the vector regardless of the VIS bit
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if (m_index == z80scc_device::CHANNEL_B)
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{
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int i = 0;
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// loop over all interrupt sources
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for (int i = 0; i < 6; i++)
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for (auto & elem : m_uart->m_int_state)
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{
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// find the first channel with an interrupt requested
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if (m_uart->m_int_state[i] & Z80_DAISY_INT)
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if (elem & Z80_DAISY_INT)
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{
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m_rr2 = m_uart->modify_vector(m_rr2, i < 3 ? z80scc_device::CHANNEL_A : z80scc_device::CHANNEL_B, m_uart->m_int_source[i] & 3);
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if ((m_uart->m_variant & (SET_ESCC | SET_CMOS)) && (m_uart->m_wr9 & WR9_BIT_IACK))
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{
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LOGINT((" - Found an INT request to ack while reading RR2\n"));
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elem = Z80_DAISY_IEO; // Set IUS bit (called IEO in z80 daisy lingo)
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m_uart->check_interrupts();
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}
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break;
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}
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i++;
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}
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}
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return m_rr2;
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@ -1567,7 +1545,9 @@ void z80scc_channel::do_sccreg_wr0_resets(UINT8 data)
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void z80scc_channel::do_sccreg_wr0(UINT8 data)
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{
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m_wr0 = data;
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m_uart->m_wr0_ptrbits = data & WR0_REGISTER_MASK;
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if (m_uart->m_variant & SET_Z85X3X)
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m_uart->m_wr0_ptrbits = data & WR0_REGISTER_MASK;
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/* Sort out SCC specific behaviours from legacy SIO behaviour */
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/* WR0_Z_* are Z80X30 specific commands */
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@ -1660,41 +1640,6 @@ void z80scc_channel::do_sccreg_wr0(UINT8 data)
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m_uart->m_wr0_ptrbits &= ~WR0_REGISTER_MASK;
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m_uart->m_wr0_ptrbits |= (m_wr0 & (WR0_REGISTER_MASK));
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}
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else if ( m_uart->m_variant & SET_Z80X30) // TODO: Implement adress decoding for Z80X30 using the shift logic described below
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{
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/*The registers in the Z80X30 are addressed via the address on AD7-AD0 and are latched by the rising
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edge of /AS. The Shift Right/Shift Left bit in the Channel B WR0 controls which bits are
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decoded to form the register address. It is placed in this register to simplify programming when the
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current state of the Shift Right/Shift Left bit is not known.
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A hardware reset forces Shift Left mode where the address is decoded from AD5-AD1. In Shift
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Right mode, the address is decoded from AD4-AD0. The Shift Right/Shift Left bit is written via a
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command to make the software writing to WR0 independent of the state of the Shift Right/Shift
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Left bit.
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While in the Shift Left mode, the register address is placed on AD4-AD1 and the Channel Select
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bit, A/B, is decoded from AD5. The register map for this case is listed in Table on page 21. In
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Shift Right mode, the register address is again placed on AD4-AD1 but the channel select A/B is
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decoded from AD0. The register map for this case is listed in Table on page 23.
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Because the Z80X30 does not contain 16 read registers, the decoding of the read registers is not
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complete; this is listed in Table on page 21 and Table on page 23 by parentheses around the register
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name. These addresses may also be used to access the read registers. Also, note that the
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Z80X30 contains only one WR2 and WR9; these registers may be written from either channel.
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Shift Left Mode is used when Channel A and B are to be programmed differently. This allows the
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software to sequence through the registers of one channel at a time. The Shift Right Mode is used
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when the channels are programmed the same. By incrementing the address, the user can program
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the same data value into both the Channel A and Channel B register.*/
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switch(data & WR0_Z_SHIFT_MASK)
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{
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case WR0_Z_SEL_SHFT_LEFT:
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LOG(("\"%s\": %c : %s - Shift Left Addressing Mode - not implemented\n", m_owner->tag(), 'A' + m_index, FUNCNAME));
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break;
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case WR0_Z_SEL_SHFT_RIGHT:
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LOG(("\"%s\": %c : %s - Shift Right Addressing Mode - not implemented\n", m_owner->tag(), 'A' + m_index, FUNCNAME));
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break;
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default:
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break;
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// LOG(("\"%s\": %c : %s - Null commands\n", m_owner->tag(), 'A' + m_index, FUNCNAME));
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}
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}
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}
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/* Write Register 1 is the control register for the various SCC interrupt and Wait/Request modes.*/
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@ -1962,7 +1907,6 @@ void z80scc_channel::do_sccreg_wr11(UINT8 data)
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*/
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void z80scc_channel::do_sccreg_wr12(UINT8 data)
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{
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// TODO: Check if BRG enabled already and restart timer with new value in case advice above is not followed by ROM
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m_wr12 = data;
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update_serial();
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LOG(("\"%s\": %c : %s %02x Low byte of Time Constant for Baudrate generator\n", m_owner->tag(), 'A' + m_index, FUNCNAME, data));
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@ -1971,7 +1915,6 @@ void z80scc_channel::do_sccreg_wr12(UINT8 data)
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/* WR13 contains the upper byte of the time constant for the baud rate generator. */
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void z80scc_channel::do_sccreg_wr13(UINT8 data)
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{
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// TODO: Check if BRG enabled already and restart timer with new value in case advice above is not followed by ROM
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m_wr13 = data;
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update_serial();
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LOG(("\"%s\": %c : %s %02x High byte of Time Constant for Baudrate generator\n", m_owner->tag(), 'A' + m_index, FUNCNAME, data));
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