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https://github.com/holub/mame
synced 2025-06-05 20:33:45 +03:00
ns32202: improve interrupt logic
This commit is contained in:
Patrick Mackinlay
parent
01cb8abbd0
commit
a733cc701c
@ -124,6 +124,9 @@ void ns32202_device::device_reset()
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m_ips = 0xff;
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m_pdir = 0xff;
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m_cictl = 0;
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set_int(false);
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set_cout(false);
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}
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void ns32202_device::set_int(bool int_state)
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@ -205,12 +208,17 @@ template <unsigned Number> void ns32202_device::ir_w(int state)
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{
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// level triggered
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if (state == BIT(m_tpl, Number))
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m_ipnd |= mask;
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{
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if (!(m_mctl & MCTL_FRZ))
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m_ipnd |= mask;
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}
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else
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m_ipnd &= ~mask;
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}
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else
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{
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// TODO: freeze bit MCTL_FRZ causes delayed edge-triggered recognition?
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// edge triggered
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if (bool(state) == BIT(m_tpl, Number) && bool(state) ^ BIT(m_line_state, Number))
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m_ipnd |= mask;
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@ -254,57 +262,54 @@ template void ns32202_device::ir_w<15>(int state);
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*/
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void ns32202_device::interrupt(s32 param)
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{
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// check for unmasked pending interrupts
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if (!(m_ipnd & ~m_imsk))
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return;
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bool int_state = false;
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if (m_mctl & MCTL_NTAR)
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// check for unmasked pending interrupts
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if (m_ipnd & ~m_imsk)
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{
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// fixed priority mode
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bool accept = false;
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// check any interrupts in-service
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if (m_isrv)
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if (m_mctl & MCTL_NTAR)
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{
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// check interrupts in descending priority order
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u16 mask = m_fprt;
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for (unsigned i = 0; i < 16; i++)
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// check any interrupts in-service
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if (m_isrv)
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{
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// check interrupt in-service
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if (m_isrv & mask)
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// check interrupts in descending priority order
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u16 mask = m_fprt;
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for (unsigned i = 0; i < 16; i++)
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{
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// check equal priority unmasked pending cascade interrupt
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if ((m_csrc & mask) && (m_ipnd & mask) && !(m_imsk & mask))
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// check interrupt in-service
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if (m_isrv & mask)
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{
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LOGMASKED(LOG_STATE, "unmasked pending cascade in-service interrupt %d\n", 31 - count_leading_zeros_32(mask));
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accept = true;
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// check equal priority unmasked pending cascade interrupt
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if ((m_csrc & mask) && (m_ipnd & mask) && !(m_imsk & mask))
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{
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LOGMASKED(LOG_STATE, "unmasked pending cascade in-service interrupt %d\n", 31 - count_leading_zeros_32(mask));
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int_state = true;
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}
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break;
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}
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break;
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}
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// check unmasked pending interrupt
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if ((m_ipnd & mask) && !(m_imsk & mask))
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{
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LOGMASKED(LOG_STATE, "unmasked pending interrupt %d\n", 31 - count_leading_zeros_32(mask));
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int_state = true;
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break;
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}
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// check unmasked pending interrupt
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if ((m_ipnd & mask) && !(m_imsk & mask))
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{
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LOGMASKED(LOG_STATE, "unmasked pending interrupt %d\n", 31 - count_leading_zeros_32(mask));
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accept = true;
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break;
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// rotate priority mask
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mask = (mask << 1) | (mask >> 15);
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}
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// rotate priority mask
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mask = (mask << 1) | (mask >> 15);
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}
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else
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int_state = true;
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}
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else
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accept = true;
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if (!accept)
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return;
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else if (!m_isrv)
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int_state = true;
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}
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else if (m_isrv)
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return;
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set_int(true);
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set_int(int_state);
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}
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u8 ns32202_device::interrupt_acknowledge(bool side_effects)
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@ -341,8 +346,9 @@ u8 ns32202_device::interrupt_acknowledge(bool side_effects)
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// mark interrupt in-service
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m_isrv |= mask;
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// clear interrupt pending
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m_ipnd &= ~(mask);
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// clear interrupt pending (only if edge-triggered or internal)
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if (!(m_eltg & mask) || ((m_line_state ^ m_tpl) & mask))
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m_ipnd &= ~mask;
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// clear l-counter interrupt pending
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if ((m_cictl & CICTL_CIEL) && (m_cictl & CICTL_CIRL) && BIT(mask, m_ciptr & 15))
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@ -351,9 +357,6 @@ u8 ns32202_device::interrupt_acknowledge(bool side_effects)
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// clear h-counter interrupt pending
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if ((m_cictl & CICTL_CIEH) && (m_cictl & CICTL_CIRH) && BIT(mask, m_ciptr >> 4))
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m_cictl &= ~CICTL_CIRH;
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// clear interrupt output
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set_int(false);
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}
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// compute acknowledge vector
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@ -379,8 +382,13 @@ u8 ns32202_device::interrupt_acknowledge(bool side_effects)
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}
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if (side_effects)
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{
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LOGMASKED(LOG_STATE, "acknowledge vector 0x%02x\n", vector);
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// clear interrupt output
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set_int(false);
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}
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return vector;
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}
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@ -571,6 +579,7 @@ template <unsigned ST1, bool SideEffects> u8 ns32202_device::hvct_r()
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void ns32202_device::eltgl_w(u8 data)
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{
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LOGMASKED(LOG_REGW, "eltgl_w 0x%02x (%s)\n", data, machine().describe_context());
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m_eltg = (m_eltg & 0xff00) | data;
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interrupt_update();
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@ -578,6 +587,7 @@ void ns32202_device::eltgl_w(u8 data)
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void ns32202_device::eltgh_w(u8 data)
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{
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LOGMASKED(LOG_REGW, "eltgh_w 0x%02x (%s)\n", data, machine().describe_context());
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m_eltg = (u16(data) << 8) | u8(m_eltg);
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interrupt_update();
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@ -620,35 +630,55 @@ void ns32202_device::csrch_w(u8 data)
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void ns32202_device::ipndl_w(u8 data)
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{
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if (BIT(data, 6))
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// clear all pending interrupts in register
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{
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// clear all pending interrupts
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LOGMASKED(LOG_REGW, "ipndl_w 0x%02x clear all pending interrupts (%s)\n", data, machine().describe_context());
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m_ipnd &= 0xff00;
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}
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else if (BIT(data, 7))
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{
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// set interrupt
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m_ipnd |= 1 << (data & 7);
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// set pending interrupt
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LOGMASKED(LOG_REGW, "ipndl_w 0x%02x set pending interrupt %d (%s)\n", data, data & 15, machine().describe_context());
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m_interrupt->adjust(attotime::zero);
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m_ipnd |= 1 << (data & 15);
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}
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else
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// clear interrupt
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m_ipnd &= ~(1 << (data & 7));
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{
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// clear pending interrupt
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LOGMASKED(LOG_REGW, "ipndl_w 0x%02x clear pending interrupt %d (%s)\n", data, data & 15, machine().describe_context());
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m_ipnd &= ~(1 << (data & 15));
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}
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m_interrupt->adjust(attotime::zero);
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}
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void ns32202_device::ipndh_w(u8 data)
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{
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if (BIT(data, 6))
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// clear all pending interrupts in register
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{
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// clear all pending interrupts
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LOGMASKED(LOG_REGW, "ipndh_w 0x%02x clear all pending interrupts (%s)\n", data, machine().describe_context());
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m_ipnd &= 0x00ff;
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}
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else if (BIT(data, 7))
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{
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// set interrupt
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m_ipnd |= 256 << (data & 7);
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// set pending interrupt
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LOGMASKED(LOG_REGW, "ipndh_w 0x%02x set pending interrupt %d (%s)\n", data, data & 15, machine().describe_context());
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m_interrupt->adjust(attotime::zero);
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m_ipnd |= 1 << (data & 15);
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}
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else
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// clear interrupt
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m_ipnd &= ~(256 << (data & 7));
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{
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// clear pending interrupt
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LOGMASKED(LOG_REGW, "ipndh_w 0x%02x clear pending interrupt %d (%s)\n", data, data & 15, machine().describe_context());
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m_ipnd &= ~(1 << (data & 15));
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}
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m_interrupt->adjust(attotime::zero);
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}
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void ns32202_device::fprtl_w(u8 data)
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@ -726,6 +756,7 @@ template <unsigned N> void ns32202_device::ccvh_w(u8 data)
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void ns32202_device::mctl_w(u8 data)
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{
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LOGMASKED(LOG_REGW, "mctl_w 0x%02x (%s)\n", data, machine().describe_context());
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if (!(m_mctl & MCTL_CFRZ) && (data & MCTL_CFRZ))
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update_ccv();
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