mirror of
https://github.com/holub/mame
synced 2025-04-22 16:31:49 +03:00
-newport: Added Display Control Bus timeout. Prevents Presenter board from being erroneously detected. [Ryan Holtz]
-sgi_mc: Fixed VDMA TLB which caused corrupt bitmap transfers. [Ryan Holtz]
This commit is contained in:
mooglyguy
MooglyGuy
parent
bef9f293b6
commit
a7e4e9b676
@ -40,7 +40,7 @@
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#define LOG_REJECTS (1 << 8)
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#define LOG_ALL (LOG_UNKNOWN | LOG_VC2 | LOG_CMAP0 | LOG_CMAP1 | LOG_XMAP0 | LOG_XMAP1 | LOG_REX3 | LOG_COMMANDS | LOG_REJECTS)
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#define VERBOSE (0)
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#define VERBOSE (0)//(LOG_REX3 | LOG_COMMANDS)
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#include "logmacro.h"
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DEFINE_DEVICE_TYPE(GIO_XL8, gio_xl8_device, "gio_xl8", "SGI 8-bit XL board")
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@ -79,6 +79,8 @@ void newport_base_device::device_start()
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m_cid = make_unique_clear<uint32_t[]>((1280+64) * (1024+64));
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m_vt_table = make_unique_clear<uint32_t[]>(2048 * 2048);
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m_dcb_timeout_timer = timer_alloc(DCB_TIMEOUT);
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save_pointer(NAME(m_rgbci), (1280+64) * (1024+64));
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save_pointer(NAME(m_olay), (1280+64) * (1024+64));
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save_pointer(NAME(m_pup), (1280+64) * (1024+64));
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@ -283,6 +285,14 @@ void newport_base_device::stop_logging()
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}
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#endif
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void newport_base_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
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{
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if (id == DCB_TIMEOUT)
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{
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m_rex3.m_status &= ~STATUS_BACKBUSY;
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}
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}
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uint8_t newport_base_device::get_cursor_pixel(int x, int y)
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{
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if (x < 0 || y < 0)
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@ -1302,7 +1312,7 @@ WRITE_LINE_MEMBER(newport_base_device::vblank_w)
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{
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if (BIT(m_vc2.m_display_ctrl, 0))
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{
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m_rex3.m_status |= 0x20;
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m_rex3.m_status |= STATUS_VRINT;
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m_gio->get_hpc3()->raise_local_irq(1, ioc2_device::INT3_LOCAL1_RETRACE);
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}
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}
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@ -1612,21 +1622,36 @@ READ64_MEMBER(newport_base_device::rex3_r)
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{
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switch (m_rex3.m_dcb_slave_select)
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{
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case 0x00:
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case DCB_ADDR_VC2:
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ret |= (uint64_t)vc2_read() << 32;
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break;
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case 0x02:
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case DCB_ADDR_CMAP0:
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ret |= (uint64_t)cmap0_read() << 32;
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break;
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case 0x03:
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case DCB_ADDR_CMAP1:
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ret |= (uint64_t)cmap1_read() << 32;
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break;
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case 0x05:
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case DCB_ADDR_XMAP0:
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ret |= (uint64_t)xmap0_read() << 32;
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break;
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case 0x06:
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case DCB_ADDR_XMAP1:
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ret |= (uint64_t)xmap1_read() << 32;
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break;
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case DCB_ADDR_RAMDAC:
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LOGMASKED(LOG_REX3, "REX3 Display Control Bus Data MSW Read from RAMDAC (not yet implemented)\n");
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break;
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case DCB_ADDR_CC1:
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LOGMASKED(LOG_REX3, "REX3 Display Control Bus Data MSW Read from CC1 (not yet implemented)\n");
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break;
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case DCB_ADDR_AB1:
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LOGMASKED(LOG_REX3, "REX3 Display Control Bus Data MSW Read from AB1 (not yet implemented)\n");
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break;
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case DCB_ADDR_PCD:
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LOGMASKED(LOG_REX3, "REX3 Display Control Bus Data MSW Read from PCD (not yet implemented)\n");
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// Presenter not connected; simulate a bus timeout
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m_rex3.m_status |= STATUS_BACKBUSY;
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m_dcb_timeout_timer->adjust(attotime::from_msec(1));
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break;
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default:
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LOGMASKED(LOG_REX3, "REX3 Display Control Bus Data MSW Read: %08x\n", m_rex3.m_dcb_data_msw);
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ret |= (uint64_t)m_rex3.m_dcb_data_msw << 32;
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@ -1723,7 +1748,7 @@ READ64_MEMBER(newport_base_device::rex3_r)
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{
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LOGMASKED(LOG_REX3, "REX3 Status Read: %08x\n", m_rex3.m_status);
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uint32_t old_status = m_rex3.m_status;
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m_rex3.m_status = 0;
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m_rex3.m_status &= ~STATUS_VRINT;
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m_gio->get_hpc3()->lower_local_irq(1, ioc2_device::INT3_LOCAL1_RETRACE);
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ret |= (uint64_t)(old_status | 3) << 32;
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}
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@ -3727,22 +3752,44 @@ WRITE64_MEMBER(newport_base_device::rex3_w)
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m_rex3.m_dcb_data_msw = data32;
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switch (m_rex3.m_dcb_slave_select)
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{
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case 0x00:
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case DCB_ADDR_VC2:
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vc2_write(data32);
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break;
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case 0x01:
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case DCB_ADDR_CMAP01:
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cmap0_write(data32);
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//cmap1_write(data32);
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break;
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case DCB_ADDR_CMAP0:
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cmap0_write(data32);
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break;
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case 0x04:
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case DCB_ADDR_CMAP1:
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//cmap1_write(data32);
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break;
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case DCB_ADDR_XMAP01:
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xmap0_write(data32);
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xmap1_write(data32);
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break;
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case 0x05:
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case DCB_ADDR_XMAP0:
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xmap0_write(data32);
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break;
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case 0x06:
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case DCB_ADDR_XMAP1:
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xmap1_write(data32);
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break;
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case DCB_ADDR_RAMDAC:
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LOGMASKED(LOG_REX3, "REX3 Display Control Bus Data MSW Write to RAMDAC (not yet implemented): %08x\n", data32);
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break;
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case DCB_ADDR_CC1:
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LOGMASKED(LOG_REX3, "REX3 Display Control Bus Data MSW Write to CC1 (not yet implemented): %08x\n", data32);
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break;
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case DCB_ADDR_AB1:
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LOGMASKED(LOG_REX3, "REX3 Display Control Bus Data MSW Write to AB1 (not yet implemented): %08x\n", data32);
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break;
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case DCB_ADDR_PCD:
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LOGMASKED(LOG_REX3, "REX3 Display Control Bus Data MSW Write to PCD (not yet implemented): %08x\n", data32);
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// Presenter not connected; simulate a bus timeout
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m_rex3.m_status |= STATUS_BACKBUSY;
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m_dcb_timeout_timer->adjust(attotime::from_msec(1));
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break;
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default:
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LOGMASKED(LOG_REX3 | LOG_UNKNOWN, "REX3 Display Control Bus Data MSW Write: %08x\n", data32);
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break;
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@ -32,6 +32,7 @@ public:
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DECLARE_WRITE_LINE_MEMBER(vblank_w);
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protected:
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virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override;
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virtual void device_add_mconfig(machine_config &config) override;
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virtual uint32_t palette_entries() const override { return 0x2000; }
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virtual void device_start() override;
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@ -39,6 +40,8 @@ protected:
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void mem_map(address_map &map) override;
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static constexpr device_timer_id DCB_TIMEOUT = 0;
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enum
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{
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DCR_CURSOR_FUNC_ENABLE_BIT = 4,
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@ -53,6 +56,35 @@ protected:
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DCR_CURSOR_SIZE_64 = 1
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};
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enum
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{
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DCB_ADDR_VC2,
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DCB_ADDR_CMAP01,
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DCB_ADDR_CMAP0,
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DCB_ADDR_CMAP1,
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DCB_ADDR_XMAP01,
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DCB_ADDR_XMAP0,
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DCB_ADDR_XMAP1,
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DCB_ADDR_RAMDAC,
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DCB_ADDR_CC1,
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DCB_ADDR_AB1,
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DCB_ADDR_PCD = 12
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};
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enum
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{
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STATUS_GFXBUSY = (1 << 3),
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STATUS_BACKBUSY = (1 << 4),
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STATUS_VRINT = (1 << 5),
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STATUS_VIDEOINT = (1 << 6),
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STATUS_GFIFOLEVEL_SHIFT = 7,
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STATUS_GFIFOLEVEL_MASK = (0x3f << STATUS_GFIFOLEVEL_SHIFT),
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STATUS_BFIFOLEVEL_SHIFT = 13,
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STATUS_BFIFOLEVEL_MASK = (0x1f << STATUS_BFIFOLEVEL_SHIFT),
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STATUS_BFIFO_INT = 18,
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STATUS_GFIFO_INT = 19
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};
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struct vc2_t
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{
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uint16_t m_vid_entry;
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@ -268,6 +300,7 @@ protected:
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std::unique_ptr<uint32_t[]> m_vt_table;
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cmap_t m_cmap0;
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uint32_t m_global_mask;
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emu_timer *m_dcb_timeout_timer;
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int m_readout_x0;
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int m_readout_y0;
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@ -23,7 +23,7 @@
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#define LOG_DMA (1 << 8)
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#define LOG_DEFAULT (LOG_READS | LOG_WRITES | LOG_RPSS | LOG_WATCHDOG | LOG_UNKNOWN)
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#define VERBOSE (0)
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#define VERBOSE (LOG_DMA)
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#include "logmacro.h"
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DEFINE_DEVICE_TYPE(SGI_MC, sgi_mc_device, "sgi_mc", "SGI Memory Controller")
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@ -196,9 +196,9 @@ uint32_t sgi_mc_device::dma_translate(uint32_t address)
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{
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for (int entry = 0; entry < 4; entry++)
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{
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if ((address & 0xffe00000) == (m_dma_tlb_entry_hi[entry] & 0xffe00000))
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if ((address & 0xffc00000) == (m_dma_tlb_entry_hi[entry] & 0xffc00000))
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{
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const uint32_t vpn_lo = (address & 0x001ff000) >> 12;
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const uint32_t vpn_lo = (address & 0x003ff000) >> 12;
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const uint32_t pte = m_space->read_dword(((m_dma_tlb_entry_lo[entry] & 0x003fffc0) << 6) + (vpn_lo << 2));
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const uint32_t offset = address & 0xfff;
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return ((pte & 0x03ffffc0) << 6) + offset;
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@ -207,91 +207,103 @@ uint32_t sgi_mc_device::dma_translate(uint32_t address)
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return 0;
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}
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void sgi_mc_device::dma_tick()
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void sgi_mc_device::dma_immediate()
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{
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uint32_t addr = m_dma_mem_addr;
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if (m_dma_control & (1 << 8))
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{ // Enable virtual address translation
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addr = dma_translate(addr);
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}
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if (m_dma_mode & (1 << 1))
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{ // Graphics to host
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if (m_dma_mode & (1 << 3))
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{ // Fill mode
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m_space->write_dword(addr, m_dma_gio64_addr);
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m_dma_mem_addr += 4;
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m_dma_count -= 4;
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}
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else
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uint32_t memory_addr = m_dma_mem_addr;
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uint32_t linecount = get_line_count();
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uint32_t zoomcount = get_zoom_count();
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uint32_t bytecount = get_byte_count();
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const uint32_t gio_addr = m_dma_gio64_addr;
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const uint32_t linewidth = get_line_width();
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const uint32_t linezoom = get_line_zoom();
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const uint32_t stride = get_stride();
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m_dma_size &= 0x0000ffff;
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m_dma_count = 0;
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while (linecount > 0)
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{
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linecount--;
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while (zoomcount > 0)
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{
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const uint32_t remaining = m_dma_count & 0x0000ffff;
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uint32_t length = 8;
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uint64_t shift = 56;
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if (remaining < 8)
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length = remaining;
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uint64_t data = m_space->read_qword(m_dma_gio64_addr);
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for (uint32_t i = 0; i < length; i++)
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zoomcount--;
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while (bytecount > 0)
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{
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m_space->write_byte(addr, (uint8_t)(data >> shift));
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addr++;
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shift -= 8;
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}
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m_dma_mem_addr += length;
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m_dma_count -= length;
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}
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}
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else
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{ // Host to graphics
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const uint32_t remaining = m_dma_count & 0x0000ffff;
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uint32_t length = 8;
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uint64_t shift = 56;
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if (remaining < 8)
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length = remaining;
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uint64_t data = 0;
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for (uint32_t i = 0; i < length; i++)
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{
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data |= (uint64_t)m_space->read_byte(addr) << shift;
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addr++;
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shift -= 8;
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}
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m_space->write_qword(m_dma_gio64_addr, data);
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m_dma_mem_addr += length;
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m_dma_count -= length;
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}
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if ((m_dma_count & 0x0000ffff) == 0)
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{ // If remaining byte count is 0, deduct zoom count
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m_dma_count -= 0x00010000;
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if (m_dma_count == 0)
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{ // If remaining zoom count is also 0, move to next line
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m_dma_mem_addr += m_dma_stride & 0x0000ffff;
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m_dma_size -= 0x00010000;
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if ((m_dma_size & 0xffff0000) == 0)
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{ // If no remaining lines, DMA is done.
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m_dma_timer->adjust(attotime::never);
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m_dma_run |= (1 << 3);
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m_dma_run &= ~(1 << 6);
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if (BIT(m_dma_control, 4))
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if (m_dma_mode & MODE_TO_HOST)
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{
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m_dma_int_cause |= (1 << 3);
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m_hpc3->raise_local_irq(0, ioc2_device::INT3_LOCAL0_MC_DMA);
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if (m_dma_mode & MODE_FILL)
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{ // Fill mode
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m_space->write_dword(dma_translate(memory_addr), m_dma_gio64_addr);
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if (m_dma_mode & MODE_DIR)
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memory_addr += 4;
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else
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memory_addr -= 4;
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bytecount -= 4;
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}
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else
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{
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uint32_t length = 8;
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uint64_t shift = 56;
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if (bytecount < 8)
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length = bytecount;
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uint64_t data = m_space->read_qword(gio_addr);
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for (uint32_t i = 0; i < length; i++)
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{
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m_space->write_byte(dma_translate(memory_addr), (uint8_t)(data >> shift));
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if (m_dma_mode & MODE_DIR)
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memory_addr++;
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else
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memory_addr--;
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shift -= 8;
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}
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bytecount -= length;
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}
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}
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else
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{
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uint32_t length = 8;
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uint64_t shift = 56;
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if (bytecount < 8)
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length = bytecount;
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uint64_t data = 0;
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for (uint32_t i = 0; i < length; i++)
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{
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data |= (uint64_t)m_space->read_byte(dma_translate(memory_addr)) << shift;
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if (m_dma_mode & MODE_DIR)
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memory_addr++;
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else
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memory_addr--;
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shift -= 8;
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}
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m_space->write_qword(gio_addr, data);
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bytecount -= length;
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}
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}
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else
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bytecount = linewidth;
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if (zoomcount > 0)
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{
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m_dma_count = (m_dma_stride & 0x03ff0000) | (m_dma_size & 0x0000ffff);
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if (m_dma_mode & MODE_DIR)
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memory_addr -= linewidth;
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else
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memory_addr += linewidth;
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}
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}
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else
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{ // If remaining zoom count is non-zero, reload byte count and return source address to the beginning of the line.
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m_dma_count |= m_dma_size & 0x0000ffff;
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m_dma_mem_addr -= m_dma_size & 0x0000ffff;
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}
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zoomcount = linezoom;
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memory_addr += stride;
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}
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m_dma_mem_addr = memory_addr;
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m_dma_timer->adjust(attotime::never);
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m_dma_run |= (1 << 3);
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m_dma_run &= ~(1 << 6);
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if (BIT(m_dma_control, 4))
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{
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m_dma_int_cause |= (1 << 3);
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m_hpc3->raise_local_irq(0, ioc2_device::INT3_LOCAL0_MC_DMA);
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}
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}
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@ -720,9 +732,6 @@ void sgi_mc_device::device_timer(emu_timer &timer, device_timer_id id, int param
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}
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else if (id == TIMER_DMA)
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{
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while (m_dma_run & (1 << 6))
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{
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dma_tick();
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}
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dma_immediate();
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}
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}
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@ -52,8 +52,24 @@ protected:
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static const device_timer_id TIMER_DMA = 1;
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private:
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enum
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{
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MODE_TO_HOST = (1 << 1),
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MODE_SYNC = (1 << 2),
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MODE_FILL = (1 << 3),
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MODE_DIR = (1 << 4),
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MODE_SNOOP = (1 << 5)
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};
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uint32_t dma_translate(uint32_t address);
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void dma_tick();
|
||||
void dma_immediate();
|
||||
|
||||
uint32_t get_line_count() { return m_dma_size >> 16; }
|
||||
uint32_t get_line_width() { return (uint16_t)m_dma_size; }
|
||||
uint32_t get_line_zoom() { return (m_dma_stride >> 16) & 0x3ff; }
|
||||
int16_t get_stride() { return (int16_t)m_dma_stride; }
|
||||
uint32_t get_zoom_count() { return (m_dma_count >> 16) & 0x3ff; }
|
||||
uint32_t get_byte_count() { return (uint16_t)m_dma_count; }
|
||||
|
||||
required_device<cpu_device> m_maincpu;
|
||||
required_device<eeprom_serial_93cxx_device> m_eeprom;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user