diff --git a/src/mame/drivers/lwriter.cpp b/src/mame/drivers/lwriter.cpp index 7cf46040af8..c88b5220ea3 100644 --- a/src/mame/drivers/lwriter.cpp +++ b/src/mame/drivers/lwriter.cpp @@ -1,22 +1,39 @@ // license:BSD-3-Clause -// copyright-holders:Joakim Larsson Edstrom +// copyright-holders:Joakim Larsson Edstrom, Jonathan Gevaryahu /****************************************************************************** Apple LaserWriter II NT driver TODO: - - Figure out what VIA pins is connected to switch on front that selects LocalTalk - - Let the board identify itself to a emulated mac driver so it displays the printer icon on the desktop + - Get the board to pass its self test, it fails long before it even bothers reading the dipswitches + - Hook up SCC and VIA interrupt pins to the 68k + - Hook up the rest of the VIA pins to a canon printer HLE stub + - Hook up ADB bitbang device to the VIA CB1, CB2 and PortA pins + - Hook up VIA Port A, bits 5 and 6 to the SW1 and SW2 panel switches - Everything else + Future: + - Let the board identify itself to a emulated mac driver so it displays the printer icon on the desktop + + Self Test LEDs at 0x800000-800001 most significant nybble: + 0x8 - cpu check? (displayed before the overlay is disabled) + 0xF - 200000-3fffff ROM checksum + 0xE - 400000-400007 Low half of DRAM individual bit tests (walking ones and zeroes) + 0xD - 5ffff8-5fffff High half of DRAM individual bit tests (walking ones and zeroes) + 0xC - 400000-5fffff comprehensive DRAM data test + 0xB - Unknown test + 0xA - dies if something to do with 600000-7fffff doesn't mirror 400000-5fffff ? + 0x8 - Unknown test + + If one of the self tests fails, the uppermost bit will oscillate (c000 4000 c000 4000 etc) forever ******************************************************************************/ /* * Hardware: 68000@11.16 MHz 8530 SCC - 6523 TPI or 6522 VIA on newer pcb:s + 65C22 VIA on newer pcbs (older pcbs might have a 6523/6525 TPI but the pinout is completely different?) 2MB DRAM 2KB SRAM - custom 335-0022 EEPROM + X2804 EEPROM (custom marked as 335-0022) [note that technically a 2808 or 2816 can go here and will work too] 1MB ROM +------------------------------------------------------------------------------------------------------------------------+=====+ @@ -79,9 +96,19 @@ public: , m_maincpu(*this, "maincpu") , m_scc(*this, "scc") , m_via(*this, "via") + , m_overlay(1) { } - DECLARE_READ16_MEMBER (bootvect_r); - DECLARE_WRITE16_MEMBER (bootvect_w); + DECLARE_READ16_MEMBER(bankedarea_r); + DECLARE_WRITE16_MEMBER(bankedarea_w); + DECLARE_WRITE8_MEMBER(led_w); + DECLARE_READ8_MEMBER(via_pa_r); + DECLARE_WRITE8_MEMBER(via_pa_w); + DECLARE_WRITE_LINE_MEMBER(via_ca2_w); + DECLARE_READ8_MEMBER(via_pb_r); + DECLARE_WRITE8_MEMBER(via_pb_w); + DECLARE_WRITE_LINE_MEMBER(via_cb1_w); + DECLARE_WRITE_LINE_MEMBER(via_cb2_w); + DECLARE_WRITE_LINE_MEMBER(via_int_w); virtual void machine_start () override; virtual void machine_reset () override; private: @@ -95,32 +122,89 @@ private: required_device m_via; #endif - // Pointer to System ROMs needed by bootvect_r and masking RAM buffer for post reset accesses - uint16_t *m_sysrom; - uint16_t m_sysram[2]; + // + bool m_overlay; }; +/* +Address maps (x = ignored; * = selects address within this range) +68k address map: +a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 (a0 via UDS/LDS) +* * * PAL16R6 U80 +* * * * * * decoded by pals +0 0 A * * * * * * * * * * * * * * * * * * * * * R ROM +0 0 A 0 0 0 * * * * * * * * * * * * * * * * * * R ROMEN1 +0 0 A 0 0 1 * * * * * * * * * * * * * * * * * * R ROMEN2 +0 0 A 0 1 0 * * * * * * * * * * * * * * * * * * R ROMEN3 +0 0 A 0 1 1 * * * * * * * * * * * * * * * * * * R ROMEN4 +0 0 A 1 x x x x x x x x x x x x x x x x x x x x OPEN BUS +0 1 * * * * * * * * * * * * * * * * * * * * * * RW DRAM +1 0 0 ? ? ? x x x x x x x x x x x x x x x x x 1 W Status LEDs and mech +1 0 1 ? ? ? x x x x x x x x x x x x x x x * * 1 R 8530 SCC Read +1 1 0 ? ? ? x x x x x x x x x x x x x x x * * 0 W 8530 SCC Write +1 1 1 ?x? ?0? ? x x x x x x x x x x x x x * * * * 0 RW 65C22 VIA +1 1 1 ?x? ?1? ? x x x x x x x x x x x x x * * * * 0 RW debugger rom/pod area +TODO: +? ? ? ? ? ? x x x x x x * * * * * * * * * * * * RW SRAM +? ? ? ? ? ? x x x x x x (*) (*) * * * * * * * * * 1 RW 2804 EEPROM + (technically a10 and a11 are ignored, but if a 2808 or 2816 is put in this spot the address lines do connect to the appropriate pins) + | | | | | +map when overlay is set, i.e. A above is considered 'x': +000000-1fffff ROM (second half is open bus) +200000-3fffff ROM (second half is open bus) +400000-5fffff DRAM? +600000-7fffff unknown +800000-83ffff LEDs and status bits to printer mechanism +840000-9fffff unknown +a00000-a3ffff SCC read +a40000-bfffff unknown +c00000-c3ffff SCC write +c40000-dfffff unknown +e00000-e3ffff VIA +e40000-f7ffff unknown +f80000-fbffff debug area (first read must be 0xAAAA5555, then 68k will jump to address of second read) +fc0000-ffffff unknown + +map when overlay is clear, i.e. A above is considered '1': +000000-1fffff unknown, maybe RAM???? maybe eeprom goes here too? eeprom is specifically disabled when overlay is set +200000-3fffff ROM (second half is open bus) +400000-5fffff DRAM? +600000-7fffff unknown +800000-83ffff LEDs and status bits to printer mechanism +840000-9fffff unknown +a00000-a3ffff SCC read +a40000-bfffff unknown +c00000-c3ffff SCC write +c40000-dfffff unknown +e00000-e3ffff VIA +e40000-f7ffff unknown +f80000-fbffff unknown +fc0000-ffffff unknown + +The ADB bitbang transceiver connects to the +*/ + static ADDRESS_MAP_START (maincpu_map, AS_PROGRAM, 16, lwriter_state) ADDRESS_MAP_UNMAP_HIGH - AM_RANGE(0x00000000, 0x00000007) AM_ROM AM_READ(bootvect_r) /* ROM mirror just during reset */ - AM_RANGE(0x00000000, 0x00000007) AM_RAM AM_WRITE(bootvect_w) /* After first write we act as RAM */ - AM_RANGE(0x00000008, 0x001fffff) AM_RAM /* 2 Mb DRAM */ - AM_RANGE(0x00200000, 0x003fffff) AM_ROM AM_REGION("roms", 0) + AM_RANGE(0x000000, 0x1fffff) AM_READWRITE(bankedarea_r, bankedarea_w) + AM_RANGE(0x200000, 0x2fffff) AM_ROM AM_REGION("rom", 0) // 1MB ROM + //AM_RANGE(0x300000, 0x3fffff) // open bus? + AM_RANGE(0x400000, 0x5fffff) AM_RAM AM_REGION("mainram", 0) AM_MIRROR(0x200000) // 2MB DRAM; the AM_MIRROR is probably wrong, but it gets the selftest to failing on test 08 instead of 0A + AM_RANGE(0x800000, 0x800001) AM_WRITE8(led_w, 0xff00) AM_MIRROR(0x1ffffe) // mirror is a guess given that the pals can only decode A18-A23 + AM_RANGE(0xc00000, 0xc00001) AM_DEVWRITE8("scc", scc8530_device, ca_w, 0x00ff) AM_MIRROR(0x1ffff8) + AM_RANGE(0xc00004, 0xc00005) AM_DEVWRITE8("scc", scc8530_device, da_w, 0x00ff) AM_MIRROR(0x1ffff8) + AM_RANGE(0xa00000, 0xa00001) AM_DEVREAD8 ("scc", scc8530_device, ca_r, 0xff00) AM_MIRROR(0x1ffff8) + AM_RANGE(0xa00004, 0xa00005) AM_DEVREAD8 ("scc", scc8530_device, da_r, 0xff00) AM_MIRROR(0x1ffff8) - AM_RANGE(0x00c00000, 0x00c00001) AM_DEVWRITE8("scc", scc8530_device, ca_w, 0x00ff) - AM_RANGE(0x00c00004, 0x00c00005) AM_DEVWRITE8("scc", scc8530_device, da_w, 0x00ff) - AM_RANGE(0x00a00000, 0x00a00001) AM_DEVREAD8 ("scc", scc8530_device, ca_r, 0xff00) - AM_RANGE(0x00a00004, 0x00a00005) AM_DEVREAD8 ("scc", scc8530_device, da_r, 0xff00) - - AM_RANGE(0x00c00002, 0x00c00003) AM_DEVWRITE8("scc", scc8530_device, cb_w, 0x00ff) - AM_RANGE(0x00c00006, 0x00c00007) AM_DEVWRITE8("scc", scc8530_device, db_w, 0x00ff) - AM_RANGE(0x00a00002, 0x00a00003) AM_DEVREAD8 ("scc", scc8530_device, cb_r, 0xff00) - AM_RANGE(0x00a00006, 0x00a00007) AM_DEVREAD8 ("scc", scc8530_device, db_r, 0xff00) + AM_RANGE(0xc00002, 0xc00003) AM_DEVWRITE8("scc", scc8530_device, cb_w, 0x00ff) AM_MIRROR(0x1ffff8) + AM_RANGE(0xc00006, 0xc00007) AM_DEVWRITE8("scc", scc8530_device, db_w, 0x00ff) AM_MIRROR(0x1ffff8) + AM_RANGE(0xa00002, 0xa00003) AM_DEVREAD8 ("scc", scc8530_device, cb_r, 0xff00) AM_MIRROR(0x1ffff8) + AM_RANGE(0xa00006, 0xa00007) AM_DEVREAD8 ("scc", scc8530_device, db_r, 0xff00) AM_MIRROR(0x1ffff8) #if TPI - AM_RANGE(0x00e00010, 0x00e0001f) AM_DEVREADWRITE8 ("tpi", tpi6523_device, read, write, 0x00ff) // Used on older boards, needs proper mapping + AM_RANGE(0xe00010, 0xe0001f) AM_DEVREADWRITE8 ("tpi", tpi6523_device, read, write, 0x00ff) AM_MIRROR(0x17ffe0) // Used on older boards, needs proper mapping #else - AM_RANGE(0x00e00000, 0x00e0001f) AM_DEVREADWRITE8 ("via", via6522_device, read, write, 0x00ff) + AM_RANGE(0xe00000, 0xe0001f) AM_DEVREADWRITE8 ("via", via6522_device, read, write, 0x00ff) AM_MIRROR(0x17ffe0) #endif ADDRESS_MAP_END @@ -130,26 +214,90 @@ INPUT_PORTS_END /* Start it up */ void lwriter_state::machine_start() { - /* Setup pointer to bootvector in ROM for bootvector handler bootvect_r */ - m_sysrom = (uint16_t*)(memregion ("roms")->base ()); + // do stuff here later on like setting up printer mechanisms HLE timers etc } -void lwriter_state::machine_reset () +void lwriter_state::machine_reset() { - /* Reset pointer to bootvector in ROM for bootvector handler bootvect_r */ - if (m_sysrom == &m_sysram[0]) /* Condition needed because memory map is not setup first time */ - m_sysrom = (uint16_t*)(memregion ("roms")->base ()); + /* Reset the VIA */ + m_via->reset(); } -/* Boot vector handler, the PCB hardwires the first 8 bytes from 0xff800000 to 0x0 at reset*/ -READ16_MEMBER (lwriter_state::bootvect_r){ - return m_sysrom[offset]; +/* 4 diagnostic LEDs, plus 4 i/o lines for the printer */ +WRITE8_MEMBER(lwriter_state::led_w) +{ + //popmessage("LED status: %02X\n", data&0xFF); + logerror("LED status: %02X\n", data&0xFF); + popmessage("LED status: %x %x %x %x %x %x %x %x\n", data&0x80, data&0x40, data&0x20, data&0x10, data&0x8, data&0x4, data&0x2, data&0x1); } -WRITE16_MEMBER (lwriter_state::bootvect_w){ - m_sysram[offset % sizeof(m_sysram)] &= ~mem_mask; - m_sysram[offset % sizeof(m_sysram)] |= (data & mem_mask); - m_sysrom = &m_sysram[0]; // redirect all upcomming accesses to masking RAM until reset. +/* via stuff */ +// second via +READ8_MEMBER(lwriter_state::via_pa_r) +{ + logerror(" VIA: Port A read!\n"); + return 0xFF; +} + +WRITE8_MEMBER(lwriter_state::via_pa_w) +{ + logerror(" VIA: Port A written with data of 0x%02x!\n", data); +} + +WRITE_LINE_MEMBER(lwriter_state::via_ca2_w) +{ + logerror(" VIA: CA2 written with %d!\n", state); +} + +READ8_MEMBER(lwriter_state::via_pb_r) +{ + logerror(" VIA: Port B read!\n"); + return 0xFF; +} + +WRITE8_MEMBER(lwriter_state::via_pb_w) +{ + logerror(" VIA: Port B written with data of 0x%02x!\n", data); + m_overlay = BIT(data,3); +} + +WRITE_LINE_MEMBER (lwriter_state::via_cb1_w) +{ + logerror(" VIA: CB1 written with %d!\n", state); +} + +WRITE_LINE_MEMBER(lwriter_state::via_cb2_w) +{ + logerror(" VIA: CB2 written with %d!\n", state); +} + +WRITE_LINE_MEMBER(lwriter_state::via_int_w) +{ + logerror(" VIA: INT output set to %d!\n", state); +} + +READ16_MEMBER(lwriter_state::bankedarea_r) +{ + uint16_t *rom = (uint16_t *)(memregion("rom")->base()); + //uint16_t *ram = (uint16_t *)(memregion("mainram")->base()); + if (m_overlay == 1) + { + rom += (offset&0x1fffff); + return *rom; + } + else + { + // what actually maps here? the sram and eeprom? + //ram += (offset&0x1fffff); + //return *ram; + return 0xFFFF; /** TODO: fix me */ + } +} + +WRITE16_MEMBER (lwriter_state::bankedarea_w) +{ + uint16_t *ram = (uint16_t *)(memregion("mainram")->base()); + COMBINE_DATA(&ram[offset]); } #define CPU_CLK (XTAL_22_3210MHz / 2) // Based on pictures form here: http://picclick.co.uk/Apple-Postscript-LaserWriter-IINT-Printer-640-4105-M6009-Mainboard-282160713108.html#&gid=1&pid=7 @@ -180,6 +328,14 @@ static MACHINE_CONFIG_START( lwriter, lwriter_state ) MCFG_DEVICE_ADD("tpi", TPI6525, 0) #else MCFG_DEVICE_ADD("via", VIA6522, 0) + MCFG_VIA6522_READPA_HANDLER(READ8(lwriter_state, via_pa_r)) + MCFG_VIA6522_READPB_HANDLER(READ8(lwriter_state, via_pb_r)) + MCFG_VIA6522_WRITEPA_HANDLER(WRITE8(lwriter_state, via_pa_w)) + MCFG_VIA6522_WRITEPB_HANDLER(WRITE8(lwriter_state, via_pb_w)) + MCFG_VIA6522_CB1_HANDLER(WRITELINE(lwriter_state, via_cb1_w)) + MCFG_VIA6522_CA2_HANDLER(WRITELINE(lwriter_state, via_ca2_w)) + MCFG_VIA6522_CB2_HANDLER(WRITELINE(lwriter_state, via_cb2_w)) + MCFG_VIA6522_IRQ_HANDLER(WRITELINE(lwriter_state, via_int_w)) #endif MACHINE_CONFIG_END @@ -214,9 +370,9 @@ MACHINE_CONFIG_END * - last three loops */ -ROM_START(lwriter) - ROM_REGION16_BE (0x1000000, "roms", 0) +ROM_START(lwriter) + ROM_REGION16_BE (0x1000000, "rom", 0) ROM_LOAD16_BYTE ("342-0545.l0", 0x000001, 0x20000, CRC (6431742d) SHA1 (040bd5b84b49b86f2b0fe9ece378bbc7a10a94ec)) ROM_LOAD16_BYTE ("342-0546.h0", 0x000000, 0x20000, CRC (c592bfb7) SHA1 (b595ae225238f7fabd1566a3133ea6154e082e2d)) ROM_LOAD16_BYTE ("342-0547.l1", 0x040001, 0x20000, CRC (205a5ea8) SHA1 (205fefbb5c67a07d57cb6184c69648321a34a8fe)) @@ -225,6 +381,8 @@ ROM_START(lwriter) ROM_LOAD16_BYTE ("342-0550.h2", 0x080000, 0x20000, CRC (82adcf85) SHA1 (e2ab728afdae802c0c67fc25c9ba278b9cb04e31)) ROM_LOAD16_BYTE ("342-0551.l3", 0x0c0001, 0x20000, CRC (176b3346) SHA1 (eb8dfc7e44f2bc884097e51a47e2f10ee091c9e9)) ROM_LOAD16_BYTE ("342-0552.h3", 0x0c0000, 0x20000, CRC (69b175c6) SHA1 (a84c82be1ec7e373bb097ee74b941920a3b091aa)) + ROM_REGION( 0x200000, "mainram", ROMREGION_ERASEFF ) + ROM_END /* YEAR NAME PARENT COMPAT MACHINE INPUT INIT, COMPANY, FULLNAME, FLAGS */