mirror of
https://github.com/holub/mame
synced 2025-05-22 13:48:55 +03:00
uPD7801 core changes:
- Fixed incorrect disassembly of some instructions. - Updated the handling of interrupts to match the documentation.
This commit is contained in:
Wilbert Pol
parent
cb6fcbbcfa
commit
a83b755c7d
@ -4115,7 +4115,7 @@ static const struct dasm_s dasm4c_7801[256] = {
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/* 0xC0 - 0xFF */
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{ MOV, "A,PA" }, { MOV, "A,PB" }, { MOV, "A,PC" }, { MOV, "A,MK" },
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{ MOV, "A,MB" }, { MOV, "A,MC" }, { MOV, "A,TM0" }, { MOV, "A,TM1" },
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{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
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{ MOV, "A,S" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
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{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
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@ -4379,12 +4379,12 @@ static const struct dasm_s dasm64_7801[256] = {
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{ ACI, "PA,%b" }, { ACI, "PB,%b" }, { ACI, "PC,%b" }, { ACI, "MK,%b" },
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{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
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{ SUI, "PA,%b" }, { SUI, "PB,%b" }, { SUI, "PC,%b" }, { SUI, "MK,%b" },
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{ OFFI, "PA,%b" }, { OFFI, "PB,%b" }, { OFFI, "PC,%b" }, { OFFI, "MK,%b" },
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{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
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{ NEI, "PA,%b" }, { NEI, "PB,%b" }, { NEI, "PC,%b" }, { NEI, "MK,%b" },
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{ SUI, "PA,%b" }, { SUI, "PB,%b" }, { SUI, "PC,%b" }, { SUI, "MK,%b" },
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{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
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{ SBI, "PA,%b" }, { SBI, "PB,%b" }, { SBI, "PC,%b" }, { SBI, "MK,%b" },
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{ NEI, "PA,%b" }, { NEI, "PB,%b" }, { NEI, "PC,%b" }, { NEI, "MK,%b" },
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{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
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{ SBI, "PA,%b" }, { SBI, "PB,%b" }, { SBI, "PC,%b" }, { SBI, "MK,%b" },
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@ -4600,7 +4600,7 @@ static const struct dasm_s dasmXX_7801[256] = {
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{ 0, dasm60_7801 }, { DAA, 0 }, { RETI, 0 }, { CALB, 0 },
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{ 0, dasm64_7801 }, { NEIW, "%a,%b" }, { SUI, "A,%b" }, { NEI, "A,%b" },
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{ MVI, "V,%b?" }, { MVI, "A,%b" }, { MVI, "B,%b" }, { MVI, "C,%b" },
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{ MVI, "V,%b" }, { MVI, "A,%b" }, { MVI, "B,%b" }, { MVI, "C,%b" },
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{ MVI, "D,%b" }, { MVI, "E,%b" }, { MVI, "H,%b" }, { MVI, "L,%b" },
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{ 0, dasm70_7801 }, { MVIW, "%a,%b" }, { SOFTI, 0 }, { JB, 0 },
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@ -3549,7 +3549,7 @@ static const struct opcode_s op48_7801[256] =
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{illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1},
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{SK_CY, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1},
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{SK_Z, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1},
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{PUSH_VA, 2,15,15,L0|L1}, {POP_VA, 2,15,15,L0|L1},
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{PUSH_VA, 2,17,17,L0|L1}, {POP_VA, 2,15,15,L0|L1},
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{SKNIT_F0, 2, 8, 8,L0|L1}, {SKNIT_FT0, 2, 8, 8,L0|L1},
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{SKNIT_F1, 2, 8, 8,L0|L1}, {SKNIT_F2, 2, 8, 8,L0|L1},
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@ -3575,7 +3575,7 @@ static const struct opcode_s op48_7801[256] =
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{SLL_A, 2, 8, 8,L0|L1}, {SLR_A, 2, 8, 8,L0|L1},
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{SLL_C, 2, 8, 8,L0|L1}, {SLR_C, 2, 8, 8,L0|L1},
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{RLD, 2,17,17,L0|L1}, {RRD, 2,17,17,L0|L1},
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{illegal2, 2, 8, 8,L0|L1}, {illegal2, 2,12,12,L0|L1},
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{illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1},
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{PER, 2,11,11,L0|L1}, {illegal2, 2, 8, 8,L0|L1},
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{PUSH_HL, 2,17,17,L0|L1}, {POP_HL, 2,15,15,L0|L1},
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@ -472,6 +472,8 @@ struct _upd7810_state
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UINT8 co1;
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UINT16 irr; /* interrupt request register */
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UINT16 itf; /* interrupt test flag register */
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int int1; /* keep track of current int1 state. Needed for 7801 irq checking. */
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int int2; /* keep track to current int2 state. Needed for 7801 irq checking. */
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/* internal helper variables */
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UINT16 txs; /* transmitter shift register */
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@ -538,6 +540,7 @@ INLINE upd7810_state *get_safe_token(const device_config *device)
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#define INTFST 0x0400
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#define INTER 0x0800
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#define INTOV 0x1000
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#define INTF0 0x2000
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/* ITF flags */
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#define INTAN4 0x0001
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@ -843,97 +846,140 @@ static void upd7810_take_irq(upd7810_state *cpustate)
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if (0 == IFF)
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return;
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/* check the interrupts in priority sequence */
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if ((IRR & INTFT0) && 0 == (MKL & 0x02))
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switch ( cpustate->config.type )
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{
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switch (cpustate->config.type)
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case TYPE_7801:
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/* 1 - SOFTI - vector at 0x0060 */
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/* 2 - INT0 - Masked by MK0 bit */
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if ( IRR & INTF0 && 0 == (MKL & 0x01 ) )
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{
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case TYPE_7810_GAMEMASTER:
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vector = 0xff2a;
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break;
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default:
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vector = 0x0008;
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irqline = UPD7810_INTF0;
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vector = 0x0004;
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IRR &= ~INTF0;
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}
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if (!((IRR & INTFT1) && 0 == (MKL & 0x04)))
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IRR&=~INTFT0;
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}
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else
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if ((IRR & INTFT1) && 0 == (MKL & 0x04))
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{
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switch (cpustate->config.type)
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/* 3 - INTT - Masked by MKT bit */
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if ( IRR & INTFT0 && 0 == ( MKL & 0x02 ) )
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{
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case TYPE_7810_GAMEMASTER:
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vector = 0xff2a;
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break;
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default:
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vector = 0x0008;
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vector = 0x0008;
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IRR &= ~INTFT0;
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}
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IRR&=~INTFT1;
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}
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else
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if ((IRR & INTF1) && 0 == (MKL & 0x08))
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{
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irqline = UPD7810_INTF1;
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vector = 0x0010;
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if (!((IRR & INTF2) && 0 == (MKL & 0x10)))
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IRR&=~INTF1;
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}
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else
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if ((IRR & INTF2) && 0 == (MKL & 0x10))
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{
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irqline = UPD7810_INTF2;
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vector = 0x0010;
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IRR&=~INTF2;
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}
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else
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if ((IRR & INTFE0) && 0 == (MKL & 0x20))
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{
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switch (cpustate->config.type)
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/* 4 - INT1 - Masked by MK1 bit */
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if ( IRR & INTF1 && 0 == ( MKL & 0x04 ) )
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{
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case TYPE_7810_GAMEMASTER:
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vector = 0xff2d;
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break;
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default:
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vector = 0x0018;
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irqline = UPD7810_INTF1;
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vector = 0x0010;
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IRR &= ~INTF1;
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}
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if (!((IRR & INTFE1) && 0 == (MKL & 0x40)))
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IRR&=~INTFE0;
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}
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else
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if ((IRR & INTFE1) && 0 == (MKL & 0x40))
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{
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switch (cpustate->config.type)
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/* 5 - INT2 - Masked by MK2 bit */
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if ( IRR & INTF2 && 0 == ( MKL & 0x08 ) )
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{
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case TYPE_7810_GAMEMASTER:
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vector = 0xff2d;
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break;
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default:
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vector = 0x0018;
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irqline = UPD7810_INTF2;
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vector = 0x0020;
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IRR &= ~INTF2;
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}
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IRR&=~INTFE1;
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}
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else
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if ((IRR & INTFEIN) && 0 == (MKL & 0x80))
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{
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vector = 0x0020;
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}
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else
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if ((IRR & INTFAD) && 0 == (MKH & 0x01))
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{
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vector = 0x0020;
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}
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else
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if ((IRR & INTFSR) && 0 == (MKH & 0x02))
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{
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vector = 0x0028;
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IRR&=~INTFSR;
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}
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else
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if ((IRR & INTFST) && 0 == (MKH & 0x04))
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{
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vector = 0x0028;
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IRR&=~INTFST;
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/* 6 - INTS - Masked by MKS bit */
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if ( IRR & INTFST && 0 == ( MKL & 0x10 ) )
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{
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vector = 0x0040;
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IRR &= ~INTFST;
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}
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break;
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default:
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/* check the interrupts in priority sequence */
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if ((IRR & INTFT0) && 0 == (MKL & 0x02))
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{
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switch (cpustate->config.type)
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{
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case TYPE_7810_GAMEMASTER:
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vector = 0xff2a;
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break;
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default:
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vector = 0x0008;
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}
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if (!((IRR & INTFT1) && 0 == (MKL & 0x04)))
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IRR&=~INTFT0;
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}
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else
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if ((IRR & INTFT1) && 0 == (MKL & 0x04))
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{
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switch (cpustate->config.type)
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{
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case TYPE_7810_GAMEMASTER:
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vector = 0xff2a;
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break;
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default:
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vector = 0x0008;
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}
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IRR&=~INTFT1;
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}
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else
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if ((IRR & INTF1) && 0 == (MKL & 0x08))
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{
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irqline = UPD7810_INTF1;
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vector = 0x0010;
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if (!((IRR & INTF2) && 0 == (MKL & 0x10)))
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IRR&=~INTF1;
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}
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else
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if ((IRR & INTF2) && 0 == (MKL & 0x10))
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{
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irqline = UPD7810_INTF2;
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vector = 0x0010;
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IRR&=~INTF2;
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}
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else
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if ((IRR & INTFE0) && 0 == (MKL & 0x20))
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{
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switch (cpustate->config.type)
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{
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case TYPE_7810_GAMEMASTER:
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vector = 0xff2d;
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break;
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default:
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vector = 0x0018;
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}
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if (!((IRR & INTFE1) && 0 == (MKL & 0x40)))
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IRR&=~INTFE0;
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}
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else
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if ((IRR & INTFE1) && 0 == (MKL & 0x40))
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{
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switch (cpustate->config.type)
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{
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case TYPE_7810_GAMEMASTER:
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vector = 0xff2d;
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break;
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default:
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vector = 0x0018;
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}
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IRR&=~INTFE1;
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}
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else
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if ((IRR & INTFEIN) && 0 == (MKL & 0x80))
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{
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vector = 0x0020;
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}
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else
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if ((IRR & INTFAD) && 0 == (MKH & 0x01))
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{
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vector = 0x0020;
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}
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else
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if ((IRR & INTFSR) && 0 == (MKH & 0x02))
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{
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vector = 0x0028;
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IRR&=~INTFSR;
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}
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else
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if ((IRR & INTFST) && 0 == (MKH & 0x04))
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{
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vector = 0x0028;
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IRR&=~INTFST;
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}
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break;
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}
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if (vector)
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{
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/* acknowledge external IRQ */
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@ -1704,6 +1750,8 @@ static CPU_INIT( upd7810 )
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state_save_register_device_item(device, 0, cpustate->ovcf);
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state_save_register_device_item(device, 0, cpustate->ovcs);
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state_save_register_device_item(device, 0, cpustate->edges);
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state_save_register_device_item(device, 0, cpustate->int1);
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state_save_register_device_item(device, 0, cpustate->int2);
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}
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#include "7810tbl.c"
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@ -1898,39 +1946,85 @@ static CPU_EXECUTE( upd7810 )
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static void set_irq_line(upd7810_state *cpustate, int irqline, int state)
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{
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if (state != CLEAR_LINE)
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/* The uPD7801 can check for falling and rising edges changes on the INT2 input */
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switch ( cpustate->config.type )
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{
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if (irqline == INPUT_LINE_NMI)
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case TYPE_7801:
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switch ( irqline )
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{
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/* no nested NMIs ? */
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// if (0 == (IRR & INTNMI))
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case UPD7810_INTF0:
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/* INT0 is level sensitive */
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if ( state == ASSERT_LINE )
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IRR |= INTF0;
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else
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IRR &= INTF0;
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break;
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case UPD7810_INTF1:
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/* INT1 is rising edge sensitive */
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if ( cpustate->int1 == CLEAR_LINE && state == ASSERT_LINE )
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IRR |= INTF1;
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cpustate->int1 = state;
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break;
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case UPD7810_INTF2:
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/* INT2 is rising or falling edge sensitive */
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/* Check if the ES bit is set then check for rising edge, otherwise falling edge */
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if ( MKL & 0x20 )
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{
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IRR |= INTNMI;
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SP--;
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WM( SP, PSW );
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SP--;
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WM( SP, PCH );
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SP--;
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WM( SP, PCL );
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IFF = 0;
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PSW &= ~(SK|L0|L1);
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PC = 0x0004;
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if ( cpustate->int2 == CLEAR_LINE && state == ASSERT_LINE )
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{
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IRR |= INTF2;
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}
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}
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else
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{
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if ( cpustate->int2 == ASSERT_LINE && state == CLEAR_LINE )
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{
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IRR |= INTF2;
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}
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}
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cpustate->int2 = state;
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break;
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}
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else
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if (irqline == UPD7810_INTF1)
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IRR |= INTF1;
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else
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if (irqline == UPD7810_INTF2)
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IRR |= INTF2;
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// gamemaster hack
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else
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if (irqline == UPD7810_INTFE1)
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IRR |= INTFE1;
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else
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logerror("upd7810_set_irq_line invalid irq line #%d\n", irqline);
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break;
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default:
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if (state != CLEAR_LINE)
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{
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if (irqline == INPUT_LINE_NMI)
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{
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/* no nested NMIs ? */
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// if (0 == (IRR & INTNMI))
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{
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IRR |= INTNMI;
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SP--;
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WM( SP, PSW );
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SP--;
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WM( SP, PCH );
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SP--;
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WM( SP, PCL );
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IFF = 0;
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PSW &= ~(SK|L0|L1);
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PC = 0x0004;
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}
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}
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else
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if (irqline == UPD7810_INTF1)
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IRR |= INTF1;
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else
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if ( irqline == UPD7810_INTF2 && ( MKL & 0x20 ) )
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IRR |= INTF2;
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// gamemaster hack
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else
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if (irqline == UPD7810_INTFE1)
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IRR |= INTFE1;
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else
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logerror("upd7810_set_irq_line invalid irq line #%d\n", irqline);
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}
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/* resetting interrupt requests is done with the SKIT/SKNIT opcodes only! */
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}
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/* resetting interrupt requests is done with the SKIT/SKNIT opcodes only! */
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}
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@ -69,6 +69,7 @@ enum
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/* IRQ lines */
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#define UPD7810_INTF1 0
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#define UPD7810_INTF2 1
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#define UPD7810_INTF0 2
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#define UPD7810_INTFE1 4
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CPU_GET_INFO( upd7810 );
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