mirror of
https://github.com/holub/mame
synced 2025-04-25 09:50:04 +03:00
8237dma: convert its remaining users and kill it (nw)
-- The apollo and bebox both boot but might need more thorough testing.
This commit is contained in:
cracyc
parent
fc8c461aca
commit
a8836f3b65
2
.gitattributes
vendored
2
.gitattributes
vendored
@ -1164,8 +1164,6 @@ src/emu/machine/7474.c svneol=native#text/plain
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src/emu/machine/7474.h svneol=native#text/plain
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src/emu/machine/8042kbdc.c svneol=native#text/plain
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src/emu/machine/8042kbdc.h svneol=native#text/plain
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src/emu/machine/8237dma.c svneol=native#text/plain
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src/emu/machine/8237dma.h svneol=native#text/plain
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src/emu/machine/8257dma.c svneol=native#text/plain
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src/emu/machine/8257dma.h svneol=native#text/plain
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src/emu/machine/aakart.c svneol=native#text/plain
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@ -160,7 +160,6 @@ EMUMACHINEOBJS = \
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$(EMUMACHINE)/74181.o \
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$(EMUMACHINE)/7474.o \
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$(EMUMACHINE)/8042kbdc.o \
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$(EMUMACHINE)/8237dma.o \
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$(EMUMACHINE)/8257dma.o \
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$(EMUMACHINE)/aakart.o \
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$(EMUMACHINE)/adc0808.o \
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@ -1,695 +0,0 @@
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/**********************************************************************
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8237 DMA interface and emulation
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The DMA works like this:
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(summarized from http://www.infran.ru/TechInfo/BSD/handbook258.html#410)
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1. The device asserts the DRQn line
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2. The DMA clears the TC (terminal count) line
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3. The DMA asserts the CPU's HRQ (halt request) line
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4. Upon acknowledgement of the halt, the DMA will let the device
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know that it needs to send information by asserting the DACKn
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line
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5. The DMA will read the byte from the device
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6. The device clears the DRQn line
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7. The DMA clears the CPU's HRQ line
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8. (steps 3-7 are repeated for every byte in the chain)
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**********************************************************************/
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#include "emu.h"
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#include "8237dma.h"
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/***************************************************************************
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MACROS
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***************************************************************************/
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#define DMA_MODE_CHANNEL(mode) ((mode) & 0x03)
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#define DMA_MODE_OPERATION(mode) ((mode) & 0x0c)
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#define DMA_MODE_AUTO_INIT(mode) ((mode) & 0x10)
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#define DMA_MODE_DIRECTION(mode) ((mode) & 0x20)
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#define DMA_MODE_TRANSFERMODE(mode) ((mode) & 0xc0)
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#define DMA8237_VERIFY_TRANSFER 0x00
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#define DMA8237_WRITE_TRANSFER 0x04
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#define DMA8237_READ_TRANSFER 0x08
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#define DMA8237_ILLEGAL_TRANSFER 0x0c
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#define DMA8237_DEMAND_MODE 0x00
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#define DMA8237_SINGLE_MODE 0x40
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#define DMA8237_BLOCK_MODE 0x80
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#define DMA8237_CASCADE_MODE 0xc0
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//**************************************************************************
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// LIVE DEVICE
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//**************************************************************************
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// device type definition
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const device_type I8237 = &device_creator<i8237_device>;
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//-------------------------------------------------
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// i8237_device - constructor
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//-------------------------------------------------
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i8237_device::i8237_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: device_t(mconfig, I8237, "Intel 8237", tag, owner, clock)
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{
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}
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//-------------------------------------------------
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// device_config_complete - perform any
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// operations now that the configuration is
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// complete
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//-------------------------------------------------
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void i8237_device::device_config_complete()
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{
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// inherit a copy of the static data
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const i8237_interface *intf = reinterpret_cast<const i8237_interface *>(static_config());
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if (intf != NULL)
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{
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*static_cast<i8237_interface *>(this) = *intf;
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}
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// or initialize to defaults if none provided
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else
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{
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memset(&m_out_hrq_cb, 0, sizeof(m_out_hrq_cb));
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memset(&m_out_eop_cb, 0, sizeof(m_out_eop_cb));
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memset(&m_in_memr_cb, 0, sizeof(m_in_memr_cb));
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memset(&m_out_memw_cb, 0, sizeof(m_out_memw_cb));
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memset(&m_in_ior_cb[0], 0, sizeof(m_in_ior_cb[0]));
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memset(&m_in_ior_cb[1], 0, sizeof(m_in_ior_cb[1]));
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memset(&m_in_ior_cb[2], 0, sizeof(m_in_ior_cb[2]));
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memset(&m_in_ior_cb[3], 0, sizeof(m_in_ior_cb[3]));
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memset(&m_out_iow_cb[0], 0, sizeof(m_out_iow_cb[0]));
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memset(&m_out_iow_cb[1], 0, sizeof(m_out_iow_cb[1]));
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memset(&m_out_iow_cb[2], 0, sizeof(m_out_iow_cb[2]));
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memset(&m_out_iow_cb[3], 0, sizeof(m_out_iow_cb[3]));
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memset(&m_out_dack_cb[0], 0, sizeof(m_out_dack_cb[0]));
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memset(&m_out_dack_cb[1], 0, sizeof(m_out_dack_cb[1]));
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memset(&m_out_dack_cb[2], 0, sizeof(m_out_dack_cb[2]));
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memset(&m_out_dack_cb[3], 0, sizeof(m_out_dack_cb[3]));
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}
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}
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//-------------------------------------------------
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// device_start - device-specific startup
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//-------------------------------------------------
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void i8237_device::device_start()
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{
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/* resolve callbacks */
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m_out_hrq_func.resolve(m_out_hrq_cb, *this);
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m_out_eop_func.resolve(m_out_eop_cb, *this);
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m_in_memr_func.resolve(m_in_memr_cb, *this);
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m_out_memw_func.resolve(m_out_memw_cb, *this);
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for (int i = 0; i < 4; i++)
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{
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m_chan[i].m_in_ior_func.resolve(m_in_ior_cb[i], *this);
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m_chan[i].m_out_iow_func.resolve(m_out_iow_cb[i], *this);
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m_chan[i].m_out_dack_func.resolve(m_out_dack_cb[i], *this);
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}
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m_timer = machine().scheduler().timer_alloc(FUNC(i8237_timerproc_callback), (void *)this);
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}
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//-------------------------------------------------
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// device_reset - device-specific reset
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//-------------------------------------------------
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void i8237_device::device_reset()
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{
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m_status = 0x0F;
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m_eop = ASSERT_LINE;
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m_state = DMA8237_SI;
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m_last_service_channel = 3;
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m_service_channel = 0;
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m_command = 0;
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m_drq = 0;
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m_mask = 0x00;
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m_hrq = 0;
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m_hlda = 0;
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for(int i = 0; i < 4; ++i)
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{
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m_chan[i].m_mode = 0;
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m_chan[i].m_address = 0;
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m_chan[i].m_count = 0;
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}
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m_timer->adjust(attotime::from_hz(clock()), 0, attotime::from_hz(clock()));
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}
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void i8237_device::i8237_do_read()
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{
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int channel = m_service_channel;
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switch( DMA_MODE_OPERATION( m_chan[ channel ].m_mode ) )
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{
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case DMA8237_WRITE_TRANSFER:
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m_temporary_data = m_chan[channel].m_in_ior_func(0);
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break;
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case DMA8237_READ_TRANSFER:
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m_temporary_data = m_in_memr_func(m_chan[ channel ].m_address);
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break;
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case DMA8237_VERIFY_TRANSFER:
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case DMA8237_ILLEGAL_TRANSFER:
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break;
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}
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}
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void i8237_device::i8237_do_write()
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{
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int channel = m_service_channel;
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switch( DMA_MODE_OPERATION( m_chan[ channel ].m_mode ) )
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{
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case DMA8237_WRITE_TRANSFER:
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m_out_memw_func(m_chan[ channel ].m_address, m_temporary_data);
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break;
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case DMA8237_READ_TRANSFER:
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m_chan[channel].m_out_iow_func(0, m_temporary_data);
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break;
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case DMA8237_VERIFY_TRANSFER:
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case DMA8237_ILLEGAL_TRANSFER:
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break;
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}
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}
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void i8237_device::i8237_advance()
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{
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int channel = m_service_channel;
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int mode = m_chan[channel].m_mode;
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switch ( DMA_MODE_OPERATION( mode ) )
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{
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case DMA8237_VERIFY_TRANSFER:
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case DMA8237_WRITE_TRANSFER:
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case DMA8237_READ_TRANSFER:
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m_chan[channel].m_high_address_changed = 0;
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if ( DMA_MODE_DIRECTION( mode ) )
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{
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m_chan[channel].m_address -= 1;
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if ( ( m_chan[channel].m_address & 0xFF ) == 0xFF )
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{
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m_chan[channel].m_high_address_changed = 1;
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}
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}
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else
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{
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m_chan[channel].m_address += 1;
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if ( ( m_chan[channel].m_address & 0xFF ) == 0x00 )
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{
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m_chan[channel].m_high_address_changed = 1;
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}
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}
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m_chan[channel].m_count--;
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if ( m_chan[channel].m_count == 0xFFFF )
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{
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/* Set TC bit for this channel */
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m_status |= ( 0x01 << channel );
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if ( DMA_MODE_AUTO_INIT( mode ) )
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{
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m_chan[channel].m_address = m_chan[channel].m_base_address;
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m_chan[channel].m_count = m_chan[channel].m_base_count;
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m_chan[channel].m_high_address_changed = 1;
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}
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else
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{
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m_mask |= ( 0x01 << channel );
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}
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}
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break;
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case DMA8237_ILLEGAL_TRANSFER:
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break;
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}
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}
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void i8237_device::i8327_set_dack(int channel)
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{
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for (int i = 0; i < 4; i++)
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{
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int state = (i == channel) ^ !BIT(m_command, 7);
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m_chan[i].m_out_dack_func(state);
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}
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}
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TIMER_CALLBACK( i8237_device::i8237_timerproc_callback )
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{
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reinterpret_cast<i8237_device*>(ptr)->i8237_timerproc();
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}
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void i8237_device::i8237_timerproc()
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{
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/* Check if operation is disabled */
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if ( m_command & 0x04 )
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{
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return;
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}
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switch ( m_state )
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{
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case DMA8237_SI:
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{
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/* Make sure EOP is high */
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if ( m_eop == CLEAR_LINE )
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{
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m_eop = ASSERT_LINE;
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m_out_eop_func(m_eop);
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}
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/* Check if a new DMA request has been received. */
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/* Bit 6 of the command register determines whether the DREQ signals are active
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high or active low. */
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UINT16 pending_request = ( ( m_command & 0x40 ) ? ~m_drq : m_drq ) & ~m_mask;
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if ( pending_request & 0x0f )
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{
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int prio_channel = 0;
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/* Determine the channel that should be serviced */
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int channel = ( m_command & 0x10 ) ? m_last_service_channel : 3;
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for ( int i = 0; i < 4; i++ )
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{
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if ( pending_request & ( 1 << channel ) )
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{
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prio_channel = channel;
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}
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channel = ( channel - 1 ) & 0x03;
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}
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/* Store the channel we will be servicing and go to the next state */
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m_service_channel = prio_channel;
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m_last_service_channel = prio_channel;
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m_hrq = 1;
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m_out_hrq_func(m_hrq);
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m_state = DMA8237_S0;
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m_timer->enable( true );
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}
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else if (m_command == 3 && (m_drq & 1))
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{
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/* Memory-to-memory transfers */
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m_hlda = 1;
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m_state = DMA8237_S0;
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}
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else
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{
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m_timer->enable( false );
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}
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break;
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}
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case DMA8237_S0:
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/* S0 is the first of the DMA service. We have requested a hold but are waiting
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for confirmation. */
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if ( m_hlda )
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{
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if ( DMA_MODE_TRANSFERMODE( m_chan[m_service_channel].m_mode ) == DMA8237_CASCADE_MODE )
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{
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/* Cascade Mode, set DACK */
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i8327_set_dack(m_service_channel);
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/* Wait until peripheral is done */
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m_state = DMA8237_SC;
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}
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else
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{
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if ( m_command & 0x01 )
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{
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/* Memory-to-memory transfers */
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m_state = DMA8237_S11;
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}
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else
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{
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/* Regular transfers */
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m_state = DMA8237_S1;
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}
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}
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}
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break;
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case DMA8237_SC: /* Cascade mode, waiting until peripheral is done */
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if ( ! ( m_drq & ( 0x01 << m_service_channel ) ) )
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{
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m_hrq = 0;
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m_hlda = 0;
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m_out_hrq_func(m_hrq);
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m_state = DMA8237_SI;
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/* Clear DACK */
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i8327_set_dack(-1);
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}
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/* Not sure if this is correct, documentation is not clear */
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/* Check if EOP output needs to be asserted */
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if ( m_status & ( 0x01 << m_service_channel ) )
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{
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m_eop = CLEAR_LINE;
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m_out_eop_func(m_eop);
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}
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break;
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case DMA8237_S1: /* Output A8-A15 */
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m_state = DMA8237_S2;
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break;
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case DMA8237_S2: /* Output A7-A0 */
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/* set DACK */
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i8327_set_dack(m_service_channel);
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/* Check for compressed timing */
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if ( m_command & 0x08 )
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{
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m_state = DMA8237_S4;
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}
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else
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{
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m_state = DMA8237_S3;
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}
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break;
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case DMA8237_S3: /* Initiate read */
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i8237_do_read();
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m_state = DMA8237_S4;
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break;
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case DMA8237_S4: /* Perform read/write */
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/* Perform read when in compressed timing mode */
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if ( m_command & 0x08 )
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{
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i8237_do_read();
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}
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/* Perform write */
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i8237_do_write();
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/* Advance */
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i8237_advance();
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{
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int channel = m_service_channel;
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switch( DMA_MODE_TRANSFERMODE( m_chan[channel].m_mode ) )
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{
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case DMA8237_DEMAND_MODE:
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/* Check for terminal count or EOP signal or DREQ begin de-asserted */
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if ( ( m_status & ( 0x01 << channel ) ) || m_eop == CLEAR_LINE || !( m_drq & ( 0x01 << channel ) ) )
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{
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m_hrq = 0;
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m_hlda = 0;
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m_out_hrq_func(m_hrq);
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m_state = DMA8237_SI;
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}
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else
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{
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m_state = m_chan[channel].m_high_address_changed ? DMA8237_S1 : DMA8237_S2;
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}
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break;
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case DMA8237_SINGLE_MODE:
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m_hrq = 0;
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m_hlda = 0;
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m_out_hrq_func(m_hrq);
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m_state = DMA8237_SI;
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break;
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case DMA8237_BLOCK_MODE:
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/* Check for terminal count or EOP signal */
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if ( ( m_status & ( 0x01 << channel ) ) || m_eop == CLEAR_LINE )
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{
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m_hrq = 0;
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m_hlda = 0;
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m_out_hrq_func(m_hrq);
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m_state = DMA8237_SI;
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}
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else
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{
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m_state = m_chan[channel].m_high_address_changed ? DMA8237_S1 : DMA8237_S2;
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}
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break;
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}
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/* Check if EOP output needs to be asserted */
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if ( m_status & ( 0x01 << channel ) )
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||||
{
|
||||
m_eop = CLEAR_LINE;
|
||||
m_out_eop_func(m_eop);
|
||||
}
|
||||
}
|
||||
|
||||
/* clear DACK */
|
||||
if ( m_state == DMA8237_SI )
|
||||
{
|
||||
i8327_set_dack(-1);
|
||||
}
|
||||
break;
|
||||
|
||||
case DMA8237_S11: /* Output A8-A15 */
|
||||
|
||||
// logerror("###### dma8237_timerproc %s: from %04x count=%x to %04x count=%x\n", tag(),
|
||||
// m_chan[0].m_address, m_chan[0].m_count,
|
||||
// m_chan[1].m_address, m_chan[1].m_count);
|
||||
|
||||
// FIXME: this will copy bytes correct, but not 16 bit words
|
||||
m_temporary_data = m_in_memr_func(m_chan[0].m_address);
|
||||
m_out_memw_func(m_chan[1].m_address, m_temporary_data);
|
||||
|
||||
m_service_channel = 0;
|
||||
|
||||
/* Advance */
|
||||
i8237_advance();
|
||||
|
||||
// advance destination channel as well
|
||||
m_chan[1].m_count--;
|
||||
m_chan[1].m_address++;
|
||||
|
||||
if (m_chan[0].m_count == 0xFFFF || m_chan[1].m_count == 0xFFFF) {
|
||||
m_hrq = 0;
|
||||
m_hlda = 0;
|
||||
m_out_hrq_func(m_hrq);
|
||||
m_state = DMA8237_SI;
|
||||
m_status |= 3; // set TC for channel 0 and 1
|
||||
m_drq &= ~3; // clear drq for channel 0 and 1
|
||||
|
||||
// logerror("!!! dma8237_timerproc DMA8237_S11 %s: m_drq=%x m_command=%x\n", tag(), m_drq, m_command);
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
READ8_MEMBER(i8237_device::i8237_r)
|
||||
{
|
||||
UINT8 data = 0xFF;
|
||||
|
||||
offset &= 0x0F;
|
||||
|
||||
switch(offset) {
|
||||
case 0:
|
||||
case 2:
|
||||
case 4:
|
||||
case 6:
|
||||
/* DMA address register */
|
||||
data = m_chan[offset / 2].m_address >> (m_msb ? 8 : 0);
|
||||
m_msb ^= 1;
|
||||
break;
|
||||
|
||||
case 1:
|
||||
case 3:
|
||||
case 5:
|
||||
case 7:
|
||||
/* DMA count register */
|
||||
data = m_chan[offset / 2].m_count >> (m_msb ? 8 : 0);
|
||||
m_msb ^= 1;
|
||||
break;
|
||||
|
||||
case 8:
|
||||
/* DMA status register */
|
||||
data = (UINT8) m_status;
|
||||
|
||||
/* TC bits are cleared on a status read */
|
||||
m_status &= 0xF0;
|
||||
break;
|
||||
|
||||
case 10:
|
||||
/* DMA mask register */
|
||||
data = m_mask;
|
||||
break;
|
||||
|
||||
case 13:
|
||||
/* DMA master clear */
|
||||
data = m_temp;
|
||||
break;
|
||||
|
||||
case 9: /* DMA write request register */
|
||||
case 11: /* DMA mode register */
|
||||
case 12: /* DMA clear byte pointer flip-flop */
|
||||
case 14: /* DMA clear mask register */
|
||||
case 15: /* DMA write mask register */
|
||||
data = 0xFF;
|
||||
break;
|
||||
}
|
||||
|
||||
return data;
|
||||
}
|
||||
|
||||
|
||||
WRITE8_MEMBER(i8237_device::i8237_w)
|
||||
{
|
||||
offset &= 0x0F;
|
||||
|
||||
// logerror("i8237_w: offset = %02x, data = %02x\n", offset, data );
|
||||
|
||||
switch(offset) {
|
||||
case 0:
|
||||
case 2:
|
||||
case 4:
|
||||
case 6:
|
||||
{
|
||||
/* DMA address register */
|
||||
int channel = offset / 2;
|
||||
if (m_msb)
|
||||
{
|
||||
m_chan[channel].m_base_address = ( m_chan[channel].m_base_address & 0x00FF ) | ( data << 8 );
|
||||
m_chan[channel].m_address = ( m_chan[channel].m_address & 0x00FF ) | ( data << 8 );
|
||||
}
|
||||
else
|
||||
{
|
||||
m_chan[channel].m_base_address = ( m_chan[channel].m_base_address & 0xFF00 ) | data;
|
||||
m_chan[channel].m_address = ( m_chan[channel].m_address & 0xFF00 ) | data;
|
||||
}
|
||||
m_msb ^= 1;
|
||||
break;
|
||||
}
|
||||
|
||||
case 1:
|
||||
case 3:
|
||||
case 5:
|
||||
case 7:
|
||||
{
|
||||
/* DMA count register */
|
||||
int channel = offset / 2;
|
||||
if (m_msb)
|
||||
{
|
||||
m_chan[channel].m_base_count = ( m_chan[channel].m_base_count & 0x00FF ) | ( data << 8 );
|
||||
m_chan[channel].m_count = ( m_chan[channel].m_count & 0x00FF ) | ( data << 8 );
|
||||
}
|
||||
else
|
||||
{
|
||||
m_chan[channel].m_base_count = ( m_chan[channel].m_base_count & 0xFF00 ) | data;
|
||||
m_chan[channel].m_count = ( m_chan[channel].m_count & 0xFF00 ) | data;
|
||||
}
|
||||
m_msb ^= 1;
|
||||
break;
|
||||
}
|
||||
|
||||
case 8:
|
||||
/* DMA command register */
|
||||
m_command = data;
|
||||
m_timer->enable( ( m_command & 0x04 ) ? 0 : 1 );
|
||||
break;
|
||||
|
||||
case 9:
|
||||
{
|
||||
/* DMA request register */
|
||||
int channel = DMA_MODE_CHANNEL(data);
|
||||
if ( data & 0x04 )
|
||||
{
|
||||
m_drq |= 0x01 << channel;
|
||||
m_timer->enable( ( m_command & 0x04 ) ? 0 : 1 );
|
||||
}
|
||||
else
|
||||
{
|
||||
m_status &= ~ ( 0x10 << channel );
|
||||
m_drq &= ~ ( 0x01 << channel );
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
case 10:
|
||||
{
|
||||
/* DMA mask register */
|
||||
int channel = DMA_MODE_CHANNEL(data);
|
||||
if (data & 0x04)
|
||||
{
|
||||
m_mask |= 0x11 << channel;
|
||||
}
|
||||
else
|
||||
{
|
||||
m_mask &= ~(0x11 << channel);
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
case 11:
|
||||
{
|
||||
/* DMA mode register */
|
||||
int channel = DMA_MODE_CHANNEL(data);
|
||||
m_chan[channel].m_mode = data;
|
||||
/* Apparently mode writes also clear the TC bit(?) */
|
||||
m_status &= ~ ( 1 << channel );
|
||||
break;
|
||||
}
|
||||
|
||||
case 12:
|
||||
/* DMA clear byte pointer flip-flop */
|
||||
m_temp = data;
|
||||
m_msb = 0;
|
||||
break;
|
||||
|
||||
case 13:
|
||||
/* DMA master clear */
|
||||
m_msb = 0;
|
||||
m_mask = 0x0f;
|
||||
m_state = DMA8237_SI;
|
||||
m_status &= 0xF0;
|
||||
m_temp = 0;
|
||||
break;
|
||||
|
||||
case 14:
|
||||
/* DMA clear mask register */
|
||||
m_mask &= ~data;
|
||||
m_mask = 0;
|
||||
break;
|
||||
|
||||
case 15:
|
||||
/* DMA write mask register */
|
||||
m_mask = data & 0x0f;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void i8237_device::i8237_drq_write(int channel, int state)
|
||||
{
|
||||
if (state)
|
||||
{
|
||||
m_drq |= ( 0x01 << channel );
|
||||
}
|
||||
else
|
||||
{
|
||||
m_drq &= ~( 0x01 << channel );
|
||||
}
|
||||
|
||||
m_timer->enable( ( m_command & 0x04 ) ? 0 : 1 );
|
||||
}
|
||||
@ -1,194 +0,0 @@
|
||||
/***************************************************************************
|
||||
|
||||
Intel 8237 Programmable DMA Controller emulation
|
||||
|
||||
Copyright Nicola Salmoria and the MAME Team.
|
||||
Visit http://mamedev.org for licensing and usage restrictions.
|
||||
|
||||
****************************************************************************
|
||||
_____ _____
|
||||
_I/OR 1 |* \_/ | 40 A7
|
||||
_I/OW 2 | | 39 A6
|
||||
_MEMR 3 | | 38 A5
|
||||
_MEMW 4 | | 37 A4
|
||||
5 | | 36 _EOP
|
||||
READY 6 | | 35 A3
|
||||
HLDA 7 | | 34 A2
|
||||
ADSTB 8 | | 33 A1
|
||||
AEN 9 | | 32 A0
|
||||
HRQ 10 | 8237 | 31 Vcc
|
||||
_CS 11 | | 30 DB0
|
||||
CLK 12 | | 29 DB1
|
||||
RESET 13 | | 28 DB2
|
||||
DACK2 14 | | 27 DB3
|
||||
DACK3 15 | | 26 DB4
|
||||
DREQ3 16 | | 25 DACK0
|
||||
DREQ2 17 | | 24 DACK1
|
||||
DREQ1 18 | | 23 DB5
|
||||
DREQ0 19 | | 22 DB6
|
||||
GND 20 |_____________| 21 DB7
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifndef __I8237__
|
||||
#define __I8237__
|
||||
|
||||
#include "emu.h"
|
||||
|
||||
|
||||
|
||||
/***************************************************************************
|
||||
DEVICE CONFIGURATION MACROS
|
||||
***************************************************************************/
|
||||
|
||||
#define MCFG_I8237_ADD(_tag, _clock, _config) \
|
||||
MCFG_DEVICE_ADD(_tag, I8237, _clock) \
|
||||
MCFG_DEVICE_CONFIG(_config)
|
||||
|
||||
#define I8237_INTERFACE(_name) \
|
||||
const i8237_interface (_name) =
|
||||
|
||||
|
||||
/***************************************************************************
|
||||
TYPE DEFINITIONS
|
||||
***************************************************************************/
|
||||
|
||||
|
||||
// ======================> i8237_interface
|
||||
|
||||
struct i8237_interface
|
||||
{
|
||||
devcb_write_line m_out_hrq_cb;
|
||||
devcb_write_line m_out_eop_cb;
|
||||
|
||||
/* accessors to main memory */
|
||||
devcb_read8 m_in_memr_cb;
|
||||
devcb_write8 m_out_memw_cb;
|
||||
|
||||
/* channel accessors */
|
||||
devcb_read8 m_in_ior_cb[4];
|
||||
devcb_write8 m_out_iow_cb[4];
|
||||
devcb_write_line m_out_dack_cb[4];
|
||||
};
|
||||
|
||||
|
||||
|
||||
// ======================> i8237_device
|
||||
|
||||
class i8237_device : public device_t,
|
||||
public i8237_interface
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
i8237_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
/* register access */
|
||||
DECLARE_READ8_MEMBER( i8237_r );
|
||||
DECLARE_WRITE8_MEMBER( i8237_w );
|
||||
/* hold acknowledge */
|
||||
WRITE_LINE_MEMBER( i8237_hlda_w ) { m_hlda = state; }
|
||||
|
||||
/* ready */
|
||||
WRITE_LINE_MEMBER( i8237_ready_w ) { }
|
||||
|
||||
/* data request */
|
||||
WRITE_LINE_MEMBER( i8237_dreq0_w ) { i8237_drq_write(0, state); }
|
||||
WRITE_LINE_MEMBER( i8237_dreq1_w ) { i8237_drq_write(1, state); }
|
||||
WRITE_LINE_MEMBER( i8237_dreq2_w ) { i8237_drq_write(2, state); }
|
||||
WRITE_LINE_MEMBER( i8237_dreq3_w ) { i8237_drq_write(3, state); }
|
||||
void i8237_drq_write(int channel, int state);
|
||||
|
||||
/* end of process */
|
||||
WRITE_LINE_MEMBER( i8237_eop_w ) { }
|
||||
|
||||
void i8237_timerproc();
|
||||
|
||||
protected:
|
||||
// device-level overrides
|
||||
virtual void device_config_complete();
|
||||
virtual void device_start();
|
||||
virtual void device_reset();
|
||||
virtual void device_post_load() { }
|
||||
virtual void device_clock_changed() { }
|
||||
|
||||
static TIMER_CALLBACK( i8237_timerproc_callback );
|
||||
static TIMER_CALLBACK( receive_event_callback );
|
||||
|
||||
private:
|
||||
|
||||
void i8237_do_read();
|
||||
void i8237_do_write();
|
||||
void i8237_advance();
|
||||
void i8327_set_dack(int channel);
|
||||
|
||||
/* States that the i8237 device can be in */
|
||||
enum dma8237_state
|
||||
{
|
||||
DMA8237_SI, /* Idle state */
|
||||
DMA8237_S0, /* HRQ has been triggered, waiting to receive HLDA */
|
||||
// DMA8237_SW, /* Wait state */
|
||||
DMA8237_SC, /* Cascade mode, waiting for peripheral */
|
||||
|
||||
/* Normal transfer states */
|
||||
DMA8237_S1, /* Output A8-A15; only used when A8-A15 really needs to be output */
|
||||
DMA8237_S2, /* Output A0-A7 */
|
||||
DMA8237_S3, /* Initiate read; skipped in compressed timing. On the S2->S3 transition DACK is set. */
|
||||
DMA8237_S4, /* Perform read/write */
|
||||
|
||||
/* Memory to memory transfer states */
|
||||
DMA8237_S11, /* Output A8-A15 */
|
||||
// DMA8237_S12, /* Output A0-A7 */
|
||||
// DMA8237_S13, /* Initiate read */
|
||||
// DMA8237_S14, /* Perform read/write */
|
||||
// DMA8237_S21, /* Output A8-A15 */
|
||||
// DMA8237_S22, /* Output A0-A7 */
|
||||
// DMA8237_S23, /* Initiate read */
|
||||
// DMA8237_S24, /* Perform read/write */
|
||||
};
|
||||
|
||||
devcb_resolved_write_line m_out_hrq_func;
|
||||
devcb_resolved_write_line m_out_eop_func;
|
||||
devcb_resolved_read8 m_in_memr_func;
|
||||
devcb_resolved_write8 m_out_memw_func;
|
||||
|
||||
emu_timer *m_timer;
|
||||
|
||||
struct
|
||||
{
|
||||
devcb_resolved_read8 m_in_ior_func;
|
||||
devcb_resolved_write8 m_out_iow_func;
|
||||
devcb_resolved_write_line m_out_dack_func;
|
||||
UINT16 m_base_address;
|
||||
UINT16 m_base_count;
|
||||
UINT16 m_address;
|
||||
UINT16 m_count;
|
||||
UINT8 m_mode;
|
||||
int m_high_address_changed;
|
||||
} m_chan[4];
|
||||
|
||||
UINT32 m_msb : 1;
|
||||
UINT32 m_eop : 1;
|
||||
UINT8 m_temp;
|
||||
UINT8 m_temporary_data;
|
||||
UINT8 m_command;
|
||||
UINT8 m_drq;
|
||||
UINT8 m_mask;
|
||||
UINT8 m_hrq;
|
||||
UINT8 m_hlda;
|
||||
|
||||
/* bits 0- 3 : Terminal count for channels 0-3
|
||||
* bits 4- 7 : Transfer in progress for channels 0-3 */
|
||||
UINT8 m_status;
|
||||
|
||||
dma8237_state m_state; /* State the device is currently in */
|
||||
int m_service_channel; /* Channel we will be servicing */
|
||||
int m_last_service_channel; /* Previous channel we serviced; used to determine channel priority. */
|
||||
};
|
||||
|
||||
|
||||
// device type definition
|
||||
extern const device_type I8237;
|
||||
|
||||
#endif
|
||||
@ -24,6 +24,15 @@
|
||||
DMA8237 Controller
|
||||
******************/
|
||||
|
||||
READ8_MEMBER(pcat_base_state::at_dma8237_2_r)
|
||||
{
|
||||
return m_dma8237_2->read(space, offset / 2);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(pcat_base_state::at_dma8237_2_w)
|
||||
{
|
||||
m_dma8237_2->write(space, offset / 2, data);
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER( pcat_base_state::pc_dma_hrq_changed )
|
||||
{
|
||||
@ -150,10 +159,7 @@ IRQ_CALLBACK_MEMBER(pcat_base_state::irq_callback)
|
||||
|
||||
WRITE_LINE_MEMBER( pcat_base_state::at_pit8254_out0_changed )
|
||||
{
|
||||
if (m_pic8259_1 )
|
||||
{
|
||||
m_pic8259_1->ir0_w(state);
|
||||
}
|
||||
m_pic8259_1->ir0_w(state);
|
||||
}
|
||||
|
||||
|
||||
@ -218,7 +224,7 @@ ADDRESS_MAP_START( pcat32_io_common, AS_IO, 32, pcat_base_state )
|
||||
AM_RANGE(0x0070, 0x007f) AM_DEVREADWRITE8("rtc", mc146818_device, read, write, 0xffffffff)
|
||||
AM_RANGE(0x0080, 0x009f) AM_READWRITE8(dma_page_select_r,dma_page_select_w, 0xffffffff)//TODO
|
||||
AM_RANGE(0x00a0, 0x00bf) AM_DEVREADWRITE8("pic8259_2", pic8259_device, read, write, 0xffffffff)
|
||||
AM_RANGE(0x00c0, 0x00df) AM_DEVREADWRITE8("dma8237_2", am9517a_device, read, write, 0xffffffff)
|
||||
AM_RANGE(0x00c0, 0x00df) AM_READWRITE8(at_dma8237_2_r, at_dma8237_2_w, 0xffffffff)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
MACHINE_CONFIG_FRAGMENT(pcat_common)
|
||||
|
||||
@ -26,6 +26,8 @@ public:
|
||||
required_device<pit8254_device> m_pit8254;
|
||||
required_device<mc146818_device> m_mc146818;
|
||||
|
||||
DECLARE_READ8_MEMBER(at_dma8237_2_r);
|
||||
DECLARE_WRITE8_MEMBER(at_dma8237_2_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(pc_dma_hrq_changed);
|
||||
DECLARE_READ8_MEMBER(pc_dma_read_byte);
|
||||
DECLARE_WRITE8_MEMBER(pc_dma_write_byte);
|
||||
|
||||
@ -1057,10 +1057,6 @@ static void apollo_reset_instr_callback(device_t *device)
|
||||
|
||||
// reset the CPU board devices
|
||||
apollo->MACHINE_RESET_CALL_MEMBER(apollo);
|
||||
apollo->dma8237_1->reset();
|
||||
apollo->dma8237_2->reset();
|
||||
apollo->pic8259_master->reset();
|
||||
apollo->pic8259_slave->reset();
|
||||
|
||||
// reset the ISA bus devices
|
||||
apollo->m_ctape->device_reset();
|
||||
|
||||
@ -14,7 +14,7 @@
|
||||
#include "emu.h"
|
||||
#include "cpu/i86/i86.h"
|
||||
#include "video/mc6845.h"
|
||||
#include "machine/8237dma.h"
|
||||
#include "machine/am9517a.h"
|
||||
|
||||
|
||||
|
||||
@ -24,6 +24,7 @@ public:
|
||||
b16_state(const machine_config &mconfig, device_type type, const char *tag)
|
||||
: driver_device(mconfig, type, tag),
|
||||
m_vram(*this, "vram"),
|
||||
m_dma8237(*this, "8237dma"),
|
||||
m_maincpu(*this, "maincpu") { }
|
||||
|
||||
UINT8 *m_char_rom;
|
||||
@ -43,7 +44,7 @@ public:
|
||||
UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
|
||||
|
||||
mc6845_device *m_mc6845;
|
||||
i8237_device *m_dma8237;
|
||||
required_device<am9517a_device> m_dma8237;
|
||||
virtual void machine_start();
|
||||
virtual void machine_reset();
|
||||
required_device<cpu_device> m_maincpu;
|
||||
@ -241,7 +242,6 @@ GFXDECODE_END
|
||||
|
||||
void b16_state::machine_start()
|
||||
{
|
||||
m_dma8237 = machine().device<i8237_device>( "dma8237" );
|
||||
m_mc6845 = machine().device<mc6845_device>("crtc");
|
||||
}
|
||||
|
||||
|
||||
@ -19,7 +19,7 @@
|
||||
#include "machine/pic8259.h"
|
||||
#include "machine/mc146818.h"
|
||||
#include "machine/pci.h"
|
||||
#include "machine/8237dma.h"
|
||||
#include "machine/am9517a.h"
|
||||
#include "machine/pckeybrd.h"
|
||||
#include "machine/8042kbdc.h"
|
||||
#include "machine/pit8253.h"
|
||||
@ -36,8 +36,8 @@
|
||||
#include "machine/ram.h"
|
||||
#include "machine/8042kbdc.h"
|
||||
|
||||
READ8_MEMBER(bebox_state::at_dma8237_1_r) { return machine().device<i8237_device>("dma8237_2")->i8237_r(space, offset / 2); }
|
||||
WRITE8_MEMBER(bebox_state::at_dma8237_1_w) { machine().device<i8237_device>("dma8237_2")->i8237_w(space, offset / 2, data); }
|
||||
READ8_MEMBER(bebox_state::at_dma8237_1_r) { return m_dma8237_2->read(space, offset / 2); }
|
||||
WRITE8_MEMBER(bebox_state::at_dma8237_1_w) { m_dma8237_2->write(space, offset / 2, data); }
|
||||
|
||||
static ADDRESS_MAP_START( bebox_mem, AS_PROGRAM, 64, bebox_state )
|
||||
AM_RANGE(0x7FFFF0F0, 0x7FFFF0F7) AM_READWRITE(bebox_cpu0_imask_r, bebox_cpu0_imask_w )
|
||||
@ -46,13 +46,13 @@ static ADDRESS_MAP_START( bebox_mem, AS_PROGRAM, 64, bebox_state )
|
||||
AM_RANGE(0x7FFFF3F0, 0x7FFFF3F7) AM_READWRITE(bebox_crossproc_interrupts_r, bebox_crossproc_interrupts_w )
|
||||
AM_RANGE(0x7FFFF4F0, 0x7FFFF4F7) AM_WRITE(bebox_processor_resets_w )
|
||||
|
||||
AM_RANGE(0x80000000, 0x8000001F) AM_DEVREADWRITE8("dma8237_1", i8237_device, i8237_r, i8237_w, U64(0xffffffffffffffff) )
|
||||
AM_RANGE(0x80000020, 0x8000003F) AM_DEVREADWRITE8("pic8259_master", pic8259_device, read, write, U64(0xffffffffffffffff) )
|
||||
AM_RANGE(0x80000000, 0x8000001F) AM_DEVREADWRITE8("dma8237_1", am9517a_device, read, write, U64(0xffffffffffffffff) )
|
||||
AM_RANGE(0x80000020, 0x8000003F) AM_DEVREADWRITE8("pic8259_1", pic8259_device, read, write, U64(0xffffffffffffffff) )
|
||||
AM_RANGE(0x80000040, 0x8000005f) AM_DEVREADWRITE8_LEGACY("pit8254", pit8253_r, pit8253_w, U64(0xffffffffffffffff) )
|
||||
AM_RANGE(0x80000060, 0x8000006F) AM_DEVREADWRITE8("kbdc", kbdc8042_device, data_r, data_w, U64(0xffffffffffffffff) )
|
||||
AM_RANGE(0x80000070, 0x8000007F) AM_DEVREADWRITE8("rtc", mc146818_device, read, write , U64(0xffffffffffffffff) )
|
||||
AM_RANGE(0x80000080, 0x8000009F) AM_READWRITE8(bebox_page_r, bebox_page_w, U64(0xffffffffffffffff) )
|
||||
AM_RANGE(0x800000A0, 0x800000BF) AM_DEVREADWRITE8("pic8259_slave", pic8259_device, read, write, U64(0xffffffffffffffff) )
|
||||
AM_RANGE(0x800000A0, 0x800000BF) AM_DEVREADWRITE8("pic8259_2", pic8259_device, read, write, U64(0xffffffffffffffff) )
|
||||
AM_RANGE(0x800000C0, 0x800000DF) AM_READWRITE8(at_dma8237_1_r, at_dma8237_1_w, U64(0xffffffffffffffff))
|
||||
AM_RANGE(0x800001F0, 0x800001F7) AM_READWRITE8(bebox_800001F0_r, bebox_800001F0_w, U64(0xffffffffffffffff) )
|
||||
AM_RANGE(0x800002F8, 0x800002FF) AM_DEVREADWRITE8( "ns16550_1", ns16550_device, ins8250_r, ins8250_w, U64(0xffffffffffffffff) )
|
||||
@ -154,9 +154,7 @@ const struct mpc105_interface mpc105_config =
|
||||
WRITE_LINE_MEMBER(bebox_state::bebox_keyboard_interrupt)
|
||||
{
|
||||
bebox_set_irq_bit(machine(), 16, state);
|
||||
if ( m_devices.pic8259_master ) {
|
||||
m_devices.pic8259_master->ir1_w(state);
|
||||
}
|
||||
m_pic8259_1->ir1_w(state);
|
||||
}
|
||||
|
||||
READ8_MEMBER(bebox_state::bebox_get_out2)
|
||||
@ -197,9 +195,9 @@ static MACHINE_CONFIG_START( bebox, bebox_state )
|
||||
|
||||
MCFG_I8237_ADD( "dma8237_2", XTAL_14_31818MHz/3, bebox_dma8237_2_config )
|
||||
|
||||
MCFG_PIC8259_ADD( "pic8259_master", WRITELINE(bebox_state,bebox_pic8259_master_set_int_line), VCC, READ8(bebox_state,get_slave_ack) )
|
||||
MCFG_PIC8259_ADD( "pic8259_1", WRITELINE(bebox_state,bebox_pic8259_master_set_int_line), VCC, READ8(bebox_state,get_slave_ack) )
|
||||
|
||||
MCFG_PIC8259_ADD( "pic8259_slave", WRITELINE(bebox_state,bebox_pic8259_slave_set_int_line), GND, NULL )
|
||||
MCFG_PIC8259_ADD( "pic8259_2", WRITELINE(bebox_state,bebox_pic8259_slave_set_int_line), GND, NULL )
|
||||
|
||||
MCFG_NS16550_ADD( "ns16550_0", bebox_uart_inteface_0, 0 ) /* TODO: Verify model */
|
||||
MCFG_NS16550_ADD( "ns16550_1", bebox_uart_inteface_1, 0 ) /* TODO: Verify model */
|
||||
|
||||
@ -11,7 +11,7 @@
|
||||
#include "cpu/z80/z80.h"
|
||||
#include "cpu/mcs48/mcs48.h"
|
||||
#include "machine/upd765.h"
|
||||
#include "machine/8237dma.h"
|
||||
#include "machine/am9517a.h"
|
||||
#include "video/upd7220.h"
|
||||
#include "dmv.lh"
|
||||
|
||||
@ -31,7 +31,7 @@ public:
|
||||
|
||||
required_device<cpu_device> m_maincpu;
|
||||
required_device<upd7220_device> m_hgdc;
|
||||
required_device<i8237_device> m_dmac;
|
||||
required_device<am9517a_device> m_dmac;
|
||||
required_device<upd765a_device> m_fdc;
|
||||
required_device<floppy_image_device> m_floppy0;
|
||||
required_device<floppy_image_device> m_floppy1;
|
||||
@ -86,7 +86,7 @@ void dmv_state::fdc_irq(bool state)
|
||||
|
||||
void dmv_state::fdc_drq(bool state)
|
||||
{
|
||||
m_dmac->i8237_drq_write(3, state);
|
||||
m_dmac->dreq3_w(state);
|
||||
}
|
||||
|
||||
READ8_MEMBER(dmv_state::fdc_dma_r)
|
||||
@ -198,7 +198,7 @@ static ADDRESS_MAP_START( dmv_io , AS_IO, 8, dmv_state)
|
||||
AM_RANGE(0x00, 0x00) AM_WRITE(leds_w)
|
||||
AM_RANGE(0x13, 0x13) AM_READ(sys_status_r)
|
||||
AM_RANGE(0x14, 0x14) AM_WRITE(fdd_motor_w)
|
||||
AM_RANGE(0x20, 0x2f) AM_DEVREADWRITE("dma8237", i8237_device, i8237_r, i8237_w)
|
||||
AM_RANGE(0x20, 0x2f) AM_DEVREADWRITE("dma8237", am9517a_device, read, write)
|
||||
AM_RANGE(0x40, 0x41) AM_READWRITE(kb_ctrl_mcu_r, kb_ctrl_mcu_w)
|
||||
AM_RANGE(0x50, 0x51) AM_DEVICE("upd765", upd765a_device, map)
|
||||
AM_RANGE(0xa0, 0xa1) AM_DEVREADWRITE("upd7220", upd7220_device, read, write)
|
||||
@ -282,7 +282,7 @@ WRITE_LINE_MEMBER( dmv_state::dma_hrq_changed )
|
||||
m_maincpu->set_input_line(INPUT_LINE_HALT, state ? ASSERT_LINE : CLEAR_LINE);
|
||||
|
||||
// Assert HLDA
|
||||
m_dmac->i8237_hlda_w(state);
|
||||
m_dmac->hack_w(state);
|
||||
}
|
||||
|
||||
READ8_MEMBER(dmv_state::memory_read_byte)
|
||||
|
||||
@ -12,7 +12,7 @@
|
||||
#include "cpu/i86/i86.h"
|
||||
#include "video/mc6845.h"
|
||||
#include "machine/pic8259.h"
|
||||
#include "machine/8237dma.h"
|
||||
#include "machine/am9517a.h"
|
||||
|
||||
|
||||
class paso1600_state : public driver_device
|
||||
@ -29,7 +29,7 @@ public:
|
||||
|
||||
required_device<cpu_device> m_maincpu;
|
||||
required_device<pic8259_device> m_pic;
|
||||
required_device<i8237_device> m_dma;
|
||||
required_device<am9517a_device> m_dma;
|
||||
required_device<mc6845_device> m_crtc;
|
||||
DECLARE_READ8_MEMBER(paso1600_pcg_r);
|
||||
DECLARE_WRITE8_MEMBER(paso1600_pcg_w);
|
||||
@ -236,7 +236,7 @@ ADDRESS_MAP_END
|
||||
|
||||
static ADDRESS_MAP_START(paso1600_io, AS_IO, 16, paso1600_state)
|
||||
ADDRESS_MAP_UNMAP_LOW
|
||||
AM_RANGE(0x0000,0x000f) AM_DEVREADWRITE8("8237dma", i8237_device, i8237_r, i8237_w, 0xffff)
|
||||
AM_RANGE(0x0000,0x000f) AM_DEVREADWRITE8("8237dma", am9517a_device, read, write, 0xffff)
|
||||
AM_RANGE(0x0010,0x0011) AM_DEVREADWRITE8("pic8259", pic8259_device, read, write, 0xffff) // i8259
|
||||
AM_RANGE(0x001a,0x001b) AM_READ(test_hi_r) // causes RAM error otherwise?
|
||||
AM_RANGE(0x0030,0x0033) AM_READWRITE8(key_r,key_w,0xffff) //UART keyboard?
|
||||
|
||||
@ -24,7 +24,7 @@
|
||||
#include "machine/3c505.h"
|
||||
#include "machine/68681.h"
|
||||
#include "machine/pc_fdc.h"
|
||||
#include "machine/8237dma.h"
|
||||
#include "machine/am9517a.h"
|
||||
#include "machine/pic8259.h"
|
||||
|
||||
#ifndef VERBOSE
|
||||
@ -116,16 +116,21 @@ public:
|
||||
: driver_device(mconfig, type, tag),
|
||||
m_maincpu(*this, MAINCPU),
|
||||
m_ctape(*this, APOLLO_CTAPE_TAG),
|
||||
m_messram_ptr(*this, "messram")
|
||||
m_messram_ptr(*this, "messram"),
|
||||
m_dma8237_1(*this, "dma8237_1"),
|
||||
m_dma8237_2(*this, "dma8237_2"),
|
||||
m_pic8259_master(*this, "pic8259_master"),
|
||||
m_pic8259_slave(*this, "pic8259_slave")
|
||||
{ }
|
||||
|
||||
required_device<cpu_device> m_maincpu;
|
||||
required_device<sc499_device> m_ctape;
|
||||
required_shared_ptr<UINT32> m_messram_ptr;
|
||||
|
||||
i8237_device *dma8237_1;
|
||||
i8237_device *dma8237_2;
|
||||
pic8259_device *pic8259_master;
|
||||
pic8259_device *pic8259_slave;
|
||||
required_device<am9517a_device> m_dma8237_1;
|
||||
required_device<am9517a_device> m_dma8237_2;
|
||||
required_device<pic8259_device> m_pic8259_master;
|
||||
required_device<pic8259_device> m_pic8259_slave;
|
||||
|
||||
DECLARE_WRITE16_MEMBER(apollo_csr_status_register_w);
|
||||
DECLARE_READ16_MEMBER(apollo_csr_status_register_r);
|
||||
@ -182,7 +187,6 @@ public:
|
||||
DECLARE_DRIVER_INIT(dn5500);
|
||||
DECLARE_DRIVER_INIT(apollo);
|
||||
|
||||
required_shared_ptr<UINT32> m_messram_ptr;
|
||||
virtual void machine_start();
|
||||
virtual void machine_reset();
|
||||
DECLARE_MACHINE_RESET(apollo);
|
||||
|
||||
@ -11,21 +11,12 @@
|
||||
|
||||
#include "emu.h"
|
||||
#include "machine/ins8250.h"
|
||||
#include "machine/8237dma.h"
|
||||
#include "machine/am9517a.h"
|
||||
#include "machine/53c810.h"
|
||||
#include "machine/upd765.h"
|
||||
#include "machine/ram.h"
|
||||
#include "machine/pic8259.h"
|
||||
|
||||
struct bebox_devices_t
|
||||
{
|
||||
pic8259_device *pic8259_master;
|
||||
pic8259_device *pic8259_slave;
|
||||
i8237_device *dma8237_1;
|
||||
i8237_device *dma8237_2;
|
||||
};
|
||||
|
||||
|
||||
class bebox_state : public driver_device
|
||||
{
|
||||
public:
|
||||
@ -39,16 +30,23 @@ public:
|
||||
m_ppc1(*this, "ppc1"),
|
||||
m_ppc2(*this, "ppc2"),
|
||||
m_lsi53c810(*this, "scsi:lsi53c810"),
|
||||
m_dma8237_1(*this, "dma8237_1"),
|
||||
m_dma8237_2(*this, "dma8237_2"),
|
||||
m_pic8259_1(*this, "pic8259_1"),
|
||||
m_pic8259_2(*this, "pic8259_2"),
|
||||
m_ram(*this, RAM_TAG){ }
|
||||
|
||||
required_device<cpu_device> m_ppc1;
|
||||
required_device<cpu_device> m_ppc2;
|
||||
required_device<lsi53c810_device> m_lsi53c810;
|
||||
required_device<am9517a_device> m_dma8237_1;
|
||||
required_device<am9517a_device> m_dma8237_2;
|
||||
required_device<pic8259_device> m_pic8259_1;
|
||||
required_device<pic8259_device> m_pic8259_2;
|
||||
required_device<ram_device> m_ram;
|
||||
UINT32 m_cpu_imask[2];
|
||||
UINT32 m_interrupts;
|
||||
UINT32 m_crossproc_interrupts;
|
||||
bebox_devices_t m_devices;
|
||||
int m_dma_channel;
|
||||
UINT16 m_dma_offset[2][4];
|
||||
UINT8 m_at_pages[0x10];
|
||||
@ -113,8 +111,8 @@ protected:
|
||||
/*----------- defined in machine/bebox.c -----------*/
|
||||
|
||||
extern const struct pit8253_config bebox_pit8254_config;
|
||||
extern const i8237_interface bebox_dma8237_1_config;
|
||||
extern const i8237_interface bebox_dma8237_2_config;
|
||||
extern const am9517a_interface bebox_dma8237_1_config;
|
||||
extern const am9517a_interface bebox_dma8237_2_config;
|
||||
extern const ins8250_interface bebox_uart_inteface_0;
|
||||
extern const ins8250_interface bebox_uart_inteface_1;
|
||||
extern const ins8250_interface bebox_uart_inteface_2;
|
||||
|
||||
@ -32,7 +32,7 @@
|
||||
|
||||
#include "machine/6840ptm.h"
|
||||
#include "machine/68681.h"
|
||||
#include "machine/8237dma.h"
|
||||
#include "machine/am9517a.h"
|
||||
#include "machine/mc146818.h"
|
||||
#include "machine/pic8259.h"
|
||||
|
||||
@ -332,22 +332,22 @@ static const UINT8 channel2page_register[8] = { 7, 3, 1, 2, 0, 11, 9, 10};
|
||||
static UINT8 dn3000_dma_channel1 = 1; // 1 = memory/ctape, 2 = floppy dma channel
|
||||
static UINT8 dn3000_dma_channel2 = 5; // 5 = memory dma channel
|
||||
|
||||
INLINE i8237_device *get_device_dma8237_1(device_t *device) {
|
||||
return device->machine().driver_data<apollo_state>()->dma8237_1;
|
||||
INLINE am9517a_device *get_device_dma8237_1(device_t *device) {
|
||||
return device->machine().driver_data<apollo_state>()->m_dma8237_1;
|
||||
}
|
||||
|
||||
INLINE i8237_device *get_device_dma8237_2(device_t *device) {
|
||||
return device->machine().driver_data<apollo_state>()->dma8237_2;
|
||||
INLINE am9517a_device *get_device_dma8237_2(device_t *device) {
|
||||
return device->machine().driver_data<apollo_state>()->m_dma8237_2;
|
||||
}
|
||||
|
||||
static void apollo_dma_fdc_drq(device_t *device, int state) {
|
||||
DLOG2(("apollo_dma_fdc_drq: state=%x", state));
|
||||
get_device_dma8237_1(device)->i8237_dreq2_w(state);
|
||||
get_device_dma8237_1(device)->dreq2_w(state);
|
||||
}
|
||||
|
||||
static void apollo_dma_ctape_drq(device_t *device, int state) {
|
||||
DLOG1(("apollo_dma_ctape_drq: state=%x", state));
|
||||
get_device_dma8237_1(device)->i8237_dreq1_w(state);
|
||||
get_device_dma8237_1(device)->dreq1_w(state);
|
||||
}
|
||||
|
||||
/*-------------------------------------------------
|
||||
@ -356,11 +356,11 @@ static void apollo_dma_ctape_drq(device_t *device, int state) {
|
||||
|
||||
WRITE8_MEMBER(apollo_state::apollo_dma_1_w){
|
||||
SLOG1(("apollo_dma_1_w: writing DMA Controller 1 at offset %02x = %02x", offset, data));
|
||||
get_device_dma8237_1(&space.device())->i8237_w(space, offset, data);
|
||||
get_device_dma8237_1(&space.device())->write(space, offset, data);
|
||||
}
|
||||
|
||||
READ8_MEMBER(apollo_state::apollo_dma_1_r){
|
||||
UINT8 data = get_device_dma8237_1(&space.device())->i8237_r(space, offset);
|
||||
UINT8 data = get_device_dma8237_1(&space.device())->read(space, offset);
|
||||
SLOG1(("apollo_dma_1_r: reading DMA Controller 1 at offset %02x = %02x", offset, data));
|
||||
return data;
|
||||
}
|
||||
@ -371,11 +371,11 @@ READ8_MEMBER(apollo_state::apollo_dma_1_r){
|
||||
|
||||
WRITE8_MEMBER(apollo_state::apollo_dma_2_w){
|
||||
SLOG1(("apollo_dma_2_w: writing DMA Controller 2 at offset %02x = %02x", offset/2, data));
|
||||
get_device_dma8237_2(&space.device())->i8237_w(space, offset / 2, data);
|
||||
get_device_dma8237_2(&space.device())->write(space, offset / 2, data);
|
||||
}
|
||||
|
||||
READ8_MEMBER(apollo_state::apollo_dma_2_r){
|
||||
UINT8 data = get_device_dma8237_2(&space.device())->i8237_r(space, offset / 2);
|
||||
UINT8 data = get_device_dma8237_2(&space.device())->read(space, offset / 2);
|
||||
SLOG1(("apollo_dma_2_r: reading DMA Controller 2 at offset %02x = %02x", offset/2, data));
|
||||
return data;
|
||||
}
|
||||
@ -553,10 +553,10 @@ WRITE_LINE_MEMBER(apollo_state::apollo_dma8237_out_eop ) {
|
||||
|
||||
WRITE_LINE_MEMBER(apollo_state::apollo_dma_1_hrq_changed ) {
|
||||
// DLOG2(("dma 1 hrq changed state %02x", state));
|
||||
get_device_dma8237_2(machine().device(APOLLO_DMA1_TAG))->i8237_dreq0_w(state);
|
||||
m_dma8237_2->dreq0_w(state);
|
||||
|
||||
/* Assert HLDA */
|
||||
dynamic_cast<i8237_device*>(machine().device(APOLLO_DMA1_TAG))->i8237_hlda_w(state);
|
||||
//m_dma8237_1->hack_w(state);
|
||||
|
||||
// cascade mode?
|
||||
// i8237_hlda_w(get_device_dma8237_2(device), state);
|
||||
@ -564,10 +564,10 @@ WRITE_LINE_MEMBER(apollo_state::apollo_dma_1_hrq_changed ) {
|
||||
|
||||
WRITE_LINE_MEMBER(apollo_state::apollo_dma_2_hrq_changed ) {
|
||||
// DLOG2(("dma 2 hrq changed state %02x", state));
|
||||
machine().device(MAINCPU)->execute().set_input_line(INPUT_LINE_HALT, state ? ASSERT_LINE : CLEAR_LINE);
|
||||
m_maincpu->set_input_line(INPUT_LINE_HALT, state ? ASSERT_LINE : CLEAR_LINE);
|
||||
|
||||
/* Assert HLDA */
|
||||
dynamic_cast<i8237_device*>(machine().device(APOLLO_DMA2_TAG))->i8237_hlda_w(state);
|
||||
m_dma8237_2->hack_w(state);
|
||||
}
|
||||
|
||||
static I8237_INTERFACE( apollo_dma8237_1_config )
|
||||
@ -600,11 +600,11 @@ static I8237_INTERFACE( apollo_dma8237_2_config )
|
||||
#define VERBOSE 0
|
||||
|
||||
INLINE pic8259_device *get_pic8259_master(device_t *device) {
|
||||
return device->machine().driver_data<apollo_state>()->pic8259_master;
|
||||
return device->machine().driver_data<apollo_state>()->m_pic8259_master;
|
||||
}
|
||||
|
||||
INLINE pic8259_device *get_pic8259_slave(device_t *device) {
|
||||
return device->machine().driver_data<apollo_state>()->pic8259_slave;
|
||||
return device->machine().driver_data<apollo_state>()->m_pic8259_slave;
|
||||
}
|
||||
|
||||
/*-------------------------------------------------
|
||||
@ -692,7 +692,7 @@ IRQ_CALLBACK_MEMBER(apollo_state::apollo_pic_acknowledge)
|
||||
WRITE_LINE_MEMBER( apollo_state::apollo_pic8259_master_set_int_line ) {
|
||||
static int interrupt_line = -1;
|
||||
if (state != interrupt_line) {
|
||||
device_t *device = pic8259_master;
|
||||
device_t *device = m_pic8259_master;
|
||||
DLOG1(("apollo_pic8259_master_set_int_line: %x", state));
|
||||
}
|
||||
interrupt_line = state;
|
||||
@ -705,13 +705,13 @@ WRITE_LINE_MEMBER( apollo_state::apollo_pic8259_master_set_int_line ) {
|
||||
apollo_set_cache_status_register(0x10, state ? 0x10 : 0x00);
|
||||
}
|
||||
|
||||
machine().device(MAINCPU)->execute().set_input_line_and_vector(M68K_IRQ_6,state ? ASSERT_LINE : CLEAR_LINE, M68K_INT_ACK_AUTOVECTOR);
|
||||
m_maincpu->set_input_line_and_vector(M68K_IRQ_6,state ? ASSERT_LINE : CLEAR_LINE, M68K_INT_ACK_AUTOVECTOR);
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER( apollo_state::apollo_pic8259_slave_set_int_line ) {
|
||||
static int interrupt_line = -1;
|
||||
if (state != interrupt_line) {
|
||||
device_t *device = pic8259_slave;
|
||||
device_t *device = m_pic8259_slave;
|
||||
DLOG1(("apollo_pic8259_slave_set_int_line: %x", state));
|
||||
interrupt_line = state;
|
||||
apollo_pic_set_irq_line(device, 3, state);
|
||||
@ -1414,11 +1414,6 @@ MACHINE_RESET_MEMBER(apollo_state,apollo)
|
||||
{
|
||||
//MLOG1(("machine_reset_apollo"));
|
||||
|
||||
dma8237_1 = machine().device<i8237_device>(APOLLO_DMA1_TAG);
|
||||
dma8237_2 = machine().device<i8237_device>(APOLLO_DMA2_TAG);
|
||||
pic8259_master = machine().device<pic8259_device>(APOLLO_PIC1_TAG);
|
||||
pic8259_slave = machine().device<pic8259_device>(APOLLO_PIC2_TAG);
|
||||
|
||||
// set configuration
|
||||
apollo_csr_set_servicemode(apollo_config(APOLLO_CONF_SERVICE_MODE));
|
||||
|
||||
|
||||
@ -49,8 +49,7 @@ void at_state::at_speaker_set_input(UINT8 data)
|
||||
|
||||
WRITE_LINE_MEMBER( at_state::at_pit8254_out0_changed )
|
||||
{
|
||||
if (m_pic8259_master)
|
||||
m_pic8259_master->ir0_w(state);
|
||||
m_pic8259_master->ir0_w(state);
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -100,7 +100,7 @@
|
||||
#include "machine/mc146818.h"
|
||||
#include "machine/pic8259.h"
|
||||
#include "machine/pit8253.h"
|
||||
#include "machine/8237dma.h"
|
||||
#include "machine/am9517a.h"
|
||||
#include "machine/idectrl.h"
|
||||
#include "machine/pci.h"
|
||||
#include "machine/intelfsh.h"
|
||||
@ -453,17 +453,13 @@ const ins8250_interface bebox_uart_inteface_3 =
|
||||
void bebox_state::fdc_interrupt(bool state)
|
||||
{
|
||||
bebox_set_irq_bit(machine(), 13, state);
|
||||
if ( m_devices.pic8259_master ) {
|
||||
m_devices.pic8259_master->ir6_w(state);
|
||||
}
|
||||
m_pic8259_1->ir6_w(state);
|
||||
}
|
||||
|
||||
|
||||
void bebox_state::fdc_dma_drq(bool state)
|
||||
{
|
||||
if ( m_devices.dma8237_1 ) {
|
||||
m_devices.dma8237_1->i8237_dreq2_w(state);
|
||||
}
|
||||
m_dma8237_1->dreq2_w(state);
|
||||
}
|
||||
|
||||
/*************************************
|
||||
@ -475,7 +471,7 @@ void bebox_state::fdc_dma_drq(bool state)
|
||||
READ64_MEMBER(bebox_state::bebox_interrupt_ack_r )
|
||||
{
|
||||
UINT32 result;
|
||||
result = m_devices.pic8259_master->acknowledge();
|
||||
result = m_pic8259_1->acknowledge();
|
||||
bebox_set_irq_bit(space.machine(), 5, 0); /* HACK */
|
||||
return ((UINT64) result) << 56;
|
||||
}
|
||||
@ -494,16 +490,12 @@ WRITE_LINE_MEMBER(bebox_state::bebox_pic8259_master_set_int_line)
|
||||
|
||||
WRITE_LINE_MEMBER(bebox_state::bebox_pic8259_slave_set_int_line)
|
||||
{
|
||||
if (m_devices.pic8259_master)
|
||||
m_devices.pic8259_master->ir2_w(state);
|
||||
m_pic8259_1->ir2_w(state);
|
||||
}
|
||||
|
||||
READ8_MEMBER(bebox_state::get_slave_ack)
|
||||
{
|
||||
if (offset==2) { // IRQ = 2
|
||||
return m_devices.pic8259_slave->acknowledge();
|
||||
}
|
||||
return 0x00;
|
||||
return m_pic8259_2->acknowledge();
|
||||
}
|
||||
|
||||
|
||||
@ -543,9 +535,7 @@ WRITE64_MEMBER(bebox_state::bebox_800003F0_w )
|
||||
WRITE_LINE_MEMBER(bebox_state::bebox_ide_interrupt)
|
||||
{
|
||||
bebox_set_irq_bit(machine(), 7, state);
|
||||
if ( m_devices.pic8259_master ) {
|
||||
m_devices.pic8259_master->ir6_w(state);
|
||||
}
|
||||
m_pic8259_1->ir6_w(state);
|
||||
}
|
||||
|
||||
|
||||
@ -692,7 +682,7 @@ WRITE_LINE_MEMBER(bebox_state::bebox_dma_hrq_changed)
|
||||
m_ppc1->set_input_line(INPUT_LINE_HALT, state ? ASSERT_LINE : CLEAR_LINE);
|
||||
|
||||
/* Assert HLDA */
|
||||
machine().device<i8237_device>("dma8237_1")->i8237_hlda_w( state );
|
||||
m_dma8237_1->hack_w( state );
|
||||
}
|
||||
|
||||
|
||||
@ -772,8 +762,7 @@ I8237_INTERFACE( bebox_dma8237_2_config )
|
||||
|
||||
WRITE_LINE_MEMBER(bebox_state::bebox_timer0_w)
|
||||
{
|
||||
if (m_devices.pic8259_master)
|
||||
m_devices.pic8259_master->ir0_w(state);
|
||||
m_pic8259_1->ir0_w(state);
|
||||
}
|
||||
|
||||
|
||||
@ -959,10 +948,6 @@ void bebox_state::device_timer(emu_timer &timer, device_timer_id id, int param,
|
||||
switch (id)
|
||||
{
|
||||
case TIMER_GET_DEVICES:
|
||||
m_devices.pic8259_master = machine().device<pic8259_device>("pic8259_master");
|
||||
m_devices.pic8259_slave = machine().device<pic8259_device>("pic8259_slave");
|
||||
m_devices.dma8237_1 = machine().device<i8237_device>("dma8237_1");
|
||||
m_devices.dma8237_2 = machine().device<i8237_device>("dma8237_2");
|
||||
break;
|
||||
default:
|
||||
assert_always(FALSE, "Unknown id in bebox_state::device_timer");
|
||||
@ -978,11 +963,6 @@ void bebox_state::device_timer(emu_timer &timer, device_timer_id id, int param,
|
||||
|
||||
void bebox_state::machine_reset()
|
||||
{
|
||||
m_devices.pic8259_master = NULL;
|
||||
m_devices.pic8259_slave = NULL;
|
||||
m_devices.dma8237_1 = NULL;
|
||||
m_devices.dma8237_2 = NULL;
|
||||
|
||||
timer_set(attotime::zero, TIMER_GET_DEVICES);
|
||||
|
||||
m_ppc1->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user