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https://github.com/holub/mame
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ns32081: new device
This commit is contained in:
Patrick Mackinlay
parent
3771e38193
commit
a89f9b274e
@ -4557,3 +4557,14 @@ if (MACHINES["BL_HANDHELDS_MENUCONTROL"]~=null) then
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MAME_DIR .. "src/devices/machine/bl_handhelds_menucontrol.h",
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}
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end
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---------------------------------------------------
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--
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--@src/devices/machine/ns32081.h,MACHINES["NS32081"] = true
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---------------------------------------------------
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if (MACHINES["NS32081"]~=null) then
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files {
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MAME_DIR .. "src/devices/machine/ns32081.cpp",
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MAME_DIR .. "src/devices/machine/ns32081.h",
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}
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end
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@ -780,6 +780,7 @@ MACHINES["EDLC"] = true
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MACHINES["WTL3132"] = true
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MACHINES["CXD1185"] = true
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MACHINES["BL_HANDHELDS_MENUCONTROL"] = true
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MACHINES["NS32081"] = true
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--------------------------------------------------
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-- specify available bus cores
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630
src/devices/machine/ns32081.cpp
Normal file
630
src/devices/machine/ns32081.cpp
Normal file
@ -0,0 +1,630 @@
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// license:BSD-3-Clause
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// copyright-holders:Patrick Mackinlay
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/*
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* National Semiconductor 32081 Floating-Point Unit.
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*
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* Sources:
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* - http://bitsavers.org/components/national/_dataBooks/1989_National_Microprocessor_Databook_32000_NSC800.pdf
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*
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* TODO:
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* - testing
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*/
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#include "emu.h"
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#include "ns32081.h"
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#include "softfloat3/source/include/softfloat.h"
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#define LOG_GENERAL (1U << 0)
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//#define VERBOSE (LOG_GENERAL)
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#include "logmacro.h"
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DEFINE_DEVICE_TYPE(NS32081, ns32081_device, "ns32081", "National Semiconductor 32081 Floating-Point Unit")
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enum fsr_mask : u32
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{
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FSR_TT = 0x00000007, // trap type
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FSR_UEN = 0x00000008, // underflow trap enable
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FSR_UF = 0x00000010, // underflow flag
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FSR_IEN = 0x00000020, // inexact result trap enable
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FSR_IF = 0x00000040, // inexact result flag
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FSR_RM = 0x00000180, // rounding mode
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FSR_SWF = 0x0000fe00, // software field
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};
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enum rm_mask : u32
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{
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RM_N = 0x00000000, // round to nearest value
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RM_Z = 0x00000080, // round toward zero
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RM_U = 0x00000100, // round toward positive infinity
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RM_D = 0x00000180, // round toward negative infinity
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};
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enum tt_mask : u32
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{
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TT_UND = 0x00000001, // underflow
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TT_OVF = 0x00000002, // overflow
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TT_DVZ = 0x00000003, // divide by zero
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TT_ILL = 0x00000004, // illegal instruction
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TT_INV = 0x00000005, // invalid operation
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TT_INX = 0x00000006, // inexact result
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TT_RSV = 0x00000007, // reserved
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};
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enum state : unsigned
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{
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IDLE = 0,
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OPERATION = 1, // awaiting operation word
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OPERAND = 2, // awaiting operands
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STATUS = 4, // status word available
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RESULT = 5, // result word available
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};
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enum idbyte : u8
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{
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FORMAT_9 = 0x3e,
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FORMAT_11 = 0xbe,
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};
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enum operand_length : unsigned
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{
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LENGTH_F = 4, // single precision
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LENGTH_L = 8, // double precision
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};
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enum size_code : unsigned
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{
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SIZE_B = 0,
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SIZE_W = 1,
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SIZE_D = 3,
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};
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ns32081_device::ns32081_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock)
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: device_t(mconfig, NS32081, tag, owner, clock)
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, ns32000_slave_interface(mconfig, *this)
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{
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}
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void ns32081_device::device_start()
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{
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save_item(NAME(m_fsr));
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save_item(NAME(m_f));
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save_item(NAME(m_idbyte));
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save_item(NAME(m_opword));
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save_item(STRUCT_MEMBER(m_op, expected));
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save_item(STRUCT_MEMBER(m_op, issued));
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save_item(STRUCT_MEMBER(m_op, value));
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save_item(NAME(m_status));
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save_item(NAME(m_state));
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save_item(NAME(m_tcy));
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m_complete = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(ns32081_device::complete), this));
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}
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void ns32081_device::device_reset()
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{
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m_fsr = 0;
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std::fill_n(&m_f[0], ARRAY_LENGTH(m_f), 0);
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m_state = IDLE;
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}
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void ns32081_device::state_add(device_state_interface &parent, int &index)
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{
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parent.state_add(index++, "FSR", m_fsr).formatstr("%04X");
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for (unsigned i = 0; i < 8; i++)
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parent.state_add(index++, util::string_format("F%d", i).c_str(), m_f[i]).formatstr("%08X");
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}
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u16 ns32081_device::read_st(int *icount)
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{
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if (m_state == STATUS)
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{
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m_state = (m_op[2].issued == m_op[2].expected) ? IDLE : RESULT;
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if (icount)
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*icount -= m_tcy;
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LOG("read_st status 0x%04x tcy %d %s (%s)\n", m_status, m_tcy,
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(m_state == RESULT ? "results pending" : "complete"), machine().describe_context());
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return m_status;
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}
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logerror("protocol error reading status word (%s)\n", machine().describe_context());
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return 0;
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}
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u16 ns32081_device::read_op()
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{
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if (m_state == RESULT && m_op[2].issued < m_op[2].expected)
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{
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u16 const data = u16(m_op[2].value >> (m_op[2].issued * 8));
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LOG("read_op word %d data 0x%04x (%s)\n", m_op[2].issued >> 1, data, machine().describe_context());
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m_op[2].issued += 2;
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if (m_op[2].issued == m_op[2].expected)
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{
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LOG("read_op last result word issued\n");
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m_state = IDLE;
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}
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return data;
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}
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logerror("protocol error reading result word (%s)\n", machine().describe_context());
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return 0;
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}
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void ns32081_device::write_id(u16 data)
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{
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bool const match = (data == FORMAT_9) || (data == FORMAT_11);
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if (match)
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{
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LOG("write_id match 0x%04x (%s)\n", data, machine().describe_context());
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m_state = OPERATION;
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}
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else
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{
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LOG("write_id ignore 0x%04x (%s)\n", data, machine().describe_context());
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m_state = IDLE;
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}
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m_idbyte = u8(data);
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}
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void ns32081_device::write_op(u16 data)
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{
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switch (m_state)
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{
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case OPERATION:
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m_opword = swapendian_int16(data);
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LOG("write_op opword 0x%04x (%s)\n", m_opword, machine().describe_context());
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// initialize operands
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for (operand &op : m_op)
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{
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op.expected = 0;
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op.issued = 0;
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op.value = 0;
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}
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// decode operands
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if (m_idbyte == FORMAT_9)
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{
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// format 9: 1111 1222 22oo ofii
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unsigned const f_length = BIT(m_opword, 2) ? LENGTH_F : LENGTH_L;
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unsigned const size = m_opword & 3;
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switch ((m_opword >> 3) & 7)
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{
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case 0: // movif
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m_op[0].expected = size + 1;
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m_op[2].expected = f_length;
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break;
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case 1: // lfsr
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m_op[0].expected = 4;
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break;
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case 2: // movlf
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m_op[0].expected = LENGTH_L;
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m_op[2].expected = f_length;
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break;
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case 3: // movfl
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m_op[0].expected = LENGTH_F;
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m_op[2].expected = f_length;
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break;
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case 4: // roundfi
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case 5: // truncfi
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case 7: // floorfi
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m_op[0].expected = f_length;
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m_op[2].expected = size + 1;
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break;
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case 6: // sfsr
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m_op[2].expected = 4;
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break;
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}
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}
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else if (m_idbyte == FORMAT_11)
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{
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// format 11: 1111 1222 22oo oo0f
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unsigned const opcode = (m_opword >> 2) & 15;
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unsigned const f_length = BIT(m_opword, 0) ? LENGTH_F : LENGTH_L;
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m_op[0].expected = f_length;
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// even opcodes have two input operands
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if (!BIT(opcode, 0))
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m_op[1].expected = f_length;
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// all operations except CMPf issue a result
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if (opcode != 2)
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m_op[2].expected = f_length;
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}
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// operand 1 in register
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if (m_op[0].expected && !(m_opword & 0xc000))
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{
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// exclude integer operands
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if (m_idbyte == FORMAT_11 || ((m_opword >> 3) & 7) > 1)
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{
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unsigned const reg = (m_opword >> 11) & 7;
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LOG("write_op read f%d\n", reg);
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m_op[0].value = m_f[reg ^ 0];
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if (m_op[0].expected == 8)
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m_op[0].value |= u64(m_f[reg ^ 1]) << 32;
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m_op[0].issued = m_op[0].expected;
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}
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}
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// operand 2 in register
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if (m_op[1].expected && !(m_opword & 0x0600))
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{
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unsigned const reg = (m_opword >> 6) & 7;
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LOG("write_op read f%d\n", reg);
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m_op[1].value = m_f[reg ^ 0];
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if (m_op[1].expected == 8)
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m_op[1].value |= u64(m_f[reg ^ 1]) << 32;
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m_op[1].issued = m_op[1].expected;
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}
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m_state = OPERAND;
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break;
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case OPERAND:
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// check awaiting operand word
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if (m_op[0].issued < m_op[0].expected || m_op[1].issued < m_op[1].expected)
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{
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unsigned const n = (m_op[0].issued < m_op[0].expected) ? 0 : 1;
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operand &op = m_op[n];
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LOG("write_op op%d data 0x%04x (%s)\n", n, data, machine().describe_context());
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// insert word into operand value
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op.value |= u64(data) << (op.issued * 8);
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op.issued += 2;
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}
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else
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logerror("protocol error unexpected operand word 0x%04x (%s)\n", data, machine().describe_context());
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break;
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}
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// start execution when all operands are available
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if (m_state == OPERAND && m_op[0].issued == m_op[0].expected && m_op[1].issued == m_op[1].expected)
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execute();
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}
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void ns32081_device::execute()
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{
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softfloat_exceptionFlags = 0;
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m_fsr &= ~FSR_TT;
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m_status = 0;
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m_tcy = 0;
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switch (m_idbyte)
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{
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case FORMAT_9:
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// format 9: 1111 1222 22oo ofii
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{
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bool const single = BIT(m_opword, 2);
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unsigned const f_length = single ? LENGTH_F : LENGTH_L;
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unsigned const size = m_opword & 3;
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switch ((m_opword >> 3) & 7)
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{
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case 0:
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// MOVif src,dest
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// gen,gen
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// read.i,write.f
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if (single)
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m_op[2].value = i32_to_f32(m_op[0].value).v;
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else
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m_op[2].value = i32_to_f64(m_op[0].value).v;
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m_op[2].expected = f_length;
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m_tcy = 53;
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break;
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case 1:
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// LFSR src
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// gen
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// read.D
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m_fsr = u16(m_op[0].value);
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switch (m_fsr & FSR_RM)
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{
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case RM_N: softfloat_roundingMode = softfloat_round_near_even; break;
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case RM_Z: softfloat_roundingMode = softfloat_round_minMag; break;
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case RM_U: softfloat_roundingMode = softfloat_round_max; break;
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case RM_D: softfloat_roundingMode = softfloat_round_min; break;
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}
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m_tcy = 18;
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break;
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case 2:
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// MOVLF src,dest
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// gen,gen
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// read.L,write.F
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m_op[2].value = f64_to_f32(float64_t{ m_op[0].value }).v;
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m_op[2].expected = f_length;
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m_tcy = (m_opword & 0xc000) ? 23 : 27;
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break;
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case 3:
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// MOVFL src,dest
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// gen,gen
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// read.F,write.L
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m_op[2].value = f32_to_f64(float32_t{ u32(m_op[0].value) }).v;
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m_op[2].expected = f_length;
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m_tcy = (m_opword & 0xc000) ? 22 : 26;
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break;
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case 4:
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// ROUNDfi src,dest
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// gen,gen
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// read.f,write.i
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if (single)
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m_op[2].value = f32_to_i64(float32_t{ u32(m_op[0].value) }, softfloat_round_near_even, true);
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else
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m_op[2].value = f64_to_i64(float64_t{ m_op[0].value }, softfloat_round_near_even, true);
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if ((size == SIZE_D && s64(m_op[2].value) != s32(m_op[2].value))
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|| (size == SIZE_W && s64(m_op[2].value) != s16(m_op[2].value))
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|| (size == SIZE_B && s64(m_op[2].value) != s8(m_op[2].value)))
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softfloat_exceptionFlags |= softfloat_flag_overflow;
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m_op[2].expected = size + 1;
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m_tcy = (m_opword & 0xc000) ? 53 : 66;
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break;
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case 5:
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// TRUNCfi src,dest
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// gen,gen
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// read.f,write.i
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if (single)
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m_op[2].value = f32_to_i64(float32_t{ u32(m_op[0].value) }, softfloat_round_minMag, true);
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else
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m_op[2].value = f64_to_i64(float64_t{ m_op[0].value }, softfloat_round_minMag, true);
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if ((size == SIZE_D && s64(m_op[2].value) != s32(m_op[2].value))
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|| (size == SIZE_W && s64(m_op[2].value) != s16(m_op[2].value))
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|| (size == SIZE_B && s64(m_op[2].value) != s8(m_op[2].value)))
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softfloat_exceptionFlags |= softfloat_flag_overflow;
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m_op[2].expected = size + 1;
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m_tcy = (m_opword & 0xc000) ? 53 : 66;
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break;
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case 6:
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// SFSR dest
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// gen
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// write.D
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m_op[2].value = m_fsr;
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m_op[2].expected = 4;
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m_tcy = 13;
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break;
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case 7:
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// FLOORfi src,dest
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// gen,gen
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// read.f,write.i
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if (single)
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m_op[2].value = f32_to_i64(float32_t{ u32(m_op[0].value) }, softfloat_round_min, true);
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else
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m_op[2].value = f64_to_i64(float64_t{ m_op[0].value }, softfloat_round_min, true);
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if ((size == SIZE_D && s64(m_op[2].value) != s32(m_op[2].value))
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|| (size == SIZE_W && s64(m_op[2].value) != s16(m_op[2].value))
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|| (size == SIZE_B && s64(m_op[2].value) != s8(m_op[2].value)))
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softfloat_exceptionFlags |= softfloat_flag_overflow;
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m_op[2].expected = size + 1;
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m_tcy = (m_opword & 0xc000) ? 53 : 66;
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break;
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}
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}
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break;
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case FORMAT_11:
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// format 11: 1111122222oooo0f
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{
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bool const single = BIT(m_opword, 0);
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||||
unsigned const f_length = single ? LENGTH_F : LENGTH_L;
|
||||
|
||||
switch ((m_opword >> 2) & 15)
|
||||
{
|
||||
case 0x0:
|
||||
// ADDf src,dest
|
||||
// gen,gen
|
||||
// read.f,rmw.f
|
||||
if (single)
|
||||
m_op[2].value = f32_add(float32_t{ u32(m_op[1].value) }, float32_t{ u32(m_op[0].value) }).v;
|
||||
else
|
||||
m_op[2].value = f64_add(float64_t{ m_op[1].value }, float64_t{ m_op[0].value }).v;
|
||||
m_op[2].expected = f_length;
|
||||
m_tcy = (m_opword & 0xc600) ? 70 : 74;
|
||||
break;
|
||||
case 0x1:
|
||||
// MOVf src,dest
|
||||
// gen,gen
|
||||
// read.f,write.f
|
||||
m_op[2].value = m_op[0].value;
|
||||
m_op[2].expected = f_length;
|
||||
m_tcy = (m_opword & 0xc000) ? 23 : 27;
|
||||
break;
|
||||
case 0x2:
|
||||
// CMPf src1,src2
|
||||
// gen,gen
|
||||
// read.f,read.f
|
||||
if (m_op[0].value == m_op[1].value)
|
||||
m_status |= SLAVE_Z;
|
||||
if ((single && f32_le(float32_t{ u32(m_op[1].value) }, float32_t{ u32(m_op[0].value) }))
|
||||
|| (!single && f64_le(float64_t{ m_op[1].value }, float64_t{ m_op[0].value })))
|
||||
m_status |= SLAVE_N;
|
||||
m_tcy = (m_opword & 0xc600) ? 45 : 49;
|
||||
break;
|
||||
case 0x3:
|
||||
// Trap(SLAVE)
|
||||
m_fsr |= TT_ILL;
|
||||
m_status = SLAVE_Q;
|
||||
break;
|
||||
case 0x4:
|
||||
// SUBf src,dest
|
||||
// gen,gen
|
||||
// read.f,rmw.f
|
||||
if (single)
|
||||
m_op[2].value = f32_sub(float32_t{ u32(m_op[1].value) }, float32_t{ u32(m_op[0].value) }).v;
|
||||
else
|
||||
m_op[2].value = f64_sub(float64_t{ m_op[1].value }, float64_t{ m_op[0].value }).v;
|
||||
m_op[2].expected = f_length;
|
||||
m_tcy = (m_opword & 0xc600) ? 70 : 74;
|
||||
break;
|
||||
case 0x5:
|
||||
// NEGf src,dest
|
||||
// gen,gen
|
||||
// read.f,write.f
|
||||
if (single)
|
||||
m_op[2].value = f32_mul(float32_t{ u32(m_op[0].value) }, i32_to_f32(-1)).v;
|
||||
else
|
||||
m_op[2].value = f64_mul(float64_t{ m_op[0].value }, i32_to_f64(-1)).v;
|
||||
m_op[2].expected = f_length;
|
||||
m_tcy = (m_opword & 0xc000) ? 20 : 24;
|
||||
break;
|
||||
case 0x8:
|
||||
// DIVf src,dest
|
||||
// gen,gen
|
||||
// read.f,rmw.f
|
||||
if (single)
|
||||
m_op[2].value = f32_div(float32_t{ u32(m_op[1].value) }, float32_t{ u32(m_op[0].value) }).v;
|
||||
else
|
||||
m_op[2].value = f64_div(float64_t{ m_op[1].value }, float64_t{ m_op[0].value }).v;
|
||||
m_op[2].expected = f_length;
|
||||
m_tcy = ((m_opword & 0xc600) ? 55 : 59) + (single ? 30 : 60);
|
||||
break;
|
||||
case 0x9:
|
||||
// Trap(SLAVE)
|
||||
m_fsr |= TT_ILL;
|
||||
m_status = SLAVE_Q;
|
||||
break;
|
||||
case 0xc:
|
||||
// MULf src,dest
|
||||
// gen,gen
|
||||
// read.f,rmw.f
|
||||
if (single)
|
||||
m_op[2].value = f32_mul(float32_t{ u32(m_op[1].value) }, float32_t{ u32(m_op[0].value) }).v;
|
||||
else
|
||||
m_op[2].value = f64_mul(float64_t{ m_op[1].value }, float64_t{ m_op[0].value }).v;
|
||||
m_op[2].expected = f_length;
|
||||
m_tcy = ((m_opword & 0xc600) ? 30 : 34) + (single ? 14 : 28);
|
||||
break;
|
||||
case 0xd:
|
||||
// ABSf src,dest
|
||||
// gen,gen
|
||||
// read.f,write.f
|
||||
if (single)
|
||||
if (f32_lt(float32_t{ u32(m_op[0].value) }, float32_t{ 0 }))
|
||||
m_op[2].value = f32_mul(float32_t{ u32(m_op[0].value) }, i32_to_f32(-1)).v;
|
||||
else
|
||||
m_op[2].value = float32_t{ u32(m_op[0].value) }.v;
|
||||
else
|
||||
if (f64_lt(float64_t{ m_op[0].value }, float64_t{ 0 }))
|
||||
m_op[2].value = f64_mul(float64_t{ m_op[0].value }, i32_to_f64(-1)).v;
|
||||
else
|
||||
m_op[2].value = float64_t{ m_op[0].value }.v;
|
||||
m_op[2].expected = f_length;
|
||||
m_tcy = (m_opword & 0xc000) ? 20 : 24;
|
||||
break;
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
// check for exceptions
|
||||
if (softfloat_exceptionFlags & softfloat_flag_underflow)
|
||||
{
|
||||
m_fsr |= FSR_UF | TT_UND;
|
||||
|
||||
if (m_fsr & FSR_UEN)
|
||||
m_status |= SLAVE_Q;
|
||||
else
|
||||
m_op[2].value = 0;
|
||||
}
|
||||
else if (softfloat_exceptionFlags & softfloat_flag_overflow)
|
||||
{
|
||||
m_fsr |= TT_OVF;
|
||||
m_status |= SLAVE_Q;
|
||||
}
|
||||
else if (softfloat_exceptionFlags & softfloat_flag_infinite)
|
||||
{
|
||||
m_fsr |= TT_DVZ;
|
||||
m_status |= SLAVE_Q;
|
||||
}
|
||||
else if (softfloat_exceptionFlags & softfloat_flag_invalid)
|
||||
m_fsr |= TT_INV;
|
||||
else if (softfloat_exceptionFlags & softfloat_flag_inexact)
|
||||
{
|
||||
m_fsr |= FSR_IF | TT_INX;
|
||||
|
||||
if (m_fsr & FSR_IEN)
|
||||
m_status |= SLAVE_Q;
|
||||
}
|
||||
|
||||
// exceptions suppress result issue
|
||||
if (m_status & SLAVE_Q)
|
||||
m_op[2].expected = 0;
|
||||
|
||||
if (VERBOSE & LOG_GENERAL)
|
||||
{
|
||||
static char const *format9[] = { "movif", "lfsr", "movlf", "movfl", "roundfi", "truncfi", "sfsr", "floorfi" };
|
||||
static char const *format11[] =
|
||||
{
|
||||
"addf", "movf", "cmpf", nullptr, "subf", "negf", nullptr, nullptr,
|
||||
"divf", nullptr, nullptr, nullptr, "mulf", "absf", nullptr, nullptr
|
||||
};
|
||||
|
||||
if (m_status & SLAVE_Q)
|
||||
LOG("execute %s 0x%x,0x%x exception\n",
|
||||
(m_idbyte == FORMAT_9)
|
||||
? format9[(m_opword >> 3) & 7]
|
||||
: format11[(m_opword >> 2) & 15],
|
||||
m_op[0].value, m_op[1].value);
|
||||
else
|
||||
LOG("execute %s 0x%x,0x%x result 0x%x\n",
|
||||
(m_idbyte == FORMAT_9)
|
||||
? format9[(m_opword >> 3) & 7]
|
||||
: format11[(m_opword >> 2) & 15],
|
||||
m_op[0].value, m_op[1].value, m_op[2].value);
|
||||
}
|
||||
|
||||
// write-back floating point register results
|
||||
if (m_op[2].expected && !(m_opword & 0x0600))
|
||||
{
|
||||
// exclude integer results (roundfi, truncfi, sfsr, floorfi)
|
||||
if (m_idbyte == FORMAT_11 || ((m_opword >> 3) & 7) < 4)
|
||||
{
|
||||
unsigned const reg = (m_opword >> 6) & 7;
|
||||
|
||||
LOG("execute write-back f%d\n", reg);
|
||||
|
||||
m_f[reg ^ 0] = u32(m_op[2].value >> 0);
|
||||
if (m_op[2].expected == 8)
|
||||
m_f[reg ^ 1] = u32(m_op[2].value >> 32);
|
||||
|
||||
m_op[2].issued = m_op[2].expected;
|
||||
}
|
||||
}
|
||||
|
||||
m_state = STATUS;
|
||||
|
||||
if (m_out_scb)
|
||||
m_complete->adjust(attotime::from_ticks(m_tcy, clock()));
|
||||
}
|
||||
|
||||
void ns32081_device::complete(void *buf, s32 param)
|
||||
{
|
||||
m_out_scb(0);
|
||||
m_out_scb(1);
|
||||
}
|
||||
60
src/devices/machine/ns32081.h
Normal file
60
src/devices/machine/ns32081.h
Normal file
@ -0,0 +1,60 @@
|
||||
// license:BSD-3-Clause
|
||||
// copyright-holders:Patrick Mackinlay
|
||||
|
||||
#ifndef MAME_MACHINE_NS32081_H
|
||||
#define MAME_MACHINE_NS32081_H
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "cpu/ns32000/slave.h"
|
||||
|
||||
class ns32081_device
|
||||
: public device_t
|
||||
, public ns32000_slave_interface
|
||||
{
|
||||
public:
|
||||
ns32081_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock);
|
||||
|
||||
virtual void state_add(device_state_interface &parent, int &index) override;
|
||||
|
||||
virtual u16 read_st(int *icount = nullptr) override;
|
||||
virtual u16 read_op() override;
|
||||
|
||||
virtual void write_id(u16 data) override;
|
||||
virtual void write_op(u16 data) override;
|
||||
|
||||
protected:
|
||||
// device_t overrides
|
||||
virtual void device_start() override;
|
||||
virtual void device_reset() override;
|
||||
|
||||
void execute();
|
||||
void complete(void *buf, s32 param);
|
||||
|
||||
private:
|
||||
emu_timer *m_complete;
|
||||
|
||||
// registers
|
||||
u32 m_fsr;
|
||||
u32 m_f[8];
|
||||
|
||||
// operating state
|
||||
u8 m_idbyte;
|
||||
u16 m_opword;
|
||||
struct operand
|
||||
{
|
||||
unsigned expected;
|
||||
unsigned issued;
|
||||
u64 value;
|
||||
}
|
||||
m_op[3];
|
||||
u16 m_status;
|
||||
|
||||
// implementation state
|
||||
unsigned m_state;
|
||||
unsigned m_tcy;
|
||||
};
|
||||
|
||||
DECLARE_DEVICE_TYPE(NS32081, ns32081_device)
|
||||
|
||||
#endif // MAME_MACHINE_NS32081_H
|
||||
Loading…
Reference in New Issue
Block a user