From a91bbaade81e2a62cf1ee193eab6ab3b830ab1f8 Mon Sep 17 00:00:00 2001 From: Scott Stone Date: Mon, 30 Apr 2012 17:19:12 +0000 Subject: [PATCH] Misc 68340 related progress. From Haze (nw) --- src/emu/cpu/m68000/m68000.h | 1 + src/emu/cpu/m68000/m68kcpu.c | 39 +++++++ src/mame/drivers/astrafr.c | 197 ++++++++++++++++++++++++++++++----- src/mame/drivers/bfm_sc4h.c | 150 ++++++++++++++++++-------- src/mame/drivers/bfm_swp.c | 98 +++++++++++++---- src/mame/drivers/mpu5.c | 62 ++++++++++- src/mame/drivers/pluto5.c | 62 ++++++++++- src/mame/includes/bfm_sc45.h | 9 ++ 8 files changed, 529 insertions(+), 89 deletions(-) diff --git a/src/emu/cpu/m68000/m68000.h b/src/emu/cpu/m68000/m68000.h index 880641ca9f5..0612bf0cf50 100644 --- a/src/emu/cpu/m68000/m68000.h +++ b/src/emu/cpu/m68000/m68000.h @@ -142,6 +142,7 @@ UINT16 m68k_get_fc(device_t *device); void m68307_set_port_callbacks(device_t *device, m68307_porta_read_callback porta_r, m68307_porta_write_callback m_m68307_porta_w, m68307_portb_read_callback portb_r, m68307_portb_write_callback m_m68307_portb_w); UINT16 m68307_get_cs(device_t *device, offs_t address); +UINT16 m68340_get_cs(device_t *device, offs_t address); void m68307_set_interrupt(device_t *device, int level, int vector); void m68307_timer0_interrupt(legacy_cpu_device *cpudev); void m68307_timer1_interrupt(legacy_cpu_device *cpudev); diff --git a/src/emu/cpu/m68000/m68kcpu.c b/src/emu/cpu/m68000/m68kcpu.c index f62a9decbaf..4964c0cb82c 100644 --- a/src/emu/cpu/m68000/m68kcpu.c +++ b/src/emu/cpu/m68000/m68kcpu.c @@ -1318,6 +1318,10 @@ void m68k_memory_interface::init16(address_space &space) write32 = m68k_write32_delegate(FUNC(address_space::write_dword), &space); } +/* todo: is it possible to calculate the address map based on CS when they change + and install handlers? Going through this logic for every memory access is + very slow */ + int m68307_calc_cs(m68ki_cpu_core *m68k, offs_t address) { m68307_sim* sim = m68k->m68307SIM; @@ -1333,6 +1337,32 @@ int m68307_calc_cs(m68ki_cpu_core *m68k, offs_t address) return 0; } +/* see note above */ + +int m68340_calc_cs(m68ki_cpu_core *m68k, offs_t address) +{ + m68340_sim* sim = m68k->m68340SIM; + + if ( !(sim->m_ba[0] & 1) ) return 1; + + for (int i=0;i<4;i++) + { + if (sim->m_ba[i] & 1) + { + int mask = ((sim->m_am[i]&0xffffff00) | 0xff); + int base = sim->m_ba[i] & 0xffffff00; + int fcmask = (sim->m_am[i] & 0xf0); + int fcbase = (sim->m_ba[i] & 0xf0) & ~(sim->m_am[i] & 0xf0); + int fc = m68k->mmu_tmp_fc; + + if ((address & ~mask) == base && ((fc << 4) & ~fcmask ) == fcbase ) return i+1; + } + } + + return 0; +} + + UINT16 m68k_memory_interface::simple_read_immediate_16_m68307(offs_t address) @@ -1820,6 +1850,15 @@ UINT16 m68307_get_cs(device_t *device, offs_t address) return m68k->m68307_currentcs; } +UINT16 m68340_get_cs(device_t *device, offs_t address) +{ + m68ki_cpu_core *m68k = m68k_get_safe_token(device); + + m68k->m68307_currentcs = m68340_calc_cs(m68k, address); + + return m68k->m68307_currentcs; +} + /**************************************************************************** * State definition ****************************************************************************/ diff --git a/src/mame/drivers/astrafr.c b/src/mame/drivers/astrafr.c index 1348da5b058..3d824c4007b 100644 --- a/src/mame/drivers/astrafr.c +++ b/src/mame/drivers/astrafr.c @@ -19,13 +19,33 @@ class astrafr_state : public driver_device { public: astrafr_state(const machine_config &mconfig, device_type type, const char *tag) - : driver_device(mconfig, type, tag) + : driver_device(mconfig, type, tag), + m_maincpu(*this, "maincpu"), + m_slavecpu(*this, "slavecpu") + { fgpa_first_read_addr = 0xffff; fgpa_rom_write_addr = 0xffff; fgpa_after_rom_write_addr = 0xffff; } + UINT32* m_cpuregion; + int m_cpuregion_size; + UINT32* m_mainram; + + UINT32* m_slavecpuregion; + int m_slavecpuregion_size; + UINT32* m_slaveram; + + + + DECLARE_READ32_MEMBER(astrafr_mem_r); + DECLARE_WRITE32_MEMBER(astrafr_mem_w); + + DECLARE_READ32_MEMBER(astrafr_slave_mem_r); + DECLARE_WRITE32_MEMBER(astrafr_slave_mem_w); + + // ports move above from game to game.. UINT16 fgpa_rom_write_addr; UINT16 fgpa_first_read_addr; @@ -91,48 +111,166 @@ public: logerror("%08x astra_fgpa_slave_w offset %02x %02x\n", pc, offset, data); } } + + // devices + required_device m_maincpu; + optional_device m_slavecpu; }; -static ADDRESS_MAP_START( astrafr_master_map, AS_PROGRAM, 32, astrafr_state ) - AM_RANGE(0x000000, 0x1fffff) AM_ROM - AM_RANGE(0x800000, 0x8000ff) AM_READWRITE8(astra_fgpa_r, astra_fgpa_w, 0xffffffff) - AM_RANGE(0x400000, 0x40ffff) AM_RAM // as_partyd set -ADDRESS_MAP_END -// probably identical, afaik they're linked units.. -static ADDRESS_MAP_START( astrafr_slave_map, AS_PROGRAM, 32, astrafr_state ) - AM_RANGE(0x000000, 0x1fffff) AM_ROM - AM_RANGE(0x800000, 0x8000ff) AM_READWRITE8(astra_fgpa_slave_r, astra_fgpa_slave_w, 0xffffffff) - AM_RANGE(0x400000, 0x40ffff) AM_RAM // as_partyd set +READ32_MEMBER(astrafr_state::astrafr_mem_r) +{ + int pc = cpu_get_pc(&space.device()); + int cs = m68340_get_cs(m_maincpu, offset * 4); + + switch ( cs ) + { + case 1: + if (offset> 24); + if (mem_mask&0x00ff0000) astra_fgpa_w(space, address+1, data >> 16); + if (mem_mask&0x0000ff00) astra_fgpa_w(space, address+2, data >> 8); + if (mem_mask&0x000000ff) astra_fgpa_w(space, address+3, data >> 0); + break; + + case 2: + offset &= 0x3fff; + COMBINE_DATA(&m_mainram[offset]); + break; + + default: + logerror("%08x maincpu write access offset %08x data %08x mem_mask %08x cs %d\n", pc, address, data, mem_mask, cs); + + } +} + +READ32_MEMBER(astrafr_state::astrafr_slave_mem_r) +{ + int pc = cpu_get_pc(&space.device()); + int cs = m68340_get_cs(m_slavecpu, offset * 4); + + switch ( cs ) + { + case 1: + if (offset> 24); + if (mem_mask&0x00ff0000) astra_fgpa_slave_w(space, address+1, data >> 16); + if (mem_mask&0x0000ff00) astra_fgpa_slave_w(space, address+2, data >> 8); + if (mem_mask&0x000000ff) astra_fgpa_slave_w(space, address+3, data >> 0); + break; + + case 2: + offset &= 0x3fff; + COMBINE_DATA(&m_slaveram[offset]); + break; + + default: + logerror("%08x slavecpu write access offset %08x data %08x mem_mask %08x cs %d\n", pc, address, data, mem_mask, cs); + + } +} + + + +static ADDRESS_MAP_START( astrafr_master_map, AS_PROGRAM, 32, astrafr_state ) + AM_RANGE(0x000000, 0xffffffff) AM_READWRITE(astrafr_mem_r, astrafr_mem_w) ADDRESS_MAP_END static ADDRESS_MAP_START( astrafr_master_alt_map, AS_PROGRAM, 32, astrafr_state ) - AM_RANGE(0x0000000, 0x01fffff) AM_ROM - AM_RANGE(0x1000000, 0x1009fff) AM_RAM // ? - AM_RANGE(0x2000000, 0x20000ff) AM_READWRITE8(astra_fgpa_r, astra_fgpa_w, 0xffffffff) + AM_RANGE(0x000000, 0xffffffff) AM_READWRITE(astrafr_mem_r, astrafr_mem_w) ADDRESS_MAP_END - - - static ADDRESS_MAP_START( astra_map, AS_PROGRAM, 32, astrafr_state ) - AM_RANGE(0x000000, 0x1fffff) AM_ROM - AM_RANGE(0x800000, 0x8000ff) AM_READWRITE8(astra_fgpa_r, astra_fgpa_w, 0xffffffff) - AM_RANGE(0x400000, 0x40ffff) AM_RAM // as_partyd set + AM_RANGE(0x000000, 0xffffffff) AM_READWRITE(astrafr_mem_r, astrafr_mem_w) ADDRESS_MAP_END -static ADDRESS_MAP_START( astra_alt_map, AS_PROGRAM, 32, astrafr_state ) - AM_RANGE(0x0000000, 0x01fffff) AM_ROM - AM_RANGE(0x1000000, 0x1009fff) AM_RAM // ? - AM_RANGE(0x2000000, 0x20000ff) AM_READWRITE8(astra_fgpa_r, astra_fgpa_w, 0xffffffff) +// probably identical, afaik they're linked units.. +static ADDRESS_MAP_START( astrafr_slave_map, AS_PROGRAM, 32, astrafr_state ) + AM_RANGE(0x000000, 0xffffffff) AM_READWRITE(astrafr_slave_mem_r, astrafr_slave_mem_w) ADDRESS_MAP_END + static INPUT_PORTS_START( astrafr ) INPUT_PORTS_END +static MACHINE_START( astra_common ) +{ + astrafr_state *state = machine.driver_data(); + + state->m_cpuregion = (UINT32*)state->memregion( "maincpu" )->base(); + state->m_cpuregion_size = state->memregion( "maincpu" )->bytes()/4; + state->m_mainram = (UINT32*)auto_alloc_array_clear(machine, UINT32, 0x10000); + + state->m_slavecpuregion = (UINT32*)state->memregion( "slavecpu" )->base(); + state->m_slavecpuregion_size = state->memregion( "slavecpu" )->bytes()/4; + state->m_slaveram = (UINT32*)auto_alloc_array_clear(machine, UINT32, 0x10000); + + +} + /* the FPGA area read/write addresses move around ... */ static MACHINE_START( astra_37 ) { @@ -140,6 +278,7 @@ static MACHINE_START( astra_37 ) state->fgpa_after_rom_write_addr = 0x30; state->fgpa_first_read_addr = 0x33; state->fgpa_rom_write_addr = 0x37; + MACHINE_START_CALL(astra_common); } static MACHINE_START( astra_2e ) @@ -148,6 +287,7 @@ static MACHINE_START( astra_2e ) state->fgpa_after_rom_write_addr = 0x20; state->fgpa_first_read_addr = 0x23; state->fgpa_rom_write_addr = 0x2e; + MACHINE_START_CALL(astra_common); } @@ -157,6 +297,8 @@ static MACHINE_CONFIG_START( astrafr_dual, astrafr_state ) MCFG_CPU_ADD("slavecpu", M68340, 16000000) MCFG_CPU_PROGRAM_MAP(astrafr_slave_map) + + MCFG_MACHINE_START( astra_common ) MACHINE_CONFIG_END static MACHINE_CONFIG_DERIVED( astrafr_dual_2e, astrafr_dual ) @@ -184,6 +326,7 @@ MACHINE_CONFIG_END static MACHINE_CONFIG_START( astra_single, astrafr_state ) MCFG_CPU_ADD("maincpu", M68340, 16000000) MCFG_CPU_PROGRAM_MAP(astra_map) + MCFG_MACHINE_START( astra_common ) MACHINE_CONFIG_END static MACHINE_CONFIG_DERIVED( astra_single_37, astra_single ) @@ -200,12 +343,14 @@ static MACHINE_START( astra_57 ) // state->fgpa_after_rom_write_addr = 0x20; // state->fgpa_first_read_addr = 0x23; state->fgpa_rom_write_addr = 0x57; + MACHINE_START_CALL(astra_common); } static MACHINE_CONFIG_START( astra_single_alt, astrafr_state ) MCFG_CPU_ADD("maincpu", M68340, 16000000) - MCFG_CPU_PROGRAM_MAP(astra_alt_map) + MCFG_CPU_PROGRAM_MAP(astra_map) + MCFG_MACHINE_START( astra_common ) MACHINE_CONFIG_END static MACHINE_CONFIG_DERIVED( astra_single_alt_57, astra_single_alt ) @@ -2169,7 +2314,7 @@ GAME( 200?, as_tble, as_tbl , astra_single, astrafr, 0, ROT0, "Astra GAME( 200?, as_tblf, as_tbl , astra_single, astrafr, 0, ROT0, "Astra", "Triple Bells (Astra, V301)" , GAME_IS_SKELETON_MECHANICAL) GAME( 200?, as_td, 0 , astra_single_2e, astrafr, astradec, ROT0, "Astra", "Twin Dragons (Astra, V103)" , GAME_IS_SKELETON_MECHANICAL) -GAME( 200?, as_twp, 0 , astra_single, astrafr, 0, ROT0, "Astra", "Twin Pots (Astra, V106)" , GAME_IS_SKELETON_MECHANICAL) +GAME( 200?, as_twp, 0 , astra_single_2e, astrafr, 0, ROT0, "Astra", "Twin Pots (Astra, V106)" , GAME_IS_SKELETON_MECHANICAL) GAME( 200?, as_twpa, as_twp , astra_single, astrafr, 0, ROT0, "Astra", "Twin Pots (Astra, V104)" , GAME_IS_SKELETON_MECHANICAL) GAME( 200?, as_vn, 0 , astrafr_dual_alt_37, astrafr, astradec_dual, ROT0, "Astra", "Vegas Nights (Astra, V205)" , GAME_IS_SKELETON_MECHANICAL) GAME( 200?, as_vcv, 0 , astra_single, astrafr, astradec, ROT0, "Astra", "Viva Cash Vegas (Astra, V005)" , GAME_IS_SKELETON_MECHANICAL) diff --git a/src/mame/drivers/bfm_sc4h.c b/src/mame/drivers/bfm_sc4h.c index 6b8a7e505b2..e419c977a24 100644 --- a/src/mame/drivers/bfm_sc4h.c +++ b/src/mame/drivers/bfm_sc4h.c @@ -58,6 +58,55 @@ UINT8 read_input_matrix(running_machine &machine, int row) return value; } +READ16_MEMBER(sc4_state::sc4_cs1_r) +{ + int pc = cpu_get_pc(&space.device()); + + if (offset<0x100000/2) + { + // allow some sets to boot, should probably return this data on Mbus once we figure out what it is + if ((pc == m_chk41addr) && (offset == m_chk41addr>>1)) + { + UINT32 r_A0 = cpu_get_reg(&space.device(), M68K_A0); + UINT32 r_A1 = cpu_get_reg(&space.device(), M68K_A1); + UINT32 r_D1 = cpu_get_reg(&space.device(), M68K_D1); + + if (r_D1 == 0x7) + { + bool valid = true; + for (int i=0;i<8;i++) + { + UINT8 code = space.read_byte(r_A0+i); + if (code != 0xff) // assume our mbus code just returns 0xff for now.. + valid = false; + } + + if (valid && m_dochk41) + { + m_dochk41 = false; + // the value is actually random.. probably based on other reads + // making this a comparison? + printf("Ident code? "); + for (int i=0;i<8;i++) + { + UINT8 code = space.read_byte(r_A1+i); + printf("%02x",code); + space.write_byte(r_A0+i, code); + } + printf("\n"); + } + } + } + + + return m_cpuregion[offset]; + } + else + logerror("%08x maincpu read access offset %08x mem_mask %04x cs %d\n", pc, offset*2, mem_mask, 1); + + return 0x0000; +} + READ16_MEMBER(sc4_state::sc4_mem_r) { int pc = cpu_get_pc(&space.device()); @@ -70,49 +119,9 @@ READ16_MEMBER(sc4_state::sc4_mem_r) switch ( cs ) { case 1: - if (offset<0x100000/2) - { - // allow some sets to boot, should probably return this data on Mbus once we figure out what it is - if ((pc == m_chk41addr) && (offset == m_chk41addr>>1)) - { - UINT32 r_A0 = cpu_get_reg(&space.device(), M68K_A0); - UINT32 r_A1 = cpu_get_reg(&space.device(), M68K_A1); - UINT32 r_D1 = cpu_get_reg(&space.device(), M68K_D1); - - if (r_D1 == 0x7) - { - bool valid = true; - for (int i=0;i<8;i++) - { - UINT8 code = space.read_byte(r_A0+i); - if (code != 0xff) // assume our mbus code just returns 0xff for now.. - valid = false; - } - - if (valid && m_dochk41) - { - m_dochk41 = false; - // the value is actually random.. probably based on other reads - // making this a comparison? - printf("Ident code? "); - for (int i=0;i<8;i++) - { - UINT8 code = space.read_byte(r_A1+i); - printf("%02x",code); - space.write_byte(r_A0+i, code); - } - printf("\n"); - } - } - } + return sc4_cs1_r(space,offset,mem_mask); - return m_cpuregion[offset]; - - } - else - logerror("%08x maincpu read access offset %08x mem_mask %04x cs %d\n", pc, offset*2, mem_mask, cs); - break; case 2: base = 0x800000/2; @@ -378,11 +387,57 @@ WRITE16_MEMBER(sc4_state::sc4_mem_w) } static ADDRESS_MAP_START( sc4_map, AS_PROGRAM, 16, sc4_state ) + AM_RANGE(0x0000000, 0x0fffff) AM_READ(sc4_cs1_r) // technically we should be going through the cs handler, but this is always set to ROM, and assuming that is a lot faster AM_RANGE(0x0000000, 0xffffff) AM_READWRITE(sc4_mem_r, sc4_mem_w) ADDRESS_MAP_END + + + +READ32_MEMBER(sc4_adder4_state::adder4_mem_r) +{ + int pc = cpu_get_pc(&space.device()); + int cs = m68340_get_cs(m_adder4cpu, offset * 4); + + switch ( cs ) + { + case 1: + return m_adder4cpuregion[offset]; + + case 2: + offset &=0x3fff; + return m_adder4ram[offset]; + + default: + logerror("%08x adder4cpu read access offset %08x mem_mask %08x cs %d\n", pc, offset*4, mem_mask, cs); + + } + + return 0x0000; +} + +WRITE32_MEMBER(sc4_adder4_state::adder4_mem_w) +{ + int pc = cpu_get_pc(&space.device()); + int cs = m68340_get_cs(m_adder4cpu, offset * 4); + + switch ( cs ) + { + default: + logerror("%08x adder4cpu write access offset %08x data %08x mem_mask %08x cs %d\n", pc, offset*4, data, mem_mask, cs); + + case 2: + offset &=0x3fff; + COMBINE_DATA(&m_adder4ram[offset]); + break; + + + } + +} + static ADDRESS_MAP_START( sc4_adder4_map, AS_PROGRAM, 32, sc4_adder4_state ) - AM_RANGE(0x000000, 0x2fffff) AM_ROM + AM_RANGE(0x00000000, 0xffffffff) AM_READWRITE(adder4_mem_r, adder4_mem_w) ADDRESS_MAP_END @@ -722,9 +777,20 @@ MACHINE_CONFIG_START( sc4, sc4_state ) MACHINE_CONFIG_END + +static MACHINE_START( adder4 ) +{ + sc4_adder4_state *state = machine.driver_data(); + state->m_adder4cpuregion = (UINT32*)state->memregion( "adder4" )->base(); + state->m_adder4ram = (UINT32*)auto_alloc_array_clear(machine, UINT32, 0x10000); + MACHINE_START_CALL(sc4); +} + MACHINE_CONFIG_DERIVED_CLASS( sc4_adder4, sc4, sc4_adder4_state ) MCFG_CPU_ADD("adder4", M68340, 25175000) // 68340 (CPU32 core) MCFG_CPU_PROGRAM_MAP(sc4_adder4_map) + + MCFG_MACHINE_START( adder4 ) MACHINE_CONFIG_END diff --git a/src/mame/drivers/bfm_swp.c b/src/mame/drivers/bfm_swp.c index a583d932f21..968fc259ca5 100644 --- a/src/mame/drivers/bfm_swp.c +++ b/src/mame/drivers/bfm_swp.c @@ -1,15 +1,5 @@ -/* Bellfruit SWP (Skill With Prizes) Video hardware */ - -/* - This is 'Cobra 3' ? - is that an expansion board for Scorpion 4, or somehow related? - The CPU is the same (68340) - - Radio Times is probably the only *COMPLETE* dump here, as it - includes the CD. Other games probably have CDs or HDDs too. - - Telly Addicts has a HDD dump (I'm assuming it's the same - platform) but no sound roms. +/* Bellfruit SWP (Skill With Prizes) Video hardware + aka Cobra 3 */ @@ -128,19 +118,80 @@ class bfm_swp_state : public driver_device { public: bfm_swp_state(const machine_config &mconfig, device_type type, const char *tag) - : driver_device(mconfig, type, tag) { } + : driver_device(mconfig, type, tag), + m_maincpu(*this, "maincpu") + { } + + UINT32* m_cpuregion; + UINT32* m_mainram; + + DECLARE_READ32_MEMBER(bfm_swp_mem_r); + DECLARE_WRITE32_MEMBER(bfm_swp_mem_w); + UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect) { return 0; } + +protected: + + // devices + required_device m_maincpu; + }; + +READ32_MEMBER(bfm_swp_state::bfm_swp_mem_r) +{ + int pc = cpu_get_pc(&space.device()); + int cs = m68340_get_cs(m_maincpu, offset * 4); + + switch ( cs ) + { + case 1: + if (offset<0x100000/4) return m_cpuregion[offset]; + + case 2: + offset&=0x3fff; + return m_mainram[offset]; + + default: + logerror("%08x maincpu read access offset %08x mem_mask %08x cs %d\n", pc, offset*4, mem_mask, cs); + + } + + return 0x0000; +} + +WRITE32_MEMBER(bfm_swp_state::bfm_swp_mem_w) +{ + int pc = cpu_get_pc(&space.device()); + int cs = m68340_get_cs(m_maincpu, offset * 4); + + switch ( cs ) + { + default: + logerror("%08x maincpu write access offset %08x data %08x mem_mask %08x cs %d\n", pc, offset*4, data, mem_mask, cs); + + case 2: + offset&=0x3fff; + COMBINE_DATA(&m_mainram[offset]); + break; + + + } + +} + + + + static ADDRESS_MAP_START( bfm_swp_map, AS_PROGRAM, 32, bfm_swp_state ) - AM_RANGE(0x000000, 0x0fffff) AM_ROM - AM_RANGE(0xb00000, 0xb03fff) AM_RAM + AM_RANGE(0x00000000, 0x000fffff) AM_ROM + AM_RANGE(0x00000000, 0xffffffff) AM_READWRITE(bfm_swp_mem_r, bfm_swp_mem_w) ADDRESS_MAP_END @@ -148,12 +199,23 @@ static INPUT_PORTS_START( bfm_swp ) INPUT_PORTS_END +static MACHINE_START( bfm_swp ) +{ + bfm_swp_state *state = machine.driver_data(); + state->m_cpuregion = (UINT32*)state->memregion( "maincpu" )->base(); + state->m_mainram = (UINT32*)auto_alloc_array_clear(machine, UINT32, 0x10000); + +} + + static MACHINE_CONFIG_START( bfm_swp, bfm_swp_state ) /* basic machine hardware */ - MCFG_CPU_ADD("maincpu", M68020,16000000) /* 68340 */ + MCFG_CPU_ADD("maincpu", M68340, 16000000) MCFG_CPU_PROGRAM_MAP(bfm_swp_map) + MCFG_MACHINE_START( bfm_swp ) + MCFG_SCREEN_ADD("screen", RASTER) MCFG_SCREEN_REFRESH_RATE(60) MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0)) @@ -232,8 +294,8 @@ ROM_START( c3_totp ) ROM_LOAD( "totpsnd.lhs", 0x000000, 0x080000, CRC(56a73136) SHA1(10656ede18de9432a8a728cc59d000b5b1bf0150) ) ROM_LOAD( "totpsnd.rhs", 0x080000, 0x080000, CRC(28d156ab) SHA1(ebf5c4e008015b9b56b3aa5228c05b8e298daa80) ) - DISK_REGION( "scsi" ) // CD or HDD - DISK_IMAGE_READONLY( "cd or hdd", 0, NO_DUMP ) + DISK_REGION( "scsi" ) // uses a CD, only one we've seen has been damaged to a point where not all data could be read tho + DISK_IMAGE_READONLY( "cd", 0, NO_DUMP ) ROM_END ROM_START( c3_ppays ) diff --git a/src/mame/drivers/mpu5.c b/src/mame/drivers/mpu5.c index 23020aee4ae..ffba3d003c3 100644 --- a/src/mame/drivers/mpu5.c +++ b/src/mame/drivers/mpu5.c @@ -45,6 +45,11 @@ public: : driver_device(mconfig, type, tag), m_maincpu(*this, "maincpu") { } + UINT32* m_cpuregion; + UINT32* m_mainram; + + DECLARE_READ32_MEMBER(mpu5_mem_r); + DECLARE_WRITE32_MEMBER(mpu5_mem_w); protected: @@ -53,17 +58,72 @@ protected: }; +READ32_MEMBER(mpu5_state::mpu5_mem_r) +{ + int pc = cpu_get_pc(&space.device()); + int cs = m68340_get_cs(m_maincpu, offset * 4); + + switch ( cs ) + { + case 1: + return m_cpuregion[offset]; + + case 4: + offset &=0x3fff; + return (m_mainram[offset]); + + default: + logerror("%08x maincpu read access offset %08x mem_mask %08x cs %d\n", pc, offset*4, mem_mask, cs); + + } + + return 0x0000; +} + +WRITE32_MEMBER(mpu5_state::mpu5_mem_w) +{ + int pc = cpu_get_pc(&space.device()); + int cs = m68340_get_cs(m_maincpu, offset * 4); + + switch ( cs ) + { + case 4: + offset &=0x3fff; + COMBINE_DATA(&m_mainram[offset]); + break; + + + + default: + logerror("%08x maincpu write access offset %08x data %08x mem_mask %08x cs %d\n", pc, offset*4, data, mem_mask, cs); + + } + +} + static ADDRESS_MAP_START( mpu5_map, AS_PROGRAM, 32, mpu5_state ) - AM_RANGE(0x000000, 0x2fffff) AM_ROM + AM_RANGE(0x00000000, 0xffffffff) AM_READWRITE(mpu5_mem_r, mpu5_mem_w) ADDRESS_MAP_END static INPUT_PORTS_START( mpu5 ) INPUT_PORTS_END + +static MACHINE_START( mpu5 ) +{ + mpu5_state *state = machine.driver_data(); + state->m_cpuregion = (UINT32*)state->memregion( "maincpu" )->base(); + state->m_mainram = (UINT32*)auto_alloc_array_clear(machine, UINT32, 0x10000); + +} + + static MACHINE_CONFIG_START( mpu5, mpu5_state ) MCFG_CPU_ADD("maincpu", M68340, 16000000) // ? MCFG_CPU_PROGRAM_MAP(mpu5_map) + MCFG_MACHINE_START( mpu5 ) + MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker") /* unknown sound */ MACHINE_CONFIG_END diff --git a/src/mame/drivers/pluto5.c b/src/mame/drivers/pluto5.c index e22c4bee9c4..25e1c0eb57e 100644 --- a/src/mame/drivers/pluto5.c +++ b/src/mame/drivers/pluto5.c @@ -28,6 +28,8 @@ --------------------------------------------------------------------- Pluto 5 Technical Notes.... + (why is this information here? it seems to be c+p straight from a tech manual + and is completely unneccessary) * Clocks... @@ -180,22 +182,78 @@ class pluto5_state : public driver_device { public: pluto5_state(const machine_config &mconfig, device_type type, const char *tag) - : driver_device(mconfig, type, tag) { } + : driver_device(mconfig, type, tag), + m_maincpu(*this, "maincpu") + { } + + UINT32* m_cpuregion; + UINT32* m_mainram; + + DECLARE_READ32_MEMBER(pluto5_mem_r); + DECLARE_WRITE32_MEMBER(pluto5_mem_w); + +protected: + + // devices + required_device m_maincpu; }; +READ32_MEMBER(pluto5_state::pluto5_mem_r) +{ + int pc = cpu_get_pc(&space.device()); + int cs = m68340_get_cs(m_maincpu, offset * 4); + + switch ( cs ) + { + case 1: + return m_cpuregion[offset]; + + default: + logerror("%08x maincpu read access offset %08x mem_mask %08x cs %d\n", pc, offset*4, mem_mask, cs); + + } + + return 0x0000; +} + +WRITE32_MEMBER(pluto5_state::pluto5_mem_w) +{ + int pc = cpu_get_pc(&space.device()); + int cs = m68340_get_cs(m_maincpu, offset * 4); + + switch ( cs ) + { + default: + logerror("%08x maincpu write access offset %08x data %08x mem_mask %08x cs %d\n", pc, offset*4, data, mem_mask, cs); + + } + +} + static ADDRESS_MAP_START( pluto5_map, AS_PROGRAM, 32, pluto5_state ) - AM_RANGE(0x000000, 0x2fffff) AM_ROM + AM_RANGE(0x00000000, 0xffffffff) AM_READWRITE(pluto5_mem_r, pluto5_mem_w) ADDRESS_MAP_END static INPUT_PORTS_START( pluto5 ) INPUT_PORTS_END +static MACHINE_START( pluto5 ) +{ + pluto5_state *state = machine.driver_data(); + state->m_cpuregion = (UINT32*)state->memregion( "maincpu" )->base(); + state->m_mainram = (UINT32*)auto_alloc_array_clear(machine, UINT32, 0x10000); + +} + static MACHINE_CONFIG_START( pluto5, pluto5_state ) MCFG_CPU_ADD("maincpu", M68340, 16000000) MCFG_CPU_PROGRAM_MAP(pluto5_map) + MCFG_MACHINE_START( pluto5 ) + + MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker") /* unknown sound */ MACHINE_CONFIG_END diff --git a/src/mame/includes/bfm_sc45.h b/src/mame/includes/bfm_sc45.h index 07dc3b47619..28660bf2bb1 100644 --- a/src/mame/includes/bfm_sc45.h +++ b/src/mame/includes/bfm_sc45.h @@ -51,6 +51,8 @@ public: DECLARE_READ16_MEMBER(sc4_mem_r); DECLARE_WRITE16_MEMBER(sc4_mem_w); + + DECLARE_READ16_MEMBER(sc4_cs1_r); }; class sc4_adder4_state : public sc4_state @@ -60,6 +62,13 @@ public: : sc4_state(mconfig, type, tag), m_adder4cpu(*this, "adder4") { } + + UINT32* m_adder4cpuregion; + UINT32* m_adder4ram; + + DECLARE_READ32_MEMBER(adder4_mem_r); + DECLARE_WRITE32_MEMBER(adder4_mem_w); + // devices required_device m_adder4cpu;