From a92cd6a8e3c8c2d5b2a51c8eaee6eb12e5f6fa0e Mon Sep 17 00:00:00 2001 From: arbee Date: Fri, 15 Jul 2016 23:24:50 -0400 Subject: [PATCH] sun4: pass 4/75 tests until MMU fault trap (nw) --- src/mame/drivers/sun4.cpp | 66 +++++++++++++++++++++++++++++---------- 1 file changed, 49 insertions(+), 17 deletions(-) diff --git a/src/mame/drivers/sun4.cpp b/src/mame/drivers/sun4.cpp index f6bbd49612d..3d310619f92 100644 --- a/src/mame/drivers/sun4.cpp +++ b/src/mame/drivers/sun4.cpp @@ -554,7 +554,7 @@ protected: UINT32 *m_rom_ptr; UINT32 m_context; UINT8 m_system_enable; - UINT32 m_buserror[4]; + UINT32 m_buserr[4]; UINT32 m_counter[4]; private: @@ -562,6 +562,7 @@ private: UINT8 m_segmap[16][4096]; UINT32 m_pagemap[16384]; UINT32 m_cachetags[0x4000]; + UINT32 m_cachedata[0x4000]; UINT32 m_ram_size, m_ram_size_words; UINT8 m_ctx_mask; // SS2 is sun4c but has 16 contexts; most have 8 UINT8 m_pmeg_mask; // SS2 is sun4c but has 16384 PTEs; most have 8192 @@ -609,6 +610,7 @@ READ32_MEMBER( sun4_state::sun4c_mmu_r ) { UINT8 asi = m_maincpu->get_asi(); int page; + UINT32 retval = 0; // make debugger fetches emulate supervisor program for best compatibility with boot PROM execution if (space.debugger_access()) asi = 9; @@ -632,16 +634,19 @@ READ32_MEMBER( sun4_state::sun4c_mmu_r ) return m_system_enable<<24; case 6: // bus error register - //printf("sun4c: read buserror, PC=%x (mask %08x)\n", m_maincpu->pc(), mem_mask); - return 0; + printf("sun4c: read buserror, PC=%x (mask %08x)\n", m_maincpu->pc(), mem_mask); + m_maincpu->set_input_line(SPARC_MAE, CLEAR_LINE); + retval = m_buserr[offset & 0xf]; + m_buserr[offset & 0xf] = 0; // clear on reading + return retval; case 8: // (d-)cache tags //logerror("sun4: read dcache tags @ %x, PC = %x\n", offset, m_maincpu->pc()); - return m_cachetags[offset&0xfff]; + return m_cachetags[(offset>>3)&0x3fff]; case 9: // (d-)cache data - logerror("sun4c: read dcache data @ %x, PC = %x\n", offset, m_maincpu->pc()); - return 0xffffffff; + //logerror("sun4c: read dcache data @ %x, PC = %x\n", offset, m_maincpu->pc()); + return m_cachedata[offset&0x3fff]; case 0xf: // UART bypass //printf("read UART bypass @ %x mask %08x\n", offset<<2, mem_mask); @@ -724,8 +729,8 @@ READ32_MEMBER( sun4_state::sun4c_mmu_r ) { printf("sun4c: INVALID PTE entry %d %08x accessed! vaddr=%x PC=%x\n", entry, m_pagemap[entry], offset <<2, m_maincpu->pc()); //m_maincpu->trap(SPARC_DATA_ACCESS_EXCEPTION); - //m_buserror[0] = 0x88; // read, invalid PTE - //m_buserror[1] = offset<<2; + //m_buserr[0] = 0x88; // read, invalid PTE + //m_buserr[1] = offset<<2; } return 0; } @@ -762,15 +767,27 @@ WRITE32_MEMBER( sun4_state::sun4c_mmu_w ) case 4: // system enable reg m_system_enable = data>>24; //printf("%08x to system enable, mask %08x\n", data, mem_mask); + if (m_system_enable & ENA_RESET) + { + m_system_enable = 0; + m_maincpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE); + m_maincpu->set_input_line(INPUT_LINE_RESET, CLEAR_LINE); + } + return; + + case 6: // bus error + printf("%08x to bus error @ %x, mask %08x\n", data, offset, mem_mask); + m_buserr[offset & 0xf] = data; return; case 8: // cache tags //logerror("sun4: %08x to cache tags @ %x, PC = %x\n", data, offset, m_maincpu->pc()); - m_cachetags[offset&0xfff] = data; + m_cachetags[(offset>>3)&0x3fff] = data & 0x03f8fffc; return; case 9: // cache data - logerror("sun4c: %08x to cache data @ %x, PC = %x\n", data, offset, m_maincpu->pc()); + //logerror("sun4c: %08x to cache data @ %x, PC = %x\n", data, offset, m_maincpu->pc()); + m_cachedata[offset&0x3fff] = data; return; case 0xf: // UART bypass @@ -818,12 +835,22 @@ WRITE32_MEMBER( sun4_state::sun4c_mmu_w ) if (m_pagemap[entry] & PM_VALID) { - m_pagemap[entry] |= PM_ACCESSED; + if ((!(m_pagemap[entry] & PM_WRITEMASK)) || + ((m_pagemap[entry] & PM_SYSMASK) && !(asi & 1))) + { + printf("sun4c: write protect MMU error (PC=%x)\n", m_maincpu->pc()); + m_buserr[0] = 0x8040; // write, protection error + m_buserr[1] = offset<<2; + m_maincpu->set_input_line(SPARC_MAE, ASSERT_LINE); + return; + } + + m_pagemap[entry] |= (PM_ACCESSED | PM_MODIFIED); UINT32 tmp = (m_pagemap[entry] & 0xffff) << 10; tmp |= (offset & 0x3ff); - //printf("sun4: write translated vaddr %08x to phys %08x type %d, PTE %08x, PC=%x\n", offset<<2, tmp<<2, (m_pagemap[entry]>>26) & 3, m_pagemap[entry], m_maincpu->pc()); + printf("sun4: write translated vaddr %08x to phys %08x type %d, PTE %08x, ASI %d, PC=%x\n", offset<<2, tmp<<2, (m_pagemap[entry]>>26) & 3, m_pagemap[entry], asi, m_maincpu->pc()); switch ((m_pagemap[entry] >> 26) & 3) { @@ -844,8 +871,8 @@ WRITE32_MEMBER( sun4_state::sun4c_mmu_w ) { printf("sun4c: INVALID PTE entry %d %08x accessed! vaddr=%x PC=%x\n", entry, m_pagemap[entry], offset <<2, m_maincpu->pc()); //m_maincpu->trap(SPARC_DATA_ACCESS_EXCEPTION); - //m_buserror[0] = 0x8; // invalid PTE - //m_buserror[1] = offset<<2; + //m_buserr[0] = 0x8; // invalid PTE + //m_buserr[1] = offset<<2; return; } break; @@ -978,8 +1005,8 @@ READ32_MEMBER( sun4_state::sun4_mmu_r ) { printf("sun4: INVALID PTE entry %d %08x accessed! vaddr=%x PC=%x\n", entry, m_pagemap[entry], offset <<2, m_maincpu->pc()); //m_maincpu->trap(SPARC_DATA_ACCESS_EXCEPTION); - //m_buserror[0] = 0x88; // read, invalid PTE - //m_buserror[1] = offset<<2; + //m_buserr2qor[0] = 0x88; // read, invalid PTE + //m_buserr[1] = offset<<2; } return 0; } @@ -1016,6 +1043,12 @@ WRITE32_MEMBER( sun4_state::sun4_mmu_w ) case 4: // system enable reg m_system_enable = data>>24; //printf("%08x to system enable, mask %08x\n", data, mem_mask); + if (m_system_enable & ENA_RESET) + { + m_system_enable = 0; + m_maincpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE); + m_maincpu->set_input_line(INPUT_LINE_RESET, CLEAR_LINE); + } return; case 7: // diag reg @@ -1320,7 +1353,6 @@ static ADDRESS_MAP_START(type1space_map, AS_PROGRAM, 32, sun4_state) AM_RANGE(0x03000000, 0x0300000f) AM_READWRITE(timer_r, timer_w) AM_MIRROR(0xfffff0) AM_RANGE(0x05000000, 0x05000003) AM_READWRITE8(irq_r, irq_w, 0xffffffff) AM_RANGE(0x06000000, 0x0607ffff) AM_ROM AM_REGION("user1", 0) -// AM_RANGE(0x07200000, 0x07200007) AM_DEVICE8(FDC_TAG, n82077aa_device, map, 0xffffffff) AM_RANGE(0x07200000, 0x07200003) AM_READWRITE8(fdc_r, fdc_w, 0xffffffff) AM_RANGE(0x08000000, 0x08000003) AM_READ(ss1_sl0_id) // slot 0 contains SCSI/DMA/Ethernet AM_RANGE(0x0e000000, 0x0e000003) AM_READ(ss1_sl3_id) // slot 3 contains video board