Sprinter/mame
2
0
Fork 0
mirror of https://github.com/holub/mame synced 2025-04-25 09:50:04 +03:00
Code Issues Actions 1 Packages Projects Releases Wiki Activity

Merge pull request #1016 from JoakimLarsson/fcisio1

Browse Source 
New Board: Force Computers ISIO-1/2
This commit is contained in:
R. Belmont 2016-07-01 08:02:18 -04:00 committed by GitHub
commit a957ae0f9a
7 changed files with 1466 additions and 361 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
scripts/target/mame/mess.lua
View File

@ -3099,6 +3099,7 @@ files {
MAME_DIR .. "src/mame/drivers/fanucs15.cpp",
MAME_DIR .. "src/mame/drivers/fanucspmg.cpp",
MAME_DIR .. "src/mame/drivers/fc100.cpp",
MAME_DIR .. "src/mame/drivers/fcisio.cpp",
MAME_DIR .. "src/mame/drivers/fcscsi.cpp",
MAME_DIR .. "src/mame/drivers/fk1.cpp",
MAME_DIR .. "src/mame/drivers/ft68m.cpp",

334
src/devices/machine/68230pit.cpp
View File

@ -1,17 +1,26 @@
// license:BSD-3-Clause
// copyright-holders:Joakim Larsson Edstr??m
// copyright-holders:Joakim Larsson Edstrom
/**********************************************************************
*
* Motorola MC68230 PI/T Parallell Interface and Timer
*
* Revisions
* 2015-07-15 JLE initial
* PORT MODES INCLUDE :
* - BIT I/O
* - UNIDIRECTIONAL 8 BIT AND 16 BIT
* - BIDIRECTIONAL 8 BIT AND 16 BIT
* PROGRAMMABLE HANDSHAKING OPTIONS
* 24-BIT PROGRAMMABLE TIMER MODES
* FIVE SEPARATE INTERRUPT VECTORS SEPARATE PORT AND TIMER INTERRUPT SERVICE REQUESTS
* REGISTERS AREREAD/WRITEAND DIRECTLY ADDRESSABLE
* REGISTERS ARE ADDRESSED FOR MOVEP (Move Peripheral) AND DMAC COMPATIBILITY
*
* Revisions: 2015-07-15 JLE initial
*
* Todo
* - Add clock and timers
* - Complete support for clock and timers
* - Add interrupt support
* - Add DMA support
* - Add double buffering for each submode
* - Add all missing registers
* - Add configuration
**********************************************************************/
#include "68230pit.h"
@ -32,9 +41,6 @@
#define LLFORMAT "%lld"
#endif
//#define LOG(x) x
//#define logerror printf
//**************************************************************************
// DEVICE TYPE DEFINITIONS
//**************************************************************************
@ -45,9 +51,7 @@ const device_type PIT68230 = &device_creator<pit68230_device>;
// pit68230_device - constructors
//-------------------------------------------------
pit68230_device::pit68230_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, UINT32 variant, const char *shortname, const char *source)
: device_t (mconfig, type, name, tag, owner, clock, shortname, source),
device_execute_interface (mconfig, *this)
, m_icount (0)
: device_t (mconfig, type, name, tag, owner, clock, shortname, source)
, m_pa_out_cb(*this)
, m_pa_in_cb(*this)
, m_pb_out_cb(*this)
@ -63,25 +67,27 @@ pit68230_device::pit68230_device(const machine_config &mconfig, device_type type
, m_paddr(0)
, m_pbddr(0)
, m_pcddr(0)
, m_pivr(0)
, m_pacr(0)
, m_pbcr(0)
, m_padr(0)
, m_pbdr(0)
, m_pcdr(0)
, m_psr(0)
, m_tcr(0)
, m_tivr(0)
, m_cpr(0)
// , m_cprh(0)
// , m_cprm(0)
// , m_cprl(0)
// , m_cprh(0) // Collectivelly handled by m_cpr
// , m_cprm(0) // Collectivelly handled by m_cpr
// , m_cprl(0) // Collectivelly handled by m_cpr
, m_cntr(0)
, m_tsr(0)
{
}
pit68230_device::pit68230_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: device_t (mconfig, PIT68230, "PIT68230", tag, owner, clock, "pit68230", __FILE__),
device_execute_interface (mconfig, *this)
, m_icount (0)
: device_t (mconfig, PIT68230, "PIT68230", tag, owner, clock, "pit68230", __FILE__)
, m_pa_out_cb (*this)
, m_pa_in_cb(*this)
, m_pb_out_cb(*this)
@ -97,17 +103,21 @@ pit68230_device::pit68230_device(const machine_config &mconfig, const char *tag,
, m_paddr(0)
, m_pbddr(0)
, m_pcddr(0)
, m_pivr(0)
, m_pacr(0)
, m_pbcr(0)
, m_padr(0)
, m_pbdr(0)
, m_pcdr(0)
, m_psr(0)
, m_tcr(0)
, m_tivr(0)
, m_cpr(0)
// , m_cprh(0)
// , m_cprm(0)
// , m_cprl(0)
// , m_cprh(0) // Collectivelly handled by m_cpr
// , m_cprm(0) // Collectivelly handled by m_cpr
// , m_cprl(0) // Collectivelly handled by m_cpr
, m_cntr(0)
, m_tsr(0)
{
}
@ -117,17 +127,40 @@ pit68230_device::pit68230_device(const machine_config &mconfig, const char *tag,
void pit68230_device::device_start ()
{
LOG(("%s\n", FUNCNAME));
m_icountptr = &m_icount;
// resolve callbacks
m_pa_out_cb.resolve_safe();
m_pa_in_cb.resolve_safe(0);
m_pb_out_cb.resolve_safe();
m_pb_in_cb.resolve_safe(0);
m_pc_out_cb.resolve_safe();
m_pc_in_cb.resolve_safe(0);
m_h1_out_cb.resolve_safe();
m_h2_out_cb.resolve_safe();
m_h3_out_cb.resolve_safe();
m_h4_out_cb.resolve_safe();
// Timers
pit_timer = timer_alloc(TIMER_ID_PIT);
// state saving
save_item(NAME(m_pgcr));
save_item(NAME(m_psrr));
save_item(NAME(m_paddr));
save_item(NAME(m_pbddr));
save_item(NAME(m_pcddr));
save_item(NAME(m_pivr));
save_item(NAME(m_pacr));
save_item(NAME(m_pbcr));
save_item(NAME(m_padr));
save_item(NAME(m_pbdr));
save_item(NAME(m_pcdr));
save_item(NAME(m_psr));
save_item(NAME(m_tcr));
save_item(NAME(m_tivr));
save_item(NAME(m_cpr));
save_item(NAME(m_cntr));
save_item(NAME(m_tsr));
}
//-------------------------------------------------
@ -142,11 +175,15 @@ void pit68230_device::device_reset ()
m_paddr = 0;
m_pbddr = 0;
m_pcddr = 0;
m_pivr = 0x0f;
m_pacr = 0; m_h2_out_cb(m_pacr);
m_pbcr = 0;
m_padr = 0; m_pa_out_cb((offs_t)0, m_padr); // TODO: check PADDR
m_pbdr = 0;
m_padr = 0; m_pa_out_cb((offs_t)0, m_padr);
m_pbdr = 0; m_pb_out_cb((offs_t)0, m_pbdr);
m_psr = 0;
m_tcr = 0;
m_tivr = 0x0f;
m_tsr = 0;
}
//-------------------------------------------------
@ -154,6 +191,22 @@ void pit68230_device::device_reset ()
//-------------------------------------------------
void pit68230_device::device_timer (emu_timer &timer, device_timer_id id, INT32 param, void *ptr)
{
switch(id)
{
case TIMER_ID_PIT:
if (m_cntr-- == 0) // Zero detect
{
/* TODO: Check mode and use preload value if required or just rollover 24 bit */
if ((m_tcr & REG_TCR_ZD) == 0)
m_cntr = m_cpr;
else // mask off to 24 bit on rollover
m_cntr &= 0xffffff;
}
break;
default:
LOG(("Unhandled Timer ID %d\n", id));
break;
}
}
void pit68230_device::h1_set (UINT8 state)
@ -170,18 +223,6 @@ void pit68230_device::portb_setbit (UINT8 bit, UINT8 state)
LOG(("%02x %lld\n", m_pbdr, machine ().firstcpu->total_cycles ()));
}
//-------------------------------------------------
// execute_run -
//-------------------------------------------------
void pit68230_device::execute_run ()
{
do {
synchronize ();
m_icount--;
} while (m_icount > 0);
}
#if VERBOSE > 2
static INT32 ow_cnt = 0;
static INT32 ow_data = 0;
@ -218,6 +259,11 @@ void pit68230_device::wr_pitreg_pcddr(UINT8 data)
m_pcddr = data;
}
void pit68230_device::wr_pitreg_pivr(UINT8 data)
{
LOG(("%s(%02x) \"%s\": Not implemented yet\n", FUNCNAME, data, m_owner->tag()));
}
void pit68230_device::wr_pitreg_pacr(UINT8 data)
{
LOG(("%s(%02x) \"%s\": %s - %02x\n", FUNCNAME, data, m_owner->tag(), FUNCNAME, data));
@ -250,9 +296,25 @@ void pit68230_device::wr_pitreg_pbcr(UINT8 data)
void pit68230_device::wr_pitreg_padr(UINT8 data)
{
LOG(("%s(%02x) \"%s\": %s - %02x\n", FUNCNAME, data, m_owner->tag(), FUNCNAME, data));
m_padr = data;
m_padr |= (data & m_paddr);
// callbacks
m_pa_out_cb ((offs_t)0, m_padr); // TODO: check PADDR
m_pa_out_cb ((offs_t)0, m_padr);
}
void pit68230_device::wr_pitreg_pbdr(UINT8 data)
{
LOG(("%s(%02x) \"%s\": %s - %02x\n", FUNCNAME, data, m_owner->tag(), FUNCNAME, data));
m_pbdr |= (data & m_pbddr);
// callbacks
m_pb_out_cb ((offs_t)0, m_pbdr & m_pbddr);
}
void pit68230_device::wr_pitreg_pcdr(UINT8 data)
{
LOG(("%s(%02x) \"%s\": %s - %02x\n", FUNCNAME, data, m_owner->tag(), FUNCNAME, data));
m_pcdr |= (data & m_pcddr);
// callbacks
m_pc_out_cb ((offs_t)0, m_pcdr);
}
void pit68230_device::wr_pitreg_psr(UINT8 data)
@ -325,9 +387,60 @@ TCR bit 0 - Timer Enable
*/
void pit68230_device::wr_pitreg_tcr(UINT8 data)
{
LOG(("%s(%02x) \"%s\": %s - %02x Timer %s\n",
FUNCNAME, data, m_owner->tag(), FUNCNAME, data, data & REG_TCR_ENABLE ? "enabled" : "disabled"));
int tout = 0;
int tiack = 0;
int irq = 0;
int psc = 0;
int clk = 0;
int pen = 0;
int sqr = 0;
LOG(("%s(%02x) %s\n", FUNCNAME, data, m_owner->tag()));
m_tcr = data;
switch (m_tcr & REG_TCR_TOUT_TIACK_MASK)
{
case REG_TCR_PC3_PC7:
case REG_TCR_PC3_PC7_DC: LOG(("- PC3 and PC7 used as I/O pins\n")); break;
case REG_TCR_TOUT_PC7_SQ:
case REG_TCR_TOUT_PC7_SQ_DC: LOG(("- PC3 used as SQuare wave TOUT and PC7 used as I/O pin - not supported yet\n")); sqr = 1; break;
case REG_TCR_TOUT_TIACK: LOG(("- PC3 used as TOUT and PC7 used as TIACK - not supported yet\n")); tout = 1; tiack = 1; break;
case REG_TCR_TOUT_TIACK_INT: LOG(("- PC3 used as TOUT and PC7 used as TIACK, Interrupts enabled - not supported yet\n")); tout = 1; tiack = 1; irq = 1; break;
case REG_TCR_TOUT_PC7: LOG(("- PC3 used as TOUT and PC7 used as I/O pin - not supported yet\n")); break;
case REG_TCR_TOUT_PC7_INT: LOG(("- PC3 used as TOUT and PC7 used as I/O pin, Interrupts enabled - not supported yet\n")); break;
}
switch (m_tcr & REG_TCR_CC_MASK)
{
case REG_TCR_CC_PC2_CLK_PSC: LOG(("- PC2 used as I/O pin,CLK and x32 prescaler are used\n")); clk = 1; psc = 1; break;
case REG_TCR_CC_TEN_CLK_PSC: LOG(("- PC2 used as Timer enable/disable, CLK and presacaler are used\n")); pen = 1; clk = 1; psc = 1; break;
case REG_TCR_CC_TIN_PSC: LOG(("- PC2 used as Timer clock and the presacaler is used - not supported yet\n")); psc = 1; break;
case REG_TCR_CC_TIN_RAW: LOG(("- PC2 used as Timer clock and the presacaler is NOT used - not supported yet\n")); break;
}
LOG(("%s", m_tcr & REG_TCR_ZR ? "- Spec violation, should always be 0!\n" : ""));
LOG(("- Timer %s when reaching 0 (zero)\n", m_tcr & REG_TCR_ZD ? "rolls over" : "reload the preload values"));
LOG(("- Timer is %s\n", m_tcr & REG_TCR_ENABLE ? "enabled" : "disabled"));
if (m_tcr & REG_TCR_ENABLE)
{
m_cntr = 0;
if (pen == 1){ LOG(("PC2 enable/disable TBD\n")); }
if (clk == 1)
{
int rate = clock() / (psc == 1 ? 32 : 1);
pit_timer->adjust(attotime::from_hz(rate), TIMER_ID_PIT, attotime::from_hz(rate));
LOG(("PIT timer started @ rate: %d and CLK: %d,\n", rate, clock()));
}
}
else
{
m_tcr = tout + tiack + irq + sqr; // remove this when the variables are used for the different modes!! Just here to to avoid warnings
}
}
void pit68230_device::wr_pitreg_tivr(UINT8 data)
{
LOG(("%s(%02x) \"%s\": \n", FUNCNAME, data, m_owner->tag()));
m_tivr = data;
}
void pit68230_device::wr_pitreg_cprh(UINT8 data)
@ -335,7 +448,6 @@ void pit68230_device::wr_pitreg_cprh(UINT8 data)
LOG(("%s(%02x) \"%s\": %s - %02x\n", FUNCNAME, data, m_owner->tag(), FUNCNAME, data));
m_cpr &= ~0xff0000;
m_cpr |= ((data << 16) & 0xff0000);
// m_cprh = data;
}
void pit68230_device::wr_pitreg_cprm(UINT8 data)
@ -343,7 +455,6 @@ void pit68230_device::wr_pitreg_cprm(UINT8 data)
LOG(("%s(%02x) \"%s\": %s - %02x\n", FUNCNAME, data, m_owner->tag(), FUNCNAME, data));
m_cpr &= ~0x00ff00;
m_cpr |= ((data << 8) & 0x00ff00);
// m_cprm = data;
}
void pit68230_device::wr_pitreg_cprl(UINT8 data)
@ -351,28 +462,41 @@ void pit68230_device::wr_pitreg_cprl(UINT8 data)
LOG(("%s(%02x) \"%s\": %s - %02x\n", FUNCNAME, data, m_owner->tag(), FUNCNAME, data));
m_cpr &= ~0x0000ff;
m_cpr |= ((data << 0) & 0x0000ff);
// m_cprl = data;
}
void pit68230_device::wr_pitreg_tsr(UINT8 data)
{
LOG(("%s(%02x) \"%s\": \n", FUNCNAME, data, m_owner->tag()));
m_tsr = data;
}
WRITE8_MEMBER (pit68230_device::write)
{
LOG(("%s %s \n",tag(), FUNCNAME));
switch (offset) {
case PIT_68230_PGCR: wr_pitreg_pgcr(data); break;
case PIT_68230_PSRR: wr_pitreg_psrr(data); break;
case PIT_68230_PADDR: wr_pitreg_paddr(data); break;
case PIT_68230_PBDDR: wr_pitreg_pbddr(data); break;
case PIT_68230_PCDDR: wr_pitreg_pcddr(data); break;
case PIT_68230_PACR: wr_pitreg_pacr(data); break;
case PIT_68230_PBCR: wr_pitreg_pbcr(data); break;
case PIT_68230_PADR: wr_pitreg_padr(data); break;
case PIT_68230_PAAR: break; // RO register so ignored
case PIT_68230_PBAR: break; // RO register so ignored
case PIT_68230_PSR: wr_pitreg_psr(data); break;
case PIT_68230_TCR: wr_pitreg_tcr(data); break;
case PIT_68230_CPRH: wr_pitreg_cprh(data); break;
case PIT_68230_CPRM: wr_pitreg_cprm(data); break;
case PIT_68230_CPRL: wr_pitreg_cprl(data); break;
case PIT_68230_PGCR: wr_pitreg_pgcr(data); break;
case PIT_68230_PSRR: wr_pitreg_psrr(data); break;
case PIT_68230_PADDR: wr_pitreg_paddr(data); break;
case PIT_68230_PBDDR: wr_pitreg_pbddr(data); break;
case PIT_68230_PCDDR: wr_pitreg_pcddr(data); break;
case PIT_68230_PIVR: wr_pitreg_pivr(data); break;
case PIT_68230_PACR: wr_pitreg_pacr(data); break;
case PIT_68230_PBCR: wr_pitreg_pbcr(data); break;
case PIT_68230_PADR: wr_pitreg_padr(data); break;
case PIT_68230_PBDR: wr_pitreg_pbdr(data); break;
case PIT_68230_PAAR: break; // Ignores write per spec, read only register
case PIT_68230_PBAR: break; // Ignores write per spec, read only register
case PIT_68230_PCDR: wr_pitreg_pcdr(data); break;
case PIT_68230_PSR: wr_pitreg_psr(data); break;
case PIT_68230_TCR: wr_pitreg_tcr(data); break;
case PIT_68230_TIVR: wr_pitreg_tivr(data); break;
case PIT_68230_CPRH: wr_pitreg_cprh(data); break;
case PIT_68230_CPRM: wr_pitreg_cprm(data); break;
case PIT_68230_CPRL: wr_pitreg_cprl(data); break;
case PIT_68230_CNTRH: break; // Ignores write per spec, read only register
case PIT_68230_CNTRM: break; // Ignores write per spec, read only register
case PIT_68230_CNTRL: break; // Ignores write per spec, read only register
case PIT_68230_TSR: wr_pitreg_tsr(data); break;
default:
LOG (("Unhandled Write of %02x to register %02x", data, offset));
}
@ -427,6 +551,12 @@ UINT8 pit68230_device::rr_pitreg_pcddr()
return m_pcddr;
}
UINT8 pit68230_device::rr_pitreg_pivr()
{
LOGR(("%s %s <- %02x\n",tag(), FUNCNAME, m_pivr));
return m_pivr;
}
UINT8 pit68230_device::rr_pitreg_pacr()
{
LOGR(("%s %s <- %02x\n",tag(), FUNCNAME, m_pacr));
@ -441,6 +571,8 @@ UINT8 pit68230_device::rr_pitreg_pbcr()
UINT8 pit68230_device::rr_pitreg_padr()
{
m_padr &= m_paddr;
m_padr |= (m_pa_in_cb() & ~m_paddr);
LOGR(("%s %s <- %02x\n",tag(), FUNCNAME, m_padr));
return m_padr;
}
@ -454,11 +586,21 @@ UINT8 pit68230_device::rr_pitreg_padr()
* RESET pin. PB0-PB7 sits on pins 17-24 on a 48 pin DIP package */
UINT8 pit68230_device::rr_pitreg_pbdr()
{
m_pbdr &= m_pbddr;
m_pbdr |= (m_pb_in_cb() & ~m_pbddr);
LOGR(("%s %s <- %02x\n",tag(), FUNCNAME, m_pbdr));
return m_pbdr;
}
/* The port A alternate register is an alternate register for reading the port A pins.
UINT8 pit68230_device::rr_pitreg_pcdr()
{
m_pcdr &= m_pcddr;
m_pcdr |= (m_pc_in_cb() & ~m_pcddr);
LOGR(("%s %s <- %02x\n",tag(), FUNCNAME, m_pcdr));
return m_pcdr;
}
/* The port A alternate register is an alternate register for reading the port A pins.
It is a read-only address and no other PI/T condition is affected. In all modes,
the instantaneous pin level is read and no input latching is performed except at the
data bus interface. Writes to this address are answered with DTACK, but the data is ignored.*/
@ -496,6 +638,36 @@ UINT8 pit68230_device::rr_pitreg_psr()
return m_psr;
}
UINT8 pit68230_device::rr_pitreg_tcr()
{
LOGR(("%s %s <- %02x\n",tag(), FUNCNAME, m_tcr));
return m_tcr;
}
UINT8 pit68230_device::rr_pitreg_tivr()
{
LOGR(("%s %s <- %02x\n",tag(), FUNCNAME, m_tivr));
return m_tivr;
}
UINT8 pit68230_device::rr_pitreg_cprh()
{
LOGR(("%s %s <- %02x\n",tag(), FUNCNAME, (m_cpr >> 16) & 0xff));
return (m_cpr >> 16) & 0xff;
}
UINT8 pit68230_device::rr_pitreg_cprm()
{
LOGR(("%s %s <- %02x\n",tag(), FUNCNAME, (m_cpr >> 8) & 0xff));
return (m_cpr >> 8) & 0xff;
}
UINT8 pit68230_device::rr_pitreg_cprl()
{
LOGR(("%s %s <- %02x\n",tag(), FUNCNAME, (m_cpr >> 0) & 0xff));
return (m_cpr >> 0) & 0xff;
}
UINT8 pit68230_device::rr_pitreg_cntrh()
{
LOGR(("%s %s <- %02x\n",tag(), FUNCNAME, (m_cntr >> 16) & 0xff));
@ -514,25 +686,39 @@ UINT8 pit68230_device::rr_pitreg_cntrl()
return (m_cntr >> 0) & 0xff;
}
UINT8 pit68230_device::rr_pitreg_tsr()
{
LOGR(("%s %s <- %02x\n",tag(), FUNCNAME, m_tsr));
return m_tsr;
}
READ8_MEMBER (pit68230_device::read){
UINT8 data;
switch (offset) {
case PIT_68230_PGCR: data = rr_pitreg_pgcr(); break;
case PIT_68230_PSRR: data = rr_pitreg_psrr(); break;
case PIT_68230_PADDR: data = rr_pitreg_paddr(); break;
case PIT_68230_PBDDR: data = rr_pitreg_pbddr(); break;
case PIT_68230_PCDDR: data = rr_pitreg_pcddr(); break;
case PIT_68230_PACR: data = rr_pitreg_pacr(); break;
case PIT_68230_PBCR: data = rr_pitreg_pbcr(); break;
case PIT_68230_PADR: data = rr_pitreg_padr(); break;
case PIT_68230_PBDR: data = rr_pitreg_pbdr(); break;
case PIT_68230_PAAR: data = rr_pitreg_paar(); break;
case PIT_68230_PBAR: data = rr_pitreg_pbar(); break;
case PIT_68230_PSR: data = rr_pitreg_psr(); break;
case PIT_68230_CNTRH: data = rr_pitreg_cntrh(); break;
case PIT_68230_CNTRM: data = rr_pitreg_cntrm(); break;
case PIT_68230_CNTRL: data = rr_pitreg_cntrl(); break;
case PIT_68230_PGCR: data = rr_pitreg_pgcr(); break;
case PIT_68230_PSRR: data = rr_pitreg_psrr(); break;
case PIT_68230_PADDR: data = rr_pitreg_paddr(); break;
case PIT_68230_PBDDR: data = rr_pitreg_pbddr(); break;
case PIT_68230_PCDDR: data = rr_pitreg_pcddr(); break;
case PIT_68230_PIVR: data = rr_pitreg_pivr(); break;
case PIT_68230_PACR: data = rr_pitreg_pacr(); break;
case PIT_68230_PBCR: data = rr_pitreg_pbcr(); break;
case PIT_68230_PADR: data = rr_pitreg_padr(); break;
case PIT_68230_PBDR: data = rr_pitreg_pbdr(); break;
case PIT_68230_PAAR: data = rr_pitreg_paar(); break;
case PIT_68230_PBAR: data = rr_pitreg_pbar(); break;
case PIT_68230_PCDR: data = rr_pitreg_pcdr(); break;
case PIT_68230_PSR: data = rr_pitreg_psr(); break;
case PIT_68230_TCR: data = rr_pitreg_tcr(); break;
case PIT_68230_TIVR: data = rr_pitreg_tivr(); break;
case PIT_68230_CPRH: data = rr_pitreg_cprh(); break;
case PIT_68230_CPRM: data = rr_pitreg_cprm(); break;
case PIT_68230_CPRL: data = rr_pitreg_cprl(); break;
case PIT_68230_CNTRH: data = rr_pitreg_cntrh(); break;
case PIT_68230_CNTRM: data = rr_pitreg_cntrm(); break;
case PIT_68230_CNTRL: data = rr_pitreg_cntrl(); break;
case PIT_68230_TSR: data = rr_pitreg_tsr(); break;
default:
LOG (("Unhandled read register %02x\n", offset));
data = 0;

57
src/devices/machine/68230pit.h
View File

@ -103,7 +103,7 @@
//**************************************************************************
// TYPE DEFINITIONS
//**************************************************************************
class pit68230_device : public device_t, public device_execute_interface
class pit68230_device : public device_t//, public device_execute_interface
{
public:
// construction/destruction
@ -131,44 +131,73 @@ class pit68230_device : public device_t, public device_execute_interface
void wr_pitreg_paddr(UINT8 data);
void wr_pitreg_pbddr(UINT8 data);
void wr_pitreg_pcddr(UINT8 data);
void wr_pitreg_pivr(UINT8 data);
void wr_pitreg_pacr(UINT8 data);
void wr_pitreg_pbcr(UINT8 data);
void wr_pitreg_padr(UINT8 data);
void wr_pitreg_pbdr(UINT8 data);
void wr_pitreg_paar(UINT8 data);
void wr_pitreg_pbar(UINT8 data);
void wr_pitreg_pcdr(UINT8 data);
void wr_pitreg_psr(UINT8 data);
void wr_pitreg_tcr(UINT8 data);
void wr_pitreg_tivr(UINT8 data);
void wr_pitreg_cprh(UINT8 data);
void wr_pitreg_cprm(UINT8 data);
void wr_pitreg_cprl(UINT8 data);
void wr_pitreg_tsr(UINT8 data);
UINT8 rr_pitreg_pgcr();
UINT8 rr_pitreg_psrr();
UINT8 rr_pitreg_paddr();
UINT8 rr_pitreg_pbddr();
UINT8 rr_pitreg_pcddr();
UINT8 rr_pitreg_pivr();
UINT8 rr_pitreg_pacr();
UINT8 rr_pitreg_pbcr();
UINT8 rr_pitreg_padr();
UINT8 rr_pitreg_pbdr();
UINT8 rr_pitreg_paar();
UINT8 rr_pitreg_pbar();
UINT8 rr_pitreg_pcdr();
UINT8 rr_pitreg_psr();
UINT8 rr_pitreg_tcr();
UINT8 rr_pitreg_tivr();
UINT8 rr_pitreg_cprh();
UINT8 rr_pitreg_cprm();
UINT8 rr_pitreg_cprl();
UINT8 rr_pitreg_cntrh();
UINT8 rr_pitreg_cntrm();
UINT8 rr_pitreg_cntrl();
UINT8 rr_pitreg_tsr();
protected:
enum {
REG_TCR_ENABLE = 0x01
REG_TCR_ENABLE = 0x01,
REG_TCR_CC_MASK = 0x06,
REG_TCR_CC_PC2_CLK_PSC = 0x00,
REG_TCR_CC_TEN_CLK_PSC = 0x02,
REG_TCR_CC_TIN_PSC = 0x04,
REG_TCR_CC_TIN_RAW = 0x06,
REG_TCR_ZR = 0x08,
REG_TCR_ZD = 0x10,
REG_TCR_TOUT_TIACK_MASK = 0xe0, // 1 1 1
REG_TCR_PC3_PC7 = 0x00, // 0 0 0
REG_TCR_PC3_PC7_DC = 0x20, // 0 0 1
REG_TCR_TOUT_PC7_SQ = 0x40, // 0 1 0
REG_TCR_TOUT_PC7_SQ_DC = 0x60, // 0 1 1
REG_TCR_TOUT_TIACK = 0x80, // 1 0 0
REG_TCR_TOUT_TIACK_INT = 0xa0, // 1 0 1
REG_TCR_TOUT_PC7 = 0xc0, // 1 1 0
REG_TCR_TOUT_PC7_INT = 0xe0, // 1 1 1
};
// device-level overrides
virtual void device_start () override;
virtual void device_reset () override;
virtual void device_timer (emu_timer &timer, device_timer_id id, int param, void *ptr) override;
virtual void execute_run () override;
// virtual void execute_run () override;
int m_icount;
devcb_write8 m_pa_out_cb;
@ -188,19 +217,29 @@ protected:
UINT8 m_paddr; // Port A Data Direction register
UINT8 m_pbddr; // Port B Data Direction register
UINT8 m_pcddr; // Port C Data Direction register
UINT8 m_pivr; // Ports Interrupt vector
UINT8 m_pacr; // Port A Control register
UINT8 m_pbcr; // Port B Control register
UINT8 m_padr; // Port A Data register
UINT8 m_pbdr; // Port B Data register
UINT8 m_pcdr; // Port C Data register
UINT8 m_psr; // Port Status Register
UINT8 m_tcr; // Timer Control Register
int m_cpr; // Counter Preload Registers (3 x 8 = 24 bits)
// UINT8 m_cprh; // Counter Preload Register High
// UINT8 m_cprm; // Counter Preload Register Mid
// UINT8 m_cprl; // Counter Preload Register Low
int m_cntr; // - The 24 bit Counter
UINT8 m_tcr; // Timer Control Register
UINT8 m_tivr; // Timer Interrupt Vector register
int m_cpr; // Counter Preload Registers (3 x 8 = 24 bits)
int m_cntr; // - The 24 bit Counter
UINT8 m_tsr; // Timer Status Register
// Timers
emu_timer *pit_timer;
enum
{
TIMER_ID_PIT
};
};
// device type definition
extern const device_type PIT68230;
#endif /* __68230PIT_H__ */

1029
src/devices/machine/scnxx562.cpp
View File

File diff suppressed because it is too large Load Diff

94
src/devices/machine/scnxx562.h
View File

@ -40,6 +40,7 @@
#define __SCNXX562_H__
#include "emu.h"
#include "cpu/z80/z80daisy.h"
//**************************************************************************
// DEVICE CONFIGURATION MACROS
@ -110,7 +111,7 @@
class duscc_device;
class duscc_channel : public device_t,
public device_serial_interface
public device_serial_interface
{
friend class duscc_device;
@ -152,9 +153,8 @@ public:
UINT8 do_dusccreg_gsr_r();
UINT8 do_dusccreg_ier_r();
UINT8 do_dusccreg_cid_r();
UINT8 do_dusccreg_ivr_r();
UINT8 do_dusccreg_ivr_ivrm_r();
UINT8 do_dusccreg_icr_r();
UINT8 do_dusccreg_ivrm_r();
UINT8 do_dusccreg_mrr_r();
UINT8 do_dusccreg_ier1_r();
UINT8 do_dusccreg_ier2_r();
@ -189,7 +189,7 @@ public:
// void do_dusccreg_rea_w(UINT8 data); // Short cutted non complex feature
void do_dusccreg_ivr_w(UINT8 data);
void do_dusccreg_icr_w(UINT8 data);
// void do_dusccreg_sea_w(UINT8 data); // Short cutted non complex feature
void do_dusccreg_sea_rea_w(UINT8 data); // Short cutted non complex feature
void do_dusccreg_mrr_w(UINT8 data);
void do_dusccreg_ier1_w(UINT8 data);
void do_dusccreg_ier2_w(UINT8 data);
@ -231,12 +231,14 @@ public:
UINT8 m_ttr;
UINT8 m_rpr;
UINT8 m_rtr;
UINT8 m_ctprh;
UINT8 m_ctprl;
// UINT8 m_ctprh;
// UINT8 m_ctprl;
unsigned int m_ctpr;
UINT8 m_ctcr;
UINT8 m_omr;
UINT8 m_cth;
UINT8 m_ctl;
// UINT8 m_cth;
// UINT8 m_ctl;
unsigned int m_ct;
UINT8 m_pcr;
UINT8 m_ccr;
UINT8 m_txfifo[4];
@ -244,14 +246,14 @@ public:
UINT8 m_rsr;
UINT8 m_trsr;
UINT8 m_ictsr;
UINT8 m_gsr;
// UINT8 m_gsr; // moved to the device since it is global
UINT8 m_ier;
// UINT8 m_rea;
UINT8 m_cid;
UINT8 m_ivr;
UINT8 m_icr;
// UINT8 m_sea;
UINT8 m_ivrm;
//UINT8 m_ivr;
//UINT8 m_icr;
// UINT8 m_sea;
//UINT8 m_ivrm;
UINT8 m_mrr;
UINT8 m_ier1;
UINT8 m_ier2;
@ -263,12 +265,12 @@ public:
UINT8 m_telr;
protected:
enum
enum // Needs to be 0-3 in unmodified prio level
{
INT_TRANSMIT = 0,
INT_EXTERNAL = 1,
INT_RECEIVE = 2,
INT_SPECIAL = 3
INT_RXREADY = 0,
INT_TXREADY = 1,
INT_RXTXSTAT = 2,
INT_EXTCTSTAT = 3
};
enum
@ -387,7 +389,19 @@ protected:
enum
{
REG_RSR_OVERRUN_ERROR = 0x20,
REG_RSR_CHAR_COMPARE = 0x80,
REG_RSR_OVERRUN_ERROR = 0x20,
REG_RSR_FRAMING_ERROR = 0x02,
REG_RSR_PARITY_ERROR = 0x01,
};
enum
{
REG_GSR_CHAN_A_RXREADY = 0x01,
REG_GSR_CHAN_B_RXREADY = 0x10,
REG_GSR_CHAN_A_TXREADY = 0x02,
REG_GSR_CHAN_B_TXREADY = 0x20,
REG_GSR_XXREADY_MASK = 0x33
};
enum
@ -399,10 +413,14 @@ protected:
enum
{
REG_GSR_CHAN_A_RXREADY = 0x01,
REG_GSR_CHAN_B_RXREADY = 0x10,
REG_GSR_CHAN_A_TXREADY = 0x02,
REG_GSR_CHAN_B_TXREADY = 0x20,
REG_IER_DCD_CTS = 0x80,
REG_IER_TXRDY = 0x40,
REG_IER_TRSR73 = 0x20,
REG_IER_RXRDY = 0x10,
REG_IER_RSR76 = 0x08,
REG_IER_RSR54 = 0x04,
REG_IER_RSR32 = 0x02,
REG_IER_RSR10 = 0x01,
};
// Register offsets, stripped from channel bit 0x20 but including A7 bit
@ -521,7 +539,6 @@ protected:
int m_rx_clock; // receive clock pulse count
int m_rx_first; // first character received
int m_rx_break; // receive break condition
// UINT8 m_rx_rr0_latch; // read register 0 latched
int m_rxd;
int m_ri; // ring indicator latch
@ -551,7 +568,7 @@ protected:
class duscc_device : public device_t
// ,public device_z80daisy_interface
,public device_z80daisy_interface
{
friend class duscc_channel;
@ -611,6 +628,11 @@ protected:
virtual void device_reset() override;
virtual machine_config_constructor device_mconfig_additions() const override;
// device_z80daisy_interface overrides
virtual int z80daisy_irq_state() override;
virtual int z80daisy_irq_ack() override;
virtual void z80daisy_irq_reti() override;
// internal interrupt management
void check_interrupts();
void reset_interrupts();
@ -658,9 +680,29 @@ protected:
devcb_write_line m_out_rtsb_cb;
devcb_write_line m_out_syncb_cb;
int m_int_state[6]; // interrupt state
devcb_write_line m_out_int_cb;
int m_int_state[8]; // interrupt state
int m_variant;
UINT8 m_gsr;
UINT8 m_ivr;
UINT8 m_ivrm;
UINT8 m_icr;
enum
{
REG_ICR_CHB = 0x01,
REG_ICR_CHA = 0x02,
REG_ICR_VEC_MOD = 0x04,
REG_ICR_V2V4_MOD = 0x08,
REG_ICR_PRIO_MASK = 0xC0,
REG_ICR_PRIO_AHI = 0x00,
REG_ICR_PRIO_BHI = 0x40,
REG_ICR_PRIO_AINT = 0x80,
REG_ICR_PRIO_BINT = 0xC0,
};
};
// device type definition

309
src/mame/drivers/fcisio.cpp Normal file
View File

@ -0,0 +1,309 @@
// license:BSD-3-Clause
// copyright-holders:Joakim Larsson Edstrom
/***************************************************************************
*
* 10/06/2016
* Force SYS68K ISIO-1/2 driver - This driver will be converted into a slot device once the VME bus driver exists.
* The ISIO board is a VME slave board that reads command and returns results through dual ported RAM to the VME bus.
*
* ISIO-1: page 385 http://bitsavers.informatik.uni-stuttgart.de/pdf/forceComputers/1988_Force_VMEbus_Products.pdf
* ISIO-2: page 395 http://bitsavers.informatik.uni-stuttgart.de/pdf/forceComputers/1988_Force_VMEbus_Products.pdf
*
* Address Map - guessed/revenged no tech doc available
* ----------------------------------------------------------
* Address Range Description LOCAL
* ----------------------------------------------------------
* 00 0000 - 00 0007 Initialisation vectors from system EPROM
* 00 0008 - 01 FFFF Local SRAM
* E0 0000 - E0 01FF DUSCC0
* E2 0000 - E0 01FF DUSCC0
* E4 0000 - E0 01FF DUSCC0
* E6 0000 - E0 01FF DUSCC0
* E8 0000 - E8 0DFF PI/T
* f0 0000 - F7 0000 EPROMs
* ----------------------------------------------------------
* Address Range Description LOCAL
* ----------------------------------------------------------
*
* Interrupt sources
* ----------------------------------------------------------
* Description Device Lvl IRQ VME board
* /Board Vector Address
* ----------------------------------------------------------
* On board Sources
* ----------------------------------------------------------
*
* TODO:
* - add PIT and DUSCC interrupts
* - add port mapping to self test jumper
* - add VME bus driver
* - write and map a 68153 device (accessable from VME side)
*
* Status: passes Self test and get stuck on no ticks for the scheduler.
* Schematics of the IRQ routing needed or a good trace of how the
* PIT and DUSCCs are hooked up to the BIM to get further.
*
****************************************************************************/
#define TODO "Driver for 68153 BIM device needed\n"
#include "emu.h"
#include "cpu/m68000/m68000.h"
#include "machine/scnxx562.h"
#include "machine/68230pit.h"
#include "bus/rs232/rs232.h"
#include "machine/clock.h"
#define VERBOSE 0
#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
#if VERBOSE == 2
#define logerror printf
#endif
#ifdef _MSC_VER
#define FUNCNAME __func__
#define LLFORMAT "%I64%"
#else
#define FUNCNAME __PRETTY_FUNCTION__
#define LLFORMAT "%lld"
#endif
#define CPU_CLOCK XTAL_20MHz /* HCJ */
#define DUSCC_CLOCK XTAL_14_7456MHz /* HCJ */
class fcisio1_state : public driver_device
{
public:
fcisio1_state(const machine_config &mconfig, device_type type, const char *tag) :
driver_device (mconfig, type, tag),
m_maincpu (*this, "maincpu")
,m_duscc0(*this, "duscc0")
,m_duscc1(*this, "duscc1")
,m_duscc2(*this, "duscc2")
,m_duscc3(*this, "duscc3")
,m_pit (*this, "pit")
{
}
DECLARE_READ16_MEMBER (bootvect_r);
DECLARE_READ8_MEMBER (config_rd);
/* Dummy driver routines */
DECLARE_READ8_MEMBER (not_implemented_r);
DECLARE_WRITE8_MEMBER (not_implemented_w);
virtual void machine_start () override;
protected:
private:
required_device<cpu_device> m_maincpu;
required_device<duscc68562_device> m_duscc0;
required_device<duscc68562_device> m_duscc1;
required_device<duscc68562_device> m_duscc2;
required_device<duscc68562_device> m_duscc3;
required_device<pit68230_device> m_pit;
// Pointer to System ROMs needed by bootvect_r
UINT16 *m_sysrom;
};
static ADDRESS_MAP_START (fcisio1_mem, AS_PROGRAM, 16, fcisio1_state)
ADDRESS_MAP_UNMAP_HIGH
AM_RANGE (0x000000, 0x000007) AM_ROM AM_READ (bootvect_r) /* Vectors mapped from System EPROM */
AM_RANGE (0x000000, 0x01ffff) AM_RAM /* SRAM */
AM_RANGE (0xe00000, 0xe001ff) AM_DEVREADWRITE8("duscc0", duscc68562_device, read, write, 0x00ff)
AM_RANGE (0xe20000, 0xe201ff) AM_DEVREADWRITE8("duscc1", duscc68562_device, read, write, 0x00ff)
AM_RANGE (0xe40000, 0xe401ff) AM_DEVREADWRITE8("duscc2", duscc68562_device, read, write, 0x00ff)
AM_RANGE (0xe60000, 0xe601ff) AM_DEVREADWRITE8("duscc3", duscc68562_device, read, write, 0x00ff)
AM_RANGE (0xe80000, 0xe80dff) AM_DEVREADWRITE8("pit", pit68230_device, read, write, 0x00ff)
AM_RANGE (0xf00000, 0xf7ffff) AM_ROM /* System EPROM Area 32Kb DEBUGGER supplied */
// AM_RANGE (0xc40000, 0xc800ff) AM_READWRITE8 (not_implemented_r, not_implemented_w, 0xffff) /* Dummy mapping af address area to display message */
ADDRESS_MAP_END
/* Start it up */
void fcisio1_state::machine_start ()
{
LOG (("machine_start\n"));
/* Setup pointer to bootvector in ROM for bootvector handler bootvect_r */
m_sysrom = (UINT16*)(memregion ("maincpu")->base () + 0xf00000);
}
/* Boot vector handler, the PCB hardwires the first 8 bytes from 0x80000 to 0x0 */
READ16_MEMBER (fcisio1_state::bootvect_r){
return m_sysrom [offset];
}
READ8_MEMBER (fcisio1_state::not_implemented_r){
static int been_here = 0;
if (!been_here++){
logerror(TODO);
printf(TODO);
}
return (UINT8) 0;
}
WRITE8_MEMBER (fcisio1_state::not_implemented_w){
static int been_here = 0;
if (!been_here++){
logerror(TODO);
printf(TODO);
}
return;
}
// TODO: Get a manual to understand the config options for real
READ8_MEMBER (fcisio1_state::config_rd){
UINT8 ret = 0;
LOG(("%s\n", FUNCNAME));
// Port B bit #7, 0x80 Self test bit, choose either of these two lines
ret &= ~0x80; // 0 = selftest
// ret |= 0x80; // 1 = no selftest
return ret;
}
/* Input ports */
static INPUT_PORTS_START (fcisio1)
INPUT_PORTS_END
static DEVICE_INPUT_DEFAULTS_START( fcisio_terminal )
DEVICE_INPUT_DEFAULTS( "RS232_TXBAUD", 0xff, RS232_BAUD_9600 )
DEVICE_INPUT_DEFAULTS( "RS232_RXBAUD", 0xff, RS232_BAUD_9600 )
DEVICE_INPUT_DEFAULTS( "RS232_STARTBITS", 0xff, RS232_STARTBITS_1 )
DEVICE_INPUT_DEFAULTS( "RS232_DATABITS", 0xff, RS232_DATABITS_8 )
DEVICE_INPUT_DEFAULTS( "RS232_PARITY", 0xff, RS232_PARITY_NONE )
DEVICE_INPUT_DEFAULTS( "RS232_STOPBITS", 0xff, RS232_STOPBITS_1 )
DEVICE_INPUT_DEFAULTS_END
/*
* Machine configuration
*/
static MACHINE_CONFIG_START (fcisio1, fcisio1_state)
/* basic machine hardware */
MCFG_CPU_ADD ("maincpu", M68010, CPU_CLOCK / 2)
MCFG_CPU_PROGRAM_MAP (fcisio1_mem)
MCFG_DUSCC68562_ADD("duscc0", DUSCC_CLOCK, 0, 0, 0, 0 )
MCFG_DUSCC_OUT_TXDA_CB(DEVWRITELINE("rs232trm", rs232_port_device, write_txd))
MCFG_DUSCC_OUT_DTRA_CB(DEVWRITELINE("rs232trm", rs232_port_device, write_dtr))
MCFG_DUSCC_OUT_RTSA_CB(DEVWRITELINE("rs232trm", rs232_port_device, write_rts))
MCFG_RS232_PORT_ADD ("rs232trm", default_rs232_devices, "terminal")
MCFG_RS232_RXD_HANDLER (DEVWRITELINE ("duscc0", duscc68562_device, rxa_w))
MCFG_RS232_CTS_HANDLER (DEVWRITELINE ("duscc0", duscc68562_device, ctsa_w))
MCFG_DEVICE_CARD_DEVICE_INPUT_DEFAULTS("terminal", fcisio_terminal)
MCFG_DUSCC68562_ADD("duscc1", DUSCC_CLOCK, 0, 0, 0, 0 )
MCFG_DUSCC68562_ADD("duscc2", DUSCC_CLOCK, 0, 0, 0, 0 )
MCFG_DUSCC68562_ADD("duscc3", DUSCC_CLOCK, 0, 0, 0, 0 )
MCFG_DEVICE_ADD ("pit", PIT68230, XTAL_20MHz / 2)
MCFG_PIT68230_PB_INPUT_CB(READ8(fcisio1_state, config_rd))
MACHINE_CONFIG_END
/* ROM definitions */
ROM_START (fcisio1)
ROM_REGION (0x1000000, "maincpu", 0)
/* ISIO ROM:s v2.1 information
* PIT setup sequence
* 00 -> REG_PGCR
* 18 -> REG_PSRR
* 0f -> Reg PADDR
* 0f -> REG_PBDDR
* fa -> REG_PACR
* 0f -> REG_PADDR
* fa -> REG_PBCR
* ff -> REG_PBDR
* 0f -> REG_PBDDR
* 10 -> REG_PGCR
* ff -> REG_PCDR
* 17 -> REG_PCDDR
* 40 -> Reg PIVR
* 00 -> REG_TCR - timer disabled, all C pins, use preload, CLK and prescaler are used
* a0 -> REG_TCR - timer disabled, The dual-function pin PC3/TOUT carries the TOUTfunction and is used as a timer interrupt request
* output. The timer interrupt is enabled ; thus, the pin is low when the timer ZDS status bit is one. The dual-function
* pin PC7/TIACK carries the TIACK function and is used as a timer interrupt acknowledge input.
* 00 -> Reg 0x12
* 00 -> REG_CPRH
* 09 -> REG_CPRM
* 00 -> REG_CPRL
* 00 -> Reg 0x16
* 00 -> Reg 0x17
* 09 -> Reg 0x18
* 00 -> Reg 0x19
* 1d -> Reg TIVR
* 0f <- REG_PBDR
* 0e -> REG_PBDR
* 0f <- REG_PBDR
* 0f <- REG_PBDR
* 0d -> REG_PDBR
* 0f <- REG_PBDR
* 0f <- REG_PBDR
* 0f <- REG_PBDR
* 0f <- REG_PBDR
* 0f <- REG_PBDR
* 0f <- REG_PBDR
* 0f <- REG_PBDR
* 0f <- REG_PBDR
* 0f <- REG_PBDR
* 0f -> REG_PBDR
* 0f <- REG_PBDR
* 0b -> REG_PBDR
* 0f <- REG_PBDR
* 0f <- REG_PBDR
* 0f -> REG_PBDR
* 0f <- REG_PBDR
* 0f -> REG_PBDR
* 0f <- REG_PBDR
* 00 <- REG_PCDR
* 00 -> REG_PCDR
* ------- repeated 16 times -------------------
* a1 -> REG_TCR - timer enabled, The dual-function pin PC3/TOUT carries the TOUTfunction and is used as a timer interrupt request
* output. The timer interrupt is enabled ; thus, the pin is low when the timer ZDS status bit is one. The dual-function
* pin PC7/TIACK carries the TIACK function and is used as a timer interrupt acknowledge input.
* ?? <- Reg 0x0c
* ---------------------------------------------
*
* DUSCC0 channel A setup sequence
* 0f 00 -> REG_CCR - Reset Tx
* 0f 40 -> REG_CCR - Reset Rx
* 00 07 -> REG_CMR1 - Async mode
* 01 38 -> REG_CMR2 - Normal polled or interrupt mode, no DMA
* 02 00 -> REG_S1R - SYN1, Secondary Address 1 Register, 0 = no sync
* 03 00 -> REG_S2R - SYN2, only used in COP dual Sync mode but alao 0 = no sync
* 04 7F -> REG_TPR - Tx 8 bits, CTS and RTS, 1 STOP bit
* 05 3d -> REG_TTR - Tx BRG 9600 (assuming a 14.7456 crystal)
* 06 1b -> REG_RPR - Rx RTS, 8 bits, no DCD, no parity
* 07 2d -> REG_RTR - Rx BRG 9600 (assuming a 14.7456 crystal)
* 0b e1 -> REG_OMR - RTS high, OUT1 = OUT2 = high, RxRdy asserted for each character,
* TxRdy asserted on threshold, Same Tx Residual Character Length as for REG_TPR
* 0a 00 -> REG_CTCR - Counter/Timer control register 00 = Zero Det Int: disabled, Zero Det Control: preset,
* Output Control: square, Prescaler: 1, Clock Source: RTxC pin
* 09 00 -> REG_CTPRL - Counter/Timer Prescaler Register Low = 0
* 08 00 -> REG_CTPRH - Counter/Timer Prescaler Register High = 0
* 0f 00 -> REG_CCR - Reset Tx
* 0f 02 -> REG_CCR - Enable Tx
* 0f 40 -> REG_CCR - Reset Rx
* 0f 42 -> REG_CCR - Enable Rx
* 0f 02 -> REG_CCR - Enable Tx
* 0f 42 -> REG_CCR - Enable Rx
* 0e 27 -> REG_PCR - TRxC = RxCLK 1x, RTxC is input, RTS, GPO2, crystal oscillator connected to X2
* 1c 10 -> REG_IER - Interrupt Enable Register: RxRdy generates interrupt
* ... chan B setup with same data....
* ---- DUSCC0 to DUSCC3, setup with same data except at the end of each setup:
* 1e 1c -> DUSCC0 REG_IVR -
* 1e 1b -> DUSCC1 REG_IVR
* 1e 1a -> DUSCC2 REG_IVR
* 1e 19 -> DUSCC3 REG_IVR
*/
ROM_LOAD16_BYTE ("ISIO-1_V2.1_L.BIN", 0xf00001, 0x4000, CRC (0d47d80f) SHA1 (541b55966f464c1cf686e36998650720950a2242))
ROM_LOAD16_BYTE ("ISIO-1_V2.1_U.BIN", 0xf00000, 0x4000, CRC (67986768) SHA1 (215f7ff90d9dbe2bea54510e3722fb33d4e54193))
ROM_END
/* Driver */
/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS */
COMP( 1986, fcisio1, 0, 0, fcisio1, fcisio1, driver_device, 0, "Force Computers Gmbh", "SYS68K/ISIO-1", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW | MACHINE_TYPE_COMPUTER )

3
src/mame/mame.lst
View File

@ -12083,6 +12083,9 @@ fccpu30 //
@source:fcscsi.cpp
fcscsi1 //
@source:fcisio.cpp
fcisio1 //
@source:fcombat.cpp
fcombat // (c) 1985 Jaleco