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A few more fixes.

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This commit is contained in:
Aaron Giles 2009-12-21 10:06:40 +00:00
parent 90c6e390f0
commit a9697769d9
11 changed files with 123 additions and 74 deletions
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3
src/emu/machine/8237dma.c
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@ -641,6 +641,8 @@ static DEVICE_START( i8237 ) {
devcb_resolve_write8(&i8237->chan[i].out_iow_func, &intf->out_iow_func[i], device);
devcb_resolve_write_line(&i8237->chan[i].out_dack_func, &intf->out_dack_func[i], device);
}
i8237->timer = timer_alloc(device->machine, dma8237_timerproc, (void *)device);
}
@ -648,7 +650,6 @@ static DEVICE_RESET( i8237 ) {
i8237_t *i8237 = get_safe_token(device);
i8237->status = 0x0F;
i8237->timer = timer_alloc(device->machine, dma8237_timerproc, (void *)device);
i8237->eop = 1;
i8237->state = DMA8237_SI;
i8237->last_service_channel = 3;

9
src/emu/mame.c
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@ -1573,6 +1573,9 @@ static void init_machine(running_machine *machine)
saveload_init(machine);
if (options_get_bool(mame_options(), OPTION_CHEAT))
cheat_init(machine);
/* disallow save state registrations starting here */
state_save_allow_registration(machine, FALSE);
}
@ -1596,9 +1599,6 @@ static TIMER_CALLBACK( soft_reset )
end_resource_tracking();
begin_resource_tracking();
/* allow save state registrations during the reset */
state_save_allow_registration(machine, TRUE);
/* call all registered reset callbacks */
for (cb = machine->mame_data->reset_callback_list; cb; cb = cb->next)
(*cb->func.reset)(machine);
@ -1611,9 +1611,6 @@ static TIMER_CALLBACK( soft_reset )
if (machine->config->video_reset != NULL)
(*machine->config->video_reset)(machine);
/* disallow save state registrations starting here */
state_save_allow_registration(machine, FALSE);
/* now we're running */
mame->current_phase = MAME_PHASE_RUNNING;

20
src/mame/audio/n8080.c
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@ -435,10 +435,10 @@ static WRITE8_HANDLER( helifire_sound_ctrl_w )
}
static TIMER_CALLBACK( spacefev_vco_voltage_timer )
static TIMER_DEVICE_CALLBACK( spacefev_vco_voltage_timer )
{
const device_config *sn = devtag_get_device(machine, "snsnd");
n8080_state *state = (n8080_state *)machine->driver_data;
const device_config *sn = devtag_get_device(timer->machine, "snsnd");
n8080_state *state = (n8080_state *)timer->machine->driver_data;
double voltage = 0;
if (state->mono_flop[2])
@ -450,10 +450,10 @@ static TIMER_CALLBACK( spacefev_vco_voltage_timer )
}
static TIMER_CALLBACK( helifire_dac_volume_timer )
static TIMER_DEVICE_CALLBACK( helifire_dac_volume_timer )
{
n8080_state *state = (n8080_state *)machine->driver_data;
double t = state->helifire_dac_timing - attotime_to_double(timer_get_time(machine));
n8080_state *state = (n8080_state *)timer->machine->driver_data;
double t = state->helifire_dac_timing - attotime_to_double(timer_get_time(timer->machine));
if (state->helifire_dac_phase)
{
@ -486,8 +486,6 @@ MACHINE_RESET( spacefev_sound )
n8080_state *state = (n8080_state *)machine->driver_data;
state->n8080_hardware = 1;
timer_pulse(machine, ATTOTIME_IN_HZ(1000), NULL, 0, spacefev_vco_voltage_timer);
state->mono_flop[0] = 0;
state->mono_flop[1] = 0;
state->mono_flop[2] = 0;
@ -548,8 +546,6 @@ MACHINE_RESET( helifire_sound )
n8080_state *state = (n8080_state *)machine->driver_data;
state->n8080_hardware = 3;
timer_pulse(machine, ATTOTIME_IN_HZ(1000), NULL, 0, helifire_dac_volume_timer);
state->helifire_dac_volume = 1;
state->helifire_dac_timing = 0;
state->helifire_dac_phase = 0;
@ -596,6 +592,8 @@ MACHINE_DRIVER_START( spacefev_sound )
MDRV_CPU_PROGRAM_MAP(n8080_sound_cpu_map)
MDRV_CPU_IO_MAP(n8080_sound_io_map)
MDRV_TIMER_ADD_PERIODIC("vco_timer", spacefev_vco_voltage_timer, HZ(1000))
/* sound hardware */
MDRV_SPEAKER_STANDARD_MONO("mono")
@ -634,6 +632,8 @@ MACHINE_DRIVER_START( helifire_sound )
MDRV_CPU_PROGRAM_MAP(n8080_sound_cpu_map)
MDRV_CPU_IO_MAP(helifire_sound_io_map)
MDRV_TIMER_ADD_PERIODIC("helifire_dac", helifire_dac_volume_timer, HZ(1000) )
/* sound hardware */
MDRV_SPEAKER_STANDARD_MONO("mono")

16
src/mame/drivers/mediagx.c
View File

@ -113,7 +113,6 @@ static INT16 *dacr;
static int dacl_ptr = 0;
static int dacr_ptr = 0;
static emu_timer *sound_timer;
static UINT8 ad1847_regs[16];
static UINT32 ad1847_sample_counter = 0;
static UINT32 ad1847_sample_rate;
@ -635,10 +634,10 @@ static void cx5510_pci_w(const device_config *busdevice, const device_config *de
/* Analog Devices AD1847 Stereo DAC */
static TIMER_CALLBACK( sound_timer_callback )
static TIMER_DEVICE_CALLBACK( sound_timer_callback )
{
ad1847_sample_counter = 0;
timer_adjust_oneshot(sound_timer, ATTOTIME_IN_MSEC(10), 0);
timer_device_adjust_oneshot(timer, ATTOTIME_IN_MSEC(10), 0);
dmadac_transfer(&dmadac[0], 1, 0, 1, dacl_ptr, dacl);
dmadac_transfer(&dmadac[1], 1, 0, 1, dacr_ptr, dacr);
@ -965,6 +964,9 @@ static MACHINE_START(mediagx)
mediagx_devices.pic8259_2 = devtag_get_device( machine, "pic8259_slave" );
mediagx_devices.dma8237_1 = devtag_get_device( machine, "dma8237_1" );
mediagx_devices.dma8237_2 = devtag_get_device( machine, "dma8237_2" );
dacl = auto_alloc_array(machine, INT16, 65536);
dacr = auto_alloc_array(machine, INT16, 65536);
}
static MACHINE_RESET(mediagx)
@ -976,11 +978,7 @@ static MACHINE_RESET(mediagx)
memcpy(bios_ram, rom, 0x40000);
device_reset(cputag_get_cpu(machine, "maincpu"));
dacl = auto_alloc_array(machine, INT16, 65536);
dacr = auto_alloc_array(machine, INT16, 65536);
sound_timer = timer_alloc(machine, sound_timer_callback, NULL);
timer_adjust_oneshot(sound_timer, ATTOTIME_IN_MSEC(10), 0);
timer_device_adjust_oneshot(devtag_get_device(machine, "sound_timer"), ATTOTIME_IN_MSEC(10), 0);
dmadac[0] = devtag_get_device(machine, "dac1");
dmadac[1] = devtag_get_device(machine, "dac2");
@ -1070,6 +1068,8 @@ static MACHINE_DRIVER_START(mediagx)
MDRV_IDE_CONTROLLER_ADD("ide", ide_interrupt)
MDRV_TIMER_ADD("sound_timer", sound_timer_callback)
MDRV_NVRAM_HANDLER( mc146818 )
/* video hardware */

3
src/mame/drivers/mhavoc.c
View File

@ -480,9 +480,12 @@ static MACHINE_DRIVER_START( mhavoc )
MDRV_CPU_ADD("gamma", M6502, MHAVOC_CLOCK_1_25M) /* 1.25 MHz */
MDRV_CPU_PROGRAM_MAP(gamma_map)
MDRV_MACHINE_START(mhavoc)
MDRV_MACHINE_RESET(mhavoc)
MDRV_NVRAM_HANDLER(generic_1fill)
MDRV_TIMER_ADD_PERIODIC("5k_timer", mhavoc_cpu_irq_clock, HZ(MHAVOC_CLOCK_5K))
/* video hardware */
MDRV_SCREEN_ADD("screen", VECTOR)
MDRV_SCREEN_REFRESH_RATE(50)

2
src/mame/drivers/model1.c
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@ -1457,6 +1457,7 @@ static MACHINE_DRIVER_START( model1 )
MDRV_CPU_ADD("audiocpu", M68000, 10000000) // verified on real h/w
MDRV_CPU_PROGRAM_MAP(model1_snd)
MDRV_MACHINE_START(model1)
MDRV_MACHINE_RESET(model1)
MDRV_NVRAM_HANDLER(generic_0fill)
@ -1500,6 +1501,7 @@ static MACHINE_DRIVER_START( model1_vr )
MDRV_CPU_CONFIG(model1_vr_tgp_config)
MDRV_CPU_PROGRAM_MAP(model1_vr_tgp_map)
MDRV_MACHINE_START(model1)
MDRV_MACHINE_RESET(model1_vr)
MDRV_NVRAM_HANDLER(generic_0fill)

57
src/mame/drivers/model2.c
View File

@ -72,7 +72,7 @@ static UINT16 *model2_soundram = NULL;
static UINT32 model2_timervals[4], model2_timerorig[4];
static int model2_timerrun[4];
static emu_timer *model2_timers[4];
static const device_config *model2_timers[4];
static int model2_ctrlmode;
static int analog_channel;
@ -271,7 +271,7 @@ static READ32_HANDLER( timers_r )
if (model2_timerrun[offset])
{
// get elapsed time, convert to units of 25 MHz
UINT32 cur = attotime_to_double(attotime_mul(timer_timeelapsed(model2_timers[offset]), 25000000));
UINT32 cur = attotime_to_double(attotime_mul(timer_device_timeelapsed(model2_timers[offset]), 25000000));
// subtract units from starting value
model2_timervals[offset] = model2_timerorig[offset] - cur;
@ -289,21 +289,21 @@ static WRITE32_HANDLER( timers_w )
model2_timerorig[offset] = model2_timervals[offset];
period = attotime_mul(ATTOTIME_IN_HZ(25000000), model2_timerorig[offset]);
timer_adjust_oneshot(model2_timers[offset], period, 0);
timer_device_adjust_oneshot(model2_timers[offset], period, 0);
model2_timerrun[offset] = 1;
}
static TIMER_CALLBACK( model2_timer_cb )
static TIMER_DEVICE_CALLBACK( model2_timer_cb )
{
int tnum = (int)(FPTR)ptr;
int bit = tnum + 2;
timer_adjust_oneshot(model2_timers[tnum], attotime_never, 0);
timer_device_adjust_oneshot(model2_timers[tnum], attotime_never, 0);
model2_intreq |= (1<<bit);
if (model2_intena & (1<<bit))
{
cputag_set_input_line(machine, "maincpu", I960_IRQ2, ASSERT_LINE);
cputag_set_input_line(timer->machine, "maincpu", I960_IRQ2, ASSERT_LINE);
}
model2_timervals[tnum] = 0;
@ -330,11 +330,12 @@ static MACHINE_RESET(model2_common)
model2_timerrun[0] = model2_timerrun[1] = model2_timerrun[2] = model2_timerrun[3] = 0;
model2_timers[0] = devtag_get_device(machine, "timer0");
model2_timers[1] = devtag_get_device(machine, "timer1");
model2_timers[2] = devtag_get_device(machine, "timer2");
model2_timers[3] = devtag_get_device(machine, "timer3");
for (i=0; i<4; i++)
{
model2_timers[i] = timer_alloc(machine, model2_timer_cb, (void*)(FPTR)i);
timer_adjust_oneshot(model2_timers[i], attotime_never, 0);
}
timer_device_adjust_oneshot(model2_timers[i], attotime_never, 0);
}
static MACHINE_RESET(model2o)
@ -1842,6 +1843,15 @@ static MACHINE_DRIVER_START( model2o )
MDRV_MACHINE_RESET(model2o)
MDRV_NVRAM_HANDLER( model2 )
MDRV_TIMER_ADD("timer0", model2_timer_cb)
MDRV_TIMER_PTR((FPTR)0)
MDRV_TIMER_ADD("timer1", model2_timer_cb)
MDRV_TIMER_PTR((FPTR)1)
MDRV_TIMER_ADD("timer2", model2_timer_cb)
MDRV_TIMER_PTR((FPTR)2)
MDRV_TIMER_ADD("timer3", model2_timer_cb)
MDRV_TIMER_PTR((FPTR)3)
MDRV_VIDEO_ATTRIBUTES(VIDEO_UPDATE_AFTER_VBLANK )
@ -1888,6 +1898,15 @@ static MACHINE_DRIVER_START( model2a )
MDRV_MACHINE_RESET(model2)
MDRV_NVRAM_HANDLER( model2 )
MDRV_TIMER_ADD("timer0", model2_timer_cb)
MDRV_TIMER_PTR((FPTR)0)
MDRV_TIMER_ADD("timer1", model2_timer_cb)
MDRV_TIMER_PTR((FPTR)1)
MDRV_TIMER_ADD("timer2", model2_timer_cb)
MDRV_TIMER_PTR((FPTR)2)
MDRV_TIMER_ADD("timer3", model2_timer_cb)
MDRV_TIMER_PTR((FPTR)3)
MDRV_VIDEO_ATTRIBUTES(VIDEO_UPDATE_AFTER_VBLANK )
MDRV_SCREEN_ADD("screen", RASTER)
@ -1938,6 +1957,15 @@ static MACHINE_DRIVER_START( model2b )
MDRV_MACHINE_RESET(model2b)
MDRV_NVRAM_HANDLER( model2 )
MDRV_TIMER_ADD("timer0", model2_timer_cb)
MDRV_TIMER_PTR((FPTR)0)
MDRV_TIMER_ADD("timer1", model2_timer_cb)
MDRV_TIMER_PTR((FPTR)1)
MDRV_TIMER_ADD("timer2", model2_timer_cb)
MDRV_TIMER_PTR((FPTR)2)
MDRV_TIMER_ADD("timer3", model2_timer_cb)
MDRV_TIMER_PTR((FPTR)3)
MDRV_VIDEO_ATTRIBUTES(VIDEO_UPDATE_AFTER_VBLANK )
MDRV_SCREEN_ADD("screen", RASTER)
@ -1972,6 +2000,15 @@ static MACHINE_DRIVER_START( model2c )
MDRV_MACHINE_RESET(model2c)
MDRV_NVRAM_HANDLER( model2 )
MDRV_TIMER_ADD("timer0", model2_timer_cb)
MDRV_TIMER_PTR((FPTR)0)
MDRV_TIMER_ADD("timer1", model2_timer_cb)
MDRV_TIMER_PTR((FPTR)1)
MDRV_TIMER_ADD("timer2", model2_timer_cb)
MDRV_TIMER_PTR((FPTR)2)
MDRV_TIMER_ADD("timer3", model2_timer_cb)
MDRV_TIMER_PTR((FPTR)3)
MDRV_VIDEO_ATTRIBUTES(VIDEO_UPDATE_AFTER_VBLANK )
MDRV_SCREEN_ADD("screen", RASTER)

3
src/mame/includes/mhavoc.h
View File

@ -17,9 +17,12 @@
/*----------- defined in machine/mhavoc.c -----------*/
TIMER_DEVICE_CALLBACK( mhavoc_cpu_irq_clock );
WRITE8_HANDLER( mhavoc_alpha_irq_ack_w );
WRITE8_HANDLER( mhavoc_gamma_irq_ack_w );
MACHINE_START( mhavoc );
MACHINE_RESET( mhavoc );
DRIVER_INIT( mhavocrv );

2
src/mame/includes/model1.h
View File

@ -19,6 +19,8 @@ WRITE16_HANDLER( model1_vr_tgp_ram_w );
ADDRESS_MAP_EXTERN( model1_vr_tgp_map, 32 );
MACHINE_START( model1 );
void model1_vr_tgp_reset( running_machine *machine );
void model1_tgp_reset(running_machine *machine, int swa);

39
src/mame/machine/mhavoc.c
View File

@ -36,7 +36,7 @@ static UINT8 speech_write_buffer;
*
*************************************/
static TIMER_CALLBACK( cpu_irq_clock )
TIMER_DEVICE_CALLBACK( mhavoc_cpu_irq_clock )
{
/* clock the LS161 driving the alpha CPU IRQ */
if (alpha_irq_clock_enable)
@ -44,7 +44,7 @@ static TIMER_CALLBACK( cpu_irq_clock )
alpha_irq_clock++;
if ((alpha_irq_clock & 0x0c) == 0x0c)
{
cputag_set_input_line(machine, "alpha", 0, ASSERT_LINE);
cputag_set_input_line(timer->machine, "alpha", 0, ASSERT_LINE);
alpha_irq_clock_enable = 0;
}
}
@ -53,7 +53,7 @@ static TIMER_CALLBACK( cpu_irq_clock )
if (has_gamma_cpu)
{
gamma_irq_clock++;
cputag_set_input_line(machine, "gamma", 0, (gamma_irq_clock & 0x08) ? ASSERT_LINE : CLEAR_LINE);
cputag_set_input_line(timer->machine, "gamma", 0, (gamma_irq_clock & 0x08) ? ASSERT_LINE : CLEAR_LINE);
}
}
@ -82,6 +82,23 @@ WRITE8_HANDLER( mhavoc_gamma_irq_ack_w )
*
*************************************/
MACHINE_START( mhavoc )
{
state_save_register_item(machine, "misc", NULL, 0, alpha_data);
state_save_register_item(machine, "misc", NULL, 0, alpha_rcvd);
state_save_register_item(machine, "misc", NULL, 0, alpha_xmtd);
state_save_register_item(machine, "misc", NULL, 0, gamma_data);
state_save_register_item(machine, "misc", NULL, 0, gamma_rcvd);
state_save_register_item(machine, "misc", NULL, 0, gamma_xmtd);
state_save_register_item(machine, "misc", NULL, 0, player_1);
state_save_register_item(machine, "misc", NULL, 0, alpha_irq_clock);
state_save_register_item(machine, "misc", NULL, 0, alpha_irq_clock_enable);
state_save_register_item(machine, "misc", NULL, 0, gamma_irq_clock);
state_save_register_item(machine, "misc", NULL, 0, speech_write_buffer);
}
MACHINE_RESET( mhavoc )
{
const address_space *space = cputag_get_address_space(machine, "alpha", ADDRESS_SPACE_PROGRAM);
@ -112,22 +129,6 @@ MACHINE_RESET( mhavoc )
alpha_irq_clock = 0;
alpha_irq_clock_enable = 1;
gamma_irq_clock = 0;
/* set a timer going for the CPU interrupt generators */
timer_pulse(machine, ATTOTIME_IN_HZ(MHAVOC_CLOCK_5K), NULL, 0, cpu_irq_clock);
state_save_register_item(machine, "misc", NULL, 0, alpha_data);
state_save_register_item(machine, "misc", NULL, 0, alpha_rcvd);
state_save_register_item(machine, "misc", NULL, 0, alpha_xmtd);
state_save_register_item(machine, "misc", NULL, 0, gamma_data);
state_save_register_item(machine, "misc", NULL, 0, gamma_rcvd);
state_save_register_item(machine, "misc", NULL, 0, gamma_xmtd);
state_save_register_item(machine, "misc", NULL, 0, player_1);
state_save_register_item(machine, "misc", NULL, 0, alpha_irq_clock);
state_save_register_item(machine, "misc", NULL, 0, alpha_irq_clock_enable);
state_save_register_item(machine, "misc", NULL, 0, gamma_irq_clock);
state_save_register_item(machine, "misc", NULL, 0, speech_write_buffer);
}

43
src/mame/machine/model1.c
View File

@ -1920,27 +1920,9 @@ WRITE16_HANDLER( model1_tgp_copro_ram_w )
}
}
void model1_tgp_reset(running_machine *machine, int swa)
MACHINE_START( model1 )
{
ram_adr = 0;
ram_data = auto_alloc_array(machine, UINT32, 0x10000);
memset(ram_data, 0, 0x10000*4);
fifoout_rpos = 0;
fifoout_wpos = 0;
fifoin_rpos = 0;
fifoin_wpos = 0;
acc = 0;
mat_stack_pos = 0;
memset(cmat, 0, sizeof(cmat));
cmat[0] = 1.0;
cmat[4] = 1.0;
cmat[8] = 1.0;
model1_dump = 0;
model1_swa = swa;
next_fn();
state_save_register_global_pointer(machine, ram_data, 0x10000);
state_save_register_global(machine, ram_adr);
@ -1960,6 +1942,28 @@ void model1_tgp_reset(running_machine *machine, int swa)
state_save_register_global(machine, list_length);
}
void model1_tgp_reset(running_machine *machine, int swa)
{
ram_adr = 0;
memset(ram_data, 0, 0x10000*4);
fifoout_rpos = 0;
fifoout_wpos = 0;
fifoin_rpos = 0;
fifoin_wpos = 0;
acc = 0;
mat_stack_pos = 0;
memset(cmat, 0, sizeof(cmat));
cmat[0] = 1.0;
cmat[4] = 1.0;
cmat[8] = 1.0;
model1_dump = 0;
model1_swa = swa;
next_fn();
}
/*********************************** Virtua Racing ***********************************/
static int copro_fifoout_rpos, copro_fifoout_wpos;
@ -1972,7 +1976,6 @@ static int copro_fifoin_num;
void model1_vr_tgp_reset( running_machine *machine )
{
ram_adr = 0;
ram_data = auto_alloc_array(machine, UINT32, 0x8000);
memset(ram_data, 0, 0x8000*4);
copro_fifoout_rpos = 0;