diff --git a/src/mame/drivers/nds.cpp b/src/mame/drivers/nds.cpp index 6324c208ad3..f493813929f 100644 --- a/src/mame/drivers/nds.cpp +++ b/src/mame/drivers/nds.cpp @@ -2,7 +2,7 @@ // copyright-holders:Ryan Holtz /*************************************************************************** - ds.cpp + nds.cpp Skeleton driver for first-generation Nintendo DS. @@ -33,12 +33,19 @@ READ32_MEMBER(nds_state::arm7_io_r) case IPCSYNC_OFFSET: return m_arm7_ipcsync; + case GAMECARD_BUS_CTRL_OFFSET: + return 0xffffffff; + case POSTFLG_OFFSET: /* Bit Use * 0 0=Booting, 1=Booted (set by BIOS/firmware) */ return m_arm7_postflg; + case WRAMSTAT_OFFSET: + printf("ARM7: read WRAMSTAT mask %08x\n", mem_mask); + return m_wramcnt; + default: verboselog(*this, 0, "[ARM7] [IO] Unknown read: %08x (%08x)\n", offset*4, mem_mask); break; @@ -108,6 +115,12 @@ WRITE32_MEMBER(nds_state::arm9_io_w) m_arm9_ipcsync |= (data & ~0xf); break; + case WRAMCNT_OFFSET: + m_wramcnt = (data>>24) & 0x3; + m_arm7wrambnk->set_bank(m_wramcnt); + m_arm9wrambnk->set_bank(m_wramcnt); + break; + case POSTFLG_OFFSET: /* Bit Use * 0 0=Booting, 1=Booted (set by BIOS/firmware) @@ -130,17 +143,45 @@ WRITE32_MEMBER(nds_state::arm9_io_w) static ADDRESS_MAP_START( nds_arm7_map, AS_PROGRAM, 32, nds_state ) AM_RANGE(0x00000000, 0x00003fff) AM_ROM AM_REGION("arm7", 0) AM_RANGE(0x02000000, 0x023fffff) AM_RAM AM_MIRROR(0x00400000) AM_SHARE("mainram") - AM_RANGE(0x03800000, 0x0380ffff) AM_RAM + AM_RANGE(0x03000000, 0x03007fff) AM_DEVICE("nds7wram", address_map_bank_device, amap32) AM_MIRROR(0x007f0000) + AM_RANGE(0x03800000, 0x0380ffff) AM_RAM AM_MIRROR(0x007f0000) AM_SHARE("arm7ram") AM_RANGE(0x04000000, 0x0400ffff) AM_READWRITE(arm7_io_r, arm7_io_w) ADDRESS_MAP_END static ADDRESS_MAP_START( nds_arm9_map, AS_PROGRAM, 32, nds_state ) - AM_RANGE(0x00000000, 0x00007fff) AM_RAM // Instruction TCM AM_RANGE(0x02000000, 0x023fffff) AM_RAM AM_MIRROR(0x00400000) AM_SHARE("mainram") + AM_RANGE(0x03000000, 0x03007fff) AM_DEVICE("nds9wram", address_map_bank_device, amap32) AM_MIRROR(0x00ff0000) AM_RANGE(0x04000000, 0x0400ffff) AM_READWRITE(arm9_io_r, arm9_io_w) AM_RANGE(0xffff0000, 0xffff0fff) AM_ROM AM_MIRROR(0x1000) AM_REGION("arm9", 0) ADDRESS_MAP_END +// ARM7 views of WRAM +static ADDRESS_MAP_START( nds7_wram_map, AS_PROGRAM, 32, nds_state ) + AM_RANGE(0x00000, 0x07fff) AM_READWRITE(wram_arm7mirror_r, wram_arm7mirror_w) + AM_RANGE(0x08000, 0x0bfff) AM_READWRITE(wram_first_half_r, wram_first_half_w) + AM_RANGE(0x0c000, 0x0ffff) AM_READWRITE(wram_first_half_r, wram_first_half_w) + AM_RANGE(0x10000, 0x13fff) AM_READWRITE(wram_second_half_r, wram_second_half_w) + AM_RANGE(0x14000, 0x17fff) AM_READWRITE(wram_second_half_r, wram_second_half_w) + AM_RANGE(0x18000, 0x1ffff) AM_READWRITE(wram_first_half_r, wram_first_half_w) +ADDRESS_MAP_END + +// ARM9 views of WRAM +static ADDRESS_MAP_START( nds9_wram_map, AS_PROGRAM, 32, nds_state ) + AM_RANGE(0x00000, 0x07fff) AM_READWRITE(wram_first_half_r, wram_first_half_w) + AM_RANGE(0x08000, 0x0bfff) AM_READWRITE(wram_second_half_r, wram_second_half_w) + AM_RANGE(0x0c000, 0x0ffff) AM_READWRITE(wram_second_half_r, wram_second_half_w) + AM_RANGE(0x10000, 0x13fff) AM_READWRITE(wram_first_half_r, wram_first_half_w) + AM_RANGE(0x14000, 0x17fff) AM_READWRITE(wram_first_half_r, wram_first_half_w) + AM_RANGE(0x18000, 0x1ffff) AM_NOP AM_WRITENOP // probably actually open bus? GBATEK describes as "random" +ADDRESS_MAP_END + +READ32_MEMBER(nds_state::wram_first_half_r) { return m_WRAM[offset]; } +READ32_MEMBER(nds_state::wram_second_half_r) { return m_WRAM[offset+0x4000]; } +WRITE32_MEMBER(nds_state::wram_first_half_w) { COMBINE_DATA(&m_WRAM[offset]); } +WRITE32_MEMBER(nds_state::wram_second_half_w) { COMBINE_DATA(&m_WRAM[offset+0x4000]); } +READ32_MEMBER(nds_state::wram_arm7mirror_r) { return m_arm7ram[offset]; } +WRITE32_MEMBER(nds_state::wram_arm7mirror_w) { COMBINE_DATA(&m_arm7ram[offset]); } + static INPUT_PORTS_START( nds ) INPUT_PORTS_END @@ -149,6 +190,9 @@ void nds_state::machine_reset() { m_arm7_postflg = 0; m_arm9_postflg = 0; + m_wramcnt = 0; + m_arm7wrambnk->set_bank(0); + m_arm9wrambnk->set_bank(0); } void nds_state::machine_start() @@ -163,6 +207,18 @@ static MACHINE_CONFIG_START( nds ) MCFG_ARM_HIGH_VECTORS() MCFG_CPU_PROGRAM_MAP(nds_arm9_map) + // WRAM + MCFG_DEVICE_ADD("nds7wram", ADDRESS_MAP_BANK, 0) + MCFG_DEVICE_PROGRAM_MAP(nds7_wram_map) + MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE) + MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32) + MCFG_ADDRESS_MAP_BANK_STRIDE(0x8000) + + MCFG_DEVICE_ADD("nds9wram", ADDRESS_MAP_BANK, 0) + MCFG_DEVICE_PROGRAM_MAP(nds9_wram_map) + MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE) + MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32) + MCFG_ADDRESS_MAP_BANK_STRIDE(0x8000) MACHINE_CONFIG_END /* Help identifying the region and revisions of the set would be greatly appreciated! */ diff --git a/src/mame/includes/nds.h b/src/mame/includes/nds.h index 6d1e04a81d9..dd5dbd635e5 100644 --- a/src/mame/includes/nds.h +++ b/src/mame/includes/nds.h @@ -1,10 +1,13 @@ // license:BSD-3-Clause // copyright-holders:Ryan Holtz +#pragma once #ifndef INCLUDES_NDS_H #define INCLUDES_NDS_H #include "cpu/arm7/arm7.h" #include "cpu/arm7/arm7core.h" +#include "machine/bankdev.h" +#include "machine/timer.h" class nds_state : public driver_device { @@ -13,7 +16,10 @@ public: : driver_device(mconfig, type, tag), m_arm7(*this, "arm7"), m_arm9(*this, "arm9"), - m_firmware(*this, "firmware") + m_firmware(*this, "firmware"), + m_arm7wrambnk(*this, "nds7wram"), + m_arm9wrambnk(*this, "nds9wram"), + m_arm7ram(*this, "arm7ram") { } void machine_start() override; @@ -27,14 +33,25 @@ public: DECLARE_READ32_MEMBER(arm9_io_r); DECLARE_WRITE32_MEMBER(arm9_io_w); + DECLARE_READ32_MEMBER(wram_first_half_r); + DECLARE_READ32_MEMBER(wram_second_half_r); + DECLARE_WRITE32_MEMBER(wram_first_half_w); + DECLARE_WRITE32_MEMBER(wram_second_half_w); + DECLARE_READ32_MEMBER(wram_arm7mirror_r); + DECLARE_WRITE32_MEMBER(wram_arm7mirror_w); + protected: required_device m_arm7; required_device m_arm9; - required_region_ptr m_firmware; + required_device m_arm7wrambnk, m_arm9wrambnk; + required_shared_ptr m_arm7ram; enum { IPCSYNC_OFFSET = 0x180/4, + GAMECARD_BUS_CTRL_OFFSET = 0x1a4/4, + WRAMSTAT_OFFSET = 0x241/4, + WRAMCNT_OFFSET = 0x247/4, POSTFLG_OFFSET = 0x300/4, POSTFLG_PBF_SHIFT = 0, POSTFLG_RAM_SHIFT = 1, @@ -45,6 +62,8 @@ protected: uint32_t m_arm7_postflg; uint32_t m_arm9_postflg; uint16_t m_arm7_ipcsync, m_arm9_ipcsync; + uint8_t m_WRAM[0x8000]; + uint8_t m_wramcnt; }; #endif // INCLUDES_NDS_H