mirror of
https://github.com/holub/mame
synced 2025-04-19 15:11:37 +03:00
-bus/a2bus: Added //SHH SYSTEME LANceGS Card. (#8264)
-machine/smc91c9x.cpp adjustments: * Reset should disable promiscuous mode. * RCR - handle promiscuous changes, adjust soft reset handling. * EPH_STATUS should be LINK_OK by default (previous code wouldn't set LINK_OK unless RX_EN is set but LANceGS won't set RX_EN unless LINK_OK is set). * B0_BANK bits 4-8 are unspecified in the documentation but LANceGS expects a 3 (used in Card detection logic). * MIR values depend on device type and resets when the mmu resets. * Reading/writing the data register needs to be aware of 8-bit I/O. * Calculate FCS. * Removed WMS OUI filtering hack.
This commit is contained in:
ksherlock
GitHub
parent
6ffc98289c
commit
a9fefd8363
@ -2460,6 +2460,8 @@ if (BUSES["A2BUS"]~=null) then
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MAME_DIR .. "src/devices/bus/a2bus/ezcgi.h",
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MAME_DIR .. "src/devices/bus/a2bus/grappler.cpp",
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MAME_DIR .. "src/devices/bus/a2bus/grappler.h",
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MAME_DIR .. "src/devices/bus/a2bus/lancegs.cpp",
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MAME_DIR .. "src/devices/bus/a2bus/lancegs.h",
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MAME_DIR .. "src/devices/bus/a2bus/laser128.cpp",
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MAME_DIR .. "src/devices/bus/a2bus/laser128.h",
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MAME_DIR .. "src/devices/bus/a2bus/mouse.cpp",
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178
src/devices/bus/a2bus/lancegs.cpp
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178
src/devices/bus/a2bus/lancegs.cpp
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@ -0,0 +1,178 @@
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// license:BSD-3-Clause
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// copyright-holders:Kelvin Sherlock
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/*********************************************************************
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lancegs.cpp
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Apple II LANceGS Card
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Kelvin Sherlock with assistance from Geoff Weiss
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SMSC LAN 91c96 and 24c04 EEPROM
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Bit 1 of C0nF switches between EEPROM (1) and Ethernet (0, default).
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This bit is write only.
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In EEPROM Mode:
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C0n4 - Clock Low
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C0n5 - Clock High
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C0n6 - Data Low
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C0n7 - Data High
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C0n8 - Read Data
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C0nF - toggle EEPROM/Ethernet
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Known EEPROM locations. All strings high ascii, 0-terminated.
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0x00: Identification string ("LANceGS Ethernet Card (c) 2000 Joachim Lange")
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0x30: Revision string
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0x40: Revision Code (1 byte)
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0x48: Production date, yy m d (4 bytes)
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0x4c: Service date, yy m d (4 bytes)
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0x50: Serial Number (2 bytes)
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0x60: MAC Address (6 bytes)
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0x66: Destination Mac Address (6 bytes) *
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0x80: IP Address (4 bytes) *
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0x84: Destination IP Address (4 bytes) *
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0x88: Netmask (4 bytes) *
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0x8c: Gateway (4 bytes) *
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* configurable with included software.
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*********************************************************************/
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#include "emu.h"
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#include "lancegs.h"
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/***************************************************************************
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PARAMETERS
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***************************************************************************/
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//**************************************************************************
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// GLOBAL VARIABLES
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//**************************************************************************
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DEFINE_DEVICE_TYPE(A2BUS_LANCEGS, a2bus_lancegs_device, "a2lancegs", "///SHH Systeme LANceGS")
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//**************************************************************************
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// LIVE DEVICE
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//**************************************************************************
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a2bus_lancegs_device::a2bus_lancegs_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
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a2bus_lancegs_device(mconfig, A2BUS_LANCEGS, tag, owner, clock)
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{
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}
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a2bus_lancegs_device::a2bus_lancegs_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock) :
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device_t(mconfig, type, tag, owner, clock),
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device_a2bus_card_interface(mconfig, *this),
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m_netinf(*this, "smc91c96"),
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m_i2cmem(*this, "i2cmem"),
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m_shadow(false)
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{
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}
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void a2bus_lancegs_device::device_add_mconfig(machine_config &config)
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{
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SMC91C96(config, m_netinf, 20_MHz_XTAL); // Datasheet fig 12.26, pg 122.
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I2C_24C04(config, m_i2cmem, 0).set_address(0x80).set_e0(1);
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m_netinf->irq_handler().set(FUNC(a2bus_lancegs_device::netinf_irq_w));
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}
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//-------------------------------------------------
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// device_start - device-specific startup
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//-------------------------------------------------
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void a2bus_lancegs_device::device_start()
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{
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save_item(NAME(m_shadow));
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}
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void a2bus_lancegs_device::device_reset()
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{
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m_shadow = false;
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}
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/*-------------------------------------------------
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read_c0nx - called for reads from this card's c0nx space
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-------------------------------------------------*/
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uint8_t a2bus_lancegs_device::read_c0nx(uint8_t offset)
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{
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if (m_shadow) {
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switch(offset) {
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case 0x08: /* read data */
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return 0xfe | m_i2cmem->read_sda();
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break;
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case 0x0f:
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return 0x33;
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break;
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default:
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return 0xff;
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break;
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}
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} else {
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const uint16_t mask = offset & 0x01 ? 0xff00: 0x00ff;
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const uint16_t value = m_netinf->read(offset >> 1, mask);
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return offset & 0x01 ? value >> 8 : value;
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}
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}
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/*-------------------------------------------------
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write_c0nx - called for writes to this card's c0nx space
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-------------------------------------------------*/
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void a2bus_lancegs_device::write_c0nx(uint8_t offset, uint8_t data)
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{
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if (offset == 0x0f) {
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m_shadow = data & 0x01;
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return;
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}
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if (m_shadow) {
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switch(offset) {
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case 0x04: /* set clock low */
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m_i2cmem->write_scl(0);
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break;
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case 0x05: /* set clock high */
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m_i2cmem->write_scl(1);
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break;
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case 0x06: /* set data low */
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m_i2cmem->write_sda(0);
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break;
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case 0x07: /* set data high */
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m_i2cmem->write_sda(1);
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break;
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default:
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break;
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}
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} else {
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const uint16_t mask = offset & 0x01 ? 0xff00: 0x00ff;
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const uint16_t value = offset & 0x01 ? data << 8 : data;
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m_netinf->write(offset >> 1, value, mask);
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}
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}
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WRITE_LINE_MEMBER( a2bus_lancegs_device::netinf_irq_w )
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{
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if (state) {
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raise_slot_irq();
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} else {
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lower_slot_irq();
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}
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}
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ROM_START(lancegs)
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ROM_REGION(0x0200, "i2cmem", 0)
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ROM_LOAD("lancegs.nv", 0x0000, 0x0200, NO_DUMP)
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ROM_END
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const tiny_rom_entry *a2bus_lancegs_device::device_rom_region() const
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{
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return ROM_NAME(lancegs);
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}
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52
src/devices/bus/a2bus/lancegs.h
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52
src/devices/bus/a2bus/lancegs.h
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@ -0,0 +1,52 @@
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// license:BSD-3-Clause
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// copyright-holders:Kelvin Sherlock
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/*********************************************************************
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lancegs.h
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Apple II LANceGS Card
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*********************************************************************/
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#ifndef MAME_BUS_A2BUS_LANCEGS_H
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#define MAME_BUS_A2BUS_LANCEGS_H
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#include "a2bus.h"
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#include "machine/smc91c9x.h"
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#include "machine/i2cmem.h"
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//**************************************************************************
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// TYPE DEFINITIONS
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//**************************************************************************
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class a2bus_lancegs_device:
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public device_t,
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public device_a2bus_card_interface
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{
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public:
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// construction/destruction
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a2bus_lancegs_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
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protected:
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a2bus_lancegs_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
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virtual void device_add_mconfig(machine_config &config) override;
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virtual const tiny_rom_entry *device_rom_region() const override;
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virtual void device_start() override;
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virtual void device_reset() override;
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virtual uint8_t read_c0nx(uint8_t offset) override;
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virtual void write_c0nx(uint8_t offset, uint8_t data) override;
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private:
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required_device<smc91c96_device> m_netinf;
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required_device<i2c_24c04_device> m_i2cmem;
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bool m_shadow;
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DECLARE_WRITE_LINE_MEMBER( netinf_irq_w );
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};
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// device type definition
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DECLARE_DEVICE_TYPE(A2BUS_LANCEGS, a2bus_lancegs_device)
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#endif // MAME_BUS_A2BUS_LANCEGS_H
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@ -71,7 +71,6 @@ smc91c9x_device::smc91c9x_device(const machine_config &mconfig, device_type type
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}
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const u8 smc91c9x_device::ETH_BROADCAST[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
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const u8 smc91c9x_device::WMS_OUI[] = { 0x00, 0xA0, 0xAF };
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//-------------------------------------------------
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// device_start - device-specific startup
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@ -95,12 +94,19 @@ void smc91c9x_device::device_start()
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m_reg[B1_IA2_3] = 0x0000; m_regmask[B1_IA2_3] = 0xffff;
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m_reg[B1_IA4_5] = 0x0000; m_regmask[B1_IA4_5] = 0xffff;
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// Revision is set based on chip type
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// Revision and MIR is based on chip type
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m_regmask[B3_REVISION] = 0x0000;
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m_regmask[B0_MIR] = 0x0000;
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if (m_device_type == dev_type::SMC91C94)
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{
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m_reg[B3_REVISION] = 0x3345;
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m_reg[B0_MIR] = 0x1212;
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}
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else if (m_device_type == dev_type::SMC91C96)
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{
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m_reg[B3_REVISION] = 0x3346;
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m_reg[B0_MIR] = 0x1818;
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}
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else
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fatalerror("device_start: Unknown device type\n");
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@ -148,12 +154,11 @@ void smc91c9x_device::device_reset()
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m_tx_retry_count = 0;
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m_reg[B0_TCR] = 0x0000; m_regmask[B0_TCR] = 0x3d87;
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m_reg[B0_EPH_STATUS] = 0x0000; m_regmask[B0_EPH_STATUS] = 0x0000;
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m_reg[B0_EPH_STATUS] = 0x4000; m_regmask[B0_EPH_STATUS] = 0x0000;
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m_reg[B0_RCR] = 0x0000; m_regmask[B0_RCR] = 0xc307;
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m_reg[B0_COUNTER] = 0x0000; m_regmask[B0_COUNTER] = 0x0000;
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m_reg[B0_MIR] = 0x1212; m_regmask[B0_MIR] = 0x0000;
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m_reg[B0_MCR] = 0x3300; m_regmask[B0_MCR] = 0x00ff;
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m_reg[B0_BANK] = 0x3300; m_regmask[B0_BANK] = 0x0007;
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m_reg[B0_BANK] = 0x3330; m_regmask[B0_BANK] = 0x0007;
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m_reg[B1_GENERAL_PURP] = 0x0000; m_regmask[B1_GENERAL_PURP] = 0xffff;
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m_reg[B1_CONTROL] = 0x0100; m_regmask[B1_CONTROL] = 0x68e7;
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@ -174,6 +179,8 @@ void smc91c9x_device::device_reset()
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m_reg[B3_ERCV] = 0x331f; m_regmask[B3_ERCV] = 0x009f;
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set_promisc(false);
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update_ethernet_irq();
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// Reset MMU
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@ -186,6 +193,10 @@ void smc91c9x_device::mmu_reset()
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m_alloc_rx = 0;
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m_alloc_tx = 0;
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// The register defaults to the MEMORY SIZE upon reset or upon the RESET MMU command.
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m_reg[B0_MIR] &= 0xff;
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m_reg[B0_MIR] |= m_reg[B0_MIR] << 8;
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// Reset fifos.
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reset_tx_fifos();
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reset_completed_rx();
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@ -394,14 +405,6 @@ int smc91c9x_device::recv_start_cb(u8 *buf, int length)
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return 0;
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}
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// discard packets not from WMS
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if (memcmp(WMS_OUI, &buf[6], 3))
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{
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LOGMASKED(LOG_RX, "received non-WMS packet OUI: %02x:%02x:%02x length %d discarded\n", buf[6], buf[7], buf[8], length);
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return 0;
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}
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// Check for active transmission
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if (m_tx_active)
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{
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@ -557,13 +560,14 @@ TIMER_CALLBACK_MEMBER(smc91c9x_device::tx_poll)
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tx_buffer[length++] = 0x00;
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// Add CRC
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// TODO: Calculate CRC
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if (1 && ((control & EBUF_CRC) || !(m_reg[B0_TCR] & NOCRC)))
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if (((control & EBUF_CRC) || !(m_reg[B0_TCR] & NOCRC)))
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{
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tx_buffer[length++] = 0x11;
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tx_buffer[length++] = 0x22;
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tx_buffer[length++] = 0x33;
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tx_buffer[length++] = 0x44;
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u32 crc = util::crc32_creator::simple(tx_buffer + 4, length - 4);
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tx_buffer[length++] = (crc >> 0) & 0xff;
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tx_buffer[length++] = (crc >> 8) & 0xff;
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tx_buffer[length++] = (crc >> 16) & 0xff;
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tx_buffer[length++] = (crc >> 24) & 0xff;
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}
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// Remove status, length
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@ -590,7 +594,7 @@ TIMER_CALLBACK_MEMBER(smc91c9x_device::tx_poll)
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if (m_reg[B0_TCR] & (EPH_LOOP | LOOP))
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send_complete_cb(length);
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else
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send(&tx_buffer[4], length);
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send(&tx_buffer[4], length, 4);
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}
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}
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@ -841,7 +845,9 @@ u16 smc91c9x_device::read(offs_t offset, u16 mem_mask)
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else
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buffer = &m_buffer[(m_reg[B2_PNR_ARR] & 0x1f) * ETHER_BUFFER_SIZE];
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result = buffer[addr++];
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result = 0;
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if ( ACCESSING_BITS_0_7 )
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result = buffer[addr++];
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if ( ACCESSING_BITS_8_15 )
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result |= buffer[addr++] << 8;
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if ( m_reg[B2_POINTER] & 0x4000 )
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@ -872,8 +878,10 @@ void smc91c9x_device::write(offs_t offset, u16 data, u16 mem_mask)
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if (offset != B0_BANK && offset < sizeof(m_reg))
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LOG("%s:smc91c9x_w(%s) = [%04X]<-%04X & (%04X & %04X)\n", machine().describe_context(), ethernet_regname[offset], offset, data, mem_mask , m_regmask[offset]);
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const uint16_t old_reg = m_reg[offset];
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mem_mask &= m_regmask[offset];
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COMBINE_DATA(&m_reg[offset]);
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const uint16_t new_reg = m_reg[offset];
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/* handle it */
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switch (offset)
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@ -911,7 +919,7 @@ void smc91c9x_device::write(offs_t offset, u16 data, u16 mem_mask)
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reset();
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}
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if ( !(data & RXEN) )
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if ( (old_reg & RXEN) && !(new_reg & RXEN))
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{
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reset_completed_rx();
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}
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@ -921,6 +929,11 @@ void smc91c9x_device::write(offs_t offset, u16 data, u16 mem_mask)
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m_reg[B0_EPH_STATUS] |= LINK_OK;
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}
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if ((old_reg ^ new_reg) & PRMS)
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{
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set_promisc(new_reg & PRMS);
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}
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if (VERBOSE & LOG_GENERAL)
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{
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if (data & SOFT_RST) LOG(" SOFT RST\n");
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@ -951,14 +964,16 @@ void smc91c9x_device::write(offs_t offset, u16 data, u16 mem_mask)
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break;
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case B1_IA4_5:
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set_promisc(m_reg[B0_RCR] & PRMS);
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set_mac((char *)&m_reg[B1_IA0_1]);
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if ( ACCESSING_BITS_8_15 )
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{
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set_promisc(m_reg[B0_RCR] & PRMS);
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set_mac((char *)&m_reg[B1_IA0_1]);
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}
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break;
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case B1_CONTROL: /* control register */
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// Clearing LE_EN clears interrupt from LINK_OK status change
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if (!(data & LE_ENABLE))
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if ( (old_reg & LE_ENABLE) && !(new_reg & LE_ENABLE))
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{
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m_reg[B2_INTERRUPT] &= ~EINT_EPH;
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update_ethernet_irq();
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@ -1002,7 +1017,8 @@ void smc91c9x_device::write(offs_t offset, u16 data, u16 mem_mask)
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else
|
||||
buffer = &m_buffer[(m_reg[B2_PNR_ARR] & 0x1f) * ETHER_BUFFER_SIZE];
|
||||
|
||||
buffer[addr++] = data;
|
||||
if ( ACCESSING_BITS_0_7 )
|
||||
buffer[addr++] = data;
|
||||
if ( ACCESSING_BITS_8_15 )
|
||||
buffer[addr++] = data >> 8;
|
||||
if ( m_reg[B2_POINTER] & AUTO_INCR)
|
||||
|
||||
@ -215,9 +215,9 @@ private:
|
||||
PTR = 0x07ff
|
||||
};
|
||||
|
||||
static constexpr u32 FCS_RESIDUE = 0xdebb20e3;
|
||||
static constexpr unsigned ETHER_BUFFER_SIZE = 256 * 6;
|
||||
static const u8 ETH_BROADCAST[];
|
||||
static const u8 WMS_OUI[];
|
||||
|
||||
// mmu
|
||||
|
||||
|
||||
@ -175,6 +175,7 @@ MIG RAM page 2 $CE02 is the speaker/slot bitfield and $CE03 is the paddle/accele
|
||||
#include "bus/a2bus/ccs7710.h"
|
||||
#include "bus/a2bus/ezcgi.h"
|
||||
#include "bus/a2bus/grappler.h"
|
||||
#include "bus/a2bus/lancegs.h"
|
||||
#include "bus/a2bus/laser128.h"
|
||||
#include "bus/a2bus/mouse.h"
|
||||
#include "bus/a2bus/pc_xporter.h"
|
||||
@ -4700,6 +4701,7 @@ static void apple2_cards(device_slot_interface &device)
|
||||
device.option_add("uniprint", A2BUS_UNIPRINT); /* Videx Uniprint parallel printer card */
|
||||
device.option_add("ccs7710", A2BUS_CCS7710); /* California Computer Systems Model 7710 Asynchronous Serial Interface */
|
||||
device.option_add("booti", A2BUS_BOOTI); /* Booti Card */
|
||||
device.option_add("lancegs", A2BUS_LANCEGS); /* ///SHH SYSTEME LANceGS Card */
|
||||
}
|
||||
|
||||
static void apple2eaux_cards(device_slot_interface &device)
|
||||
|
||||
@ -115,6 +115,7 @@
|
||||
#include "bus/a2bus/ezcgi.h"
|
||||
#include "bus/a2bus/grappler.h"
|
||||
//#include "bus/a2bus/hostram.h"
|
||||
#include "bus/a2bus/lancegs.h"
|
||||
#include "bus/a2bus/laser128.h"
|
||||
#include "bus/a2bus/mouse.h"
|
||||
//#include "bus/a2bus/pc_xporter.h"
|
||||
@ -4788,6 +4789,7 @@ static void apple2_cards(device_slot_interface &device)
|
||||
device.option_add("uniprint", A2BUS_UNIPRINT); /* Videx Uniprint parallel printer card */
|
||||
device.option_add("ccs7710", A2BUS_CCS7710); /* California Computer Systems Model 7710 Asynchronous Serial Interface */
|
||||
device.option_add("booti", A2BUS_BOOTI); /* Booti Card */
|
||||
device.option_add("lancegs", A2BUS_LANCEGS); /* ///SHH SYSTEME LANceGS Card */
|
||||
}
|
||||
|
||||
void apple2gs_state::apple2gs(machine_config &config)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user