From aa2b3bb471da33934e57143a441aae2e953b9592 Mon Sep 17 00:00:00 2001 From: Fabio Priuli Date: Tue, 5 Mar 2013 12:01:47 +0000 Subject: [PATCH] srccleaned + minor fixes. nw. --- src/mess/drivers/snes.c | 497 +++++++++++++++++---------------- src/mess/machine/snescart.c | 1 - src/mess/machine/sns_bsx.c | 79 +++--- src/mess/machine/sns_bsx.h | 66 ++--- src/mess/machine/sns_rom.c | 55 ++-- src/mess/machine/sns_rom.h | 18 +- src/mess/machine/sns_rom21.c | 53 ++-- src/mess/machine/sns_rom21.h | 12 +- src/mess/machine/sns_sdd1.c | 92 +++--- src/mess/machine/sns_sdd1.h | 48 ++-- src/mess/machine/sns_sfx.c | 27 +- src/mess/machine/sns_sfx.h | 12 +- src/mess/machine/sns_slot.c | 192 ++++++------- src/mess/machine/sns_slot.h | 24 +- src/mess/machine/sns_spc7110.c | 333 +++++++++++----------- src/mess/machine/sns_spc7110.h | 64 ++--- src/mess/machine/sns_sufami.c | 30 +- src/mess/machine/sns_sufami.h | 16 +- src/mess/machine/sns_upd.c | 24 +- src/mess/machine/sns_upd.h | 28 +- 20 files changed, 845 insertions(+), 826 deletions(-) diff --git a/src/mess/drivers/snes.c b/src/mess/drivers/snes.c index 5ab132beef1..4005e69a5c7 100644 --- a/src/mess/drivers/snes.c +++ b/src/mess/drivers/snes.c @@ -73,7 +73,7 @@ UINT8 st010_read_ram(snes_state *state, UINT16 addr) { UINT16 temp = state->m_upd96050->dataram_r(addr/2); UINT8 res; - + if (addr & 1) { res = temp>>8; @@ -82,14 +82,14 @@ UINT8 st010_read_ram(snes_state *state, UINT16 addr) { res = temp & 0xff; } - + return res; } void st010_write_ram(snes_state *state, UINT16 addr, UINT8 data) { UINT16 temp = state->m_upd96050->dataram_r(addr/2); - + if (addr & 1) { temp &= 0xff; @@ -100,7 +100,7 @@ void st010_write_ram(snes_state *state, UINT16 addr, UINT8 data) temp &= 0xff00; temp |= data; } - + state->m_upd96050->dataram_w(addr/2, temp); } @@ -111,10 +111,10 @@ static READ8_HANDLER( snes_lo_r ) UINT16 address = offset & 0xffff; // take care of add-on chip access - if (state->m_has_addon_chip == HAS_OBC1 + if (state->m_has_addon_chip == HAS_OBC1 && (offset < 0x400000 && address >= 0x6000 && address < 0x8000)) return obc1_read(space, offset, mem_mask); - if (state->m_has_addon_chip == HAS_CX4 + if (state->m_has_addon_chip == HAS_CX4 && (offset < 0x400000 && address >= 0x6000 && address < 0x8000)) return CX4_read(address - 0x6000); if (state->m_has_addon_chip == HAS_RTC @@ -127,7 +127,7 @@ static READ8_HANDLER( snes_lo_r ) if (offset == 0x600000 || offset == 0x600001) return (offset & 1) ? st010_get_sr() : st010_get_dr(); } - if (state->m_cart[0].mode == SNES_MODE_21 && state->m_has_addon_chip == HAS_DSP1 + if (state->m_cart[0].mode == SNES_MODE_21 && state->m_has_addon_chip == HAS_DSP1 && (offset < 0x200000 && address >= 0x6000 && address < 0x8000)) return (address < 0x7000) ? dsp_get_dr() : dsp_get_sr(); if (state->m_cart[0].mode == SNES_MODE_20 && state->m_has_addon_chip == HAS_DSP1) @@ -136,11 +136,11 @@ static READ8_HANDLER( snes_lo_r ) return (address < 0xc000) ? dsp_get_dr() : dsp_get_sr(); if (offset >= 0x600000 && offset < 0x700000 && (offset & 0x8000) == 0x0000) return (address < 0x4000) ? dsp_get_dr() : dsp_get_sr(); - } + } if ((state->m_has_addon_chip == HAS_DSP2 || state->m_has_addon_chip == HAS_DSP3) && (offset >= 0x200000 && offset < 0x400000 && (offset & 0x8000) == 0x8000)) return (address < 0xc000) ? dsp_get_dr() : dsp_get_sr(); - if (state->m_has_addon_chip == HAS_DSP4 + if (state->m_has_addon_chip == HAS_DSP4 && (offset >= 0x300000 && offset < 0x400000 && (offset & 0x8000) == 0x8000)) return (address < 0xc000) ? dsp_get_dr() : dsp_get_sr(); if (state->m_has_addon_chip == HAS_SDD1 @@ -148,7 +148,7 @@ static READ8_HANDLER( snes_lo_r ) return sdd1_mmio_read(space, (UINT32)address); if ((state->m_has_addon_chip == HAS_SPC7110 || state->m_has_addon_chip == HAS_SPC7110_RTC) && offset < 0x400000) - { + { UINT16 limit = (state->m_has_addon_chip == HAS_SPC7110_RTC) ? 0x4842 : 0x483f; if (address >= 0x4800 && address <= limit) return spc7110_mmio_read(space, (UINT32)address); @@ -162,10 +162,10 @@ static READ8_HANDLER( snes_lo_r ) return spc7110_mmio_read(space, 0x4800); if (state->m_has_addon_chip == HAS_SUPERFX && state->m_superfx != NULL && offset < 0x400000) - { + { if (address >= 0x3000 && address < 0x3300) return superfx_mmio_read(state->m_superfx, address); - if (address >= 0x6000 && address < 0x8000) // here it should be snes_ram[0xe00000+...] but there are mirroring issues + if (address >= 0x6000 && address < 0x8000) // here it should be snes_ram[0xe00000+...] but there are mirroring issues return superfx_access_ram(state->m_superfx) ? snes_ram[0xf00000 + (offset & 0x1fff)] : snes_open_bus_r(space, 0); } if (state->m_has_addon_chip == HAS_SUPERFX && state->m_superfx != NULL @@ -185,7 +185,7 @@ static READ8_HANDLER( snes_lo_r ) if (state->m_has_addon_chip == HAS_SUPERFX && state->m_superfx != NULL && offset >= 0x600000) return superfx_access_ram(state->m_superfx) ? snes_ram[0x800000 + offset] : snes_open_bus_r(space, 0); - + // base cart access if (offset < 0x300000) return snes_r_bank1(space, offset, 0xff); @@ -197,18 +197,18 @@ static READ8_HANDLER( snes_lo_r ) return snes_r_bank4(space, offset - 0x600000, 0xff); else return snes_r_bank5(space, offset - 0x700000, 0xff); -} +} static READ8_HANDLER( snes_hi_r ) { snes_state *state = space.machine().driver_data(); UINT16 address = offset & 0xffff; - + // take care of add-on chip access - if (state->m_has_addon_chip == HAS_OBC1 + if (state->m_has_addon_chip == HAS_OBC1 && (offset < 0x400000 && address >= 0x6000 && address < 0x8000)) return obc1_read(space, offset, mem_mask); - if (state->m_has_addon_chip == HAS_CX4 + if (state->m_has_addon_chip == HAS_CX4 && (offset < 0x400000 && address >= 0x6000 && address < 0x8000)) return CX4_read(address - 0x6000); if (state->m_has_addon_chip == HAS_RTC @@ -221,7 +221,7 @@ static READ8_HANDLER( snes_hi_r ) if (offset == 0x600000 || offset == 0x600001) return (offset & 1) ? st010_get_sr() : st010_get_dr(); } - if (state->m_cart[0].mode == SNES_MODE_21 && state->m_has_addon_chip == HAS_DSP1 + if (state->m_cart[0].mode == SNES_MODE_21 && state->m_has_addon_chip == HAS_DSP1 && (offset < 0x200000 && address >= 0x6000 && address < 0x8000)) return (address < 0x7000) ? dsp_get_dr() : dsp_get_sr(); if (state->m_cart[0].mode == SNES_MODE_20 && state->m_has_addon_chip == HAS_DSP1) @@ -234,7 +234,7 @@ static READ8_HANDLER( snes_hi_r ) if ((state->m_has_addon_chip == HAS_DSP2 || state->m_has_addon_chip == HAS_DSP3) && (offset >= 0x200000 && offset < 0x400000 && (offset & 0x8000) == 0x8000)) return (address < 0xc000) ? dsp_get_dr() : dsp_get_sr(); - if (state->m_has_addon_chip == HAS_DSP4 + if (state->m_has_addon_chip == HAS_DSP4 && (offset >= 0x300000 && offset < 0x400000 && (offset & 0x8000) == 0x8000)) return (address < 0xc000) ? dsp_get_dr() : dsp_get_sr(); if (state->m_has_addon_chip == HAS_SDD1 @@ -244,7 +244,7 @@ static READ8_HANDLER( snes_hi_r ) return sdd1_read(space.machine(), offset - 0x400000); if ((state->m_has_addon_chip == HAS_SPC7110 || state->m_has_addon_chip == HAS_SPC7110_RTC) && offset < 0x400000) - { + { UINT16 limit = (state->m_has_addon_chip == HAS_SPC7110_RTC) ? 0x4842 : 0x483f; if (address >= 0x4800 && address <= limit) return spc7110_mmio_read(space, (UINT32)address); @@ -253,68 +253,68 @@ static READ8_HANDLER( snes_hi_r ) if (offset >= 0x300000 && offset < 0x310000 && address >= 0x6000 && address < 0x8000) return snes_ram[0x306000 + (address & 0x1fff)]; } - if ((state->m_has_addon_chip == HAS_SPC7110 || state->m_has_addon_chip == HAS_SPC7110_RTC) + if ((state->m_has_addon_chip == HAS_SPC7110 || state->m_has_addon_chip == HAS_SPC7110_RTC) && offset >= 0x500000) return spc7110_bank7_read(space, offset - 0x400000); if (state->m_has_addon_chip == HAS_SUPERFX && state->m_superfx != NULL) - return space.read_byte(offset); // [80-ff] same as [00-7f] - + return space.read_byte(offset); // [80-ff] same as [00-7f] + // base cart access if (offset < 0x400000) return snes_r_bank6(space, offset, 0xff); else return snes_r_bank7(space, offset - 0x400000, 0xff); -} +} static WRITE8_HANDLER( snes_lo_w ) { snes_state *state = space.machine().driver_data(); UINT16 address = offset & 0xffff; - + // take care of add-on chip access - if (state->m_has_addon_chip == HAS_OBC1 + if (state->m_has_addon_chip == HAS_OBC1 && (offset < 0x400000 && address >= 0x6000 && address < 0x8000)) - { obc1_write(space, offset, data, mem_mask); return; } - if (state->m_has_addon_chip == HAS_CX4 + { obc1_write(space, offset, data, mem_mask); return; } + if (state->m_has_addon_chip == HAS_CX4 && (offset < 0x400000 && address >= 0x6000 && address < 0x8000)) - { CX4_write(space.machine(), address - 0x6000, data); return; } + { CX4_write(space.machine(), address - 0x6000, data); return; } if (state->m_has_addon_chip == HAS_RTC && (offset < 0x400000 && (address == 0x2800 || address == 0x2801))) - { srtc_write(space.machine(), offset, data); return; } + { srtc_write(space.machine(), offset, data); return; } if (state->m_has_addon_chip == HAS_ST010 || state->m_has_addon_chip == HAS_ST011) { if (offset >= 0x680000 && offset < 0x700000 && address < 0x1000) - { st010_write_ram(state, address, data); return; } + { st010_write_ram(state, address, data); return; } if (offset == 0x600000) - { st010_set_dr(data); return; } + { st010_set_dr(data); return; } if (offset == 0x600001) - { st010_set_sr(data); return; } + { st010_set_sr(data); return; } } - if (state->m_cart[0].mode == SNES_MODE_21 && state->m_has_addon_chip == HAS_DSP1 + if (state->m_cart[0].mode == SNES_MODE_21 && state->m_has_addon_chip == HAS_DSP1 && (offset < 0x200000 && address >= 0x6000 && address < 0x8000)) - { dsp_set_dr(data); return; } + { dsp_set_dr(data); return; } if (state->m_cart[0].mode == SNES_MODE_20 && state->m_has_addon_chip == HAS_DSP1) { if (offset >= 0x200000 && offset < 0x400000 && (offset & 0x8000) == 0x8000) - { dsp_set_dr(data); return; } + { dsp_set_dr(data); return; } if (offset >= 0x600000 && offset < 0x700000 && (offset & 0x8000) == 0x0000) - { dsp_set_dr(data); return; } + { dsp_set_dr(data); return; } } if ((state->m_has_addon_chip == HAS_DSP2 || state->m_has_addon_chip == HAS_DSP3) && (offset >= 0x200000 && offset < 0x400000 && (offset & 0x8000) == 0x8000)) { if (address < 0xc000) - { dsp_set_dr(data); return; } + { dsp_set_dr(data); return; } else - { dsp_set_sr(data); return; } + { dsp_set_sr(data); return; } } - if (state->m_has_addon_chip == HAS_DSP4 + if (state->m_has_addon_chip == HAS_DSP4 && (offset >= 0x300000 && offset < 0x400000 && (offset & 0x8000) == 0x8000)) { if (address < 0xc000) - { dsp_set_dr(data); return; } + { dsp_set_dr(data); return; } else - { dsp_set_sr(data); return; } + { dsp_set_sr(data); return; } } if (state->m_has_addon_chip == HAS_SDD1 && offset < 0x400000) { @@ -325,27 +325,27 @@ static WRITE8_HANDLER( snes_lo_w ) } } if ((state->m_has_addon_chip == HAS_SPC7110 || state->m_has_addon_chip == HAS_SPC7110_RTC) && offset < 0x400000) - { + { UINT16 limit = (state->m_has_addon_chip == HAS_SPC7110_RTC) ? 0x4842 : 0x483f; if (address >= 0x4800 && address <= limit) - { spc7110_mmio_write(space.machine(), (UINT32)address, data); return; } + { spc7110_mmio_write(space.machine(), (UINT32)address, data); return; } if (offset < 0x10000 && address >= 0x6000 && address < 0x8000) - { snes_ram[0x306000 + (address & 0x1fff)] = data; return; } + { snes_ram[0x306000 + (address & 0x1fff)] = data; return; } if (offset >= 0x300000 && offset < 0x310000 && address >= 0x6000 && address < 0x8000) - { snes_ram[0x306000 + (address & 0x1fff)] = data; return; } + { snes_ram[0x306000 + (address & 0x1fff)] = data; return; } } if (state->m_has_addon_chip == HAS_SUPERFX && state->m_superfx != NULL - && offset < 0x400000) - { + && offset < 0x400000) + { if (address >= 0x3000 && address < 0x3300) - { superfx_mmio_write(state->m_superfx, address, data); return; } - if (address >= 0x6000 && address < 0x8000) // here it should be snes_ram[0xe00000+...] but there are mirroring issues - { snes_ram[0xf00000 + (offset & 0x1fff)] = data; return; } + { superfx_mmio_write(state->m_superfx, address, data); return; } + if (address >= 0x6000 && address < 0x8000) // here it should be snes_ram[0xe00000+...] but there are mirroring issues + { snes_ram[0xf00000 + (offset & 0x1fff)] = data; return; } } if (state->m_has_addon_chip == HAS_SUPERFX && state->m_superfx != NULL && offset >= 0x600000) - { snes_ram[0x800000 + offset] = data; return; } - + { snes_ram[0x800000 + offset] = data; return; } + // base cart access if (offset < 0x300000) snes_w_bank1(space, offset, data, 0xff); @@ -357,57 +357,57 @@ static WRITE8_HANDLER( snes_lo_w ) snes_w_bank4(space, offset - 0x600000, data, 0xff); else snes_w_bank5(space, offset - 0x700000, data, 0xff); -} +} static WRITE8_HANDLER( snes_hi_w ) { snes_state *state = space.machine().driver_data(); UINT16 address = offset & 0xffff; - + // take care of add-on chip access - if (state->m_has_addon_chip == HAS_OBC1 + if (state->m_has_addon_chip == HAS_OBC1 && (offset < 0x400000 && address >= 0x6000 && address < 0x8000)) - { obc1_write(space, offset, data, mem_mask); return; } - if (state->m_has_addon_chip == HAS_CX4 + { obc1_write(space, offset, data, mem_mask); return; } + if (state->m_has_addon_chip == HAS_CX4 && (offset < 0x400000 && address >= 0x6000 && address < 0x8000)) - { CX4_write(space.machine(), address - 0x6000, data); return; } + { CX4_write(space.machine(), address - 0x6000, data); return; } if (state->m_has_addon_chip == HAS_RTC && (offset < 0x400000 && (address == 0x2800 || address == 0x2801))) - { srtc_write(space.machine(), offset, data); return; } + { srtc_write(space.machine(), offset, data); return; } if (state->m_has_addon_chip == HAS_ST010 || state->m_has_addon_chip == HAS_ST011) { if (offset >= 0x680000 && offset < 0x700000 && address < 0x1000) - { st010_write_ram(state, address, data); return; } + { st010_write_ram(state, address, data); return; } if (offset == 0x600000) - { st010_set_dr(data); return; } + { st010_set_dr(data); return; } if (offset == 0x600001) - { st010_set_sr(data); return; } + { st010_set_sr(data); return; } } - if (state->m_cart[0].mode == SNES_MODE_21 && state->m_has_addon_chip == HAS_DSP1 + if (state->m_cart[0].mode == SNES_MODE_21 && state->m_has_addon_chip == HAS_DSP1 && (offset < 0x200000 && address >= 0x6000 && address < 0x8000)) - { dsp_set_dr(data); return; } + { dsp_set_dr(data); return; } if (state->m_cart[0].mode == SNES_MODE_20 && state->m_has_addon_chip == HAS_DSP1) { if (offset >= 0x200000 && offset < 0x400000 && (offset & 0x8000) == 0x8000) - { dsp_set_dr(data); return; } + { dsp_set_dr(data); return; } if (offset >= 0x600000 && offset < 0x700000 && (offset & 0x8000) == 0x0000) - { dsp_set_dr(data); return; } - } + { dsp_set_dr(data); return; } + } if ((state->m_has_addon_chip == HAS_DSP2 || state->m_has_addon_chip == HAS_DSP3) && (offset >= 0x200000 && offset < 0x400000 && (offset & 0x8000) == 0x8000)) { if (address < 0xc000) - { dsp_set_dr(data); return; } + { dsp_set_dr(data); return; } else - { dsp_set_sr(data); return; } + { dsp_set_sr(data); return; } } - if (state->m_has_addon_chip == HAS_DSP4 + if (state->m_has_addon_chip == HAS_DSP4 && (offset >= 0x300000 && offset < 0x400000 && (offset & 0x8000) == 0x8000)) { if (address < 0xc000) - { dsp_set_dr(data); return; } + { dsp_set_dr(data); return; } else - { dsp_set_sr(data); return; } + { dsp_set_sr(data); return; } } if (state->m_has_addon_chip == HAS_SDD1 && offset < 0x400000) { @@ -418,24 +418,24 @@ static WRITE8_HANDLER( snes_hi_w ) } } if ((state->m_has_addon_chip == HAS_SPC7110 || state->m_has_addon_chip == HAS_SPC7110_RTC) && offset < 0x400000) - { + { UINT16 limit = (state->m_has_addon_chip == HAS_SPC7110_RTC) ? 0x4842 : 0x483f; if (address >= 0x4800 && address <= limit) - { spc7110_mmio_write(space.machine(), (UINT32)address, data); return; } + { spc7110_mmio_write(space.machine(), (UINT32)address, data); return; } if (offset < 0x10000 && address >= 0x6000 && address < 0x8000) - { snes_ram[0x306000 + (address & 0x1fff)] = data; return; } + { snes_ram[0x306000 + (address & 0x1fff)] = data; return; } if (offset >= 0x300000 && offset < 0x310000 && address >= 0x6000 && address < 0x8000) - { snes_ram[0x306000 + (address & 0x1fff)] = data; return; } + { snes_ram[0x306000 + (address & 0x1fff)] = data; return; } } if (state->m_has_addon_chip == HAS_SUPERFX && state->m_superfx != NULL) - { space.write_byte(offset, data); return; } // [80-ff] same as [00-7f] - + { space.write_byte(offset, data); return; } // [80-ff] same as [00-7f] + // base cart access if (offset < 0x400000) snes_w_bank6(space, offset, data, 0xff); else snes_w_bank7(space, offset, data - 0x400000, 0xff); -} +} static READ8_HANDLER( superfx_r_bank1 ) { @@ -1100,7 +1100,7 @@ static MACHINE_START( snes_mess ) machine.add_notifier(MACHINE_NOTIFY_EXIT, machine_notify_delegate(FUNC(snes_machine_stop),&machine)); MACHINE_START_CALL(snes); - + switch (state->m_has_addon_chip) { case HAS_SDD1: @@ -1133,16 +1133,16 @@ static MACHINE_RESET( snes_mess ) // see if there's a uPD7725 DSP in the machine config state->m_upd7725 = machine.device("dsp"); - + // if we have a DSP, halt it for the moment if (state->m_upd7725) machine.device("dsp")->execute().set_input_line(INPUT_LINE_RESET, ASSERT_LINE); - + // ditto for a uPD96050 (Seta ST-010 or ST-011) state->m_upd96050 = machine.device("setadsp"); if (state->m_upd96050) machine.device("setadsp")->execute().set_input_line(INPUT_LINE_RESET, ASSERT_LINE); - + switch (state->m_has_addon_chip) { case HAS_DSP1: @@ -1158,15 +1158,15 @@ static MACHINE_RESET( snes_mess ) state->m_has_addon_chip = HAS_NONE; // prevent crash trying to access NULL device } break; - + case HAS_RTC: srtc_init(machine); break; - + case HAS_OBC1: obc1_init(machine); break; - + case HAS_ST010: case HAS_ST011: // cartridge uses the DSP, let 'er rip @@ -1178,7 +1178,7 @@ static MACHINE_RESET( snes_mess ) state->m_has_addon_chip = HAS_NONE; // prevent crash trying to access NULL device } break; - + default: break; } @@ -1470,8 +1470,8 @@ public: snsnew_state(const machine_config &mconfig, device_type type, const char *tag) : snes_state(mconfig, type, tag), m_slotcart(*this, "snsslot") - { } - + { } + optional_device m_slotcart; int m_type; }; @@ -1489,7 +1489,7 @@ static READ8_HANDLER( snes20_hi_r ) { snsnew_state *state = space.machine().driver_data(); UINT16 address = offset & 0xffff; - + if (offset < 0x400000) { if (address < 0x2000) @@ -1498,7 +1498,7 @@ static READ8_HANDLER( snes20_hi_r ) return snes_r_io(space, address); if (address >= 0x6000 && address < 0x8000) return snes_open_bus_r(space, 0); - if (address >= 0x8000) + if (address >= 0x8000) return state->m_slotcart->m_cart->read_h(space, offset); } else if (offset < 0x700000) @@ -1508,10 +1508,10 @@ static READ8_HANDLER( snes20_hi_r ) else return state->m_slotcart->m_cart->read_h(space, offset); } - + // ROM & NVRAM access return state->m_slotcart->m_cart->read_h(space, offset); -} +} static WRITE8_HANDLER( snes20_hi_w ) { @@ -1524,17 +1524,17 @@ static WRITE8_HANDLER( snes20_hi_w ) if (address >= 0x2000 && address < 0x6000) snes_w_io(space, address, data); } - else if (offset >= 0x700000) // NVRAM access + else if (offset >= 0x700000) // NVRAM access { state->m_slotcart->m_cart->write_h(space, offset, data); } -} +} static READ8_HANDLER( snes20_lo_r ) { snsnew_state *state = space.machine().driver_data(); UINT16 address = offset & 0xffff; - + if (offset < 0x400000) { if (address < 0x2000) @@ -1543,7 +1543,7 @@ static READ8_HANDLER( snes20_lo_r ) return snes_r_io(space, address); if (address >= 0x6000 && address < 0x8000) return snes_open_bus_r(space, 0); - if (address >= 0x8000) + if (address >= 0x8000) return state->m_slotcart->m_cart->read_l(space, offset); } else if (offset < 0x700000) @@ -1553,15 +1553,15 @@ static READ8_HANDLER( snes20_lo_r ) else return state->m_slotcart->m_cart->read_l(space, offset); } - + // ROM & NVRAM access return state->m_slotcart->m_cart->read_l(space, offset); -} +} static WRITE8_HANDLER( snes20_lo_w ) { snes20_hi_w(space, offset, data, 0xff); -} +} // HiROM @@ -1570,7 +1570,7 @@ static READ8_HANDLER( snes21_lo_r ) { snsnew_state *state = space.machine().driver_data(); UINT16 address = offset & 0xffff; - + if (offset < 0x400000) { if (address < 0x2000) @@ -1590,10 +1590,10 @@ static READ8_HANDLER( snes21_lo_r ) if (address >= 0x8000) return state->m_slotcart->m_cart->read_l(space, offset); } - + // ROM & NVRAM access return state->m_slotcart->m_cart->read_l(space, offset); -} +} static WRITE8_HANDLER( snes21_lo_w ) { @@ -1615,15 +1615,15 @@ static WRITE8_HANDLER( snes21_lo_w ) } } } - else if (offset >= 0x700000) // NVRAM access + else if (offset >= 0x700000) // NVRAM access state->m_slotcart->m_cart->write_l(space, offset, data); -} +} static READ8_HANDLER( snes21_hi_r ) { snsnew_state *state = space.machine().driver_data(); UINT16 address = offset & 0xffff; - + if (offset < 0x400000) { if (address < 0x2000) @@ -1643,10 +1643,10 @@ static READ8_HANDLER( snes21_hi_r ) if (address >= 0x8000) return state->m_slotcart->m_cart->read_h(space, offset); } - + // ROM & NVRAM access return state->m_slotcart->m_cart->read_h(space, offset); -} +} static WRITE8_HANDLER( snes21_hi_w ) { @@ -1668,9 +1668,9 @@ static WRITE8_HANDLER( snes21_hi_w ) } } } - else if (offset >= 0x700000) // NVRAM access + else if (offset >= 0x700000) // NVRAM access state->m_slotcart->m_cart->write_h(space, offset, data); -} +} // SuperFX / GSU @@ -1678,7 +1678,7 @@ static READ8_HANDLER( snesfx_hi_r ) { snsnew_state *state = space.machine().driver_data(); UINT16 address = offset & 0xffff; - + if (offset < 0x400000) { if (address < 0x2000) @@ -1692,22 +1692,22 @@ static READ8_HANDLER( snesfx_hi_r ) } if (address >= 0x6000 && address < 0x8000) { - return state->m_slotcart->m_cart->read_h(space, offset); //RAM + return state->m_slotcart->m_cart->read_h(space, offset); //RAM } if (address >= 0x8000) - return state->m_slotcart->m_cart->read_h(space, offset); //ROM + return state->m_slotcart->m_cart->read_h(space, offset); //ROM } else if (offset < 0x600000) - return state->m_slotcart->m_cart->read_h(space, offset); //ROM - - return state->m_slotcart->m_cart->read_h(space, offset); //RAM -} + return state->m_slotcart->m_cart->read_h(space, offset); //ROM + + return state->m_slotcart->m_cart->read_h(space, offset); //RAM +} static READ8_HANDLER( snesfx_lo_r ) { snsnew_state *state = space.machine().driver_data(); UINT16 address = offset & 0xffff; - + if (offset < 0x400000) { if (address < 0x2000) @@ -1721,16 +1721,16 @@ static READ8_HANDLER( snesfx_lo_r ) } if (address >= 0x6000 && address < 0x8000) { - return state->m_slotcart->m_cart->read_l(space, offset); //RAM + return state->m_slotcart->m_cart->read_l(space, offset); //RAM } if (address >= 0x8000) - return state->m_slotcart->m_cart->read_l(space, offset); //ROM + return state->m_slotcart->m_cart->read_l(space, offset); //ROM } else if (offset < 0x600000) - return state->m_slotcart->m_cart->read_l(space, offset); //ROM - - return state->m_slotcart->m_cart->read_l(space, offset); //RAM -} + return state->m_slotcart->m_cart->read_l(space, offset); //ROM + + return state->m_slotcart->m_cart->read_l(space, offset); //RAM +} static WRITE8_HANDLER( snesfx_hi_w ) { @@ -1752,7 +1752,7 @@ static WRITE8_HANDLER( snesfx_hi_w ) } else state->m_slotcart->m_cart->write_h(space, offset, data); -} +} static WRITE8_HANDLER( snesfx_lo_w ) { @@ -1774,7 +1774,7 @@ static WRITE8_HANDLER( snesfx_lo_w ) } else state->m_slotcart->m_cart->write_l(space, offset, data); -} +} // SPC-7110 @@ -1782,7 +1782,7 @@ static READ8_HANDLER( snespc7110_hi_r ) { snsnew_state *state = space.machine().driver_data(); UINT16 address = offset & 0xffff; - + if (offset < 0x400000) { if (address < 0x2000) @@ -1792,7 +1792,7 @@ static READ8_HANDLER( snespc7110_hi_r ) UINT16 limit = (state->m_slotcart->get_type() == SNES_SPC7110_RTC) ? 0x4843 : 0x4840; if (address >= 0x4800 && address < limit) return state->m_slotcart->m_cart->chip_read(space, address); - + return snes_r_io(space, address); } if (address >= 0x6000 && address < 0x8000) @@ -1806,13 +1806,13 @@ static READ8_HANDLER( snespc7110_hi_r ) return state->m_slotcart->m_cart->read_h(space, offset); } return state->m_slotcart->m_cart->read_h(space, offset); -} +} static READ8_HANDLER( snespc7110_lo_r ) { snsnew_state *state = space.machine().driver_data(); UINT16 address = offset & 0xffff; - + if (offset < 0x400000) { if (address < 0x2000) @@ -1822,7 +1822,7 @@ static READ8_HANDLER( snespc7110_lo_r ) UINT16 limit = (state->m_slotcart->get_type() == SNES_SPC7110_RTC) ? 0x4843 : 0x4840; if (address >= 0x4800 && address < limit) return state->m_slotcart->m_cart->chip_read(space, address); - + return snes_r_io(space, address); } if (address >= 0x6000 && address < 0x8000) @@ -1839,7 +1839,7 @@ static READ8_HANDLER( snespc7110_lo_r ) return state->m_slotcart->m_cart->chip_read(space, 0x4800); return snes_open_bus_r(space, 0); -} +} static WRITE8_HANDLER( snespc7110_hi_w ) { @@ -1867,7 +1867,7 @@ static WRITE8_HANDLER( snespc7110_hi_w ) state->m_slotcart->m_cart->write_l(space, offset, data); } } -} +} static WRITE8_HANDLER( snespc7110_lo_w ) { @@ -1895,7 +1895,7 @@ static WRITE8_HANDLER( snespc7110_lo_w ) state->m_slotcart->m_cart->write_l(space, offset, data); } } -} +} // S-DD1 @@ -1904,7 +1904,7 @@ static READ8_HANDLER( snesdd1_lo_r ) { snsnew_state *state = space.machine().driver_data(); UINT16 address = offset & 0xffff; - + if (offset < 0x400000) { if (address < 0x2000) @@ -1913,7 +1913,7 @@ static READ8_HANDLER( snesdd1_lo_r ) { if (address >= 0x4800 && address < 0x4808) return state->m_slotcart->m_cart->chip_read(space, address); - + return snes_r_io(space, address); } if (address >= 0x6000 && address < 0x8000) @@ -1921,10 +1921,10 @@ static READ8_HANDLER( snesdd1_lo_r ) if (address >= 0x8000) return state->m_slotcart->m_cart->read_l(space, offset); } - + // ROM & NVRAM access return state->m_slotcart->m_cart->read_l(space, offset); -} +} static WRITE8_HANDLER( snesdd1_lo_w ) { @@ -1951,22 +1951,22 @@ static WRITE8_HANDLER( snesdd1_lo_w ) } if (offset >= 0x700000 && address < 0x8000 && state->m_slotcart->m_cart->get_nvram_size()) return state->m_slotcart->m_cart->write_l(space, offset, data); -} +} static READ8_HANDLER( snesdd1_hi_r ) { snsnew_state *state = space.machine().driver_data(); - + if (offset >= 0x400000) return state->m_slotcart->m_cart->read_h(space, offset); - else + else return snesdd1_lo_r(space, offset, 0xff); -} +} static WRITE8_HANDLER( snesdd1_hi_w ) { snesdd1_lo_w(space, offset, data, 0xff); -} +} // BS-X @@ -1975,7 +1975,7 @@ static READ8_HANDLER( snesbsx_hi_r ) { snsnew_state *state = space.machine().driver_data(); UINT16 address = offset & 0xffff; - + if (offset < 0x400000) { if (address < 0x2000) @@ -1990,16 +1990,16 @@ static READ8_HANDLER( snesbsx_hi_r ) } if (address >= 0x6000 && address < 0x8000) { - if (offset >= 0x200000) + if (offset >= 0x200000) return state->m_slotcart->m_cart->read_l(space, offset); else return snes_open_bus_r(space, 0); } - if (address >= 0x8000) + if (address >= 0x8000) return state->m_slotcart->m_cart->read_l(space, offset); } return state->m_slotcart->m_cart->read_l(space, offset); -} +} static WRITE8_HANDLER( snesbsx_hi_w ) { @@ -2025,24 +2025,24 @@ static WRITE8_HANDLER( snesbsx_hi_w ) } if (address >= 0x6000 && address < 0x8000) { - if (offset >= 0x200000) + if (offset >= 0x200000) return state->m_slotcart->m_cart->write_l(space, offset, data); } - if (address >= 0x8000) + if (address >= 0x8000) return state->m_slotcart->m_cart->write_l(space, offset, data); } return state->m_slotcart->m_cart->write_l(space, offset, data); -} +} static READ8_HANDLER( snesbsx_lo_r ) { return snesbsx_hi_r(space, offset, 0xff); -} +} static WRITE8_HANDLER( snesbsx_lo_w ) { snesbsx_hi_w(space, offset, data, 0xff); -} +} static READ8_HANDLER( snesnew_lo_r ) @@ -2050,23 +2050,23 @@ static READ8_HANDLER( snesnew_lo_r ) snsnew_state *state = space.machine().driver_data(); // take care of add-on IO - if (state->m_slotcart->get_type() == SNES_DSP + if (state->m_slotcart->get_type() == SNES_DSP && (offset >= 0x200000 && offset < 0x400000 && (offset & 0x8000) == 0x8000)) return state->m_slotcart->m_cart->chip_read(space, offset & 0x7fff); - else if (state->m_slotcart->get_type() == SNES_DSP_MODE21 - && (offset < 0x200000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000)) + else if (state->m_slotcart->get_type() == SNES_DSP_MODE21 + && (offset < 0x200000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000)) return state->m_slotcart->m_cart->chip_read(space, offset & 0x1fff); - else if (state->m_slotcart->get_type() == SNES_DSP4 - && (offset >= 0x300000 && offset < 0x400000 && (offset & 0x8000) == 0x8000)) + else if (state->m_slotcart->get_type() == SNES_DSP4 + && (offset >= 0x300000 && offset < 0x400000 && (offset & 0x8000) == 0x8000)) return state->m_slotcart->m_cart->chip_read(space, offset & 0x7fff); - else if (state->m_slotcart->get_type() == SNES_OBC1 - && (offset < 0x400000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000)) + else if (state->m_slotcart->get_type() == SNES_OBC1 + && (offset < 0x400000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000)) return state->m_slotcart->m_cart->chip_read(space, offset); - else if ((state->m_slotcart->get_type() == SNES_ST010 || state->m_slotcart->get_type() == SNES_ST011) - && (offset >= 0x680000 && offset < 0x700000 && (offset & 0xffff) < 0x1000)) + else if ((state->m_slotcart->get_type() == SNES_ST010 || state->m_slotcart->get_type() == SNES_ST011) + && (offset >= 0x680000 && offset < 0x700000 && (offset & 0xffff) < 0x1000)) return state->m_slotcart->m_cart->chip_read(space, offset); else if (state->m_slotcart->get_type() == SNES_SRTC - && (offset < 0x400000 && (offset & 0xffff) == 0x2800)) + && (offset < 0x400000 && (offset & 0xffff) == 0x2800)) return state->m_slotcart->m_cart->chip_read(space, offset & 0xffff); else { @@ -2084,57 +2084,60 @@ static READ8_HANDLER( snesnew_lo_r ) case SNES_POKEMON: case SNES_BANANA: return snes20_lo_r(space, offset, 0xff); - + case SNES_MODE21: case SNES_DSP_MODE21: case SNES_SRTC: case SNES_BSXHI: return snes21_lo_r(space, offset, 0xff); - + case SNES_SFX: return snesfx_lo_r(space, offset, 0xff); - + case SNES_SPC7110: case SNES_SPC7110_RTC: return snespc7110_lo_r(space, offset, 0xff); - + case SNES_SDD1: return snesdd1_lo_r(space, offset, 0xff); - + case SNES_BSX: return snesbsx_lo_r(space, offset, 0xff); } } return snes_open_bus_r(space, 0); -} +} static READ8_HANDLER( snesnew_hi_r ) { snsnew_state *state = space.machine().driver_data(); - + // take care of add-on IO if (state->m_slotcart->get_type() == SNES_DSP && (offset >= 0x200000 && offset < 0x400000 && (offset & 0x8000) == 0x8000)) return state->m_slotcart->m_cart->chip_read(space, offset & 0x7fff); - else if (state->m_slotcart->get_type() == SNES_DSP_MODE21 - && (offset < 0x200000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000)) + else if (state->m_slotcart->get_type() == SNES_DSP_MODE21 + && (offset < 0x200000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000)) return state->m_slotcart->m_cart->chip_read(space, offset & 0x1fff); - else if (state->m_slotcart->get_type() == SNES_DSP4 - && (offset >= 0x300000 && offset < 0x400000 && (offset & 0x8000) == 0x8000)) + else if (state->m_slotcart->get_type() == SNES_DSP4 + && (offset >= 0x300000 && offset < 0x400000 && (offset & 0x8000) == 0x8000)) return state->m_slotcart->m_cart->chip_read(space, offset & 0x7fff); - else if (state->m_slotcart->get_type() == SNES_OBC1 - && (offset < 0x400000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000)) + else if (state->m_slotcart->get_type() == SNES_OBC1 + && (offset < 0x400000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000)) return state->m_slotcart->m_cart->chip_read(space, offset); - else if ((state->m_slotcart->get_type() == SNES_ST010 || state->m_slotcart->get_type() == SNES_ST011) - && (offset >= 0x680000 && offset < 0x700000 && (offset & 0xffff) < 0x1000)) + else if ((state->m_slotcart->get_type() == SNES_ST010 || state->m_slotcart->get_type() == SNES_ST011) + && (offset >= 0x680000 && offset < 0x700000 && (offset & 0xffff) < 0x1000)) return state->m_slotcart->m_cart->chip_read(space, offset); - else if (state->m_slotcart->get_type() == SNES_SRTC - && (offset < 0x400000 && (offset & 0xffff) == 0x2800)) + else if ((state->m_slotcart->get_type() == SNES_ST010 || state->m_slotcart->get_type() == SNES_ST011) + && (offset == 0x600000 || offset == 0x600001)) + return state->m_slotcart->m_cart->chip_read(space, offset); + else if (state->m_slotcart->get_type() == SNES_SRTC + && (offset < 0x400000 && (offset & 0xffff) == 0x2800)) return state->m_slotcart->m_cart->chip_read(space, offset & 0xffff); else if ((state->m_slotcart->get_type() == SNES_POKEMON || state->m_slotcart->get_type() == SNES_BANANA) - && (offset & 0x70000) == 0x0000) + && (offset & 0x70000) == 0x0000) { -// printf("hi read %x\n", offset); +// printf("hi read %x\n", offset); return state->m_slotcart->m_cart->chip_read(space, offset); } else @@ -2153,57 +2156,60 @@ static READ8_HANDLER( snesnew_hi_r ) case SNES_POKEMON: case SNES_BANANA: return snes20_hi_r(space, offset, 0xff); - + case SNES_MODE21: case SNES_DSP_MODE21: case SNES_SRTC: case SNES_BSXHI: return snes21_hi_r(space, offset, 0xff); - + case SNES_SFX: return snesfx_hi_r(space, offset, 0xff); - + case SNES_SPC7110: case SNES_SPC7110_RTC: return snespc7110_hi_r(space, offset, 0xff); - + case SNES_SDD1: return snesdd1_hi_r(space, offset, 0xff); - + case SNES_BSX: return snesbsx_hi_r(space, offset, 0xff); } } return snes_open_bus_r(space, 0); -} +} static WRITE8_HANDLER( snesnew_lo_w ) { snsnew_state *state = space.machine().driver_data(); - + // take care of add-on IO if (state->m_slotcart->get_type() == SNES_DSP && (offset >= 0x200000 && offset < 0x400000 && (offset & 0x8000) == 0x8000)) state->m_slotcart->m_cart->chip_write(space, offset & 0x7fff, data); - else if (state->m_slotcart->get_type() == SNES_DSP_MODE21 - && (offset < 0x200000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000)) + else if (state->m_slotcart->get_type() == SNES_DSP_MODE21 + && (offset < 0x200000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000)) state->m_slotcart->m_cart->chip_write(space, offset & 0x1fff, data); - else if (state->m_slotcart->get_type() == SNES_DSP4 - && (offset >= 0x300000 && offset < 0x400000 && (offset & 0x8000) == 0x8000)) + else if (state->m_slotcart->get_type() == SNES_DSP4 + && (offset >= 0x300000 && offset < 0x400000 && (offset & 0x8000) == 0x8000)) state->m_slotcart->m_cart->chip_write(space, offset & 0x7fff, data); - else if (state->m_slotcart->get_type() == SNES_OBC1 - && (offset < 0x400000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000)) + else if (state->m_slotcart->get_type() == SNES_OBC1 + && (offset < 0x400000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000)) state->m_slotcart->m_cart->chip_write(space, offset, data); - else if ((state->m_slotcart->get_type() == SNES_ST010 || state->m_slotcart->get_type() == SNES_ST011) - && (offset >= 0x680000 && offset < 0x700000 && (offset & 0xffff) < 0x1000)) + else if ((state->m_slotcart->get_type() == SNES_ST010 || state->m_slotcart->get_type() == SNES_ST011) + && (offset >= 0x680000 && offset < 0x700000 && (offset & 0xffff) < 0x1000)) + state->m_slotcart->m_cart->chip_write(space, offset, data); + else if ((state->m_slotcart->get_type() == SNES_ST010 || state->m_slotcart->get_type() == SNES_ST011) + && (offset == 0x600000 || offset == 0x600001)) state->m_slotcart->m_cart->chip_write(space, offset, data); else if (state->m_slotcart->get_type() == SNES_SRTC - && (offset < 0x400000 && (offset & 0xffff) == 0x2801)) + && (offset < 0x400000 && (offset & 0xffff) == 0x2801)) state->m_slotcart->m_cart->chip_write(space, offset & 0xffff, data); else if (state->m_slotcart->get_type() == SNES_BANANA - && (offset & 0x78000) == 0x8000) - { -// printf("lo write %x\n", offset); + && (offset & 0x78000) == 0x8000) + { +// printf("lo write %x\n", offset); state->m_slotcart->m_cart->chip_write(space, offset, data); } else @@ -2223,61 +2229,64 @@ static WRITE8_HANDLER( snesnew_lo_w ) case SNES_BANANA: snes20_lo_w(space, offset, data, 0xff); break; - + case SNES_MODE21: case SNES_DSP_MODE21: case SNES_SRTC: case SNES_BSXHI: snes21_lo_w(space, offset, data, 0xff); break; - + case SNES_SFX: snesfx_lo_w(space, offset, data, 0xff); break; - + case SNES_SPC7110: case SNES_SPC7110_RTC: snespc7110_lo_w(space, offset, data, 0xff); break; - + case SNES_SDD1: snesdd1_lo_w(space, offset, data, 0xff); break; - + case SNES_BSX: snesbsx_lo_w(space, offset, data, 0xff); break; } } -} +} static WRITE8_HANDLER( snesnew_hi_w ) { snsnew_state *state = space.machine().driver_data(); - + // take care of add-on IO if (state->m_slotcart->get_type() == SNES_DSP && (offset >= 0x200000 && offset < 0x400000 && (offset & 0x8000) == 0x8000)) state->m_slotcart->m_cart->chip_write(space, offset & 0x7fff, data); - else if (state->m_slotcart->get_type() == SNES_DSP_MODE21 - && (offset < 0x200000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000)) + else if (state->m_slotcart->get_type() == SNES_DSP_MODE21 + && (offset < 0x200000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000)) state->m_slotcart->m_cart->chip_write(space, offset & 0x1fff, data); - else if (state->m_slotcart->get_type() == SNES_DSP4 - && (offset >= 0x300000 && offset < 0x400000 && (offset & 0x8000) == 0x8000)) + else if (state->m_slotcart->get_type() == SNES_DSP4 + && (offset >= 0x300000 && offset < 0x400000 && (offset & 0x8000) == 0x8000)) state->m_slotcart->m_cart->chip_write(space, offset & 0x7fff, data); - else if (state->m_slotcart->get_type() == SNES_OBC1 - && (offset < 0x400000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000)) + else if (state->m_slotcart->get_type() == SNES_OBC1 + && (offset < 0x400000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000)) return state->m_slotcart->m_cart->chip_write(space, offset, data); - else if ((state->m_slotcart->get_type() == SNES_ST010 || state->m_slotcart->get_type() == SNES_ST011) - && (offset >= 0x680000 && offset < 0x700000 && (offset & 0xffff) < 0x1000)) + else if ((state->m_slotcart->get_type() == SNES_ST010 || state->m_slotcart->get_type() == SNES_ST011) + && (offset >= 0x680000 && offset < 0x700000 && (offset & 0xffff) < 0x1000)) + state->m_slotcart->m_cart->chip_write(space, offset, data); + else if ((state->m_slotcart->get_type() == SNES_ST010 || state->m_slotcart->get_type() == SNES_ST011) + && (offset == 0x600000 || offset == 0x600001)) state->m_slotcart->m_cart->chip_write(space, offset, data); else if (state->m_slotcart->get_type() == SNES_SRTC - && (offset < 0x400000 && (offset & 0xffff) == 0x2801)) + && (offset < 0x400000 && (offset & 0xffff) == 0x2801)) state->m_slotcart->m_cart->chip_write(space, offset & 0xffff, data); else if ((state->m_slotcart->get_type() == SNES_POKEMON) - && (offset & 0x70000) == 0x0000) - { -// printf("hi write %x\n", offset); + && (offset & 0x70000) == 0x0000) + { +// printf("hi write %x\n", offset); state->m_slotcart->m_cart->chip_write(space, offset, data); } else @@ -2297,33 +2306,33 @@ static WRITE8_HANDLER( snesnew_hi_w ) case SNES_BANANA: snes20_hi_w(space, offset, data, 0xff); break; - + case SNES_MODE21: case SNES_DSP_MODE21: case SNES_SRTC: case SNES_BSXHI: snes21_hi_w(space, offset, data, 0xff); break; - + case SNES_SFX: snesfx_hi_w(space, offset, data, 0xff); break; - + case SNES_SPC7110: case SNES_SPC7110_RTC: snespc7110_hi_w(space, offset, data, 0xff); break; - + case SNES_SDD1: snesdd1_hi_w(space, offset, data, 0xff); break; - + case SNES_BSX: snesbsx_hi_w(space, offset, data, 0xff); break; } } -} +} static ADDRESS_MAP_START( snesnew_map, AS_PROGRAM, 8, snsnew_state ) @@ -2334,26 +2343,26 @@ ADDRESS_MAP_END static SLOT_INTERFACE_START(snes_cart) SLOT_INTERFACE_INTERNAL("lorom", SNS_LOROM) - SLOT_INTERFACE_INTERNAL("lorom_bsx", SNS_LOROM_BSX) // LoROM + BS-X slot - unsupported - SLOT_INTERFACE_INTERNAL("lorom_cx4", SNS_LOROM) // Cart + CX4 - unsupported + SLOT_INTERFACE_INTERNAL("lorom_bsx", SNS_LOROM_BSX) // LoROM + BS-X slot - unsupported + SLOT_INTERFACE_INTERNAL("lorom_cx4", SNS_LOROM) // Cart + CX4 - unsupported SLOT_INTERFACE_INTERNAL("lorom_dsp", SNS_LOROM_NECDSP) SLOT_INTERFACE_INTERNAL("lorom_dsp4", SNS_LOROM_NECDSP) SLOT_INTERFACE_INTERNAL("lorom_obc1", SNS_LOROM_OBC1) - SLOT_INTERFACE_INTERNAL("lorom_sa1", SNS_LOROM) // Cart + SA1 - unsupported + SLOT_INTERFACE_INTERNAL("lorom_sa1", SNS_LOROM) // Cart + SA1 - unsupported SLOT_INTERFACE_INTERNAL("lorom_sdd1", SNS_LOROM_SDD1) SLOT_INTERFACE_INTERNAL("lorom_sfx", SNS_LOROM_SUPERFX) - SLOT_INTERFACE_INTERNAL("lorom_sgb", SNS_LOROM) // SuperGB base cart - unsupported + SLOT_INTERFACE_INTERNAL("lorom_sgb", SNS_LOROM) // SuperGB base cart - unsupported SLOT_INTERFACE_INTERNAL("lorom_st010", SNS_LOROM_SETA10) SLOT_INTERFACE_INTERNAL("lorom_st011", SNS_LOROM_SETA11) - SLOT_INTERFACE_INTERNAL("lorom_st018", SNS_LOROM) // Cart + ST018 - unsupported - SLOT_INTERFACE_INTERNAL("lorom_sufami", SNS_LOROM_SUFAMI) // Sufami Turbo base cart + SLOT_INTERFACE_INTERNAL("lorom_st018", SNS_LOROM) // Cart + ST018 - unsupported + SLOT_INTERFACE_INTERNAL("lorom_sufami", SNS_LOROM_SUFAMI) // Sufami Turbo base cart SLOT_INTERFACE_INTERNAL("hirom", SNS_HIROM) - SLOT_INTERFACE_INTERNAL("hirom_bsx", SNS_HIROM_BSX) // HiROM + BS-X slot - unsupported + SLOT_INTERFACE_INTERNAL("hirom_bsx", SNS_HIROM_BSX) // HiROM + BS-X slot - unsupported SLOT_INTERFACE_INTERNAL("hirom_dsp", SNS_HIROM_NECDSP) SLOT_INTERFACE_INTERNAL("hirom_spc7110", SNS_HIROM_SPC7110) SLOT_INTERFACE_INTERNAL("hirom_spcrtc", SNS_HIROM_SPC7110_RTC) SLOT_INTERFACE_INTERNAL("hirom_srtc", SNS_HIROM_SRTC) - SLOT_INTERFACE_INTERNAL("bsxrom", SNS_ROM_BSX) // BS-X base cart - partial support only + SLOT_INTERFACE_INTERNAL("bsxrom", SNS_ROM_BSX) // BS-X base cart - partial support only // pirate carts SLOT_INTERFACE_INTERNAL("lorom_poke", SNS_LOROM_POKEMON) SLOT_INTERFACE_END @@ -2365,18 +2374,30 @@ static MACHINE_START( snesnew ) state->m_type = state->m_slotcart->get_type(); - MACHINE_START_CALL(snes); + MACHINE_START_CALL(snes_mess); - // FIXME: why installing handlers here does not work? it would allow to clean up handlers above... + // in progress... switch (state->m_type) { case SNES_MODE21: - case SNES_MODE25: - case SNES_DSP_MODE21: machine.device("maincpu")->memory().space(AS_PROGRAM).install_legacy_readwrite_handler(0x000000, 0x7dffff, FUNC(snes21_lo_r), FUNC(snes21_lo_w)); machine.device("maincpu")->memory().space(AS_PROGRAM).install_legacy_readwrite_handler(0x800000, 0xffffff, FUNC(snes21_hi_r), FUNC(snes21_hi_w)); set_5a22_map(*state->m_maincpu); break; + case SNES_DSP_MODE21: +// machine.device("maincpu")->memory().space(AS_PROGRAM).install_legacy_readwrite_handler(0x000000, 0x7dffff, FUNC(snes21_lo_r), FUNC(snes21_lo_w)); +// machine.device("maincpu")->memory().space(AS_PROGRAM).install_legacy_readwrite_handler(0x800000, 0xffffff, FUNC(snes21_hi_r), FUNC(snes21_hi_w)); +// machine.device("maincpu")->memory().space(AS_PROGRAM).install_read_handler(0x006000, 0x007fff, 0x1f0000, 0, read8_delegate(FUNC(device_sns_cart_interface::chip_read),state->m_slotcart->m_cart)); +// machine.device("maincpu")->memory().space(AS_PROGRAM).install_write_handler(0x006000, 0x007fff, 0x1f0000, 0, write8_delegate(FUNC(device_sns_cart_interface::chip_write),state->m_slotcart->m_cart)); +// set_5a22_map(*state->m_maincpu); + break; + case SNES_SRTC: +// machine.device("maincpu")->memory().space(AS_PROGRAM).install_legacy_readwrite_handler(0x000000, 0x7dffff, FUNC(snes21_lo_r), FUNC(snes21_lo_w)); +// machine.device("maincpu")->memory().space(AS_PROGRAM).install_legacy_readwrite_handler(0x800000, 0xffffff, FUNC(snes21_hi_r), FUNC(snes21_hi_w)); +// machine.device("maincpu")->memory().space(AS_PROGRAM).install_read_handler(0x002800, 0x002800, 0x3f0000, 0, read8_delegate(FUNC(device_sns_cart_interface::chip_read),state->m_slotcart->m_cart)); +// machine.device("maincpu")->memory().space(AS_PROGRAM).install_write_handler(0x002801, 0x002801, 0x3f0000, 0, write8_delegate(FUNC(device_sns_cart_interface::chip_write),state->m_slotcart->m_cart)); +// set_5a22_map(*state->m_maincpu); + break; } } diff --git a/src/mess/machine/snescart.c b/src/mess/machine/snescart.c index 3c25884a1d9..d7afa5dbc23 100644 --- a/src/mess/machine/snescart.c +++ b/src/mess/machine/snescart.c @@ -1312,4 +1312,3 @@ DRIVER_INIT_MEMBER(snes_state,snesst) #include "machine/snesrtc.c" #include "machine/snessdd1.c" #include "machine/snes7110.c" - diff --git a/src/mess/machine/sns_bsx.c b/src/mess/machine/sns_bsx.c index 37056d42824..b3dcca93e84 100644 --- a/src/mess/machine/sns_bsx.c +++ b/src/mess/machine/sns_bsx.c @@ -1,7 +1,7 @@ /*********************************************************************************************************** - + BS-X Satellaview cartridge emulation (for SNES/SFC) - + Copyright MESS Team. Visit http://mamedev.org for licensing and usage restrictions. @@ -89,7 +89,7 @@ void sns_rom_bsmempak_device::device_start() m_command = 0; m_write_old = 0; m_write_new = 0; - + m_flash_enable = 0; m_read_enable = 0; m_write_enable = 0; @@ -129,26 +129,26 @@ UINT8 BSX_base::read(UINT32 offset) mame_printf_debug("BS-X Base Unit reg read outside correct range!\n"); return 0x00; } - - switch (offset) - { + + switch (offset) + { // no 218b? no 218d? no 2191? no 2195? no 219a-219f? - case 0x2192: + case 0x2192: { UINT8 counter = r2192_counter++; - if (r2192_counter >= 18) + if (r2192_counter >= 18) r2192_counter = 0; - - if (counter == 0) + + if (counter == 0) { system_time curtime, *systime = &curtime; - m_machine.current_datetime(curtime); + m_machine.current_datetime(curtime); r2192_hour = systime->local_time.hour; r2192_minute = systime->local_time.minute; r2192_second = systime->local_time.second; } - - switch (counter) + + switch (counter) { case 0: return 0x00; //??? case 1: return 0x00; //??? @@ -169,7 +169,7 @@ UINT8 BSX_base::read(UINT32 offset) case 16: return 0x00; //??? case 17: return 0x00; //??? } - } + } break; case 0x2193: @@ -191,25 +191,25 @@ void BSX_base::write(UINT32 offset, UINT8 data) mame_printf_debug("BS-X Base Unit reg write outside correct range!\n"); return; } - - switch(offset) + + switch(offset) { // no 218d? no 2190? no 2195? no 2196? no 2198? no 219a-219f? case 0x218f: - regs[6] >>= 1; // 0x218e - regs[6] = regs[7] - regs[6]; // 0x218f - 0x218e - regs[7] >>= 1; // 0x218f + regs[6] >>= 1; // 0x218e + regs[6] = regs[7] - regs[6]; // 0x218f - 0x218e + regs[7] >>= 1; // 0x218f break; - + case 0x2191: regs[offset - 0x2188] = data; r2192_counter = 0; break; - + case 0x2192: - regs[8] = data; // sets 0x2190 + regs[8] = data; // sets 0x2190 break; - + default: regs[offset - 0x2188] = data; break; @@ -266,8 +266,8 @@ void sns_rom_bsx_device::access_update() rom_access = 0; else { -// rom_access = BIT(m_cart_regs[0x02], 7) + 1; - rom_access = 1; // for whatever reason bsxsore changes access mode here and then fails to read the ROM properly! +// rom_access = BIT(m_cart_regs[0x02], 7) + 1; + rom_access = 1; // for whatever reason bsxsore changes access mode here and then fails to read the ROM properly! printf("rom_access %s\n", !BIT(m_cart_regs[0x02], 7) ? "Lo" : "Hi"); } } @@ -317,7 +317,7 @@ READ8_MEMBER(sns_rom_bsx_device::read_l) int bank = (rom_access == 1) ? (offset / 0x10000) : (offset / 0x8000); return m_rom[rom_bank_map[bank] * 0x8000 + (offset & 0x7fff)]; } - + return 0x00; } @@ -330,7 +330,7 @@ READ8_MEMBER(sns_rom_bsx_device::read_h) if (m_slot->m_cart && m_slot->m_cart->get_rom_size()) return m_slot->m_cart->read_l(space, offset); } - + // if not in any of the cases above... //$00-3f|80-bf:8000-ffff //$40-7f|c0-ff:0000-ffff @@ -341,7 +341,7 @@ READ8_MEMBER(sns_rom_bsx_device::read_h) int bank = (rom_access == 1) ? (offset / 0x10000) : (offset / 0x8000); return m_rom[rom_bank_map[bank] * 0x8000 + (offset & 0x7fff)]; } - + return 0x00; } @@ -378,7 +378,7 @@ WRITE8_MEMBER(sns_rom_bsx_device::write_l) // 0x70-0x77:0x0000-0xffff -> PRAM m_pram[offset & 0x7ffff] = data; } - + // if not in any of the cases above... //$00-3f|80-bf:8000-ffff //$40-7f|c0-ff:0000-ffff @@ -394,7 +394,7 @@ WRITE8_MEMBER(sns_rom_bsx_device::write_h) // write to cart... return; } - + // if not in any of the cases above... //$00-3f|80-bf:8000-ffff //$40-7f|c0-ff:0000-ffff @@ -407,18 +407,18 @@ READ8_MEMBER(sns_rom_bsx_device::chip_read) { if ((offset & 0xffff) >= 0x2188 && (offset & 0xffff) < 0x21a0) return m_base_unit->read(offset & 0xffff); - - if ((offset & 0xf0ffff) == 0x005000) //$[00-0f]:5000 reg access + + if ((offset & 0xf0ffff) == 0x005000) //$[00-0f]:5000 reg access { UINT8 n = (offset >> 16) & 0x0f; return m_cart_regs[n]; } - - if ((offset & 0xf8f000) == 0x105000) //$[10-17]:[5000-5fff] SRAM access + + if ((offset & 0xf8f000) == 0x105000) //$[10-17]:[5000-5fff] SRAM access { return m_nvram[((offset >> 16) & 7) * 0x1000 + (offset & 0xfff)]; } - + return 0x00; } @@ -426,16 +426,16 @@ WRITE8_MEMBER(sns_rom_bsx_device::chip_write) { if ((offset & 0xffff) >= 0x2188 && (offset & 0xffff) < 0x21a0) m_base_unit->write(offset & 0xffff, data); - - if ((offset & 0xf0ffff) == 0x005000) //$[00-0f]:5000 reg access + + if ((offset & 0xf0ffff) == 0x005000) //$[00-0f]:5000 reg access { UINT8 n = (offset >> 16) & 0x0f; m_cart_regs[n] = data; if (n == 0x0e && data & 0x80) access_update(); } - - if ((offset & 0xf8f000) == 0x105000) //$[10-17]:[5000-5fff] SRAM access + + if ((offset & 0xf8f000) == 0x105000) //$[10-17]:[5000-5fff] SRAM access { m_nvram[((offset >> 16) & 7) * 0x1000 + (offset & 0xfff)] = data; } @@ -583,4 +583,3 @@ READ8_MEMBER(sns_rom_bsmempak_device::read_h) WRITE8_MEMBER(sns_rom_bsmempak_device::write_l) { } - diff --git a/src/mess/machine/sns_bsx.h b/src/mess/machine/sns_bsx.h index 96dd0ae47c2..baddd2f82d4 100644 --- a/src/mess/machine/sns_bsx.h +++ b/src/mess/machine/sns_bsx.h @@ -17,7 +17,7 @@ public: private: // regs - UINT8 regs[0x18]; // 0x2188-0x219f + UINT8 regs[0x18]; // 0x2188-0x219f // counter + clock UINT8 r2192_counter; @@ -34,12 +34,12 @@ public: // construction/destruction sns_rom_bsx_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock); sns_rom_bsx_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // device-level overrides virtual void device_start(); virtual void device_config_complete() { m_shortname = "sns_rom_bsx"; } virtual machine_config_constructor device_mconfig_additions() const; - + // additional reading and writing virtual DECLARE_READ8_MEMBER(read_l); virtual DECLARE_READ8_MEMBER(read_h); @@ -47,23 +47,23 @@ public: virtual DECLARE_WRITE8_MEMBER(write_h); virtual DECLARE_READ8_MEMBER(chip_read); virtual DECLARE_WRITE8_MEMBER(chip_write); - + // base regs BSX_base *m_base_unit; - + // cart regs UINT8 m_cart_regs[16]; - UINT8 access_00_1f; // 1 = CART, 0 = NOTHING - UINT8 access_80_9f; // 1 = CART, 0 = NOTHING - UINT8 access_40_4f; // 1 = NOTHING, 0 = PRAM - UINT8 access_50_5f; // 1 = NOTHING, 0 = PRAM - UINT8 access_60_6f; // 1 = PRAM, 0 = NOTHING - UINT8 rom_access; // 2 = HiROM, 1 = LoROM, 0 = PRAM + UINT8 access_00_1f; // 1 = CART, 0 = NOTHING + UINT8 access_80_9f; // 1 = CART, 0 = NOTHING + UINT8 access_40_4f; // 1 = NOTHING, 0 = PRAM + UINT8 access_50_5f; // 1 = NOTHING, 0 = PRAM + UINT8 access_60_6f; // 1 = PRAM, 0 = NOTHING + UINT8 rom_access; // 2 = HiROM, 1 = LoROM, 0 = PRAM void access_update(); - - + + UINT8 m_pram[0x80000]; - + private: required_device m_slot; }; @@ -75,20 +75,20 @@ class sns_rom_bsxlo_device : public sns_rom_device public: // construction/destruction sns_rom_bsxlo_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // device-level overrides virtual void device_start(); virtual void device_config_complete() { m_shortname = "sns_rom_bsxlo"; } virtual machine_config_constructor device_mconfig_additions() const; - + // additional reading and writing virtual DECLARE_READ8_MEMBER(read_l); virtual DECLARE_READ8_MEMBER(read_h); -// virtual DECLARE_WRITE8_MEMBER(write_l); -// virtual DECLARE_WRITE8_MEMBER(write_h); -// virtual DECLARE_READ8_MEMBER(chip_read); -// virtual DECLARE_WRITE8_MEMBER(chip_write); - +// virtual DECLARE_WRITE8_MEMBER(write_l); +// virtual DECLARE_WRITE8_MEMBER(write_h); +// virtual DECLARE_READ8_MEMBER(chip_read); +// virtual DECLARE_WRITE8_MEMBER(chip_write); + private: required_device m_slot; }; @@ -100,20 +100,20 @@ class sns_rom_bsxhi_device : public sns_rom21_device public: // construction/destruction sns_rom_bsxhi_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // device-level overrides virtual void device_start(); virtual void device_config_complete() { m_shortname = "sns_rom_bsxhi"; } virtual machine_config_constructor device_mconfig_additions() const; - + // additional reading and writing virtual DECLARE_READ8_MEMBER(read_l); virtual DECLARE_READ8_MEMBER(read_h); virtual DECLARE_WRITE8_MEMBER(write_l); virtual DECLARE_WRITE8_MEMBER(write_h); - // virtual DECLARE_READ8_MEMBER(chip_read); - // virtual DECLARE_WRITE8_MEMBER(chip_write); - + // virtual DECLARE_READ8_MEMBER(chip_read); + // virtual DECLARE_WRITE8_MEMBER(chip_write); + private: required_device m_slot; }; @@ -126,24 +126,24 @@ class sns_rom_bsmempak_device : public sns_rom_device public: // construction/destruction sns_rom_bsmempak_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // device-level overrides virtual void device_start(); virtual void device_config_complete() { m_shortname = "sns_bsmempak"; } - + // additional reading and writing virtual DECLARE_READ8_MEMBER(read_l); virtual DECLARE_READ8_MEMBER(read_h); virtual DECLARE_WRITE8_MEMBER(write_l); -// virtual DECLARE_WRITE8_MEMBER(write_h); -// virtual DECLARE_READ8_MEMBER(chip_read); -// virtual DECLARE_WRITE8_MEMBER(chip_write); - +// virtual DECLARE_WRITE8_MEMBER(write_h); +// virtual DECLARE_READ8_MEMBER(chip_read); +// virtual DECLARE_WRITE8_MEMBER(chip_write); + // flash regs UINT32 m_command; UINT8 m_write_old; UINT8 m_write_new; - + int m_flash_enable; int m_read_enable; int m_write_enable; diff --git a/src/mess/machine/sns_rom.c b/src/mess/machine/sns_rom.c index b87f1d287a9..b2eda6435a7 100644 --- a/src/mess/machine/sns_rom.c +++ b/src/mess/machine/sns_rom.c @@ -1,10 +1,10 @@ /*********************************************************************************************************** - + Super NES/Famicom (LoROM) cartridge emulation (for SNES/SFC) - + Copyright MESS Team. Visit http://mamedev.org for licensing and usage restrictions. - + ***********************************************************************************************************/ @@ -62,7 +62,7 @@ void sns_rom_obc1_device::device_start() // or from rom? m_offset = (m_ram[0x1ff5] & 0x01) ? 0x1800 : 0x1c00; m_address = (m_ram[0x1ff6] & 0x7f); - m_shift = (m_ram[0x1ff6] & 0x03) << 1; + m_shift = (m_ram[0x1ff6] & 0x03) << 1; save_item(NAME(m_ram)); save_item(NAME(m_address)); @@ -84,7 +84,7 @@ READ8_MEMBER(sns_rom_device::read_h) { UINT8 value = 0xff; UINT16 address = offset & 0xffff; - + if (offset < 0x700000) { int bank = offset / 0x10000; @@ -107,7 +107,7 @@ READ8_MEMBER(sns_rom_device::read_h) value = m_nvram[offset & mask]; } else - value = 0xff; // this should never happened... + value = 0xff; // this should never happened... } else { @@ -125,7 +125,7 @@ WRITE8_MEMBER(sns_rom_device::write_l) WRITE8_MEMBER(sns_rom_device::write_h) { - if (offset >= 0x700000) // SRAM + if (offset >= 0x700000) // SRAM { if (m_nvram_size > 0x8000) { @@ -161,18 +161,18 @@ WRITE8_MEMBER( sns_rom_pokemon_device::chip_write ) // same as above but additional read/write handling for the add-on chip /*************************************************************************** - + Based on C++ implementation by Byuu in BSNES. - + Byuu's code is released under GNU General Public License version 2 as published by the Free Software Foundation. - + The implementation below is released under the MAME license for use in MAME, MESS and derivatives by permission of Byuu - + Copyright (for the implementation below) MESS Team. Visit http://mamedev.org for licensing and usage restrictions. - + ***********************************************************************************************************/ @@ -180,34 +180,34 @@ READ8_MEMBER( sns_rom_obc1_device::chip_read ) { UINT16 address = offset & 0x1fff; UINT8 value; - + switch (address) { case 0x1ff0: value = m_ram[m_offset + (m_address << 2) + 0]; break; - + case 0x1ff1: value = m_ram[m_offset + (m_address << 2) + 1]; break; - + case 0x1ff2: value = m_ram[m_offset + (m_address << 2) + 2]; break; - + case 0x1ff3: value = m_ram[m_offset + (m_address << 2) + 3]; break; - + case 0x1ff4: value = m_ram[m_offset + (m_address >> 2) + 0x200]; break; - + default: value = m_ram[address]; break; } - + return value; } @@ -216,45 +216,44 @@ WRITE8_MEMBER( sns_rom_obc1_device::chip_write ) { UINT16 address = offset & 0x1fff; UINT8 temp; - + switch(address) { case 0x1ff0: m_ram[m_offset + (m_address << 2) + 0] = data; break; - + case 0x1ff1: m_ram[m_offset + (m_address << 2) + 1] = data; break; - + case 0x1ff2: m_ram[m_offset + (m_address << 2) + 2] = data; break; - + case 0x1ff3: m_ram[m_offset + (m_address << 2) + 3] = data; break; - + case 0x1ff4: temp = m_ram[m_offset + (m_address >> 2) + 0x200]; temp = (temp & ~(3 << m_shift)) | ((data & 0x03) << m_shift); m_ram[m_offset + (m_address >> 2) + 0x200] = temp; break; - + case 0x1ff5: m_offset = (data & 0x01) ? 0x1800 : 0x1c00; m_ram[address & 0x1fff] = data; break; - + case 0x1ff6: m_address = data & 0x7f; m_shift = (data & 0x03) << 1; m_ram[address & 0x1fff] = data; break; - + default: m_ram[address & 0x1fff] = data; break; } } - diff --git a/src/mess/machine/sns_rom.h b/src/mess/machine/sns_rom.h index edbf038a449..a4062f8cca9 100644 --- a/src/mess/machine/sns_rom.h +++ b/src/mess/machine/sns_rom.h @@ -7,13 +7,13 @@ // ======================> sns_rom_device class sns_rom_device : public device_t, - public device_sns_cart_interface + public device_sns_cart_interface { public: // construction/destruction sns_rom_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock); sns_rom_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // device-level overrides virtual void device_start(); virtual void device_config_complete() { m_shortname = "sns_rom"; } @@ -32,14 +32,14 @@ class sns_rom_pokemon_device : public sns_rom_device public: // construction/destruction sns_rom_pokemon_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // device-level overrides virtual void device_start(); virtual void device_config_complete() { m_shortname = "sns_rom_pokemon"; } - + // reading and writing - virtual DECLARE_READ8_MEMBER(chip_read); // protection device - virtual DECLARE_WRITE8_MEMBER(chip_write); // protection device + virtual DECLARE_READ8_MEMBER(chip_read); // protection device + virtual DECLARE_WRITE8_MEMBER(chip_write); // protection device UINT8 m_latch; }; @@ -50,15 +50,15 @@ class sns_rom_obc1_device : public sns_rom_device public: // construction/destruction sns_rom_obc1_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // device-level overrides virtual void device_start(); virtual void device_config_complete() { m_shortname = "sns_rom_obc1"; } - + // additional reading and writing virtual DECLARE_READ8_MEMBER(chip_read); virtual DECLARE_WRITE8_MEMBER(chip_write); - + int m_address; int m_offset; int m_shift; diff --git a/src/mess/machine/sns_rom21.c b/src/mess/machine/sns_rom21.c index dd2e8d786d1..01d8a4a90b6 100644 --- a/src/mess/machine/sns_rom21.c +++ b/src/mess/machine/sns_rom21.c @@ -1,10 +1,10 @@ /*********************************************************************************************************** - + Super NES/Famicom (HiROM) cartridge emulation (for SNES/SFC) - + Copyright MESS Team. Visit http://mamedev.org for licensing and usage restrictions. - + ***********************************************************************************************************/ @@ -51,7 +51,7 @@ void sns_rom21_srtc_device::device_start() m_index = -1; // at this stage, rtc_ram is not yet allocated. this will be fixed when converting RTC to be a separate device. -// update_time(); +// update_time(); save_item(NAME(m_mode)); save_item(NAME(m_index)); @@ -66,7 +66,7 @@ void sns_rom21_srtc_device::device_start() READ8_MEMBER(sns_rom21_device::read_l) { UINT16 address = offset & 0xffff; - + if (offset >= 0x300000 && offset < 0x400000 && address < 0x8000) { if (m_nvram_size > 0) @@ -77,7 +77,7 @@ READ8_MEMBER(sns_rom21_device::read_l) return m_nvram[(offset - 0x6000) & mask]; } } - + // here ROM banks from 128 to 255, mirrored twice int bank = (offset & 0x3fffff) / 0x8000; return m_rom[rom_bank_map[bank + 0x80] * 0x8000 + (offset & 0x7fff)]; @@ -86,7 +86,7 @@ READ8_MEMBER(sns_rom21_device::read_l) READ8_MEMBER(sns_rom21_device::read_h) { UINT16 address = offset & 0xffff; - + if (offset >= 0x300000 && offset < 0x400000 && address < 0x8000) { if (m_nvram_size > 0) @@ -97,7 +97,7 @@ READ8_MEMBER(sns_rom21_device::read_h) return m_nvram[(offset - 0x6000) & mask]; } } - + // here ROM banks from 0 to 127, mirrored twice int bank = (offset & 0x3fffff) / 0x8000; return m_rom[rom_bank_map[bank] * 0x8000 + (offset & 0x7fff)]; @@ -111,7 +111,7 @@ WRITE8_MEMBER(sns_rom21_device::write_l) WRITE8_MEMBER(sns_rom21_device::write_h) { UINT16 address = offset & 0xffff; - + if (offset >= 0x300000 && offset < 0x400000 && address < 0x8000) { if (m_nvram_size > 0) @@ -127,18 +127,18 @@ WRITE8_MEMBER(sns_rom21_device::write_h) // Hi-ROM + S-RTC (used by Daikaijuu Monogatari II) // same as above but additional read/write handling for the RTC /*************************************************************************** - + Based on C++ implementation by Byuu in BSNES. - + Byuu's code is released under GNU General Public License version 2 as published by the Free Software Foundation. - + The implementation below is released under the MAME license for use in MAME, MESS and derivatives by permission of Byuu - + Copyright (for the implementation below) MESS Team. Visit http://mamedev.org for licensing and usage restrictions. - + ***************************************************************************/ static const UINT8 srtc_months[12] = @@ -175,11 +175,11 @@ UINT8 sns_rom21_srtc_device::srtc_weekday( UINT32 year, UINT32 month, UINT32 day { UINT32 y = 1900, m = 1; // Epoch is 1900-01-01 UINT32 sum = 0; // Number of days passed since epoch - + year = MAX(1900, year); month = MAX(1, MIN(12, month)); day = MAX(1, MIN(31, day)); - + while (y < year) { UINT8 leapyear = 0; @@ -194,7 +194,7 @@ UINT8 sns_rom21_srtc_device::srtc_weekday( UINT32 year, UINT32 month, UINT32 day sum += leapyear ? 366 : 365; y++; } - + while (m < month) { UINT32 days = srtc_months[m - 1]; @@ -214,19 +214,19 @@ UINT8 sns_rom21_srtc_device::srtc_weekday( UINT32 year, UINT32 month, UINT32 day sum += days; m++; } - + sum += day - 1; return (sum + 1) % 7; // 1900-01-01 was a Monday } // this gets called only for accesses at 0x2800, -// because for 0x2801 open bus gets returned... +// because for 0x2801 open bus gets returned... READ8_MEMBER(sns_rom21_srtc_device::chip_read) { if (m_mode != RTCM_Read) return 0x00; - + if (m_index < 0) { update_time(); @@ -246,29 +246,29 @@ READ8_MEMBER(sns_rom21_srtc_device::chip_read) WRITE8_MEMBER(sns_rom21_srtc_device::chip_write) { data &= 0x0f; // Only the low four bits are used - + if (data == 0x0d) { m_mode = RTCM_Read; m_index = -1; return; } - + if (data == 0x0e) { m_mode = RTCM_Command; return; } - + if (data == 0x0f) return; // Unknown behaviour - + if (m_mode == RTCM_Write) { if (m_index >= 0 && m_index < 12) { m_rtc_ram[m_index++] = data; - + if (m_index == 12) { // Day of week is automatically calculated and written @@ -276,7 +276,7 @@ WRITE8_MEMBER(sns_rom21_srtc_device::chip_write) UINT32 month = m_rtc_ram[8]; UINT32 year = m_rtc_ram[9] + m_rtc_ram[10] * 10 + m_rtc_ram[11] * 100; year += 1000; - + m_rtc_ram[m_index++] = srtc_weekday(year, month, day); } } @@ -303,4 +303,3 @@ WRITE8_MEMBER(sns_rom21_srtc_device::chip_write) } } } - diff --git a/src/mess/machine/sns_rom21.h b/src/mess/machine/sns_rom21.h index a24feb00584..659c84fdc0d 100644 --- a/src/mess/machine/sns_rom21.h +++ b/src/mess/machine/sns_rom21.h @@ -7,13 +7,13 @@ // ======================> sns_rom21_device class sns_rom21_device : public device_t, - public device_sns_cart_interface + public device_sns_cart_interface { public: // construction/destruction sns_rom21_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock); sns_rom21_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // device-level overrides virtual void device_start(); virtual void device_config_complete() { m_shortname = "sns_rom21"; } @@ -32,11 +32,11 @@ class sns_rom21_srtc_device : public sns_rom21_device public: // construction/destruction sns_rom21_srtc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // device-level overrides virtual void device_start(); virtual void device_config_complete() { m_shortname = "sns_rom21_srtc"; } - + // reading and writing virtual DECLARE_READ8_MEMBER(chip_read); virtual DECLARE_WRITE8_MEMBER(chip_write); @@ -49,10 +49,10 @@ public: RTCM_Read, RTCM_Write }; - + void update_time(); UINT8 srtc_weekday(UINT32 year, UINT32 month, UINT32 day); - + //this is now allocated in the main snes cart class, to allow saving to nvram //UINT8 m_rtc_ram[13]; INT32 m_mode; diff --git a/src/mess/machine/sns_sdd1.c b/src/mess/machine/sns_sdd1.c index 2c91e74f179..3bdaaf81ae9 100644 --- a/src/mess/machine/sns_sdd1.c +++ b/src/mess/machine/sns_sdd1.c @@ -1,13 +1,13 @@ /*********************************************************************************************************** - + S-DD1 add-on chip emulation (for SNES/SFC) - + Based on Andreas Naive Public Domain code. Code ported by MooglyGuy and updated to slots by Fabio Priuli. - + Copyright MESS Team. Visit http://mamedev.org for licensing and usage restrictions. - + ***********************************************************************************************************/ @@ -30,21 +30,21 @@ void SDD1__IM::IM_prepareDecomp(UINT32 in_buf) UINT8 SDD1__IM::IM_getCodeword(UINT8 *ROM, UINT32 *mmc, const UINT8 code_len) { UINT8 codeword = ROM[SSD1_ADD(m_byte_ptr)] << m_bit_count; - + ++m_bit_count; - + if (codeword & 0x80) { codeword |= ROM[SSD1_ADD((m_byte_ptr + 1))] >> (9 - m_bit_count); m_bit_count += code_len; } - + if (m_bit_count & 0x08) { m_byte_ptr++; m_bit_count &= 0x07; } - + return codeword; } @@ -87,9 +87,9 @@ void SDD1__GCD::GCD_getRunCount(UINT8 *ROM, UINT32 *mmc, UINT8 code_num, UINT8* 0x78, 0x38, 0x58, 0x18, 0x68, 0x28, 0x48, 0x08, 0x70, 0x30, 0x50, 0x10, 0x60, 0x20, 0x40, 0x00, }; - + UINT8 codeword = m_IM->IM_getCodeword(ROM, mmc, code_num); - + if (codeword & 0x80) { *LPSind = 1; @@ -112,12 +112,12 @@ void SDD1__BG::BG_prepareDecomp() UINT8 SDD1__BG::BG_getBit(UINT8 *ROM, UINT32 *mmc, UINT8* endOfRun) { UINT8 bit; - + if (!(m_MPScount || m_LPSind)) { m_GCD->GCD_getRunCount(ROM, mmc, m_code_num, &(m_MPScount), &(m_LPSind)); } - + if (m_MPScount) { bit = 0; @@ -128,7 +128,7 @@ UINT8 SDD1__BG::BG_getBit(UINT8 *ROM, UINT32 *mmc, UINT8* endOfRun) bit = 1; m_LPSind = 0; } - + if (m_MPScount || m_LPSind) { (*endOfRun) = 0; @@ -137,7 +137,7 @@ UINT8 SDD1__BG::BG_getBit(UINT8 *ROM, UINT32 *mmc, UINT8* endOfRun) { (*endOfRun) = 1; } - + return bit; } @@ -200,14 +200,14 @@ UINT8 SDD1__PEM::PEM_getBit(UINT8 *ROM, UINT32 *mmc, UINT8 context) { UINT8 endOfRun; UINT8 bit; - + SDD1__PEM_ContextInfo *pContInfo = &(m_contextInfo)[context]; UINT8 currStatus = pContInfo->status; const SDD1__PEM_state* pState = &(PEM_evolution_table[currStatus]); UINT8 currentMPS = pContInfo->MPS; - + bit = m_BG[pState->code_num]->BG_getBit(ROM, mmc, &endOfRun); - + if (endOfRun) { if (bit) @@ -223,7 +223,7 @@ UINT8 SDD1__PEM::PEM_getBit(UINT8 *ROM, UINT32 *mmc, UINT8 context) pContInfo->status = pState->nextIfMPS; } } - + return bit ^ currentMPS; } @@ -258,7 +258,7 @@ UINT8 SDD1__CM::CM_getBit(UINT8 *ROM, UINT32 *mmc) UINT8 currContext; UINT16 *context_bits; UINT8 bit = 0; - + switch (m_bitplanesInfo) { case 0x00: @@ -278,9 +278,9 @@ UINT8 SDD1__CM::CM_getBit(UINT8 *ROM, UINT32 *mmc) m_currBitplane = m_bit_number & 0x07; break; } - + context_bits = &(m_prevBitplaneBits)[m_currBitplane]; - + currContext = (m_currBitplane & 0x01) << 4; switch (m_contextBitsInfo) { @@ -297,14 +297,14 @@ UINT8 SDD1__CM::CM_getBit(UINT8 *ROM, UINT32 *mmc) currContext |= ((*context_bits & 0x0180) >> 5) | (*context_bits & 0x0003); break; } - + bit = m_PEM->PEM_getBit(ROM, mmc, currContext); - + *context_bits <<= 1; *context_bits |= bit; - + m_bit_number++; - + return bit; } @@ -321,7 +321,7 @@ void SDD1__OL::OL_launch(UINT8 *ROM, UINT32 *mmc) { UINT8 i; UINT8 register1 = 0, register2 = 0; - + switch (m_bitplanesInfo) { case 0x00: @@ -341,7 +341,7 @@ void SDD1__OL::OL_launch(UINT8 *ROM, UINT32 *mmc) { if (m_CM->CM_getBit(ROM, mmc)) register1 |= i; - + if (m_CM->CM_getBit(ROM, mmc)) register2 |= i; } @@ -381,7 +381,7 @@ SDD1__emu::SDD1__emu(running_machine &machine) m_BG6 = auto_alloc(machine, SDD1__BG(m_GCD, 6)); m_BG7 = auto_alloc(machine, SDD1__BG(m_GCD, 7)); m_PEM = auto_alloc(machine, SDD1__PEM(m_BG0, m_BG1, m_BG2, m_BG3, - m_BG4, m_BG5, m_BG6, m_BG7)); + m_BG4, m_BG5, m_BG6, m_BG7)); m_CM = auto_alloc(machine, SDD1__CM(m_PEM)); m_OL = auto_alloc(machine, SDD1__OL(m_CM)); } @@ -400,7 +400,7 @@ void SDD1__emu::SDD1emu_decompress(UINT8 *ROM, UINT32 *mmc, UINT32 in_buf, UINT1 m_PEM->PEM_prepareDecomp(); m_CM->CM_prepareDecomp(ROM, mmc, in_buf); m_OL->OL_prepareDecomp(ROM, mmc, in_buf, out_len, out_buf); - + m_OL->OL_launch(ROM, mmc); } @@ -428,23 +428,23 @@ sns_rom_sdd1_device::sns_rom_sdd1_device(const machine_config &mconfig, const ch void sns_rom_sdd1_device::device_start() { UINT8 i; - + m_sdd1_enable = 0x00; m_xfer_enable = 0x00; - + m_mmc[0] = 0 << 20; m_mmc[1] = 1 << 20; m_mmc[2] = 2 << 20; m_mmc[3] = 3 << 20; - + for(i = 0; i < 8; i++) { m_dma[i].addr = 0; m_dma[i].size = 0; } - + m_sdd1emu = auto_alloc(machine(), SDD1__emu(machine())); - + m_buffer.data = (UINT8*)auto_alloc_array(machine(), UINT8, 0x10000); m_buffer.ready = 0; @@ -461,7 +461,7 @@ void sns_rom_sdd1_device::device_start() READ8_MEMBER( sns_rom_sdd1_device::chip_read ) { UINT16 addr = offset & 0xffff; - + switch (addr) { case 0x4804: @@ -473,8 +473,8 @@ READ8_MEMBER( sns_rom_sdd1_device::chip_read ) case 0x4807: return (m_mmc[3] >> 20) & 7; } - -// we should never get here, but... + +// we should never get here, but... return 0; } @@ -482,7 +482,7 @@ READ8_MEMBER( sns_rom_sdd1_device::chip_read ) WRITE8_MEMBER( sns_rom_sdd1_device::chip_write ) { UINT16 addr = offset & 0xffff; - + if ((addr & 0x4380) == 0x4300) { UINT8 channel = (addr >> 4) & 7; @@ -507,7 +507,7 @@ WRITE8_MEMBER( sns_rom_sdd1_device::chip_write ) } return; } - + switch(addr) { case 0x4800: @@ -516,7 +516,7 @@ WRITE8_MEMBER( sns_rom_sdd1_device::chip_write ) case 0x4801: m_xfer_enable = data; break; - + case 0x4804: m_mmc[0] = (data & 7) << 20; break; @@ -530,7 +530,7 @@ WRITE8_MEMBER( sns_rom_sdd1_device::chip_write ) m_mmc[3] = (data & 7) << 20; break; } - + } UINT8 sns_rom_sdd1_device::read_helper(UINT32 addr) @@ -552,14 +552,14 @@ UINT8 sns_rom_sdd1_device::read_helper(UINT32 addr) // this really should stream byte-by-byte, but it's not necessary since the size is known m_buffer.offset = 0; m_buffer.size = m_dma[i].size ? m_dma[i].size : 65536; - + // SDD1_emu calls this function; it needs to access uncompressed data; // so temporarily disable decompression mode for decompress() call. m_sdd1emu->SDD1emu_decompress(m_rom, m_mmc, addr, m_buffer.size, m_buffer.data); - + m_buffer.ready = 1; } - + // fetch a decompressed byte; once buffer is depleted, disable channel and invalidate buffer data = m_buffer.data[(UINT16)m_buffer.offset++]; if (m_buffer.offset >= m_buffer.size) @@ -567,7 +567,7 @@ UINT8 sns_rom_sdd1_device::read_helper(UINT32 addr) m_buffer.ready = 0; m_xfer_enable &= ~(1 << i); } - + return data; } } @@ -597,6 +597,6 @@ READ8_MEMBER(sns_rom_sdd1_device::read_h) WRITE8_MEMBER(sns_rom_sdd1_device::write_l) { - if (offset >= 0x700000 && (offset & 0xffff) < 0x8000 && m_nvram_size > 0) // SRAM + if (offset >= 0x700000 && (offset & 0xffff) < 0x8000 && m_nvram_size > 0) // SRAM m_nvram[offset & 0x1fff] = data; } diff --git a/src/mess/machine/sns_sdd1.h b/src/mess/machine/sns_sdd1.h index d00d4e78196..2c8c75e4027 100644 --- a/src/mess/machine/sns_sdd1.h +++ b/src/mess/machine/sns_sdd1.h @@ -9,10 +9,10 @@ class SDD1__IM //Input Manager { public: SDD1__IM() {} - + UINT32 m_byte_ptr; UINT8 m_bit_count; - + void IM_prepareDecomp(UINT32 in_buf); UINT8 IM_getCodeword(UINT8 *ROM, UINT32 *mmc, const UINT8 code_len); }; @@ -22,9 +22,9 @@ class SDD1__GCD //Golomb-Code Decoder public: SDD1__GCD(SDD1__IM* associatedIM) : m_IM(associatedIM) { } - + SDD1__IM* m_IM; - + void GCD_getRunCount(UINT8 *ROM, UINT32 *mmc, UINT8 code_num, UINT8* MPScount, UINT8* LPSind); }; @@ -34,12 +34,12 @@ public: SDD1__BG(SDD1__GCD* associatedGCD, UINT8 code) : m_code_num(code), m_GCD(associatedGCD) { } - + UINT8 m_code_num; UINT8 m_MPScount; UINT8 m_LPSind; SDD1__GCD* m_GCD; - + void BG_prepareDecomp(); UINT8 BG_getBit(UINT8 *ROM, UINT32 *mmc, UINT8* endOfRun); } ; @@ -54,10 +54,10 @@ class SDD1__PEM //Probability Estimation Module { public: SDD1__PEM( - SDD1__BG* associatedBG0, SDD1__BG* associatedBG1, - SDD1__BG* associatedBG2, SDD1__BG* associatedBG3, - SDD1__BG* associatedBG4, SDD1__BG* associatedBG5, - SDD1__BG* associatedBG6, SDD1__BG* associatedBG7) + SDD1__BG* associatedBG0, SDD1__BG* associatedBG1, + SDD1__BG* associatedBG2, SDD1__BG* associatedBG3, + SDD1__BG* associatedBG4, SDD1__BG* associatedBG5, + SDD1__BG* associatedBG6, SDD1__BG* associatedBG7) { m_BG[0] = associatedBG0; m_BG[1] = associatedBG1; @@ -68,10 +68,10 @@ public: m_BG[6] = associatedBG6; m_BG[7] = associatedBG7; } - + SDD1__PEM_ContextInfo m_contextInfo[32]; SDD1__BG* m_BG[8]; - + void PEM_prepareDecomp(); UINT8 PEM_getBit(UINT8 *ROM, UINT32 *mmc, UINT8 context); } ; @@ -82,14 +82,14 @@ class SDD1__CM public: SDD1__CM(SDD1__PEM* associatedPEM) : m_PEM(associatedPEM) { } - + UINT8 m_bitplanesInfo; UINT8 m_contextBitsInfo; UINT8 m_bit_number; UINT8 m_currBitplane; UINT16 m_prevBitplaneBits[8]; SDD1__PEM* m_PEM; - + void CM_prepareDecomp(UINT8 *ROM, UINT32 *mmc, UINT32 first_byte); UINT8 CM_getBit(UINT8 *ROM, UINT32 *mmc); } ; @@ -100,12 +100,12 @@ class SDD1__OL public: SDD1__OL(SDD1__CM* associatedCM) : m_CM(associatedCM) { } - + UINT8 m_bitplanesInfo; UINT16 m_length; UINT8* m_buffer; SDD1__CM* m_CM; - + void OL_prepareDecomp(UINT8 *ROM, UINT32 *mmc, UINT32 first_byte, UINT16 out_len, UINT8 *out_buf); void OL_launch(UINT8 *ROM, UINT32 *mmc); } ; @@ -114,9 +114,9 @@ class SDD1__emu { public: SDD1__emu(running_machine &machine); - + running_machine &machine() const { return m_machine; } - + SDD1__IM* m_IM; SDD1__GCD* m_GCD; SDD1__BG* m_BG0; SDD1__BG* m_BG1; SDD1__BG* m_BG2; SDD1__BG* m_BG3; @@ -124,9 +124,9 @@ public: SDD1__PEM* m_PEM; SDD1__CM* m_CM; SDD1__OL* m_OL; - + void SDD1emu_decompress(UINT8 *ROM, UINT32 *mmc, UINT32 in_buf, UINT16 out_len, UINT8 *out_buf); - + private: running_machine& m_machine; }; @@ -136,13 +136,13 @@ private: // ======================> sns_rom_sdd1_device class sns_rom_sdd1_device : public device_t, - public device_sns_cart_interface + public device_sns_cart_interface { public: // construction/destruction sns_rom_sdd1_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock); sns_rom_sdd1_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // device-level overrides virtual void device_start(); virtual void device_config_complete() { m_shortname = "sns_rom_sdd1"; } @@ -159,13 +159,13 @@ public: UINT8 m_sdd1_enable; // channel bit-mask UINT8 m_xfer_enable; // channel bit-mask UINT32 m_mmc[4]; // memory map controller ROM indices - + struct { UINT32 addr; // $43x2-$43x4 -- DMA transfer address UINT16 size; // $43x5-$43x6 -- DMA transfer size } m_dma[8]; - + SDD1__emu* m_sdd1emu; struct diff --git a/src/mess/machine/sns_sfx.c b/src/mess/machine/sns_sfx.c index 9129e8f9490..6fc35228b75 100644 --- a/src/mess/machine/sns_sfx.c +++ b/src/mess/machine/sns_sfx.c @@ -1,10 +1,10 @@ /*********************************************************************************************************** - + SuperFX add-on chip emulation (for SNES/SFC) - + Copyright MESS Team. Visit http://mamedev.org for licensing and usage restrictions. - + ***********************************************************************************************************/ @@ -110,13 +110,13 @@ WRITE8_MEMBER( sns_rom_superfx_device::chip_write ) READ8_MEMBER( sns_rom_superfx_device::read_l ) { UINT16 address = offset & 0xffff; - + if (offset < 0x400000) { if (address >= 0x6000 && address < 0x8000) { if (superfx_access_ram(m_superfx)) - return sfx_ram[offset & 0x1fff]; + return sfx_ram[offset & 0x1fff]; } if (address >= 0x8000) return m_rom[rom_bank_map[offset / 0x10000] * 0x8000 + (offset & 0x7fff)]; @@ -139,10 +139,10 @@ READ8_MEMBER( sns_rom_superfx_device::read_l ) else { if (superfx_access_ram(m_superfx)) - return sfx_ram[offset & 0xfffff]; + return sfx_ram[offset & 0xfffff]; } - - return 0xff; // should be open bus... + + return 0xff; // should be open bus... } @@ -167,13 +167,13 @@ WRITE8_MEMBER( sns_rom_superfx_device::write_l ) READ8_MEMBER(sns_rom_superfx_device::read_h) { UINT16 address = offset & 0xffff; - + if (offset < 0x400000) { if (address >= 0x6000 && address < 0x8000) { if (superfx_access_ram(m_superfx)) - return sfx_ram[offset & 0x1fff]; + return sfx_ram[offset & 0x1fff]; } if (address >= 0x8000) return m_rom[rom_bank_map[offset / 0x10000] * 0x8000 + (offset & 0x7fff)]; @@ -196,10 +196,10 @@ READ8_MEMBER(sns_rom_superfx_device::read_h) else { if (superfx_access_ram(m_superfx)) - return sfx_ram[offset & 0xfffff]; + return sfx_ram[offset & 0xfffff]; } - - return 0xff; // should be open bus... + + return 0xff; // should be open bus... } WRITE8_MEMBER( sns_rom_superfx_device::write_h ) @@ -219,4 +219,3 @@ WRITE8_MEMBER( sns_rom_superfx_device::write_h ) sfx_ram[offset & 0xfffff] = data; } } - diff --git a/src/mess/machine/sns_sfx.h b/src/mess/machine/sns_sfx.h index 0d01c5f0d69..3fea338e76b 100644 --- a/src/mess/machine/sns_sfx.h +++ b/src/mess/machine/sns_sfx.h @@ -13,14 +13,14 @@ class sns_rom_superfx_device : public sns_rom_device public: // construction/destruction sns_rom_superfx_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // device-level overrides virtual void device_start(); virtual void device_config_complete() { m_shortname = "sns_rom_superfx"; } virtual machine_config_constructor device_mconfig_additions() const; - + required_device m_superfx; - + // additional reading and writing virtual DECLARE_READ8_MEMBER(read_l); virtual DECLARE_WRITE8_MEMBER(write_l); @@ -28,7 +28,7 @@ public: virtual DECLARE_WRITE8_MEMBER(write_h); virtual DECLARE_READ8_MEMBER(chip_read); virtual DECLARE_WRITE8_MEMBER(chip_write); - + virtual DECLARE_READ8_MEMBER(superfx_r_bank1); virtual DECLARE_READ8_MEMBER(superfx_r_bank2); virtual DECLARE_READ8_MEMBER(superfx_r_bank3); @@ -36,8 +36,8 @@ public: virtual DECLARE_WRITE8_MEMBER(superfx_w_bank2); virtual DECLARE_WRITE8_MEMBER(superfx_w_bank3); virtual DECLARE_WRITE_LINE_MEMBER(snes_extern_irq_w); - - + + UINT8 sfx_ram[0x200000]; }; diff --git a/src/mess/machine/sns_slot.c b/src/mess/machine/sns_slot.c index e5ce634bdcf..13ca62bbf20 100644 --- a/src/mess/machine/sns_slot.c +++ b/src/mess/machine/sns_slot.c @@ -1,11 +1,11 @@ /*********************************************************************************************************** - + SNES cart emulation (through slot devices) - + ***********************************************************************************************************/ @@ -96,7 +96,7 @@ void device_sns_cart_interface::rtc_ram_alloc(running_machine &machine, UINT32 s //------------------------------------------------- -// addon_bios_alloc - alloc the space for the +// addon_bios_alloc - alloc the space for the // (optional) add-on CPU bios //------------------------------------------------- @@ -111,17 +111,17 @@ void device_sns_cart_interface::addon_bios_alloc(running_machine &machine, UINT3 //------------------------------------------------- -// rom_map_setup - setup map of rom banks in 32K +// rom_map_setup - setup map of rom banks in 32K // blocks, so to simplify ROM access //------------------------------------------------- void device_sns_cart_interface::rom_map_setup(UINT32 size) { int i; - // setup the rom_bank_map array to faster ROM read + // setup the rom_bank_map array to faster ROM read for (i = 0; i < size / 0x8000; i++) rom_bank_map[i] = i; - + // fill up remaining blocks with mirrors while (i % 256) { @@ -135,12 +135,12 @@ void device_sns_cart_interface::rom_map_setup(UINT32 size) } // check bank map! -// for (i = 0; i < 256; i++) -// { -// printf("bank %3d = %3d\t", i, rom_bank_map[i]); -// if ((i%8) == 7) -// printf("\n"); -// } +// for (i = 0; i < 256; i++) +// { +// printf("bank %3d = %3d\t", i, rom_bank_map[i]); +// if ((i%8) == 7) +// printf("\n"); +// } } //************************************************************************** @@ -244,8 +244,8 @@ static const sns_slot slot_list[] = { SNES_STROM, "strom"}, // pirate carts { SNES_POKEMON, "lorom_poke"}, - { SNES_BANANA, "lorom_paja"}, // wip - { SNES_SOULBLAD, "lorom_sbld"} // wip + { SNES_BANANA, "lorom_paja"}, // wip + { SNES_SOULBLAD, "lorom_sbld"} // wip }; static int sns_get_pcb_id(const char *slot) @@ -255,7 +255,7 @@ static int sns_get_pcb_id(const char *slot) if (!mame_stricmp(slot_list[i].slot_option, slot)) return slot_list[i].pcb_id; } - + return 0; } @@ -266,7 +266,7 @@ static const char *sns_get_slot(int type) if (slot_list[i].pcb_id == type) return slot_list[i].slot_option; } - + return "lorom"; } @@ -285,10 +285,10 @@ UINT32 base_sns_cart_slot_device::snes_skip_header( UINT8 *ROM, UINT32 rom_size { UINT8 header[512]; UINT32 offset = 512; - + /* Check for a header (512 bytes) */ memcpy(header, ROM, 512); - + if ((header[8] == 0xaa) && (header[9] == 0xbb) && (header[10] == 0x04)) { /* Found an SWC identifier */ @@ -310,7 +310,7 @@ UINT32 base_sns_cart_slot_device::snes_skip_header( UINT8 *ROM, UINT32 rom_size logerror("No header found.\n"); offset = 0; } - + return offset; } @@ -326,17 +326,17 @@ static int snes_validate_infoblock( UINT8 *infoblock, UINT32 offset ) UINT16 ichecksum = infoblock[offset + 0x1c] | (infoblock[offset + 0x1d] << 8); UINT8 reset_opcode = infoblock[(offset & ~0x7fff) | (reset_vector & 0x7fff)]; //first opcode executed upon reset UINT8 mapper = infoblock[offset + 0x15] & ~0x10; //mask off irrelevant FastROM-capable bit - + /* $00:[000-7fff] contains uninitialized RAM and MMIO. reset vector must point to ROM at $00:[8000-ffff] to be considered valid. */ if (reset_vector < 0x8000) return 0; - + /* some images duplicate the header in multiple locations, and others have completely invalid header information that cannot be relied upon. The code below will analyze the first opcode executed at the specified reset vector to determine the probability that this is the correct header. Score is assigned accordingly. */ - + /* most likely opcodes */ if (reset_opcode == 0x78 //sei || reset_opcode == 0x18 //clc (clc; xce) @@ -346,7 +346,7 @@ static int snes_validate_infoblock( UINT8 *infoblock, UINT32 offset ) || reset_opcode == 0x5c //jml $nnnnnn ) score += 8; - + /* plausible opcodes */ if (reset_opcode == 0xc2 //rep #$nn || reset_opcode == 0xe2 //sep #$nn @@ -361,7 +361,7 @@ static int snes_validate_infoblock( UINT8 *infoblock, UINT32 offset ) || reset_opcode == 0x22 //jsl $nnnnnn ) score += 4; - + /* implausible opcodes */ if (reset_opcode == 0x40 //rti || reset_opcode == 0x60 //rts @@ -371,7 +371,7 @@ static int snes_validate_infoblock( UINT8 *infoblock, UINT32 offset ) || reset_opcode == 0xcc //cpy $nnnn ) score -= 4; - + /* least likely opcodes */ if (reset_opcode == 0x00 //brk #$nn || reset_opcode == 0x02 //cop #$nn @@ -380,47 +380,47 @@ static int snes_validate_infoblock( UINT8 *infoblock, UINT32 offset ) || reset_opcode == 0xff //sbc $nnnnnn,x ) score -= 8; - + /* Sometimes, both the header and reset vector's first opcode will match ... fallback and rely on info validity in these cases to determine more likely header. */ - + /* a valid checksum is the biggest indicator of a valid header. */ if ((checksum + ichecksum) == 0xffff && (checksum != 0) && (ichecksum != 0)) score += 4; - + /* then there are the expected mapper values */ if (offset == 0x007fc0 && mapper == 0x20) // 0x20 is usually LoROM score += 2; - + if (offset == 0x00ffc0 && mapper == 0x21) // 0x21 is usually HiROM score += 2; - + if (offset == 0x007fc0 && mapper == 0x22) // 0x22 is usually ExLoROM score += 2; - + if (offset == 0x40ffc0 && mapper == 0x25) // 0x25 is usually ExHiROM score += 2; - + /* finally, there are valid values in the Company, Region etc. fields */ if (infoblock[offset + 0x1a] == 0x33) // Company field: 0x33 indicates extended header score += 2; - + if (infoblock[offset + 0x16] < 0x08) // ROM Type field score++; - + if (infoblock[offset + 0x17] < 0x10) // ROM Size field score++; - + if (infoblock[offset + 0x18] < 0x08) // SRAM Size field score++; - + if (infoblock[offset + 0x19] < 14) // Region field score++; - + /* do we still have a positive score? */ if (score < 0) score = 0; - + return score; } @@ -445,20 +445,20 @@ static UINT32 snes_find_hilo_mode( UINT8 *buffer, UINT32 buf_len ) /* Images larger than 32mbits are likely ExHiRom */ if (valid_mode25) valid_mode25 += 4; - + if ((valid_mode20 >= valid_mode21) && (valid_mode20 >= valid_mode25)) - retvalue = 0x007fc0; + retvalue = 0x007fc0; else if (valid_mode21 >= valid_mode25) retvalue = 0x00ffc0; else retvalue = 0x40ffc0; - + logerror( "\t HiROM/LoROM id: %s (LoROM: %d , HiROM: %d, ExHiROM: %d)\n", - (retvalue == 0x007fc0) ? "LoROM" : - (retvalue == 0x00ffc0) ? "HiROM" : - (retvalue == 0x40ffc0) ? "ExHiROM" : "Other", - valid_mode20, valid_mode21, valid_mode25); - + (retvalue == 0x007fc0) ? "LoROM" : + (retvalue == 0x00ffc0) ? "HiROM" : + (retvalue == 0x40ffc0) ? "ExHiROM" : "Other", + valid_mode20, valid_mode21, valid_mode25); + return retvalue; } @@ -472,23 +472,23 @@ static int snes_find_addon_chip( UINT8 *buffer, UINT32 start_offs ) case 0x01: case 0x02: break; - + case 0x03: if (buffer[start_offs + 0x15] == 0x30) return SNES_DSP4; else return SNES_DSP; - + case 0x04: return SNES_DSP; - + case 0x05: // DSP2 can be detected by (buffer[start_offs + 0x15] == 0x20) - // DSP3 is harder to detect, and one has to rely on the manufacturer (Bandai) + // DSP3 is harder to detect, and one has to rely on the manufacturer (Bandai) // by checking (buffer[start_offs + 0x15] == 0x30) && (buffer[start_offs + 0x1a] == 0xb2) // in other cases is DSP1, but we do treat all these together... return SNES_DSP; - + case 0x13: // Mario Chip 1 case 0x14: // GSU-x case 0x15: // GSU-x @@ -496,41 +496,41 @@ static int snes_find_addon_chip( UINT8 *buffer, UINT32 start_offs ) if (buffer[start_offs + 0x15] == 0x20) return SNES_SFX; break; - + case 0x25: return SNES_OBC1; - + case 0x32: // needed by a Sample game (according to ZSNES) case 0x34: case 0x35: if (buffer[start_offs + 0x15] == 0x23) return SNES_SA1; break; - + case 0x43: case 0x45: if (buffer[start_offs + 0x15] == 0x32) return SNES_SDD1; break; - + case 0x55: if (buffer[start_offs + 0x15] == 0x35) return SNES_SRTC; break; - + case 0xe3: return SNES_Z80GB; - + case 0xf3: return SNES_CX4; - + case 0xf5: if (buffer[start_offs + 0x15] == 0x30) return SNES_ST018; else if (buffer[start_offs + 0x15] == 0x3a) return SNES_SPC7110; break; - + case 0xf6: /* These Seta ST-01X chips have both 0x30 at 0xffd5, they only differ for the 'size' at 0xffd7 */ @@ -538,12 +538,12 @@ static int snes_find_addon_chip( UINT8 *buffer, UINT32 start_offs ) return SNES_ST011; else return SNES_ST010; - + case 0xf9: if (buffer[start_offs + 0x15] == 0x3a) return SNES_SPC7110_RTC; break; - + default: break; } @@ -585,7 +585,7 @@ bool base_sns_cart_slot_device::call_load() m_cart->rom_map_setup(len); - // check for on-cart CPU bios + // check for on-cart CPU bios if (software_entry() != NULL) { if (get_software_region("addon")) @@ -605,10 +605,10 @@ bool base_sns_cart_slot_device::call_load() else m_type = sns_get_pcb_id(slot_name); } - + setup_custom_mappers(); - + setup_nvram(); if (m_cart->get_nvram_size() || m_cart->get_rtc_ram_size()) @@ -620,18 +620,18 @@ bool base_sns_cart_slot_device::call_load() memcpy(m_cart->get_nvram_base(), temp_nvram, m_cart->get_nvram_size()); if (m_cart->get_rtc_ram_size()) memcpy(m_cart->get_rtc_ram_base(), temp_nvram + m_cart->get_nvram_size(), m_cart->get_rtc_ram_size()); - + if (temp_nvram) auto_free(machine(), temp_nvram); } - + printf("Type %d\n", m_type); internal_header_logging(ROM, len); return IMAGE_INIT_PASS; } - + return IMAGE_INIT_PASS; } @@ -652,7 +652,7 @@ void base_sns_cart_slot_device::call_unload() memcpy(temp_nvram, m_cart->get_nvram_base(), m_cart->get_nvram_size()); if (m_cart->get_rtc_ram_size()) memcpy(temp_nvram + m_cart->get_nvram_size(), m_cart->get_rtc_ram_base(), m_cart->get_rtc_ram_size()); - + battery_save(temp_nvram, tot_size); if (temp_nvram) auto_free(machine(), temp_nvram); @@ -676,7 +676,7 @@ void base_sns_cart_slot_device::setup_nvram() UINT8 sram_size = (m_type == SNES_SFX) ? (ROM[0x00ffbd] & 0x07) : (ROM[hilo_mode + 0x18] & 0x07); if (sram_size) { - UINT32 max = (hilo_mode == 0x007fc0) ? 0x80000 : 0x20000; // MODE20 vs MODE21 + UINT32 max = (hilo_mode == 0x007fc0) ? 0x80000 : 0x20000; // MODE20 vs MODE21 size = 1024 << (ROM[0x00ffbd] & 0x07); if (size > max) size = max; @@ -729,12 +729,12 @@ int base_sns_cart_slot_device::get_cart_type(UINT8 *ROM, UINT32 len) break; case 0x00ffc0: // HiRom case 0x40ffc0: // ExHiRom - type = SNES_MODE21; + type = SNES_MODE21; break; default: break; } - + // detect Sufami Turbo... if (type == SNES_MODE20 && !memcmp(ROM, "BANDAI SFC-ADX", 14)) { @@ -757,7 +757,7 @@ int base_sns_cart_slot_device::get_cart_type(UINT8 *ROM, UINT32 len) type = SNES_BSMEMPAK; } } - + // check for add-on chips... if (len >= hilo_mode + 0x1a) { @@ -808,13 +808,13 @@ const char * base_sns_cart_slot_device::get_default_card_software(const machine_ int type; core_fread(m_file, ROM, len); - + type = get_cart_type(ROM, len); slot_string = sns_get_slot(type); - + global_free(ROM); clear(); - + return slot_string; } @@ -882,7 +882,7 @@ WRITE8_MEMBER(base_sns_cart_slot_device::chip_write) static int char_to_int_conv( char id ) { int value; - + if (id == '1') value = 0x01; else if (id == '2') value = 0x02; else if (id == '3') value = 0x03; @@ -899,7 +899,7 @@ static int char_to_int_conv( char id ) else if (id == 'E') value = 0x0e; else if (id == 'F') value = 0x0f; else value = 0x00; - + return value; } @@ -939,7 +939,7 @@ void base_sns_cart_slot_device::internal_header_logging(UINT8 *ROM, UINT32 len) UNK, UNK }; - + /* Some known countries */ static const char *const countries[] = { @@ -948,7 +948,7 @@ void base_sns_cart_slot_device::internal_header_logging(UINT8 *ROM, UINT32 len) /* 8*/ "Spain (PAL)", "Germany, Austria & Switzerland (PAL)", "Italy (PAL)", "Hong Kong & China (PAL)", /* c*/ "Indonesia (PAL)", "South Korea (NTSC)", UNK, UNK, }; - + /* Some known companies (integrations to the list from Snes9x) */ static const char *const companies[] = { @@ -1007,7 +1007,7 @@ void base_sns_cart_slot_device::internal_header_logging(UINT8 *ROM, UINT32 len) default: break; } - + // detect Sufami Turbo... if (type == SNES_MODE20 && !memcmp(ROM, "BANDAI SFC-ADX", 14)) { @@ -1016,7 +1016,7 @@ void base_sns_cart_slot_device::internal_header_logging(UINT8 *ROM, UINT32 len) else type = SNES_STROM; } - + // detect BS-X Base Cart if (!memcmp(ROM + hilo_mode, "Satellaview BS-X ", 21)) type = SNES_BSX; @@ -1030,7 +1030,7 @@ void base_sns_cart_slot_device::internal_header_logging(UINT8 *ROM, UINT32 len) type = SNES_BSMEMPAK; } } - + addon = snes_find_addon_chip(ROM, hilo_mode); if (addon != -1) { @@ -1041,59 +1041,59 @@ void base_sns_cart_slot_device::internal_header_logging(UINT8 *ROM, UINT32 len) else type = addon; } - + /* Company */ for (int i = 0; i < 2; i++) company_id[i] = ROM[hilo_mode - 0x10 + i]; company = (char_to_int_conv(company_id[0]) << 4) + char_to_int_conv(company_id[1]); if (company == 0) company = ROM[hilo_mode + 0x1a]; - + /* ROM ID */ for(int i = 0; i < 4; i++ ) rom_id[i] = ROM[hilo_mode - 0x0d + i]; - + /* Title */ for(int i = 0; i < 21; i++ ) title[i] = ROM[hilo_mode + i]; - + /* RAM */ if (((ROM[hilo_mode + 0x16] & 0xf) == 1) || ((ROM[hilo_mode + 0x16] & 0xf) == 2) || ((ROM[hilo_mode + 0x16] & 0xf) == 4) || ((ROM[hilo_mode + 0x16] & 0xf) == 5)) has_ram = 1; - + /* SRAM */ if (((ROM[hilo_mode + 0x16] & 0xf) == 2) || ((ROM[hilo_mode + 0x16] & 0xf) == 5) || ((ROM[hilo_mode + 0x16] & 0xf) == 6)) has_sram = 1; - + logerror( "ROM DETAILS\n" ); logerror( "===========\n\n" ); logerror( "\tTotal blocks: 0x%x\n", len); logerror( "\tROM bank size: %s \n", - (type == SNES_MODE20) ? "LoROM" : - (type == SNES_MODE21) ? "HiROM" : - (type == SNES_MODE22) ? "ExLoROM" : - (type == SNES_MODE25) ? "ExHiROM" : "Other (BSX or ST)" ); + (type == SNES_MODE20) ? "LoROM" : + (type == SNES_MODE21) ? "HiROM" : + (type == SNES_MODE22) ? "ExLoROM" : + (type == SNES_MODE25) ? "ExHiROM" : "Other (BSX or ST)" ); logerror( "\tCompany: %s [%.2s]\n", companies[company], company_id ); logerror( "\tROM ID: %.4s\n\n", rom_id ); - + logerror( "HEADER DETAILS\n" ); logerror( "==============\n\n" ); logerror( "\tName: %.21s\n", title ); logerror( "\tSpeed: %s [%d]\n", (ROM[hilo_mode + 0x15] & 0xf0) ? "FastROM" : "SlowROM", (ROM[hilo_mode + 0x15] & 0xf0) >> 4); logerror( "\tBank size: %s [%d]\n", (ROM[hilo_mode + 0x15] & 0xf) ? "HiROM" : "LoROM", ROM[hilo_mode + 0x15] & 0xf); - + logerror( "\tType: %s", cart_types[type]); if (has_ram) logerror( ", RAM"); if (has_sram) logerror( ", SRAM"); logerror( " [%d]\n", ROM[hilo_mode + 0x16]); - + logerror( "\tSize: %d megabits [%d]\n", 1 << (ROM[hilo_mode + 0x17] - 7), ROM[hilo_mode + 0x17]); logerror( "\tSRAM: %d kilobits [%d]\n", ROM[hilo_mode + 0x18] * 8, ROM[hilo_mode + 0x18] ); logerror( "\tCountry: %s [%d]\n", countries[ROM[hilo_mode + 0x19]], ROM[hilo_mode + 0x19]); @@ -1103,6 +1103,6 @@ void base_sns_cart_slot_device::internal_header_logging(UINT8 *ROM, UINT32 len) logerror( "\tChecksum: %X %X\n", ROM[hilo_mode + 0x1f], ROM[hilo_mode + 0x1e]); logerror( "\tNMI Address: %2X%2Xh\n", ROM[hilo_mode + 0x2b], ROM[hilo_mode + 0x2a]); logerror( "\tStart Address: %2X%2Xh\n\n", ROM[hilo_mode + 0x2d], ROM[hilo_mode + 0x2c]); - + logerror( "\tMode: %d\n", type); } diff --git a/src/mess/machine/sns_slot.h b/src/mess/machine/sns_slot.h index 3504aa32018..da1510a112c 100644 --- a/src/mess/machine/sns_slot.h +++ b/src/mess/machine/sns_slot.h @@ -11,8 +11,8 @@ enum { SNES_MODE20 = 0, SNES_MODE21, - SNES_MODE22, // ExLoROM - not used anymore in emulation (only to log info), will be removed - SNES_MODE25, // ExHiROM - not used anymore in emulation (only to log info), will be removed + SNES_MODE22, // ExLoROM - not used anymore in emulation (only to log info), will be removed + SNES_MODE25, // ExHiROM - not used anymore in emulation (only to log info), will be removed SNES_CX4, SNES_DSP, SNES_DSP_MODE21, @@ -36,8 +36,8 @@ enum SNES_STROM, // pirate carts SNES_POKEMON, - SNES_BANANA, // wip - SNES_SOULBLAD // wip + SNES_BANANA, // wip + SNES_SOULBLAD // wip }; @@ -79,18 +79,18 @@ public: virtual UINT32 get_rtc_ram_size() { return m_rtc_ram_size; }; virtual void rom_map_setup(UINT32 size); - + // internal state UINT8 *m_rom; UINT8 *m_nvram; UINT8 *m_bios; - UINT8 *m_rtc_ram; // temp pointer to save RTC ram to nvram (will disappear when RTCs become devices) + UINT8 *m_rtc_ram; // temp pointer to save RTC ram to nvram (will disappear when RTCs become devices) UINT32 m_rom_size; UINT32 m_nvram_size; UINT32 m_bios_size; - UINT32 m_rtc_ram_size; // temp + UINT32 m_rtc_ram_size; // temp - UINT8 rom_bank_map[256]; // 32K chunks of rom + UINT8 rom_bank_map[256]; // 32K chunks of rom }; @@ -105,11 +105,11 @@ public: // construction/destruction base_sns_cart_slot_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock); virtual ~base_sns_cart_slot_device(); - + // device-level overrides virtual void device_start(); virtual void device_config_complete(); - + // image-level overrides virtual bool call_load(); virtual void call_unload(); @@ -146,8 +146,8 @@ public: // this should be private, but then there is some problem installing delegates in the driver... //private: - device_sns_cart_interface* m_cart; - + device_sns_cart_interface* m_cart; + int m_type; }; diff --git a/src/mess/machine/sns_spc7110.c b/src/mess/machine/sns_spc7110.c index 3bf57cce652..5c2d655024c 100644 --- a/src/mess/machine/sns_spc7110.c +++ b/src/mess/machine/sns_spc7110.c @@ -1,18 +1,18 @@ /*********************************************************************************************************** - + SPC-7110 add-on chip emulation (for SNES/SFC) - + Based on C++ implementation by Byuu in BSNES. - + Byuu's code is released under GNU General Public License version 2 as published by the Free Software Foundation. The implementation below is released under the MAME license for use in MAME, MESS and derivatives by permission of Byuu - + Copyright (for the implementation below) MESS Team. Visit http://mamedev.org for licensing and usage restrictions. - + ***********************************************************************************************************/ @@ -59,7 +59,7 @@ void sns_rom_spc7110_device::spc7110_start() m_r480a = 0x00; m_r480b = 0x00; m_r480c = 0x00; - + m_r4811 = 0x00; m_r4812 = 0x00; m_r4813 = 0x00; @@ -68,11 +68,11 @@ void sns_rom_spc7110_device::spc7110_start() m_r4816 = 0x00; m_r4817 = 0x00; m_r4818 = 0x00; - + m_r481x = 0x00; m_r4814_latch = 0; m_r4815_latch = 0; - + m_r4820 = 0x00; m_r4821 = 0x00; m_r4822 = 0x00; @@ -89,20 +89,20 @@ void sns_rom_spc7110_device::spc7110_start() m_r482d = 0x00; m_r482e = 0x00; m_r482f = 0x00; - + m_r4830 = 0x00; m_r4831 = 0; - m_dx_offset = spc7110_datarom_addr(0 * 0x100000, 0x200000); // we would need the rom length here... + m_dx_offset = spc7110_datarom_addr(0 * 0x100000, 0x200000); // we would need the rom length here... m_r4832 = 1; - m_ex_offset = spc7110_datarom_addr(1 * 0x100000, 0x200000); // we would need the rom length here... + m_ex_offset = spc7110_datarom_addr(1 * 0x100000, 0x200000); // we would need the rom length here... m_r4833 = 2; - m_fx_offset = spc7110_datarom_addr(2 * 0x100000, 0x200000); // we would need the rom length here... + m_fx_offset = spc7110_datarom_addr(2 * 0x100000, 0x200000); // we would need the rom length here... m_r4834 = 0x00; - + m_r4840 = 0x00; m_r4841 = 0x00; m_r4842 = 0x00; - + m_decomp = auto_alloc(machine(), SPC7110_Decomp(machine())); save_item(NAME(m_ram)); @@ -169,7 +169,7 @@ void sns_rom_spc7110_device::device_start() void sns_rom_spc7110rtc_device::device_start() { memset(rom_bank_map, 0, sizeof(rom_bank_map)); - + spc7110_start(); // RTC @@ -179,8 +179,8 @@ void sns_rom_spc7110rtc_device::device_start() m_rtc_offset = 0; // at this stage, rtc_ram is not yet allocated. this will be fixed when converting RTC to be a separate device. -// spc7110_update_time(0); - +// spc7110_update_time(0); + save_item(NAME(m_rtc_state)); save_item(NAME(m_rtc_mode)); save_item(NAME(m_rtc_index)); @@ -202,7 +202,7 @@ static const UINT8 spc7110_evolution_table[53][4] = { 0x08, 10, 4, 0 }, { 0x03, 12, 5, 0 }, { 0x01, 15, 5, 0 }, - + { 0x5a, 7, 7, 1 }, { 0x3f, 19, 8, 0 }, { 0x2c, 21, 9, 0 }, @@ -216,7 +216,7 @@ static const UINT8 spc7110_evolution_table[53][4] = { 0x04, 32, 17, 0 }, { 0x03, 34, 18, 0 }, { 0x02, 35, 5, 0 }, - + { 0x5a, 20, 20, 1 }, { 0x48, 39, 21, 0 }, { 0x3a, 40, 22, 0 }, @@ -237,7 +237,7 @@ static const UINT8 spc7110_evolution_table[53][4] = { 0x03, 34, 37, 0 }, { 0x02, 35, 38, 0 }, { 0x02, 36, 5, 0 }, - + { 0x58, 39, 40, 1 }, { 0x4d, 47, 41, 0 }, { 0x43, 48, 42, 0 }, @@ -246,7 +246,7 @@ static const UINT8 spc7110_evolution_table[53][4] = { 0x2e, 51, 45, 0 }, { 0x29, 44, 46, 0 }, { 0x25, 45, 24, 0 }, - + { 0x56, 47, 48, 1 }, { 0x4f, 47, 49, 0 }, { 0x47, 48, 50, 0 }, @@ -258,10 +258,10 @@ static const UINT8 spc7110_evolution_table[53][4] = static const UINT8 spc7110_mode2_context_table[32][2] = { { 1, 2 }, - + { 3, 8 }, { 13, 14 }, - + { 15, 16 }, { 17, 18 }, { 19, 20 }, @@ -274,7 +274,7 @@ static const UINT8 spc7110_mode2_context_table[32][2] = { 25, 26 }, { 27, 28 }, { 29, 30 }, - + { 31, 31 }, { 31, 31 }, { 31, 31 }, @@ -291,7 +291,7 @@ static const UINT8 spc7110_mode2_context_table[32][2] = { 31, 31 }, { 31, 31 }, { 31, 31 }, - + { 31, 31 }, }; @@ -300,7 +300,7 @@ SPC7110_Decomp::SPC7110_Decomp(running_machine &machine) { m_decomp_buffer = (UINT8*)auto_alloc_array(machine, UINT8, SPC7110_DECOMP_BUFFER_SIZE); reset(); - + for (int i = 0; i < 256; i++) { #define map(x, y) (((i >> x) & 1) << y) @@ -327,7 +327,7 @@ void SPC7110_Decomp::reset() //mode 3 is invalid; this is treated as a special case to always return 0x00 //set to mode 3 so that reading decomp port before starting first decomp will return 0x00 m_decomp_mode = 3; - + m_decomp_buffer_rdoffset = 0; m_decomp_buffer_wroffset = 0; m_decomp_buffer_length = 0; @@ -337,25 +337,25 @@ void SPC7110_Decomp::init(running_machine &machine, UINT8 *ROM, UINT32 len, UINT { m_decomp_mode = mode; m_decomp_offset = offset; - + m_decomp_buffer_rdoffset = 0; m_decomp_buffer_wroffset = 0; m_decomp_buffer_length = 0; - + //reset context states for (int i = 0; i < 32; i++) { m_context[i].index = 0; m_context[i].invert = 0; } - + switch (m_decomp_mode) { case 0: mode0(1, ROM, len); break; case 1: mode1(1, ROM, len); break; case 2: mode2(1, ROM, len); break; } - + //decompress up to requested output data index while (index--) { @@ -366,7 +366,7 @@ void SPC7110_Decomp::init(running_machine &machine, UINT8 *ROM, UINT32 len, UINT UINT8 SPC7110_Decomp::read(UINT8 *ROM, UINT32 len) { UINT8 data; - + if (m_decomp_buffer_length == 0) { //decompress at least (SPC7110_DECOMP_BUFFER_SIZE / 2) bytes to the buffer @@ -375,20 +375,20 @@ UINT8 SPC7110_Decomp::read(UINT8 *ROM, UINT32 len) case 0: mode0(0, ROM, len); break; - + case 1: mode1(0, ROM, len); break; - + case 2: mode2(0, ROM, len); break; - + default: return 0x00; } } - + data = m_decomp_buffer[m_decomp_buffer_rdoffset++]; m_decomp_buffer_rdoffset &= SPC7110_DECOMP_BUFFER_SIZE - 1; m_decomp_buffer_length--; @@ -416,7 +416,7 @@ void SPC7110_Decomp::mode0(UINT8 init, UINT8 *ROM, UINT32 len) { static UINT8 val, in, span; static INT32 out, inverts, lps, in_count; - + if (init == 1) { out = inverts = lps = 0; @@ -426,7 +426,7 @@ void SPC7110_Decomp::mode0(UINT8 init, UINT8 *ROM, UINT32 len) in_count = 8; return; } - + while (m_decomp_buffer_length < (SPC7110_DECOMP_BUFFER_SIZE >> 1)) { for (int bit = 0; bit < 8; bit++) @@ -440,11 +440,11 @@ void SPC7110_Decomp::mode0(UINT8 init, UINT8 *ROM, UINT32 len) { con += 15; } - + //get prob and mps prob = probability(con); mps = (((out >> 15) & 1) ^ m_context[con].invert); - + //get bit if (val <= span - prob) //mps { @@ -459,15 +459,15 @@ void SPC7110_Decomp::mode0(UINT8 init, UINT8 *ROM, UINT32 len) out = (out << 1) + 1 - mps; flag_lps = 1; } - + //renormalize while (span < 0x7f) { shift++; - + span = (span << 1) + 1; val = (val << 1) + (in >> 7); - + in <<= 1; if (--in_count == 0) { @@ -475,11 +475,11 @@ void SPC7110_Decomp::mode0(UINT8 init, UINT8 *ROM, UINT32 len) in_count = 8; } } - + //update processing info lps = (lps << 1) + flag_lps; inverts = (inverts << 1) + m_context[con].invert; - + //update context state if (flag_lps & toggle_invert(con)) { @@ -494,7 +494,7 @@ void SPC7110_Decomp::mode0(UINT8 init, UINT8 *ROM, UINT32 len) m_context[con].index = next_mps(con); } } - + //save byte write(out); } @@ -505,7 +505,7 @@ void SPC7110_Decomp::mode1(UINT8 init, UINT8 *ROM, UINT32 len) static INT32 pixelorder[4], realorder[4]; static UINT8 in, val, span; static INT32 out, inverts, lps, in_count; - + if (init == 1) { for (int i = 0; i < 4; i++) @@ -519,7 +519,7 @@ void SPC7110_Decomp::mode1(UINT8 init, UINT8 *ROM, UINT32 len) in_count = 8; return; } - + while (m_decomp_buffer_length < (SPC7110_DECOMP_BUFFER_SIZE >> 1)) { UINT16 data; @@ -530,7 +530,7 @@ void SPC7110_Decomp::mode1(UINT8 init, UINT8 *ROM, UINT32 len) UINT32 b = ((out >> (7 * 2)) & 3); UINT32 c = ((out >> (8 * 2)) & 3); UINT32 con = (a == b) ? (b != c) : (b == c) ? 2 : 4 - (a == c); - + //update pixel order UINT32 m, n; for (m = 0; m < 4; m++) @@ -545,13 +545,13 @@ void SPC7110_Decomp::mode1(UINT8 init, UINT8 *ROM, UINT32 len) pixelorder[n] = pixelorder[n - 1]; } pixelorder[0] = a; - + //calculate the real pixel order for (m = 0; m < 4; m++) { realorder[m] = pixelorder[m]; } - + //rotate reference pixel c value to top for (m = 0; m < 4; m++) { @@ -565,7 +565,7 @@ void SPC7110_Decomp::mode1(UINT8 init, UINT8 *ROM, UINT32 len) realorder[n] = realorder[n - 1]; } realorder[0] = c; - + //rotate reference pixel b value to top for (m = 0; m < 4; m++) { @@ -579,7 +579,7 @@ void SPC7110_Decomp::mode1(UINT8 init, UINT8 *ROM, UINT32 len) realorder[n] = realorder[n - 1]; } realorder[0] = b; - + //rotate reference pixel a value to top for (m = 0; m < 4; m++) { @@ -593,14 +593,14 @@ void SPC7110_Decomp::mode1(UINT8 init, UINT8 *ROM, UINT32 len) realorder[n] = realorder[n - 1]; } realorder[0] = a; - + //get 2 symbols for (int bit = 0; bit < 2; bit++) { //get prob UINT32 prob = probability(con); UINT32 shift = 0; - + //get symbol UINT32 flag_lps; if (val <= span - prob) //mps @@ -614,15 +614,15 @@ void SPC7110_Decomp::mode1(UINT8 init, UINT8 *ROM, UINT32 len) span = prob - 1; flag_lps = 1; } - + //renormalize while (span < 0x7f) { shift++; - + span = (span << 1) + 1; val = (val << 1) + (in >> 7); - + in <<= 1; if (--in_count == 0) { @@ -630,11 +630,11 @@ void SPC7110_Decomp::mode1(UINT8 init, UINT8 *ROM, UINT32 len) in_count = 8; } } - + //update processing info lps = (lps << 1) + flag_lps; inverts = (inverts << 1) + m_context[con].invert; - + //update context state if (flag_lps & toggle_invert(con)) { @@ -648,16 +648,16 @@ void SPC7110_Decomp::mode1(UINT8 init, UINT8 *ROM, UINT32 len) { m_context[con].index = next_mps(con); } - + //get next context con = 5 + (con << 1) + ((lps ^ inverts) & 1); } - + //get pixel b = realorder[(lps ^ inverts) & 3]; out = (out << 2) + b; } - + //turn pixel data into bitplanes data = morton_2x8(out); write(data >> 8); @@ -671,7 +671,7 @@ void SPC7110_Decomp::mode2(UINT8 init, UINT8 *ROM, UINT32 len) static UINT8 bitplanebuffer[16], buffer_index; static UINT8 in, val, span; static INT32 out0, out1, inverts, lps, in_count; - + if (init == 1) { for (int i = 0; i < 16; i++) @@ -686,7 +686,7 @@ void SPC7110_Decomp::mode2(UINT8 init, UINT8 *ROM, UINT32 len) in_count = 8; return; } - + while (m_decomp_buffer_length < (SPC7110_DECOMP_BUFFER_SIZE >> 1)) { UINT32 data; @@ -698,7 +698,7 @@ void SPC7110_Decomp::mode2(UINT8 init, UINT8 *ROM, UINT32 len) UINT32 c = ((out1 >> (0 * 4)) & 15); UINT32 con = 0; UINT32 refcon = (a == b) ? (b != c) : (b == c) ? 2 : 4 - (a == c); - + //update pixel order UINT32 m, n; for (m = 0; m < 16; m++) @@ -713,13 +713,13 @@ void SPC7110_Decomp::mode2(UINT8 init, UINT8 *ROM, UINT32 len) pixelorder[n] = pixelorder[n - 1]; } pixelorder[0] = a; - + //calculate the real pixel order for (m = 0; m < 16; m++) { realorder[m] = pixelorder[m]; } - + //rotate reference pixel c value to top for (m = 0; m < 16; m++) { @@ -733,7 +733,7 @@ void SPC7110_Decomp::mode2(UINT8 init, UINT8 *ROM, UINT32 len) realorder[n] = realorder[n - 1]; } realorder[0] = c; - + //rotate reference pixel b value to top for (m = 0; m < 16; m++) { @@ -747,7 +747,7 @@ void SPC7110_Decomp::mode2(UINT8 init, UINT8 *ROM, UINT32 len) realorder[n] = realorder[n - 1]; } realorder[0] = b; - + //rotate reference pixel a value to top for (m = 0; m < 16; m++) { @@ -761,15 +761,15 @@ void SPC7110_Decomp::mode2(UINT8 init, UINT8 *ROM, UINT32 len) realorder[n] = realorder[n - 1]; } realorder[0] = a; - + //get 4 symbols for (int bit = 0; bit < 4; bit++) { UINT32 invertbit, shift; - + //get prob UINT32 prob = probability(con); - + //get symbol UINT32 flag_lps; if (val <= span - prob) //mps @@ -783,16 +783,16 @@ void SPC7110_Decomp::mode2(UINT8 init, UINT8 *ROM, UINT32 len) span = prob - 1; flag_lps = 1; } - + //renormalize shift = 0; while (span < 0x7f) { shift++; - + span = (span << 1) + 1; val = (val << 1) + (in >> 7); - + in <<= 1; if (--in_count == 0) { @@ -800,12 +800,12 @@ void SPC7110_Decomp::mode2(UINT8 init, UINT8 *ROM, UINT32 len) in_count = 8; } } - + //update processing info lps = (lps << 1) + flag_lps; invertbit = m_context[con].invert; inverts = (inverts << 1) + invertbit; - + //update context state if (flag_lps & toggle_invert(con)) { @@ -819,24 +819,24 @@ void SPC7110_Decomp::mode2(UINT8 init, UINT8 *ROM, UINT32 len) { m_context[con].index = next_mps(con); } - + //get next context con = spc7110_mode2_context_table[con][flag_lps ^ invertbit] + (con == 1 ? refcon : 0); } - + //get pixel b = realorder[(lps ^ inverts) & 0x0f]; out1 = (out1 << 4) + ((out0 >> 28) & 0x0f); out0 = (out0 << 4) + b; } - + //convert pixel data into bitplanes data = morton_4x8(out0); write(data >> 24); write(data >> 16); bitplanebuffer[buffer_index++] = data >> 8; bitplanebuffer[buffer_index++] = data >> 0; - + if (buffer_index == 16) { for (int i = 0; i < 16; i++) @@ -937,16 +937,16 @@ void sns_rom_spc7110_device::spc7110_update_time(UINT8 offset) system_time curtime, *systime = &curtime; machine().current_datetime(curtime); int update = 1; - + m_rtc_offset += offset; - + // TEST: can we go beyond 24hrs of rounding?!? I doubt it will ever go beyond 3600, but I could be wrong... assert(m_rtc_offset < 86400); - + /* do not update if CR0 or CR2 timer disable flags are set */ if ((m_rtc_ram[13] & 0x01) || (m_rtc_ram[15] & 0x03)) update = 0; - + if (update) { /* update time with offset, assuming offset < 3600s */ @@ -954,43 +954,43 @@ void sns_rom_spc7110_device::spc7110_update_time(UINT8 offset) UINT8 minute = systime->local_time.minute; UINT8 hour = systime->local_time.hour; UINT8 mday = systime->local_time.mday; - + while (m_rtc_offset >= 3600) { m_rtc_offset -= 3600; hour++; - + if (hour == 24) { mday++; hour = 0; } } - + while (m_rtc_offset >= 60) { m_rtc_offset -= 60; minute++; - + if (minute == 60) { hour++; minute = 0; } } - + while (m_rtc_offset) { m_rtc_offset -= 1; second++; - + if (second == 60) { minute++; second = 0; } } - + m_rtc_ram[0] = second % 10; m_rtc_ram[1] = second / 10; m_rtc_ram[2] = minute % 10; @@ -1023,14 +1023,14 @@ READ8_MEMBER(sns_rom_spc7110_device::read_l) if (address >= 0x8000) return m_rom[rom_bank_map[offset / 0x8000] * 0x8000 + (offset & 0x7fff)]; } - + return 0xff; } READ8_MEMBER(sns_rom_spc7110_device::read_h) { UINT16 address = offset & 0xfffff; - + if (offset < 0x400000) { if (address >= 0x6000 && address < 0x8000) @@ -1074,13 +1074,13 @@ READ8_MEMBER(sns_rom_spc7110_device::chip_read) UINT8 *ROM = get_rom_base(); UINT32 len = get_rom_size(); UINT16 addr = offset & 0xffff; - + switch (addr) { //================== //decompression unit //================== - + case 0x4800: { UINT16 counter = (m_r4809 + (m_r480a << 8)); @@ -1106,32 +1106,32 @@ READ8_MEMBER(sns_rom_spc7110_device::chip_read) m_r480c &= 0x7f; return status; } - + //============== //data port unit //============== - + case 0x4810: { UINT8 data; UINT32 address, adjust, adjustaddr; - + if (m_r481x != 0x07) return 0x00; - + address = spc7110_data_pointer(); adjust = spc7110_data_adjust(); if (m_r4818 & 8) { adjust = (INT16)adjust; //16-bit sign extend } - + adjustaddr = address; if (m_r4818 & 2) { adjustaddr += adjust; spc7110_set_data_adjust(adjust + 1); } - + data = ROM[spc7110_datarom_addr(adjustaddr, len)]; if (!(m_r4818 & 2)) { @@ -1140,7 +1140,7 @@ READ8_MEMBER(sns_rom_spc7110_device::chip_read) { increment = (INT16)increment; //16-bit sign extend } - + if ((m_r4818 & 16) == 0) { spc7110_set_data_pointer(address + increment); @@ -1150,7 +1150,7 @@ READ8_MEMBER(sns_rom_spc7110_device::chip_read) spc7110_set_data_adjust(adjust + increment); } } - + return data; } case 0x4811: return m_r4811; @@ -1169,14 +1169,14 @@ READ8_MEMBER(sns_rom_spc7110_device::chip_read) { return 0x00; } - + address = spc7110_data_pointer(); adjust = spc7110_data_adjust(); if (m_r4818 & 8) { adjust = (INT16)adjust; //16-bit sign extend } - + data = ROM[spc7110_datarom_addr(address + adjust, len)]; if ((m_r4818 & 0x60) == 0x60) { @@ -1189,14 +1189,14 @@ READ8_MEMBER(sns_rom_spc7110_device::chip_read) spc7110_set_data_adjust(adjust + adjust); } } - + return data; } - + //========= //math unit //========= - + case 0x4820: return m_r4820; case 0x4821: return m_r4821; case 0x4822: return m_r4822; @@ -1218,17 +1218,17 @@ READ8_MEMBER(sns_rom_spc7110_device::chip_read) m_r482f &= 0x7f; return status; } - + //=================== //memory mapping unit //=================== - + case 0x4830: return m_r4830; case 0x4831: return m_r4831; case 0x4832: return m_r4832; case 0x4833: return m_r4833; case 0x4834: return m_r4834; - + //==================== //real-time clock unit //==================== @@ -1238,7 +1238,7 @@ READ8_MEMBER(sns_rom_spc7110_device::chip_read) UINT8 data = 0; if (m_rtc_state == RTCS_Inactive || m_rtc_state == RTCS_ModeSelect) return 0x00; - + m_r4842 = 0x80; data = m_rtc_ram[m_rtc_index]; m_rtc_index = (m_rtc_index + 1) & 15; @@ -1260,13 +1260,13 @@ WRITE8_MEMBER(sns_rom_spc7110_device::chip_write) UINT8 *ROM = get_rom_base(); UINT32 len = get_rom_size(); UINT16 addr = offset & 0xffff; - + switch (addr) { //================== //decompression unit //================== - + case 0x4801: m_r4801 = data; break; case 0x4802: m_r4802 = data; break; case 0x4803: m_r4803 = data; break; @@ -1276,7 +1276,7 @@ WRITE8_MEMBER(sns_rom_spc7110_device::chip_write) { UINT32 table, index, address, mode, offset; m_r4806 = data; - + table = (m_r4801 + (m_r4802 << 8) + (m_r4803 << 16)); index = (m_r4804 << 2); //length = (m_r4809 + (m_r480a << 8)); @@ -1285,22 +1285,22 @@ WRITE8_MEMBER(sns_rom_spc7110_device::chip_write) offset = (ROM[address + 1] << 16) + (ROM[address + 2] << 8) + (ROM[address + 3] << 0); - + m_decomp->init(machine(), ROM, len, mode, offset, (m_r4805 + (m_r4806 << 8)) << mode); m_r480c = 0x80; } break; - + case 0x4807: m_r4807 = data; break; case 0x4808: m_r4808 = data; break; case 0x4809: m_r4809 = data; break; case 0x480a: m_r480a = data; break; case 0x480b: m_r480b = data; break; - + //============== //data port unit //============== - + case 0x4811: m_r4811 = data; m_r481x |= 0x01; break; case 0x4812: m_r4812 = data; m_r481x |= 0x02; break; case 0x4813: m_r4813 = data; m_r481x |= 0x04; break; @@ -1320,7 +1320,7 @@ WRITE8_MEMBER(sns_rom_spc7110_device::chip_write) { break; } - + if ((m_r4818 & 0x60) == 0x20) { UINT32 increment = spc7110_data_adjust() & 0xff; @@ -1341,7 +1341,7 @@ WRITE8_MEMBER(sns_rom_spc7110_device::chip_write) } break; } - + case 0x4815: { m_r4815 = data; @@ -1358,7 +1358,7 @@ WRITE8_MEMBER(sns_rom_spc7110_device::chip_write) { break; } - + if ((m_r4818 & 0x60) == 0x20) { UINT32 increment = spc7110_data_adjust() & 0xff; @@ -1379,23 +1379,23 @@ WRITE8_MEMBER(sns_rom_spc7110_device::chip_write) } break; } - + case 0x4816: m_r4816 = data; break; case 0x4817: m_r4817 = data; break; case 0x4818: { if (m_r481x != 0x07) break; - + m_r4818 = data; m_r4814_latch = m_r4815_latch = 0; break; } - + //========= //math unit //========= - + case 0x4820: m_r4820 = data; break; case 0x4821: m_r4821 = data; break; case 0x4822: m_r4822 = data; break; @@ -1404,13 +1404,13 @@ WRITE8_MEMBER(sns_rom_spc7110_device::chip_write) case 0x4825: { m_r4825 = data; - + if (m_r482e & 1) { //signed 16-bit x 16-bit multiplication INT16 r0 = (INT16)(m_r4824 + (m_r4825 << 8)); INT16 r1 = (INT16)(m_r4820 + (m_r4821 << 8)); - + INT32 result = r0 * r1; m_r4828 = result; m_r4829 = result >> 8; @@ -1422,32 +1422,32 @@ WRITE8_MEMBER(sns_rom_spc7110_device::chip_write) //unsigned 16-bit x 16-bit multiplication UINT16 r0 = (UINT16)(m_r4824 + (m_r4825 << 8)); UINT16 r1 = (UINT16)(m_r4820 + (m_r4821 << 8)); - + UINT32 result = r0 * r1; m_r4828 = result; m_r4829 = result >> 8; m_r482a = result >> 16; m_r482b = result >> 24; } - + m_r482f = 0x80; break; } - + case 0x4826: m_r4826 = data; break; case 0x4827: { m_r4827 = data; - + if (m_r482e & 1) { //signed 32-bit x 16-bit division INT32 dividend = (INT32)(m_r4820 + (m_r4821 << 8) + (m_r4822 << 16) + (m_r4823 << 24)); INT16 divisor = (INT16)(m_r4826 + (m_r4827 << 8)); - + INT32 quotient; INT16 remainder; - + if (divisor) { quotient = (INT32)(dividend / divisor); @@ -1459,12 +1459,12 @@ WRITE8_MEMBER(sns_rom_spc7110_device::chip_write) quotient = 0; remainder = dividend & 0xffff; } - + m_r4828 = quotient; m_r4829 = quotient >> 8; m_r482a = quotient >> 16; m_r482b = quotient >> 24; - + m_r482c = remainder; m_r482d = remainder >> 8; } @@ -1473,10 +1473,10 @@ WRITE8_MEMBER(sns_rom_spc7110_device::chip_write) //unsigned 32-bit x 16-bit division UINT32 dividend = (UINT32)(m_r4820 + (m_r4821 << 8) + (m_r4822 << 16) + (m_r4823 << 24)); UINT16 divisor = (UINT16)(m_r4826 + (m_r4827 << 8)); - + UINT32 quotient; UINT16 remainder; - + if (divisor) { quotient = (UINT32)(dividend / divisor); @@ -1488,20 +1488,20 @@ WRITE8_MEMBER(sns_rom_spc7110_device::chip_write) quotient = 0; remainder = dividend & 0xffff; } - + m_r4828 = quotient; m_r4829 = quotient >> 8; m_r482a = quotient >> 16; m_r482b = quotient >> 24; - + m_r482c = remainder; m_r482d = remainder >> 8; } - + m_r482f = 0x80; break; } - + case 0x482e: { //reset math unit @@ -1509,48 +1509,48 @@ WRITE8_MEMBER(sns_rom_spc7110_device::chip_write) m_r4824 = m_r4825 = m_r4826 = m_r4827 = 0; m_r4828 = m_r4829 = m_r482a = m_r482b = 0; m_r482c = m_r482d = 0; - + m_r482e = data; break; } - + //=================== //memory mapping unit //=================== - + case 0x4830: m_r4830 = data; break; - + case 0x4831: { m_r4831 = data; m_dx_offset = spc7110_datarom_addr(data * 0x100000, len); break; } - + case 0x4832: { m_r4832 = data; m_ex_offset = spc7110_datarom_addr(data * 0x100000, len); break; } - + case 0x4833: { m_r4833 = data; m_fx_offset = spc7110_datarom_addr(data * 0x100000, len); break; } - + case 0x4834: m_r4834 = data; break; - + //==================== //real-time clock unit //==================== - + case 0x4840: { m_r4840 = data; - + if (!(m_r4840 & 1)) { //disable RTC @@ -1565,11 +1565,11 @@ WRITE8_MEMBER(sns_rom_spc7110_device::chip_write) } } break; - + case 0x4841: { m_r4841 = data; - + switch (m_rtc_state) { case RTCS_ModeSelect: @@ -1581,39 +1581,39 @@ WRITE8_MEMBER(sns_rom_spc7110_device::chip_write) m_rtc_index = 0; } break; - + case RTCS_IndexSelect: m_r4842 = 0x80; m_rtc_index = data & 15; if (m_rtc_mode == RTCM_Linear) m_rtc_state = RTCS_Write; break; - + case RTCS_Write: m_r4842 = 0x80; - + //control register 0 if (m_rtc_index == 13) { //increment second counter if (data & 2) spc7110_update_time(1); - + //round minute counter if (data & 8) { spc7110_update_time(0); - + UINT8 second = m_rtc_ram[0] + m_rtc_ram[1] * 10; //clear seconds m_rtc_ram[0] = 0; m_rtc_ram[1] = 0; - + if (second >= 30) spc7110_update_time(60); } } - + //control register 2 if (m_rtc_index == 15) { @@ -1621,17 +1621,17 @@ WRITE8_MEMBER(sns_rom_spc7110_device::chip_write) if ((data & 1) && !(m_rtc_ram[15] & 1)) { spc7110_update_time(0); - + //clear seconds m_rtc_ram[0] = 0; m_rtc_ram[1] = 0; } - + //disable timer if ((data & 2) && !(m_rtc_ram[15] & 2)) spc7110_update_time(0); } - + m_rtc_ram[m_rtc_index] = data & 15; m_rtc_index = (m_rtc_index + 1) & 15; break; @@ -1640,4 +1640,3 @@ WRITE8_MEMBER(sns_rom_spc7110_device::chip_write) break; } } - diff --git a/src/mess/machine/sns_spc7110.h b/src/mess/machine/sns_spc7110.h index 8b9a2afadbf..7321707a288 100644 --- a/src/mess/machine/sns_spc7110.h +++ b/src/mess/machine/sns_spc7110.h @@ -23,18 +23,18 @@ class SPC7110_Decomp { public: SPC7110_Decomp(running_machine &machine); - + running_machine &machine() const { return m_machine; } - + void init(running_machine &machine, UINT8 *ROM, UINT32 len, UINT32 mode, UINT32 offset, UINT32 index); void reset(); - + UINT8 read(UINT8 *ROM, UINT32 len); void write(UINT8 data); void mode0(UINT8 init, UINT8 *ROM, UINT32 len); void mode1(UINT8 init, UINT8 *ROM, UINT32 len); void mode2(UINT8 init, UINT8 *ROM, UINT32 len); - + UINT8 dataread(UINT8 *ROM, UINT32 len); UINT8 probability(UINT32 n); UINT8 next_lps(UINT32 n); @@ -42,25 +42,25 @@ public: UINT8 toggle_invert(UINT32 n); UINT32 morton_2x8(UINT32 data); UINT32 morton_4x8(UINT32 data); - + UINT32 m_decomp_mode; UINT32 m_decomp_offset; - + UINT8 *m_decomp_buffer; UINT32 m_decomp_buffer_rdoffset; UINT32 m_decomp_buffer_wroffset; UINT32 m_decomp_buffer_length; - + struct ContextState { UINT8 index; UINT8 invert; } m_context[32]; - + UINT32 m_morton16[2][256]; UINT32 m_morton32[4][256]; - - + + private: running_machine& m_machine; UINT32 m_rom_size; @@ -74,7 +74,7 @@ public: // construction/destruction sns_rom_spc7110_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock); sns_rom_spc7110_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // device-level overrides virtual void device_start(); virtual void device_config_complete() { m_shortname = "sns_rom_spc7110"; } @@ -95,7 +95,7 @@ public: void spc7110_set_data_pointer(UINT32 addr); void spc7110_set_data_adjust(UINT32 addr); void spc7110_update_time(UINT8 offset); - + //================== //decompression unit @@ -112,9 +112,9 @@ public: UINT8 m_r480a; // compression length high UINT8 m_r480b; // decompression control register UINT8 m_r480c; // decompression status - + SPC7110_Decomp* m_decomp; - + UINT8 m_r4811; // data pointer low UINT8 m_r4812; // data pointer high UINT8 m_r4813; // data pointer bank @@ -123,12 +123,12 @@ public: UINT8 m_r4816; // data increment low UINT8 m_r4817; // data increment high UINT8 m_r4818; // data port control register - + UINT8 m_r481x; - + UINT8 m_r4814_latch; UINT8 m_r4815_latch; - + //========= //math unit //========= @@ -148,7 +148,7 @@ public: UINT8 m_r482d; // 16-bit remainder B1 UINT8 m_r482e; // math control register UINT8 m_r482f; // math status - + //=================== //memory mapping unit //=================== @@ -157,27 +157,27 @@ public: UINT8 m_r4832; // $[e0-ef]:[0000-ffff] mapping UINT8 m_r4833; // $[f0-ff]:[0000-ffff] mapping UINT8 m_r4834; // ??? - + UINT32 m_dx_offset; UINT32 m_ex_offset; UINT32 m_fx_offset; - + //==================== //real-time clock unit //==================== UINT8 m_r4840; // RTC latch UINT8 m_r4841; // RTC index/data port UINT8 m_r4842; // RTC status - + UINT32 m_rtc_state; UINT32 m_rtc_mode; UINT32 m_rtc_index; - + UINT64 m_rtc_offset; //this is now allocated in the main snes cart class, to allow saving to nvram //UINT8 m_rtc_ram[16]; // 0-12 secs, min, hrs, etc.; 13-14-15 control registers - + UINT8 m_ram[0x2000]; }; @@ -188,22 +188,22 @@ class sns_rom_spc7110rtc_device : public sns_rom_spc7110_device public: // construction/destruction sns_rom_spc7110rtc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // device-level overrides virtual void device_start(); virtual void device_config_complete() { m_shortname = "sns_rom_spc7110rtc"; } - + // reading and writing // we just use the spc7110 ones for the moment, pending the split of regs 0x4840-0x4842 (RTC) from the base add-on -// virtual DECLARE_READ8_MEMBER(read_l); -// virtual DECLARE_READ8_MEMBER(read_h); -// virtual DECLARE_WRITE8_MEMBER(write_l); - -// virtual DECLARE_READ8_MEMBER(chip_read); -// virtual DECLARE_WRITE8_MEMBER(chip_write); +// virtual DECLARE_READ8_MEMBER(read_l); +// virtual DECLARE_READ8_MEMBER(read_h); +// virtual DECLARE_WRITE8_MEMBER(write_l); + +// virtual DECLARE_READ8_MEMBER(chip_read); +// virtual DECLARE_WRITE8_MEMBER(chip_write); }; - + // device type definition extern const device_type SNS_HIROM_SPC7110; extern const device_type SNS_HIROM_SPC7110_RTC; diff --git a/src/mess/machine/sns_sufami.c b/src/mess/machine/sns_sufami.c index d04922a7b92..cbe5bc7e675 100644 --- a/src/mess/machine/sns_sufami.c +++ b/src/mess/machine/sns_sufami.c @@ -1,15 +1,15 @@ /*********************************************************************************************************** - + Bandai Sufami Turbo cartridge emulation (for SNES/SFC) - + Copyright MESS Team. Visit http://mamedev.org for licensing and usage restrictions. - + This is basically a standard LoROM cart with two slots for ST minicarts The content of each slot (with ROM and RAM) is mapped to a separate memory range Slot 1: ROM [20-3f][8000-ffff], RAM [60-63][8000-ffff] Slot 2: ROM [40-5f][8000-ffff], RAM [70-73][8000-ffff] - + ***********************************************************************************************************/ @@ -81,32 +81,32 @@ READ8_MEMBER(sns_rom_sufami_device::read_l) READ8_MEMBER(sns_rom_sufami_device::read_h) { - if (offset < 0x200000) // SUFAMI TURBO ROM + if (offset < 0x200000) // SUFAMI TURBO ROM { int bank = offset / 0x10000; return m_rom[rom_bank_map[bank] * 0x8000 + (offset & 0x7fff)]; } - if (offset >= 0x200000 && offset < 0x400000) // SLOT1 STROM + if (offset >= 0x200000 && offset < 0x400000) // SLOT1 STROM { if (m_slot1->m_cart) return m_slot1->m_cart->read_l(space, offset - 0x200000); } - if (offset >= 0x400000 && offset < 0x600000) // SLOT2 STROM + if (offset >= 0x400000 && offset < 0x600000) // SLOT2 STROM { if (m_slot2->m_cart) return m_slot2->m_cart->read_l(space, offset - 0x400000); } - if (offset >= 0x600000 && offset < 0x640000) // SLOT1 RAM + if (offset >= 0x600000 && offset < 0x640000) // SLOT1 RAM { if (m_slot1->m_cart && (offset & 0xffff) > 0x8000) return m_slot1->m_cart->read_h(space, offset - 0x600000); } - if (offset >= 0x700000 && offset < 0x740000) // SLOT2 RAM + if (offset >= 0x700000 && offset < 0x740000) // SLOT2 RAM { if (m_slot2->m_cart && (offset & 0xffff) > 0x8000) return m_slot2->m_cart->read_h(space, offset - 0x700000); } - + return 0xff; } @@ -117,18 +117,18 @@ WRITE8_MEMBER(sns_rom_sufami_device::write_l) WRITE8_MEMBER(sns_rom_sufami_device::write_h) { - if (offset >= 0x600000 && offset < 0x640000) // SLOT1 RAM + if (offset >= 0x600000 && offset < 0x640000) // SLOT1 RAM { if (m_slot1->m_cart && (offset & 0xffff) > 0x8000) return m_slot1->m_cart->write_h(space, offset - 0x600000, data); } - - if (offset >= 0x700000 && offset < 0x740000) // SLOT2 RAM + + if (offset >= 0x700000 && offset < 0x740000) // SLOT2 RAM { if (m_slot2->m_cart && (offset & 0xffff) > 0x8000) return m_slot2->m_cart->write_h(space, offset - 0x700000, data); } - + } /*------------------------------------------------- @@ -172,5 +172,3 @@ WRITE8_MEMBER(sns_rom_strom_device::write_h) m_nvram[bank * 0x8000 + (offset & 0x7fff)] = data; } } - - diff --git a/src/mess/machine/sns_sufami.h b/src/mess/machine/sns_sufami.h index 6bd15af027c..f6878afd9c7 100644 --- a/src/mess/machine/sns_sufami.h +++ b/src/mess/machine/sns_sufami.h @@ -12,12 +12,12 @@ class sns_rom_sufami_device : public sns_rom_device public: // construction/destruction sns_rom_sufami_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // device-level overrides virtual void device_start(); virtual void device_config_complete() { m_shortname = "sns_rom_sufami"; } virtual machine_config_constructor device_mconfig_additions() const; - + // additional reading and writing virtual DECLARE_READ8_MEMBER(read_l); virtual DECLARE_READ8_MEMBER(read_h); @@ -36,16 +36,16 @@ class sns_rom_strom_device : public sns_rom_device public: // construction/destruction sns_rom_strom_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // device-level overrides virtual void device_start(); virtual void device_config_complete() { m_shortname = "sns_strom"; } - + // additional reading and writing - virtual DECLARE_READ8_MEMBER(read_l); // used for ROM - virtual DECLARE_READ8_MEMBER(read_h); // used for ROM - virtual DECLARE_WRITE8_MEMBER(write_l); // used for RAM - virtual DECLARE_WRITE8_MEMBER(write_h); // used for RAM + virtual DECLARE_READ8_MEMBER(read_l); // used for ROM + virtual DECLARE_READ8_MEMBER(read_h); // used for ROM + virtual DECLARE_WRITE8_MEMBER(write_l); // used for RAM + virtual DECLARE_WRITE8_MEMBER(write_h); // used for RAM }; diff --git a/src/mess/machine/sns_upd.c b/src/mess/machine/sns_upd.c index b9f40451127..eaa8839616c 100644 --- a/src/mess/machine/sns_upd.c +++ b/src/mess/machine/sns_upd.c @@ -1,11 +1,11 @@ /*********************************************************************************************************** - + UPD7725 / UPD96050 add-on chip emulation (for SNES/SFC) used in carts with DSP-1, DSP-1A, DSP-1B, DSP-2, DSP-3, DSP-4, ST-010 & ST-011 add-on chips - + Copyright MESS Team. Visit http://mamedev.org for licensing and usage restrictions. - + ***********************************************************************************************************/ @@ -24,19 +24,19 @@ const device_type SNS_LOROM_SETA11 = &device_creator; sns_rom20_necdsp_device::sns_rom20_necdsp_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : sns_rom_device(mconfig, SNS_LOROM_NECDSP, "SNES Cart (LoROM) + NEC DSP", tag, owner, clock), - m_upd7725(*this, "dsp") + m_upd7725(*this, "dsp") { } sns_rom21_necdsp_device::sns_rom21_necdsp_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : sns_rom21_device(mconfig, SNS_HIROM_NECDSP, "SNES Cart (HiROM) + NEC DSP", tag, owner, clock), - m_upd7725(*this, "dsp") + m_upd7725(*this, "dsp") { } sns_rom_setadsp_device::sns_rom_setadsp_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock) : sns_rom_device(mconfig, type, name, tag, owner, clock), - m_upd96050(*this, "dsp") + m_upd96050(*this, "dsp") { } @@ -223,6 +223,9 @@ READ8_MEMBER( sns_rom_setadsp_device::chip_read ) else return temp & 0xff; } + if (offset == 0x600000 || offset == 0x600001) + return (offset & 1) ? m_upd96050->snesdsp_read(FALSE) : m_upd96050->snesdsp_read(TRUE); + return 0xff; } @@ -233,7 +236,7 @@ WRITE8_MEMBER( sns_rom_setadsp_device::chip_write ) { UINT16 address = offset & 0xffff; UINT16 temp = m_upd96050->dataram_r(address/2); - + if (offset & 1) { temp &= 0xff; @@ -244,10 +247,14 @@ WRITE8_MEMBER( sns_rom_setadsp_device::chip_write ) temp &= 0xff00; temp |= data; } - + m_upd96050->dataram_w(address/2, temp); return; } + if (offset == 0x600000) + m_upd96050->snesdsp_write(TRUE, data); + if (offset == 0x600001) + m_upd96050->snesdsp_write(FALSE, data); } @@ -316,4 +323,3 @@ machine_config_constructor sns_rom_seta11dsp_device::device_mconfig_additions() { return MACHINE_CONFIG_NAME( snes_st011 ); } - diff --git a/src/mess/machine/sns_upd.h b/src/mess/machine/sns_upd.h index 2acde6e47ab..3a82d13ba7a 100644 --- a/src/mess/machine/sns_upd.h +++ b/src/mess/machine/sns_upd.h @@ -13,18 +13,18 @@ class sns_rom20_necdsp_device : public sns_rom_device public: // construction/destruction sns_rom20_necdsp_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // device-level overrides virtual void device_start(); virtual void device_config_complete() { m_shortname = "sns_rom_necdsp"; } virtual machine_config_constructor device_mconfig_additions() const; - + required_device m_upd7725; - + // additional reading and writing virtual DECLARE_READ8_MEMBER(chip_read); virtual DECLARE_WRITE8_MEMBER(chip_write); - + virtual DECLARE_READ32_MEMBER(necdsp_prg_r); virtual DECLARE_READ16_MEMBER(necdsp_data_r); }; @@ -36,18 +36,18 @@ class sns_rom21_necdsp_device : public sns_rom21_device public: // construction/destruction sns_rom21_necdsp_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // device-level overrides virtual void device_start(); virtual void device_config_complete() { m_shortname = "sns_rom21_necdsp"; } virtual machine_config_constructor device_mconfig_additions() const; - + required_device m_upd7725; - + // additional reading and writing virtual DECLARE_READ8_MEMBER(chip_read); virtual DECLARE_WRITE8_MEMBER(chip_write); - + virtual DECLARE_READ32_MEMBER(necdsp_prg_r); virtual DECLARE_READ16_MEMBER(necdsp_data_r); }; @@ -59,17 +59,17 @@ class sns_rom_setadsp_device : public sns_rom_device public: // construction/destruction sns_rom_setadsp_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock); - + // device-level overrides virtual void device_start(); virtual void device_config_complete() { m_shortname = "sns_rom_setadsp"; } - + required_device m_upd96050; - + // additional reading and writing virtual DECLARE_READ8_MEMBER(chip_read); virtual DECLARE_WRITE8_MEMBER(chip_write); - + virtual DECLARE_READ32_MEMBER(setadsp_prg_r); virtual DECLARE_READ16_MEMBER(setadsp_data_r); }; @@ -81,7 +81,7 @@ class sns_rom_seta10dsp_device : public sns_rom_setadsp_device public: // construction/destruction sns_rom_seta10dsp_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // device-level overrides virtual void device_config_complete() { m_shortname = "sns_rom_seta10"; } virtual machine_config_constructor device_mconfig_additions() const; @@ -94,7 +94,7 @@ class sns_rom_seta11dsp_device : public sns_rom_setadsp_device public: // construction/destruction sns_rom_seta11dsp_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // device-level overrides virtual void device_config_complete() { m_shortname = "sns_rom_seta11"; } virtual machine_config_constructor device_mconfig_additions() const;