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mediagx: fix config register access (nw)

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This commit is contained in:
cracyc 2013-06-13 03:43:40 +00:00
parent ef715ac4bd
commit aa526af88b
3 changed files with 15 additions and 39 deletions
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18
src/mame/drivers/funkball.c
View File

@ -247,35 +247,27 @@ READ8_MEMBER(funkball_state::io20_r)
UINT8 r = 0;
// 0x22, 0x23, Cyrix configuration registers
if (offset == 0x02)
if (offset == 0x00)
{
}
else if (offset == 0x03)
else if (offset == 0x01)
{
r = funkball_config_reg_r();
}
else
{
r = m_pic8259_1->read(space, offset);
}
return r;
}
WRITE8_MEMBER(funkball_state::io20_w)
{
// 0x22, 0x23, Cyrix configuration registers
if (offset == 0x02)
if (offset == 0x00)
{
m_funkball_config_reg_sel = data;
}
else if (offset == 0x03)
else if (offset == 0x01)
{
funkball_config_reg_w(data);
}
else
{
m_pic8259_1->write(space, offset, data);
}
}
WRITE8_MEMBER( funkball_state::flash_w )
@ -405,8 +397,8 @@ static ADDRESS_MAP_START(funkball_map, AS_PROGRAM, 32, funkball_state)
ADDRESS_MAP_END
static ADDRESS_MAP_START(funkball_io, AS_IO, 32, funkball_state)
AM_RANGE(0x0020, 0x0023) AM_READWRITE8(io20_r, io20_w, 0xffff0000)
AM_IMPORT_FROM(pcat32_io_common)
AM_RANGE(0x0020, 0x003f) AM_READWRITE8(io20_r, io20_w, 0xffffffff)
AM_RANGE(0x00e8, 0x00ef) AM_NOP
// AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff)

18
src/mame/drivers/mediagx.c
View File

@ -482,35 +482,27 @@ READ8_MEMBER(mediagx_state::io20_r)
UINT8 r = 0;
// 0x22, 0x23, Cyrix configuration registers
if (offset == 0x02)
if (offset == 0x00)
{
}
else if (offset == 0x03)
else if (offset == 0x01)
{
r = m_mediagx_config_regs[m_mediagx_config_reg_sel];
}
else
{
r = m_pic8259_1->read(space, offset);
}
return r;
}
WRITE8_MEMBER(mediagx_state::io20_w)
{
// 0x22, 0x23, Cyrix configuration registers
if (offset == 0x02)
if (offset == 0x00)
{
m_mediagx_config_reg_sel = data;
}
else if (offset == 0x03)
else if (offset == 0x01)
{
m_mediagx_config_regs[m_mediagx_config_reg_sel] = data;
}
else
{
m_pic8259_1->write(space, offset, data);
}
}
READ32_MEMBER(mediagx_state::parallel_port_r)
@ -755,8 +747,8 @@ static ADDRESS_MAP_START( mediagx_map, AS_PROGRAM, 32, mediagx_state )
ADDRESS_MAP_END
static ADDRESS_MAP_START(mediagx_io, AS_IO, 32, mediagx_state )
AM_RANGE(0x0020, 0x0023) AM_READWRITE8(io20_r, io20_w, 0xffff0000)
AM_IMPORT_FROM(pcat32_io_common)
AM_RANGE(0x0020, 0x003f) AM_READWRITE8(io20_r, io20_w, 0xffffffff)
AM_RANGE(0x00e8, 0x00eb) AM_NOP // I/O delay port
AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff)
AM_RANGE(0x0378, 0x037b) AM_READWRITE(parallel_port_r, parallel_port_w)

18
src/mame/drivers/pinball2k.c
View File

@ -386,35 +386,27 @@ READ8_MEMBER(pinball2k_state::io20_r)
UINT8 r = 0;
// 0x22, 0x23, Cyrix configuration registers
if (offset == 0x02)
if (offset == 0x00)
{
}
else if (offset == 0x03)
else if (offset == 0x01)
{
r = m_mediagx_config_regs[m_mediagx_config_reg_sel];
}
else
{
r = m_pic8259_1->read(space, offset);
}
return r;
}
WRITE8_MEMBER(pinball2k_state::io20_w)
{
// 0x22, 0x23, Cyrix configuration registers
if (offset == 0x02)
if (offset == 0x00)
{
m_mediagx_config_reg_sel = data;
}
else if (offset == 0x03)
else if (offset == 0x01)
{
m_mediagx_config_regs[m_mediagx_config_reg_sel] = data;
}
else
{
m_pic8259_1->write(space, offset, data);
}
}
READ32_MEMBER(pinball2k_state::parallel_port_r)
@ -465,8 +457,8 @@ static ADDRESS_MAP_START( mediagx_map, AS_PROGRAM, 32, pinball2k_state )
ADDRESS_MAP_END
static ADDRESS_MAP_START(mediagx_io, AS_IO, 32, pinball2k_state )
AM_RANGE(0x0020, 0x0023) AM_READWRITE8(io20_r, io20_w, 0xffff0000)
AM_IMPORT_FROM(pcat32_io_common)
AM_RANGE(0x0020, 0x003f) AM_READWRITE8(io20_r, io20_w, 0xffffffff)
AM_RANGE(0x00e8, 0x00eb) AM_NOP // I/O delay port
AM_RANGE(0x0378, 0x037b) AM_READWRITE(parallel_port_r, parallel_port_w)
AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write)