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bus/vme: major overhaul

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- add support for address modifiers
 - add support for shared interrupt request lines
 - add support for interrupt acknowledge daisy chain
 - add support for bus error
 - add slot device option aggregator
 - standardized slot device file, device and class naming
 - enp10: implement vme interface
 - hk68v10: convert to slot device, improve boot vector and rom handling
 - mzr8105: convert to slot device, improve boot vector and rom handling, add vme short space access
 - mzr8300: convert to slot device, expose to bus
 - sys68k*: convert to slot device, improve boot vector and rom handling
 - force/fccpu20: converted to slot device
 - sgi/ip4: converted to twin tower chassis with ip4 slot device
This commit is contained in:
Patrick Mackinlay 2023-09-13 13:20:27 +07:00
parent 1e31d416a8
commit aa5b612270
57 changed files with 2337 additions and 2445 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

72
scripts/src/bus.lua
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@ -2643,38 +2643,50 @@ end
if (BUSES["VME"]~=null) then
files {
MAME_DIR .. "src/devices/bus/vme/enp10.cpp",
MAME_DIR .. "src/devices/bus/vme/enp10.h",
MAME_DIR .. "src/devices/bus/vme/mvme187.cpp",
MAME_DIR .. "src/devices/bus/vme/mvme187.h",
MAME_DIR .. "src/devices/bus/vme/tp881v.cpp",
MAME_DIR .. "src/devices/bus/vme/tp881v.h",
MAME_DIR .. "src/devices/bus/vme/vme.cpp",
MAME_DIR .. "src/devices/bus/vme/vme.h",
MAME_DIR .. "src/devices/bus/vme/vme_cp31.cpp",
MAME_DIR .. "src/devices/bus/vme/vme_cp31.h",
MAME_DIR .. "src/devices/bus/vme/vme_fccpu20.cpp",
MAME_DIR .. "src/devices/bus/vme/vme_fccpu20.h",
MAME_DIR .. "src/devices/bus/vme/vme_fcisio.cpp",
MAME_DIR .. "src/devices/bus/vme/vme_fcisio.h",
MAME_DIR .. "src/devices/bus/vme/vme_fcscsi.cpp",
MAME_DIR .. "src/devices/bus/vme/vme_fcscsi.h",
MAME_DIR .. "src/devices/bus/vme/vme_hcpu30.cpp",
MAME_DIR .. "src/devices/bus/vme/vme_hcpu30.h",
MAME_DIR .. "src/devices/bus/vme/vme_mvme120.cpp",
MAME_DIR .. "src/devices/bus/vme/vme_mvme120.h",
MAME_DIR .. "src/devices/bus/vme/vme_mvme180.cpp",
MAME_DIR .. "src/devices/bus/vme/vme_mvme180.h",
MAME_DIR .. "src/devices/bus/vme/vme_mvme181.cpp",
MAME_DIR .. "src/devices/bus/vme/vme_mvme181.h",
MAME_DIR .. "src/devices/bus/vme/vme_mvme327a.cpp",
MAME_DIR .. "src/devices/bus/vme/vme_mvme327a.h",
MAME_DIR .. "src/devices/bus/vme/vme_mvme350.cpp",
MAME_DIR .. "src/devices/bus/vme/vme_mvme350.h",
MAME_DIR .. "src/devices/bus/vme/vme_mzr8300.cpp",
MAME_DIR .. "src/devices/bus/vme/vme_mzr8300.h",
MAME_DIR .. "src/devices/bus/vme/vme_smvme2000.cpp",
MAME_DIR .. "src/devices/bus/vme/vme_smvme2000.h",
MAME_DIR .. "src/devices/bus/vme/vme_cards.cpp",
MAME_DIR .. "src/devices/bus/vme/vme_cards.h",
MAME_DIR .. "src/devices/bus/vme/cp31.cpp",
MAME_DIR .. "src/devices/bus/vme/cp31.h",
MAME_DIR .. "src/devices/bus/vme/enp10.cpp",
MAME_DIR .. "src/devices/bus/vme/enp10.h",
MAME_DIR .. "src/devices/bus/vme/hcpu30.cpp",
MAME_DIR .. "src/devices/bus/vme/hcpu30.h",
MAME_DIR .. "src/devices/bus/vme/hk68v10.cpp",
MAME_DIR .. "src/devices/bus/vme/hk68v10.h",
MAME_DIR .. "src/devices/bus/vme/mvme120.cpp",
MAME_DIR .. "src/devices/bus/vme/mvme120.h",
MAME_DIR .. "src/devices/bus/vme/mvme147.cpp",
MAME_DIR .. "src/devices/bus/vme/mvme147.h",
MAME_DIR .. "src/devices/bus/vme/mvme180.cpp",
MAME_DIR .. "src/devices/bus/vme/mvme180.h",
MAME_DIR .. "src/devices/bus/vme/mvme181.cpp",
MAME_DIR .. "src/devices/bus/vme/mvme181.h",
MAME_DIR .. "src/devices/bus/vme/mvme187.cpp",
MAME_DIR .. "src/devices/bus/vme/mvme187.h",
MAME_DIR .. "src/devices/bus/vme/mvme327a.cpp",
MAME_DIR .. "src/devices/bus/vme/mvme327a.h",
MAME_DIR .. "src/devices/bus/vme/mvme350.cpp",
MAME_DIR .. "src/devices/bus/vme/mvme350.h",
MAME_DIR .. "src/devices/bus/vme/mzr8105.cpp",
MAME_DIR .. "src/devices/bus/vme/mzr8105.h",
MAME_DIR .. "src/devices/bus/vme/mzr8300.cpp",
MAME_DIR .. "src/devices/bus/vme/mzr8300.h",
MAME_DIR .. "src/devices/bus/vme/smvme2000.cpp",
MAME_DIR .. "src/devices/bus/vme/smvme2000.h",
MAME_DIR .. "src/devices/bus/vme/sys68k_cpu1.cpp",
MAME_DIR .. "src/devices/bus/vme/sys68k_cpu1.h",
MAME_DIR .. "src/devices/bus/vme/sys68k_cpu20.cpp",
MAME_DIR .. "src/devices/bus/vme/sys68k_cpu20.h",
MAME_DIR .. "src/devices/bus/vme/sys68k_cpu30.cpp",
MAME_DIR .. "src/devices/bus/vme/sys68k_cpu30.h",
MAME_DIR .. "src/devices/bus/vme/sys68k_iscsi.cpp",
MAME_DIR .. "src/devices/bus/vme/sys68k_iscsi.h",
MAME_DIR .. "src/devices/bus/vme/sys68k_isio.cpp",
MAME_DIR .. "src/devices/bus/vme/sys68k_isio.h",
MAME_DIR .. "src/devices/bus/vme/tp881v.cpp",
MAME_DIR .. "src/devices/bus/vme/tp881v.h",
}
end

3
src/devices/bus/vme/vme_cp31.cpp → src/devices/bus/vme/cp31.cpp
View File

@ -25,7 +25,7 @@
#include "emu.h"
#include "vme_cp31.h"
#include "cp31.h"
#define LOG_INT (1U << 1)
@ -272,7 +272,6 @@ vme_cp31_card_device::vme_cp31_card_device(const machine_config &mconfig, device
, m_p_ram(*this, "dram")
, m_sysrom(*this, "user1")
{
m_slot = 1;
}
//

6
src/devices/bus/vme/vme_cp31.h → src/devices/bus/vme/cp31.h
View File

@ -1,7 +1,7 @@
// license:BSD-3-Clause
// copyright-holders:Sergey Svishchev
#ifndef MAME_BUS_VME_VME_CP31_H
#define MAME_BUS_VME_VME_CP31_H
#ifndef MAME_BUS_VME_CP31_H
#define MAME_BUS_VME_CP31_H
#pragma once
@ -69,4 +69,4 @@ private:
void cpu_space_map(address_map &map);
};
#endif // MAME_BUS_VME_VME_CP31_H
#endif // MAME_BUS_VME_CP31_H

89
src/devices/bus/vme/enp10.cpp
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@ -8,8 +8,6 @@
* - Ethernet Node Processor ENP-30 Reference Guide (6213000-05B), Communication Machinery Corporation, November 15, 1988
*
* TODO:
* - vme interface
* - address/interrupt configuration
* - verify registers
* - uart?
*/
@ -31,14 +29,15 @@
#define VERBOSE 0
#include "logmacro.h"
DEFINE_DEVICE_TYPE(CMC_ENP10, cmc_enp10_device, "cmc_enp10", "CMC ENP-10")
DEFINE_DEVICE_TYPE(VME_ENP10, vme_enp10_card_device, "enp10", "CMC ENP-10")
cmc_enp10_device::cmc_enp10_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock)
: device_t(mconfig, CMC_ENP10, tag, owner, clock)
vme_enp10_card_device::vme_enp10_card_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock)
: device_t(mconfig, VME_ENP10, tag, owner, clock)
, device_vme_card_interface(mconfig, *this)
, m_cpu(*this, "cpu")
, m_net(*this, "net")
, m_led(*this, "led%u", 0U)
, m_base(*this, "BASE")
, m_boot(*this, "boot")
{
}
@ -60,58 +59,75 @@ ROM_START(enp10)
ROM_END
static INPUT_PORTS_START(enp10)
PORT_START("BASE")
PORT_CONFNAME(0xff, 0xde, "Base Address")
PORT_CONFSETTING(0xd8, "0xd80000")
PORT_CONFSETTING(0xda, "0xda0000")
PORT_CONFSETTING(0xdc, "0xdc0000")
PORT_CONFSETTING(0xde, "0xde0000")
INPUT_PORTS_END
const tiny_rom_entry *cmc_enp10_device::device_rom_region() const
const tiny_rom_entry *vme_enp10_card_device::device_rom_region() const
{
return ROM_NAME(enp10);
}
ioport_constructor cmc_enp10_device::device_input_ports() const
ioport_constructor vme_enp10_card_device::device_input_ports() const
{
return INPUT_PORTS_NAME(enp10);
}
void cmc_enp10_device::device_start()
void vme_enp10_card_device::device_start()
{
m_led.resolve();
save_item(NAME(m_ivr));
save_item(NAME(m_csr));
save_item(NAME(m_ier));
save_item(NAME(m_tir));
save_item(NAME(m_rir));
save_item(NAME(m_uir));
save_item(NAME(m_exr));
save_item(NAME(m_csr));
save_item(NAME(m_rer));
save_item(NAME(m_exr));
save_item(NAME(m_hir));
}
void cmc_enp10_device::device_reset()
void vme_enp10_card_device::device_reset()
{
m_boot.select(0);
m_ivr = 0;
m_csr = 0;
m_ier = 0;
m_tir = 0;
m_rir = 0;
m_uir = 0;
m_exr = 0;
m_csr = 0;
m_rer = 0;
m_exr = 0;
m_hir = 0;
u32 const base = m_base->read() << 16;
vme_space(vme::AM_39).install_device(base, base | 0x1'ffff, *this, &vme_enp10_card_device::vme_map);
vme_space(vme::AM_3d).install_device(base, base | 0x1'ffff, *this, &vme_enp10_card_device::vme_map);
vme_irq_w<4>(1);
}
void cmc_enp10_device::device_add_mconfig(machine_config &config)
void vme_enp10_card_device::device_add_mconfig(machine_config &config)
{
M68000(config, m_cpu, 20_MHz_XTAL / 2);
m_cpu->set_addrmap(AS_PROGRAM, &cmc_enp10_device::cpu_mem);
m_cpu->set_addrmap(AS_PROGRAM, &vme_enp10_card_device::cpu_map);
AM7990(config, m_net, 20_MHz_XTAL / 2);
m_net->intr_out().set_inputline(m_cpu, INPUT_LINE_IRQ6).invert();
m_net->dma_in().set([this](offs_t offset) { return m_cpu->space(0).read_word(offset); });
m_net->dma_out().set([this](offs_t offset, u16 data, u16 mem_mask) { m_cpu->space(0).write_word(offset, data, mem_mask); });
vme_iack().set(FUNC(vme_enp10_card_device::iack_r));
}
void cmc_enp10_device::cpu_mem(address_map &map)
void vme_enp10_card_device::cpu_map(address_map &map)
{
map(0xf0'0000, 0xf1'ffff).ram().share("ram");
map(0xf8'0000, 0xf8'3fff).rom().region("eprom", 0).mirror(0x02'0000);
@ -128,7 +144,7 @@ void cmc_enp10_device::cpu_mem(address_map &map)
// uart: 16 byte registers 10-2f?
map(0xef'8010, 0xef'802f).noprw();
// fe'0080 vector? w:host vectored interrupt, r:slave address msb
map(0xfe'0080, 0xfe'0081).umask16(0x00ff).rw(FUNC(vme_enp10_card_device::addr_r), FUNC(vme_enp10_card_device::irq_w));
map(0xfe'00a0, 0xfe'00a1).umask16(0x00ff).lrw8(
[this]() { return m_csr; }, "csr_r",
@ -156,10 +172,45 @@ void cmc_enp10_device::cpu_mem(address_map &map)
// TODO: verify the next two registers
map(0xfe'0e00, 0xfe'0e01).umask16(0x00ff).lrw8(NAME([this]() { return m_hir; }), NAME([this](u8 data) { m_hir = data; interrupt(); }));
map(0xfe'0f00, 0xfe'0f01).umask16(0x00ff).lrw8(NAME([this]() { reset(); return 0; }), NAME([this](u8 data) { reset(); }));
map(0xfe'0f00, 0xfe'0fff).umask16(0x00ff).lrw8(NAME([this]() { reset(); return 0; }), NAME([this](u8 data) { reset(); }));
}
void cmc_enp10_device::interrupt()
void vme_enp10_card_device::vme_map(address_map &map)
{
map(0x0'0000, 0x1'efff).lrw16(
[this](offs_t offset, u16 mem_mask) { return m_cpu->space(0).read_word(0xf0'0000 | (offset << 1), mem_mask); }, "mem_r",
[this](offs_t offset, u16 data, u16 mem_mask) { m_cpu->space(0).write_word(0xf0'0000 | (offset << 1), data, mem_mask); }, "mem_w");
map(0x1'f000, 0x1'ffff).lrw16(
[this](offs_t offset, u16 mem_mask) { return m_cpu->space(0).read_word(0xfe'0000 | (offset << 1), mem_mask); }, "reg_r",
[this](offs_t offset, u16 data, u16 mem_mask) { m_cpu->space(0).write_word(0xfe'0000 | (offset << 1), mem_mask); }, "reg_w");
}
u8 vme_enp10_card_device::addr_r()
{
LOG("addr_r (%s)\n", machine().describe_context());
// TODO: what is returned here?
return m_base->read();
}
void vme_enp10_card_device::irq_w(u8 data)
{
LOG("irq 0x%02x (%s)\n", data, machine().describe_context());
m_ivr = data;
vme_irq_w<4>(0);
}
u8 vme_enp10_card_device::iack_r()
{
vme_irq_w<4>(1);
return m_ivr;
}
void vme_enp10_card_device::interrupt()
{
bool const enable = BIT(m_ier, 7);

19
src/devices/bus/vme/enp10.h
View File

@ -10,12 +10,12 @@
#include "machine/am79c90.h"
#include "bus/vme/vme.h"
class cmc_enp10_device
class vme_enp10_card_device
: public device_t
, public device_vme_card_interface
{
public:
cmc_enp10_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock);
vme_enp10_card_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock);
protected:
virtual const tiny_rom_entry *device_rom_region() const override;
@ -25,7 +25,12 @@ protected:
virtual void device_reset() override;
private:
void cpu_mem(address_map &map);
void cpu_map(address_map &map);
void vme_map(address_map &map);
u8 addr_r();
void irq_w(u8 data);
u8 iack_r();
void interrupt();
@ -33,19 +38,21 @@ private:
required_device<am7990_device> m_net;
output_finder<2> m_led;
required_ioport m_base;
u8 m_ivr; // interrupt vector register
u8 m_csr; // control/status register
u8 m_ier; // interrupt enable register
u8 m_tir; // transmit interrupt register
u8 m_rir; // receive interrupt register
u8 m_uir; // utility interrupt register
u8 m_exr; // exception register
u8 m_csr; // control/status register
u8 m_rer; // ram/rom enable register
u8 m_exr; // exception register
u8 m_hir; // host interrupt register
memory_view m_boot;
};
DECLARE_DEVICE_TYPE(CMC_ENP10, cmc_enp10_device)
DECLARE_DEVICE_TYPE(VME_ENP10, vme_enp10_card_device)
#endif // MAME_BUS_VME_ENP10_H

3
src/devices/bus/vme/vme_hcpu30.cpp → src/devices/bus/vme/hcpu30.cpp
View File

@ -30,7 +30,7 @@
*/
#include "emu.h"
#include "vme_hcpu30.h"
#include "hcpu30.h"
#define LOG_INT (1U << 1)
@ -542,7 +542,6 @@ vme_hcpu30_card_device::vme_hcpu30_card_device(const machine_config &mconfig, de
, m_dips(*this, "SA1")
{
LOG("vme_hcpu30_card_device::vme_hcpu30_card_device ctor: %s\n", tag);
m_slot = 1;
}
//

6
src/devices/bus/vme/vme_hcpu30.h → src/devices/bus/vme/hcpu30.h
View File

@ -1,7 +1,7 @@
// license:BSD-3-Clause
// copyright-holders:Sergey Svishchev
#ifndef MAME_BUS_VME_VME_HCPU30_H
#define MAME_BUS_VME_VME_HCPU30_H
#ifndef MAME_BUS_VME_HCPU30_H
#define MAME_BUS_VME_HCPU30_H
#pragma once
@ -91,4 +91,4 @@ private:
void oscpu_space_map(address_map &map);
};
#endif // MAME_BUS_VME_VME_HCPU30_H
#endif // MAME_BUS_VME_HCPU30_H

152
src/mame/heurikon/hk68v10.cpp → src/devices/bus/vme/hk68v10.cpp
View File

@ -165,9 +165,9 @@
****************************************************************************/
#include "emu.h"
#include "hk68v10.h"
#include "cpu/m68000/m68010.h"
#include "bus/vme/vme.h"
#include "machine/z80scc.h"
#include "machine/z8536.h"
#include "bus/rs232/rs232.h"
#include "machine/clock.h"
@ -186,60 +186,34 @@
#define FUNCNAME __PRETTY_FUNCTION__
#endif
namespace {
#define BAUDGEN_CLOCK 19.6608_MHz_XTAL /* Raltron */
#define SCC_CLOCK (BAUDGEN_CLOCK / 4) /* through a 74LS393 counter */
class hk68v10_state : public driver_device
DEFINE_DEVICE_TYPE(VME_HK68V10, vme_hk68v10_card_device, "hk68v10", "Heurikon HK68/V10")
vme_hk68v10_card_device::vme_hk68v10_card_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock)
: device_t(mconfig, VME_HK68V10, tag, owner, clock)
, device_vme_card_interface(mconfig, *this)
, m_maincpu(*this, "maincpu")
, m_sccterm(*this, "scc")
, m_eprom(*this, "eprom")
, m_ram(*this, "ram")
//,m_cart(*this, "exp_rom1")
{
public:
hk68v10_state(const machine_config &mconfig, device_type type, const char *tag) :
driver_device(mconfig, type, tag),
m_maincpu(*this, "maincpu")
, m_sccterm(*this, "scc")
// ,m_cart(*this, "exp_rom1")
{
}
}
void hk68v10(machine_config &config);
private:
uint16_t bootvect_r(offs_t offset);
void bootvect_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
//uint16_t vme_a24_r();
//void vme_a24_w(uint16_t data);
//uint16_t vme_a16_r();
//void vme_a16_w(uint16_t data);
virtual void machine_start() override;
virtual void machine_reset() override;
void hk68v10_mem(address_map &map);
required_device<cpu_device> m_maincpu;
required_device<scc8530_device> m_sccterm;
// Pointer to System ROMs needed by bootvect_r and masking RAM buffer for post reset accesses
uint16_t *m_sysrom = nullptr;
uint16_t m_sysram[4]{};
};
void hk68v10_state::hk68v10_mem(address_map &map)
void vme_hk68v10_card_device::hk68v10_mem(address_map &map)
{
map.unmap_value_high();
map(0x000000, 0x000007).ram().w(FUNC(hk68v10_state::bootvect_w)); /* After first write we act as RAM */
map(0x000000, 0x000007).rom().r(FUNC(hk68v10_state::bootvect_r)); /* ROM mirror just durin reset */
map(0x000008, 0x1fffff).ram(); /* 2 Mb RAM */
map(0xFC0000, 0xFC3fff).rom(); /* System EPROM Area 16Kb HBUG */
map(0xFC4000, 0xFDffff).rom(); /* System EPROM Area an additional 112Kb for System ROM */
map(0x000000, 0x1fffff).ram().share("ram"); /* 2 Mb RAM */
map(0xfc0000, 0xfdffff).rom().region("eprom", 0); /* System EPROM Area 128Kb HBUG */
map(0xFE9000, 0xFE9007).rw("cio", FUNC(z8536_device::read), FUNC(z8536_device::write)).umask16(0xff00);
map(0xfea000, 0xfea000).rw(m_sccterm, FUNC(scc8530_device::ca_r), FUNC(scc8530_device::ca_w)); /* Dual serial port Z80-SCC */
map(0xfea002, 0xfea002).rw(m_sccterm, FUNC(scc8530_device::cb_r), FUNC(scc8530_device::cb_w)); /* Dual serial port Z80-SCC */
map(0xfea004, 0xfea004).rw(m_sccterm, FUNC(scc8530_device::da_r), FUNC(scc8530_device::da_w)); /* Dual serial port Z80-SCC */
map(0xfea006, 0xfea006).rw(m_sccterm, FUNC(scc8530_device::db_r), FUNC(scc8530_device::db_w)); /* Dual serial port Z80-SCC */
//map(0x100000, 0xfeffff).rw(FUNC(hk68v10_state::vme_a24_r), FUNC(hk68v10_state::vme_a24_w)); /* VMEbus Rev B addresses (24 bits) - not verified */
//map(0xff0000, 0xffffff).rw(FUNC(hk68v10_state::vme_a16_r), FUNC(hk68v10_state::vme_a16_w)); /* VMEbus Rev B addresses (16 bits) - not verified */
//map(0x100000, 0xfeffff).rw(FUNC(vme_hk68v10_card_device::vme_a24_r), FUNC(vme_hk68v10_card_device::vme_a24_w)); /* VMEbus Rev B addresses (24 bits) - not verified */
//map(0xff0000, 0xffffff).rw(FUNC(vme_hk68v10_card_device::vme_a16_r), FUNC(vme_hk68v10_card_device::vme_a16_w)); /* VMEbus Rev B addresses (16 bits) - not verified */
}
/* Input ports */
@ -247,65 +221,45 @@ static INPUT_PORTS_START (hk68v10)
INPUT_PORTS_END
/* Start it up */
void hk68v10_state::machine_start ()
void vme_hk68v10_card_device::device_start ()
{
LOG(("%s\n", FUNCNAME));
}
void vme_hk68v10_card_device::device_reset ()
{
LOG(("%s\n", FUNCNAME));
/* Setup pointer to bootvector in ROM for bootvector handler bootvect_r */
m_sysrom = (uint16_t*)(memregion ("maincpu")->base () + 0x0fc0000);
}
m_maincpu->space(AS_PROGRAM).install_rom(0, m_eprom->bytes() - 1, m_eprom->base());
/* Support CPU resets
TODO: Investigate why the user need two 'softreset' commands for the below to work. Eg F3 + F11 + F3 + F11
If only one 'softreset' is given the reset PC gets the RAM content, not the intended ROM vector.
Race conditions? Wrong call order in memory system? Debugger prefetch accesses? Better way to to this?
*/
void hk68v10_state::machine_reset ()
{
LOG(("%s\n", FUNCNAME));
/* Reset pointer to bootvector in ROM for bootvector handler bootvect_r */
if (m_sysrom == &m_sysram[0]) /* Condition needed because memory map is not setup first time */
m_sysrom = (uint16_t*)(memregion ("maincpu")->base () + 0x0fc0000);
}
/* Boot vector handler, the PCB hardwires the first 8 bytes from 0xfc0000 to 0x0 at reset*/
/*
Right after HBUG reset the bootvector is masked by RAM:
FC001C: move.w #$700, $fe4000.l
FC0024: move.l #$0, $0.l # <- zeroing the reset vector
FC002E: move.l #$0, $4.l # There is for sure some hardware mapping going in here
*/
uint16_t hk68v10_state::bootvect_r(offs_t offset){
LOG(("%s %s\n", FUNCNAME, m_sysrom != &m_sysram[0] ? "as reset" : "as swapped"));
return m_sysrom[offset];
}
void hk68v10_state::bootvect_w(offs_t offset, uint16_t data, uint16_t mem_mask){
LOG (("%s offset %08x, mask %08x, data %04x\n", FUNCNAME, offset, mem_mask, data));
m_sysram[offset % std::size(m_sysram)] &= ~mem_mask;
m_sysram[offset % std::size(m_sysram)] |= (data & mem_mask);
m_sysrom = &m_sysram[0]; // redirect all upcoming accesses to masking RAM until reset.
m_boot_mph = m_maincpu->space(AS_PROGRAM).install_read_tap(0x000006, 0x000007, "boot",
[this](offs_t offset, uint16_t &data, uint16_t mem_mask)
{
if (!machine().side_effects_disabled() && ACCESSING_BITS_0_7)
{
m_maincpu->space(AS_PROGRAM).install_ram(0, m_ram.bytes() - 1, m_ram.target());
m_boot_mph.remove();
}
});
}
#if 0
/* Dummy VME access methods until the VME bus device is ready for use */
uint16_t hk68v10_state::vme_a24_r(){
uint16_t vme_hk68v10_card_device::vme_a24_r(){
LOG(("%s\n", FUNCNAME));
return (uint16_t) 0;
}
void hk68v10_state::vme_a24_w(uint16_t data){
void vme_hk68v10_card_device::vme_a24_w(uint16_t data){
LOG(("%s\n", FUNCNAME));
}
uint16_t hk68v10_state::vme_a16_r(){
uint16_t vme_hk68v10_card_device::vme_a16_r(){
LOG(("%s\n", FUNCNAME));
return (uint16_t) 0;
}
void hk68v10_state::vme_a16_w(uint16_t data){
void vme_hk68v10_card_device::vme_a16_w(uint16_t data){
LOG(("%s\n", FUNCNAME));
}
#endif
@ -333,18 +287,14 @@ void hk68v10_state::vme_a16_w(uint16_t data){
* Original HBUG configuration word: 0x003D = 0000 0000 0011 1101
*/
static void hk68_vme_cards(device_slot_interface &device)
{
}
/*
* Machine configuration
*/
void hk68v10_state::hk68v10(machine_config &config)
void vme_hk68v10_card_device::device_add_mconfig(machine_config &config)
{
/* basic machine hardware */
M68010(config, m_maincpu, 10_MHz_XTAL);
m_maincpu->set_addrmap(AS_PROGRAM, &hk68v10_state::hk68v10_mem);
m_maincpu->set_addrmap(AS_PROGRAM, &vme_hk68v10_card_device::hk68v10_mem);
Z8536(config, "cio", SCC_CLOCK);
@ -357,17 +307,15 @@ void hk68v10_state::hk68v10(machine_config &config)
rs232_port_device &rs232trm(RS232_PORT(config, "rs232trm", default_rs232_devices, "terminal"));
rs232trm.rxd_handler().set(m_sccterm, FUNC(scc8530_device::rxa_w));
rs232trm.cts_handler().set(m_sccterm, FUNC(scc8530_device::ctsa_w));
VME(config, "vme", 0);
VME_SLOT(config, "slot1", hk68_vme_cards, nullptr, 1, "vme");
}
/* ROM definitions */
ROM_START (hk68v10)
ROM_REGION (0x1000000, "maincpu", 0)
ROM_REGION16_BE (0x20000, "eprom", 0)
ROM_LOAD16_BYTE ("hk68kv10.u23.bin", 0x0001, 0x2000, CRC (632aa026) SHA1 (f2b1ed0cc38dfbeb1602c013e00757015400720d))
ROM_LOAD16_BYTE ("hk68kv10.u12.bin", 0x0000, 0x2000, CRC (f2d688e9) SHA1 (e68699965645f0ce53de47625163c3eb02c8b727))
ROM_LOAD16_BYTE ("hk68kv10.u23.bin", 0xFC0001, 0x2000, CRC (632aa026) SHA1 (f2b1ed0cc38dfbeb1602c013e00757015400720d))
ROM_LOAD16_BYTE ("hk68kv10.u12.bin", 0xFC0000, 0x2000, CRC (f2d688e9) SHA1 (e68699965645f0ce53de47625163c3eb02c8b727))
/*
* System ROM information
*
@ -400,9 +348,17 @@ ROM_START (hk68v10)
*/
ROM_END
} // anonymous namespace
const tiny_rom_entry *vme_hk68v10_card_device::device_rom_region() const
{
return ROM_NAME(hk68v10);
}
ioport_constructor vme_hk68v10_card_device::device_input_ports() const
{
return INPUT_PORTS_NAME(hk68v10);
}
/* Driver */
/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS */
COMP( 1985, hk68v10, 0, 0, hk68v10, hk68v10, hk68v10_state, empty_init, "Heurikon Corporation", "HK68/V10", MACHINE_NO_SOUND_HW )
//COMP( 1985, hk68v10, 0, 0, hk68v10, hk68v10, vme_hk68v10_card_device, empty_init, "Heurikon Corporation", "HK68/V10", MACHINE_NO_SOUND_HW )

44
src/devices/bus/vme/hk68v10.h Normal file
View File

@ -0,0 +1,44 @@
// license:BSD-3-Clause
// copyright-holders:Joakim Larsson Edstrom
#ifndef MAME_BUS_VME_HK68V10_H
#define MAME_BUS_VME_HK68V10_H
#pragma once
#include "bus/vme/vme.h"
#include "machine/z80scc.h"
class vme_hk68v10_card_device
: public device_t
, public device_vme_card_interface
{
public:
vme_hk68v10_card_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock);
protected:
virtual const tiny_rom_entry *device_rom_region() const override;
virtual void device_add_mconfig(machine_config &config) override;
virtual ioport_constructor device_input_ports() const override;
virtual void device_start() override;
virtual void device_reset() override;
private:
//uint16_t vme_a24_r();
//void vme_a24_w(uint16_t data);
//uint16_t vme_a16_r();
//void vme_a16_w(uint16_t data);
void hk68v10_mem(address_map &map);
required_device<cpu_device> m_maincpu;
required_device<scc8530_device> m_sccterm;
required_memory_region m_eprom;
required_shared_ptr<uint16_t> m_ram;
memory_passthrough_handler m_boot_mph;
};
DECLARE_DEVICE_TYPE(VME_HK68V10, vme_hk68v10_card_device)
#endif // MAME_BUS_VME_HK68V10_H

10
src/devices/bus/vme/vme_mvme120.cpp → src/devices/bus/vme/mvme120.cpp
View File

@ -20,7 +20,7 @@
*/
#include "emu.h"
#include "vme_mvme120.h"
#include "mvme120.h"
#ifdef _MSC_VER
#define FUNCNAME __func__
@ -41,10 +41,10 @@
#define MVME122_MFP_CLOCK ( MVME122_CPU_CLOCK / 4 )
// The four MVME12x card variants.
DEFINE_DEVICE_TYPE(VME_MVME120, vme_mvme120_card_device, "mvme120", "Motorola MVME-120")
DEFINE_DEVICE_TYPE(VME_MVME121, vme_mvme121_card_device, "mvme121", "Motorola MVME-121")
DEFINE_DEVICE_TYPE(VME_MVME122, vme_mvme122_card_device, "mvme122", "Motorola MVME-122")
DEFINE_DEVICE_TYPE(VME_MVME123, vme_mvme123_card_device, "mvme123", "Motorola MVME-123")
DEFINE_DEVICE_TYPE(VME_MVME120, vme_mvme120_card_device, "mvme120", "Motorola MVME120")
DEFINE_DEVICE_TYPE(VME_MVME121, vme_mvme121_card_device, "mvme121", "Motorola MVME121")
DEFINE_DEVICE_TYPE(VME_MVME122, vme_mvme122_card_device, "mvme122", "Motorola MVME122")
DEFINE_DEVICE_TYPE(VME_MVME123, vme_mvme123_card_device, "mvme123", "Motorola MVME123")
static INPUT_PORTS_START(mvme120)
PORT_START("S3")

6
src/devices/bus/vme/vme_mvme120.h → src/devices/bus/vme/mvme120.h
View File

@ -1,7 +1,7 @@
// license:BSD-3-Clause
// copyright-holders:Katherine Rohl
#ifndef MAME_BUS_VME_VME_MVME120_H
#define MAME_BUS_VME_VME_MVME120_H
#ifndef MAME_BUS_VME_MVME120_H
#define MAME_BUS_VME_MVME120_H
#pragma once
@ -150,4 +150,4 @@ protected:
virtual void device_add_mconfig(machine_config &config) override;
};
#endif // MAME_BUS_VME_VME_MVME120_H
#endif // MAME_BUS_VME_MVME120_H

176
src/mame/motorola/mvme147.cpp → src/devices/bus/vme/mvme147.cpp
View File

@ -153,10 +153,9 @@
****************************************************************************/
#include "emu.h"
#include "mvme147.h"
#include "cpu/m68000/m68030.h"
#include "bus/vme/vme.h"
#include "bus/vme/vme_mvme350.h"
#include "machine/z80scc.h"
#include "bus/rs232/rs232.h"
#include "machine/clock.h"
#include "machine/timekpr.h"
@ -173,82 +172,44 @@
#endif
namespace {
/* from documentation: http://www.m88k.com/Docs/147/147aih.pdf but crystal and divider not known */
#define BAUDGEN_CLOCK 5_MHz_XTAL
#define SCC_CLOCK (BAUDGEN_CLOCK) /* This gives prompt at the RS232 terminal device (9600) */
class mvme147_state : public driver_device
DEFINE_DEVICE_TYPE(VME_MVME147, vme_mvme147_card_device, "mvme147", "Motorola MVME147")
vme_mvme147_card_device::vme_mvme147_card_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock)
: device_t(mconfig, VME_MVME147, tag, owner, clock)
, device_vme_card_interface(mconfig, *this)
, m_maincpu (*this, "maincpu")
, m_sccterm(*this, "scc")
, m_sccterm2(*this, "scc2")
, m_system(*this, "system")
, m_ram(*this, "ram")
{
public:
mvme147_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device (mconfig, type, tag)
, m_maincpu (*this, "maincpu")
, m_sccterm(*this, "scc")
, m_sccterm2(*this, "scc2")
{
}
}
void mvme147(machine_config &config);
private:
uint32_t bootvect_r(offs_t offset);
void bootvect_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
/* PCC - Peripheral Channel Controller */
//uint32_t pcc32_r(offs_t offset);
//void pcc32_w(offs_t offset, uint32_t data);
uint16_t pcc16_r(offs_t offset);
void pcc16_w(offs_t offset, uint16_t data);
uint8_t pcc8_r(offs_t offset);
void pcc8_w(offs_t offset, uint8_t data);
uint8_t vmechip_r(offs_t offset);
void vmechip_w(offs_t offset, uint8_t data);
//uint16_t vme_a24_r();
//void vme_a24_w(uint16_t data);
//uint16_t vme_a16_r();
//void vme_a16_w(uint16_t data);
virtual void machine_start () override;
virtual void machine_reset () override;
void mvme147_mem(address_map &map);
required_device<cpu_device> m_maincpu;
required_device<scc85c30_device> m_sccterm;
required_device<scc85c30_device> m_sccterm2;
// Pointer to System ROMs needed by bootvect_r and masking RAM buffer for post reset accesses
uint32_t *m_sysrom = nullptr;
uint32_t m_sysram[2]{};
// PCC registers
uint8_t m_genpurp_stat = 0;
// VME chip registers
uint8_t m_vc_cntl_conf = 0;
};
void mvme147_state::mvme147_mem(address_map &map)
void vme_mvme147_card_device::mvme147_mem(address_map &map)
{
map.unmap_value_high();
map(0x00000000, 0x00000007).ram().w(FUNC(mvme147_state::bootvect_w)); /* After first write we act as RAM */
map(0x00000000, 0x00000007).rom().r(FUNC(mvme147_state::bootvect_r)); /* ROM mirror just during reset */
map(0x00000008, 0x003fffff).ram(); /* 4 Mb RAM */
map(0xff800000, 0xff9fffff).rom().region("roms", 0x800000); //mirror(0x00780000); /* ROM/EEPROM bank 1 - 147bug */
map(0xffa00000, 0xffbfffff).rom().region("roms", 0xa00000); //mirror(0x00780000); /* ROM/EEPROM bank 2 - unpopulated */
map(0x00000008, 0x003fffff).ram().share("ram"); /* 4 Mb RAM */
map(0xff800000, 0xff83ffff).rom().region("system", 0).mirror(0x1c0000); //mirror(0x00780000); /* ROM/EEPROM bank 1 - 147bug */
//map(0xffa00000, 0xffbfffff).rom().region("user", 0); //mirror(0x00780000); /* ROM/EEPROM bank 2 - unpopulated */
/* SGS-Thompson M48T18 RAM and clock chip, only 4088 bytes used, and 8 bytes for the RTC, out of 8Kb though */
map(0xfffe0000, 0xfffe0fff).rw("m48t18", FUNC(timekeeper_device::read), FUNC(timekeeper_device::write));
//map(0xfffe1000, 0xfffe100f).rw(FUNC(mvme147_state::pcc32_r), FUNC(mvme147_state::pcc32_w)); /* PCC 32 bits registers - needs U64 cast defined to work */
map(0xfffe1010, 0xfffe1017).rw(FUNC(mvme147_state::pcc16_r), FUNC(mvme147_state::pcc16_w)); /* PCC 16 bits registers */
map(0xfffe1018, 0xfffe102f).rw(FUNC(mvme147_state::pcc8_r), FUNC(mvme147_state::pcc8_w)); /* PCC 8 bits registers */
map(0xfffe2000, 0xfffe201b).rw(FUNC(mvme147_state::vmechip_r), FUNC(mvme147_state::vmechip_w)).umask32(0x00ff00ff); /* VMEchip 8 bits registers on odd adresses */
//map(0xfffe1000, 0xfffe100f).rw(FUNC(vme_mvme147_card_device::pcc32_r), FUNC(vme_mvme147_card_device::pcc32_w)); /* PCC 32 bits registers - needs U64 cast defined to work */
map(0xfffe1010, 0xfffe1017).rw(FUNC(vme_mvme147_card_device::pcc16_r), FUNC(vme_mvme147_card_device::pcc16_w)); /* PCC 16 bits registers */
map(0xfffe1018, 0xfffe102f).rw(FUNC(vme_mvme147_card_device::pcc8_r), FUNC(vme_mvme147_card_device::pcc8_w)); /* PCC 8 bits registers */
map(0xfffe2000, 0xfffe201b).rw(FUNC(vme_mvme147_card_device::vmechip_r), FUNC(vme_mvme147_card_device::vmechip_w)).umask32(0x00ff00ff); /* VMEchip 8 bits registers on odd adresses */
map(0xfffe3000, 0xfffe3003).rw(m_sccterm, FUNC(scc85c30_device::ab_dc_r), FUNC(scc85c30_device::ab_dc_w)); /* Port 1&2 - Dual serial port Z80-SCC */
map(0xfffe3800, 0xfffe3803).rw(m_sccterm2, FUNC(scc85c30_device::ab_dc_r), FUNC(scc85c30_device::ab_dc_w)); /* Port 3&4 - Dual serial port Z80-SCC */
//map(0x100000, 0xfeffff).rw(FUNC(mvme147_state::vme_a24_r), FUNC(mvme147_state::vme_a24_w)); /* VMEbus Rev B addresses (24 bits) - not verified */
//map(0xff0000, 0xffffff).rw(FUNC(mvme147_state::vme_a16_r), FUNC(mvme147_state::vme_a16_w)); /* VMEbus Rev B addresses (16 bits) - not verified */
//map(0x100000, 0xfeffff).rw(FUNC(vme_mvme147_card_device::vme_a24_r), FUNC(vme_mvme147_card_device::vme_a24_w)); /* VMEbus Rev B addresses (24 bits) - not verified */
//map(0xff0000, 0xffffff).rw(FUNC(vme_mvme147_card_device::vme_a16_r), FUNC(vme_mvme147_card_device::vme_a16_w)); /* VMEbus Rev B addresses (16 bits) - not verified */
}
/* Input ports */
@ -256,42 +217,38 @@ static INPUT_PORTS_START (mvme147)
INPUT_PORTS_END
/* Start it up */
void mvme147_state::machine_start ()
void vme_mvme147_card_device::device_start ()
{
LOG("%s\n", FUNCNAME);
/* Setup pointer to bootvector in ROM for bootvector handler bootvect_r */
m_sysrom = (uint32_t*)(memregion ("roms")->base () + 0x800000);
m_genpurp_stat = 0x02; /* Indicate power up reset */
m_vc_cntl_conf = 0x01; /* We are the system controller */
}
void mvme147_state::machine_reset ()
void vme_mvme147_card_device::device_reset ()
{
LOG("%s\n", FUNCNAME);
/* Reset pointer to bootvector in ROM for bootvector handler bootvect_r */
if (m_sysrom == &m_sysram[0]) /* Condition needed because memory map is not setup first time */
m_sysrom = (uint32_t*)(memregion ("roms")->base () + 0x800000);
m_maincpu->space(AS_PROGRAM).install_rom(0, m_system->bytes() - 1, m_system->base());
m_boot_mph = m_maincpu->space(AS_PROGRAM).install_read_tap(0x000004, 0x000007, "boot",
[this](offs_t offset, uint32_t &data, uint32_t mem_mask)
{
if (!machine().side_effects_disabled() && ACCESSING_BITS_0_15)
{
m_maincpu->space(AS_PROGRAM).install_ram(0, m_ram.bytes() - 1, m_ram.target());
m_boot_mph.remove();
}
});
m_genpurp_stat &= 0xfe; /* Clear parity error bit - not used by MAME at this point so just for the record */
}
/* Boot vector handler, the PCB hardwires the first 8 bytes from 0xff800000 to 0x0 at reset*/
uint32_t mvme147_state::bootvect_r(offs_t offset){
return m_sysrom[offset];
}
void mvme147_state::bootvect_w(offs_t offset, uint32_t data, uint32_t mem_mask){
m_sysram[offset % std::size(m_sysram)] &= ~mem_mask;
m_sysram[offset % std::size(m_sysram)] |= (data & mem_mask);
m_sysrom = &m_sysram[0]; // redirect all upcoming accesses to masking RAM until reset.
}
/****
* PCC - Peripheral Channel Controller driver, might deserve its own driver but will rest here until another board wants it
*/
#if 0 /* Doesn't compile atm */
uint32_t mvme147_state::pcc32_r(offs_t offset){
uint32_t vme_mvme147_card_device::pcc32_r(offs_t offset){
LOG("%s[%04x]", FUNCNAME, offset);
switch(offset)
{
@ -301,7 +258,7 @@ uint32_t mvme147_state::pcc32_r(offs_t offset){
return 0x00;
}
void mvme147_state::pcc32_w(offs_t offset, uint32_t data){
void vme_mvme147_card_device::pcc32_w(offs_t offset, uint32_t data){
LOG("%s[%04x]= %08lx", FUNCNAME, offset, data);
switch(offset)
{
@ -317,7 +274,7 @@ void mvme147_state::pcc32_w(offs_t offset, uint32_t data){
#define P16_TIMER2_PRELOAD (P16BASE + 4)
#define P16_TIMER2_COUNT (P16BASE + 6)
uint16_t mvme147_state::pcc16_r(offs_t offset){
uint16_t vme_mvme147_card_device::pcc16_r(offs_t offset){
uint16_t ret = 0;
LOG("Call to %s[%04x]", FUNCNAME, offset);
@ -333,7 +290,7 @@ uint16_t mvme147_state::pcc16_r(offs_t offset){
return ret;
}
void mvme147_state::pcc16_w(offs_t offset, uint16_t data){
void vme_mvme147_card_device::pcc16_w(offs_t offset, uint16_t data){
LOG("Call to %s[%04x] <- %04x - ", FUNCNAME, offset, data);
switch(offset)
{
@ -374,7 +331,7 @@ void mvme147_state::pcc16_w(offs_t offset, uint16_t data){
#define P8_PRINTER_DATA 0xfffe2800
#define P8_PRINTER_STATUS 0xfffe2800
uint8_t mvme147_state::pcc8_r(offs_t offset){
uint8_t vme_mvme147_card_device::pcc8_r(offs_t offset){
uint8_t ret = 0;
LOG("Call to %s[%04x] ", FUNCNAME, offset);
@ -421,7 +378,7 @@ uint8_t mvme147_state::pcc8_r(offs_t offset){
return ret;
}
void mvme147_state::pcc8_w(offs_t offset, uint8_t data){
void vme_mvme147_card_device::pcc8_w(offs_t offset, uint8_t data){
LOG("Call to %s[%04x] <- %02x - ", FUNCNAME, offset, data);
switch(offset + P8BASE)
{
@ -497,7 +454,7 @@ void mvme147_state::pcc8_w(offs_t offset, uint8_t data){
#define VC_GCSR_BASE_ADR 0xfffe201B
uint8_t mvme147_state::vmechip_r(offs_t offset){
uint8_t vme_mvme147_card_device::vmechip_r(offs_t offset){
uint8_t ret = 0;
LOG("Call to %s[%04x] ", FUNCNAME, offset);
@ -584,7 +541,7 @@ uint8_t mvme147_state::vmechip_r(offs_t offset){
return ret;
}
void mvme147_state::vmechip_w(offs_t offset, uint8_t data){
void vme_mvme147_card_device::vmechip_w(offs_t offset, uint8_t data){
LOG("Call to %s[%04x] <- %02x - ", FUNCNAME, offset, data);
switch(offset * 2 + VCBASE)
{
@ -613,41 +570,33 @@ void mvme147_state::vmechip_w(offs_t offset, uint8_t data){
#if 0
/* Dummy VME access methods until the VME bus device is ready for use */
uint16_t mvme147_state::vme_a24_r(){
uint16_t vme_mvme147_card_device::vme_a24_r(){
LOG("%s\n", FUNCNAME);
return (uint16_t) 0;
}
void mvme147_state::vme_a24_w(uint16_t data){
void vme_mvme147_card_device::vme_a24_w(uint16_t data){
LOG("%s\n", FUNCNAME);
}
uint16_t mvme147_state::vme_a16_r(){
uint16_t vme_mvme147_card_device::vme_a16_r(){
LOG("%s\n", FUNCNAME);
return (uint16_t) 0;
}
void mvme147_state::vme_a16_w(uint16_t data){
void vme_mvme147_card_device::vme_a16_w(uint16_t data){
LOG("%s\n", FUNCNAME);
}
#endif
static void mvme147_vme_cards(device_slot_interface &device)
{
device.option_add("mvme350", VME_MVME350);
}
/*
* Machine configuration
*/
void mvme147_state::mvme147(machine_config &config)
void vme_mvme147_card_device::device_add_mconfig(machine_config &config)
{
/* basic machine hardware */
M68030(config, m_maincpu, 16_MHz_XTAL);
m_maincpu->set_addrmap(AS_PROGRAM, &mvme147_state::mvme147_mem);
VME(config, "vme", 0);
VME_SLOT(config, "slot1", mvme147_vme_cards, nullptr, 1, "vme");
m_maincpu->set_addrmap(AS_PROGRAM, &vme_mvme147_card_device::mvme147_mem);
M48T02(config, "m48t18", 0); /* t08 differs only in accepted voltage levels compared to t18 */
@ -666,12 +615,12 @@ void mvme147_state::mvme147(machine_config &config)
/* ROM definitions */
ROM_START (mvme147)
ROM_REGION32_BE(0xf00000, "roms", 0)
ROM_REGION32_BE(0x40000, "system", 0)
ROM_DEFAULT_BIOS("147bug-v2.44")
ROM_SYSTEM_BIOS(0, "147bug-v2.44", "MVME147 147bug v2.44")
ROMX_LOAD("147bug-2.44-u22.bin", 0x800000, 0x20000, CRC (da09ce8a) SHA1 (3eaa8fa802187d9b08f453ff1ba64f5113a195a9), ROM_SKIP(1) | ROM_BIOS(0))
ROMX_LOAD("147bug-2.44-u30.bin", 0x800001, 0x20000, CRC (f883e17d) SHA1 (01fe43e5ddfd3cf8aabb5a5959c80a8b5ec5d895), ROM_SKIP(1) | ROM_BIOS(0))
ROMX_LOAD("147bug-2.44-u22.bin", 0x00000, 0x20000, CRC (da09ce8a) SHA1 (3eaa8fa802187d9b08f453ff1ba64f5113a195a9), ROM_SKIP(1) | ROM_BIOS(0))
ROMX_LOAD("147bug-2.44-u30.bin", 0x00001, 0x20000, CRC (f883e17d) SHA1 (01fe43e5ddfd3cf8aabb5a5959c80a8b5ec5d895), ROM_SKIP(1) | ROM_BIOS(0))
/*
* System ROM information
*
@ -697,8 +646,8 @@ ROM_START (mvme147)
*/
ROM_SYSTEM_BIOS(1, "147bug-v2.43", "MVME147 147bug v2.43")
ROMX_LOAD("5741b42e.bin", 0x800000, 0x20000, CRC (2ba98f97) SHA1 (5f18c6dd6a7b03067890f0164ef3d37ced907d7f), ROM_SKIP(1) | ROM_BIOS(1))
ROMX_LOAD("5741b41e.bin", 0x800001, 0x20000, CRC (dfa014f2) SHA1 (ff9db90a05c295819ce7ca7c1a6ac67b04003728), ROM_SKIP(1) | ROM_BIOS(1))
ROMX_LOAD("5741b42e.bin", 0x00000, 0x20000, CRC (2ba98f97) SHA1 (5f18c6dd6a7b03067890f0164ef3d37ced907d7f), ROM_SKIP(1) | ROM_BIOS(1))
ROMX_LOAD("5741b41e.bin", 0x00001, 0x20000, CRC (dfa014f2) SHA1 (ff9db90a05c295819ce7ca7c1a6ac67b04003728), ROM_SKIP(1) | ROM_BIOS(1))
/*
* System ROM information
*
@ -708,9 +657,16 @@ ROM_START (mvme147)
ROM_END
} // anonymous namespace
const tiny_rom_entry *vme_mvme147_card_device::device_rom_region() const
{
return ROM_NAME(mvme147);
}
ioport_constructor vme_mvme147_card_device::device_input_ports() const
{
return INPUT_PORTS_NAME(mvme147);
}
/* Driver */
// YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS
COMP( 1989, mvme147, 0, 0, mvme147, mvme147, mvme147_state, empty_init, "Motorola", "MVME-147", MACHINE_NO_SOUND_HW )
//COMP( 1989, mvme147, 0, 0, mvme147, mvme147, vme_mvme147_card_device, empty_init, "Motorola", "MVME-147", MACHINE_NO_SOUND_HW )

59
src/devices/bus/vme/mvme147.h Normal file
View File

@ -0,0 +1,59 @@
// license:BSD-3-Clause
// copyright-holders:Joakim Larsson Edstrom
#ifndef MAME_BUS_VME_MVME147_H
#define MAME_BUS_VME_MVME147_H
#pragma once
#include "bus/vme/vme.h"
#include "machine/z80scc.h"
class vme_mvme147_card_device
: public device_t
, public device_vme_card_interface
{
public:
vme_mvme147_card_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock);
protected:
virtual const tiny_rom_entry *device_rom_region() const override;
virtual void device_add_mconfig(machine_config &config) override;
virtual ioport_constructor device_input_ports() const override;
virtual void device_start() override;
virtual void device_reset() override;
private:
/* PCC - Peripheral Channel Controller */
//uint32_t pcc32_r(offs_t offset);
//void pcc32_w(offs_t offset, uint32_t data);
uint16_t pcc16_r(offs_t offset);
void pcc16_w(offs_t offset, uint16_t data);
uint8_t pcc8_r(offs_t offset);
void pcc8_w(offs_t offset, uint8_t data);
uint8_t vmechip_r(offs_t offset);
void vmechip_w(offs_t offset, uint8_t data);
//uint16_t vme_a24_r();
//void vme_a24_w(uint16_t data);
//uint16_t vme_a16_r();
//void vme_a16_w(uint16_t data);
void mvme147_mem(address_map &map);
required_device<cpu_device> m_maincpu;
required_device<scc85c30_device> m_sccterm;
required_device<scc85c30_device> m_sccterm2;
required_memory_region m_system;
required_shared_ptr<uint32_t> m_ram;
memory_passthrough_handler m_boot_mph;
// PCC registers
uint8_t m_genpurp_stat = 0;
// VME chip registers
uint8_t m_vc_cntl_conf = 0;
};
DECLARE_DEVICE_TYPE(VME_MVME147, vme_mvme147_card_device)
#endif // MAME_BUS_VME_MVME147_H

26
src/devices/bus/vme/vme_mvme180.cpp → src/devices/bus/vme/mvme180.cpp
View File

@ -12,14 +12,14 @@
*/
#include "emu.h"
#include "vme_mvme180.h"
#include "mvme180.h"
#define VERBOSE 0
#include "logmacro.h"
DEFINE_DEVICE_TYPE(VME_MVME180, vme_mvme180_device, "mvme180", "Motorola MVME180")
DEFINE_DEVICE_TYPE(VME_MVME180, vme_mvme180_card_device, "mvme180", "Motorola MVME180")
vme_mvme180_device::vme_mvme180_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock)
vme_mvme180_card_device::vme_mvme180_card_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock)
: device_t(mconfig, VME_MVME180, tag, owner, clock)
, device_vme_card_interface(mconfig, *this)
, m_cpu(*this, "cpu")
@ -42,31 +42,31 @@ ROM_END
static INPUT_PORTS_START(mvme180)
INPUT_PORTS_END
const tiny_rom_entry *vme_mvme180_device::device_rom_region() const
const tiny_rom_entry *vme_mvme180_card_device::device_rom_region() const
{
return ROM_NAME(mvme180);
}
ioport_constructor vme_mvme180_device::device_input_ports() const
ioport_constructor vme_mvme180_card_device::device_input_ports() const
{
return INPUT_PORTS_NAME(mvme180);
}
void vme_mvme180_device::device_start()
void vme_mvme180_card_device::device_start()
{
m_isr = 0;
m_imr = 0;
}
void vme_mvme180_device::device_reset()
void vme_mvme180_card_device::device_reset()
{
m_boot.select(0);
}
void vme_mvme180_device::device_add_mconfig(machine_config &config)
void vme_mvme180_card_device::device_add_mconfig(machine_config &config)
{
MC88100(config, m_cpu, 40_MHz_XTAL / 2);
m_cpu->set_addrmap(AS_PROGRAM, &vme_mvme180_device::cpu_mem);
m_cpu->set_addrmap(AS_PROGRAM, &vme_mvme180_card_device::cpu_mem);
MC88200(config, m_mmu[0], 40_MHz_XTAL / 2, 0x7e);
m_mmu[0]->set_mbus(m_cpu, AS_PROGRAM);
@ -77,7 +77,7 @@ void vme_mvme180_device::device_add_mconfig(machine_config &config)
m_cpu->set_cmmu_d(m_mmu[1]);
SCN2681(config, m_duart, 3.6864_MHz_XTAL);
m_duart->irq_cb().set(FUNC(vme_mvme180_device::irq_w<6>));
m_duart->irq_cb().set(FUNC(vme_mvme180_card_device::irq_w<6>));
m_duart->outport_cb().set([this](u8 data) { LOG("port 0x%02x\n", data); });
RS232_PORT(config, m_serial[0], default_rs232_devices, "terminal");
@ -90,7 +90,7 @@ void vme_mvme180_device::device_add_mconfig(machine_config &config)
m_serial[1]->rxd_handler().set(m_duart, FUNC(scn2681_device::rx_b_w));
}
void vme_mvme180_device::cpu_mem(address_map &map)
void vme_mvme180_card_device::cpu_mem(address_map &map)
{
map(0x0000'0000, 0x007f'ffff).view(m_boot);
m_boot[0](0x0000'0000, 0x0003'ffff).rom().region("eprom", 0);
@ -115,7 +115,7 @@ void vme_mvme180_device::cpu_mem(address_map &map)
// 0xffee'0000 // clear abort interrupt?
}
template <unsigned N> void vme_mvme180_device::irq_w(int state)
template <unsigned N> void vme_mvme180_card_device::irq_w(int state)
{
LOG("irq_w<%d> %d\n", N, state);
if (state)
@ -126,7 +126,7 @@ template <unsigned N> void vme_mvme180_device::irq_w(int state)
interrupt();
}
void vme_mvme180_device::interrupt()
void vme_mvme180_card_device::interrupt()
{
m_cpu->set_input_line(INPUT_LINE_IRQ0, bool(m_isr & m_imr));
}

6
src/devices/bus/vme/vme_mvme180.h → src/devices/bus/vme/mvme180.h
View File

@ -14,12 +14,12 @@
#include "bus/rs232/rs232.h"
class vme_mvme180_device
class vme_mvme180_card_device
: public device_t
, public device_vme_card_interface
{
public:
vme_mvme180_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock);
vme_mvme180_card_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock);
protected:
// device_t overrides
@ -47,6 +47,6 @@ private:
u8 m_imr; // interrupt mask register
};
DECLARE_DEVICE_TYPE(VME_MVME180, vme_mvme180_device)
DECLARE_DEVICE_TYPE(VME_MVME180, vme_mvme180_card_device)
#endif // MAME_BUS_VME_MVME180_H

26
src/devices/bus/vme/vme_mvme181.cpp → src/devices/bus/vme/mvme181.cpp
View File

@ -23,14 +23,14 @@
*/
#include "emu.h"
#include "vme_mvme181.h"
#include "mvme181.h"
#define VERBOSE 0
#include "logmacro.h"
DEFINE_DEVICE_TYPE(VME_MVME181, vme_mvme181_device, "mvme181", "Motorola MVME181")
DEFINE_DEVICE_TYPE(VME_MVME181, vme_mvme181_card_device, "mvme181", "Motorola MVME181")
vme_mvme181_device::vme_mvme181_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock)
vme_mvme181_card_device::vme_mvme181_card_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock)
: device_t(mconfig, VME_MVME181, tag, owner, clock)
, device_vme_card_interface(mconfig, *this)
, m_cpu(*this, "cpu")
@ -54,17 +54,17 @@ ROM_END
static INPUT_PORTS_START(mvme181)
INPUT_PORTS_END
const tiny_rom_entry *vme_mvme181_device::device_rom_region() const
const tiny_rom_entry *vme_mvme181_card_device::device_rom_region() const
{
return ROM_NAME(mvme181);
}
ioport_constructor vme_mvme181_device::device_input_ports() const
ioport_constructor vme_mvme181_card_device::device_input_ports() const
{
return INPUT_PORTS_NAME(mvme181);
}
void vme_mvme181_device::device_start()
void vme_mvme181_card_device::device_start()
{
m_isr = 0;
m_imr = 0;
@ -87,15 +87,15 @@ void vme_mvme181_device::device_start()
});
}
void vme_mvme181_device::device_reset()
void vme_mvme181_card_device::device_reset()
{
m_boot.select(0);
}
void vme_mvme181_device::device_add_mconfig(machine_config &config)
void vme_mvme181_card_device::device_add_mconfig(machine_config &config)
{
MC88100(config, m_cpu, 40_MHz_XTAL / 2);
m_cpu->set_addrmap(AS_PROGRAM, &vme_mvme181_device::cpu_mem);
m_cpu->set_addrmap(AS_PROGRAM, &vme_mvme181_card_device::cpu_mem);
MC88200(config, m_mmu[0], 40_MHz_XTAL / 2, 0x7e);
m_mmu[0]->set_mbus(m_cpu, AS_PROGRAM);
@ -108,7 +108,7 @@ void vme_mvme181_device::device_add_mconfig(machine_config &config)
DS1315(config, m_rtc, 0); // DS1216
SCN2681(config, m_duart, 3.6864_MHz_XTAL); // SCC68692C1A44
m_duart->irq_cb().set(FUNC(vme_mvme181_device::irq_w<6>));
m_duart->irq_cb().set(FUNC(vme_mvme181_card_device::irq_w<6>));
m_duart->outport_cb().set([this](u8 data) { LOG("port 0x%02x\n", data); });
RS232_PORT(config, m_serial[0], default_rs232_devices, "terminal");
@ -121,7 +121,7 @@ void vme_mvme181_device::device_add_mconfig(machine_config &config)
m_serial[1]->rxd_handler().set(m_duart, FUNC(scn2681_device::rx_b_w));
}
void vme_mvme181_device::cpu_mem(address_map &map)
void vme_mvme181_card_device::cpu_mem(address_map &map)
{
map(0x0000'0000, 0x007f'ffff).view(m_boot);
m_boot[0](0x0000'0000, 0x0007'ffff).rom().region("eprom", 0);
@ -145,7 +145,7 @@ void vme_mvme181_device::cpu_mem(address_map &map)
// 0xffee'0000 // clear abort interrupt?
}
template <unsigned N> void vme_mvme181_device::irq_w(int state)
template <unsigned N> void vme_mvme181_card_device::irq_w(int state)
{
LOG("irq_w<%d> %d\n", N, state);
if (state)
@ -156,7 +156,7 @@ template <unsigned N> void vme_mvme181_device::irq_w(int state)
interrupt();
}
void vme_mvme181_device::interrupt()
void vme_mvme181_card_device::interrupt()
{
m_cpu->set_input_line(INPUT_LINE_IRQ0, bool(m_isr & m_imr));
}

6
src/devices/bus/vme/vme_mvme181.h → src/devices/bus/vme/mvme181.h
View File

@ -14,12 +14,12 @@
#include "bus/vme/vme.h"
#include "bus/rs232/rs232.h"
class vme_mvme181_device
class vme_mvme181_card_device
: public device_t
, public device_vme_card_interface
{
public:
vme_mvme181_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock);
vme_mvme181_card_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock);
protected:
virtual const tiny_rom_entry *device_rom_region() const override;
@ -47,6 +47,6 @@ private:
u8 m_imr; // interrupt mask register
};
DECLARE_DEVICE_TYPE(VME_MVME181, vme_mvme181_device)
DECLARE_DEVICE_TYPE(VME_MVME181, vme_mvme181_card_device)
#endif // MAME_BUS_VME_MVME181_H

20
src/devices/bus/vme/mvme187.cpp
View File

@ -57,10 +57,10 @@
#define VERBOSE 0
#include "logmacro.h"
DEFINE_DEVICE_TYPE(MVME187, mvme187_device, "mvme187", "Motorola MVME187")
DEFINE_DEVICE_TYPE(VME_MVME187, vme_mvme187_card_device, "mvme187", "Motorola MVME187")
mvme187_device::mvme187_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock)
: device_t(mconfig, MVME187, tag, owner, clock)
vme_mvme187_card_device::vme_mvme187_card_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock)
: device_t(mconfig, VME_MVME187, tag, owner, clock)
, device_vme_card_interface(mconfig, *this)
, m_cpu(*this, "cpu")
, m_mmu(*this, "mmu%u", 0U)
@ -83,29 +83,29 @@ ROM_END
static INPUT_PORTS_START(mvme187)
INPUT_PORTS_END
const tiny_rom_entry *mvme187_device::device_rom_region() const
const tiny_rom_entry *vme_mvme187_card_device::device_rom_region() const
{
return ROM_NAME(mvme187);
}
ioport_constructor mvme187_device::device_input_ports() const
ioport_constructor vme_mvme187_card_device::device_input_ports() const
{
return INPUT_PORTS_NAME(mvme187);
}
void mvme187_device::device_start()
void vme_mvme187_card_device::device_start()
{
}
void mvme187_device::device_reset()
void vme_mvme187_card_device::device_reset()
{
m_boot.select(0);
}
void mvme187_device::device_add_mconfig(machine_config &config)
void vme_mvme187_card_device::device_add_mconfig(machine_config &config)
{
MC88100(config, m_cpu, 50_MHz_XTAL / 2);
m_cpu->set_addrmap(AS_PROGRAM, &mvme187_device::cpu_mem);
m_cpu->set_addrmap(AS_PROGRAM, &vme_mvme187_card_device::cpu_mem);
MC88200(config, m_mmu[0], 50_MHz_XTAL / 2, 0x77);
m_mmu[0]->set_mbus(m_cpu, AS_PROGRAM);
@ -128,7 +128,7 @@ void mvme187_device::device_add_mconfig(machine_config &config)
I82596_BE32(config, m_lan, 20'000'000);
}
void mvme187_device::cpu_mem(address_map &map)
void vme_mvme187_card_device::cpu_mem(address_map &map)
{
map(0x0000'0000, 0x00ff'ffff).view(m_boot);
m_boot[0](0x0000'0000, 0x0007'ffff).rom().region("eprom", 0);

6
src/devices/bus/vme/mvme187.h
View File

@ -17,12 +17,12 @@
#include "bus/vme/vme.h"
#include "bus/rs232/rs232.h"
class mvme187_device
class vme_mvme187_card_device
: public device_t
, public device_vme_card_interface
{
public:
mvme187_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock);
vme_mvme187_card_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock);
protected:
virtual const tiny_rom_entry *device_rom_region() const override;
@ -46,6 +46,6 @@ private:
memory_view m_boot;
};
DECLARE_DEVICE_TYPE(MVME187, mvme187_device)
DECLARE_DEVICE_TYPE(VME_MVME187, vme_mvme187_card_device)
#endif // MAME_BUS_VME_MVME187_H

2
src/devices/bus/vme/vme_mvme327a.cpp → src/devices/bus/vme/mvme327a.cpp
View File

@ -12,7 +12,7 @@
*/
#include "emu.h"
#include "vme_mvme327a.h"
#include "mvme327a.h"
#include "bus/nscsi/hd.h"
#include "bus/nscsi/cd.h"

0
src/devices/bus/vme/vme_mvme327a.h → src/devices/bus/vme/mvme327a.h
View File

4
src/devices/bus/vme/vme_mvme350.cpp → src/devices/bus/vme/mvme350.cpp
View File

@ -128,7 +128,7 @@
****************************************************************************/
#include "emu.h"
#include "vme_mvme350.h"
#include "mvme350.h"
#include "cpu/m68000/m68010.h"
#include "machine/68230pit.h"
@ -149,7 +149,7 @@
// GLOBAL VARIABLES
//**************************************************************************
DEFINE_DEVICE_TYPE(VME_MVME350, vme_mvme350_card_device, "mvme350", "Motorola MVME-350 Intelligent Tape Controller")
DEFINE_DEVICE_TYPE(VME_MVME350, vme_mvme350_card_device, "mvme350", "Motorola MVME350")
#define MVME350_CPU_TAG "mvme350_cpu"
#define MVME350_ROM "mvme350_rom"

6
src/devices/bus/vme/vme_mvme350.h → src/devices/bus/vme/mvme350.h
View File

@ -1,7 +1,7 @@
// license:BSD-3-Clause
// copyright-holders:Joakim Larsson Edstrom
#ifndef MAME_BUS_VME_VME_MVME350_H
#define MAME_BUS_VME_VME_MVME350_H
#ifndef MAME_BUS_VME_MVME350_H
#define MAME_BUS_VME_MVME350_H
#pragma once
@ -32,4 +32,4 @@ private:
void mvme350_mem(address_map &map);
};
#endif // MAME_BUS_VME_VME_MVME350_H
#endif // MAME_BUS_VME_MVME350_H

63
src/mame/mizar/mzr8105.cpp → src/devices/bus/vme/mzr8105.cpp
View File

@ -163,60 +163,48 @@
*
****************************************************************************/
#include "emu.h"
#include "bus/vme/vme.h"
#include "bus/vme/vme_mzr8300.h"
#include "bus/vme/vme_mvme350.h"
#include "mzr8105.h"
#include "cpu/m68000/m68000.h"
#include "machine/clock.h"
DEFINE_DEVICE_TYPE(VME_MZR8105, vme_mzr8105_card_device, "mzr8105", "Mizar VME8105")
namespace {
class mzr8105_state : public driver_device
vme_mzr8105_card_device::vme_mzr8105_card_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock)
: device_t(mconfig, VME_MZR8105, tag, owner, clock)
, device_vme_card_interface(mconfig, *this)
, m_maincpu (*this, "maincpu")
{
public:
mzr8105_state(const machine_config &mconfig, device_type type, const char *tag) :
driver_device (mconfig, type, tag)
,m_maincpu (*this, "maincpu")
{
}
}
void mzr8105(machine_config &config);
void vme_mzr8105_card_device::device_start()
{
}
private:
void mzr8105_mem(address_map &map);
required_device<cpu_device> m_maincpu;
};
void vme_mzr8105_card_device::device_reset()
{
}
void mzr8105_state::mzr8105_mem(address_map &map)
void vme_mzr8105_card_device::mzr8105_mem(address_map &map)
{
map.unmap_value_high();
/* The ROMs contains an OS9 bootloader. It is position independent but reset vector suggests that it sits flat on adress 0 (zero) */
map(0x000000, 0x003fff).rom().region("roms", 0x000000); /* System EPROM Area 16Kb OS9 DEBUG - not verified */
map(0x004000, 0x01ffff).rom().region("roms", 0x004000);/* System EPROM Area 112Kb for System ROM - not verified */
map(0x000000, 0x01ffff).rom().region("roms", 0); /* System EPROM Area 16Kb OS9 DEBUG - not verified */
map(0x020000, 0x03ffff).ram(); /* Not verified */
// map(0x100000, 0xfeffff).rw(FUNC(mzr8105_state::vme_a24_r), FUNC(mzr8105_state::vme_a24_w)); /* VMEbus Rev B addresses (24 bits) - not verified */
// map(0xff0000, 0xffffff).rw(FUNC(mzr8105_state::vme_a16_r), FUNC(mzr8105_state::vme_a16_w)); /* VMEbus Rev B addresses (16 bits) - not verified */
// map(0x100000, 0xfeffff).rw(FUNC(vme_mzr8105_card_device::vme_a24_r), FUNC(vme_mzr8105_card_device::vme_a24_w)); /* VMEbus Rev B addresses (24 bits) - not verified */
map(0xff0000, 0xffffff).rw(FUNC(device_vme_card_interface::vme_read16<vme::AM_29>), FUNC(device_vme_card_interface::vme_write16<vme::AM_29>)); /* VMEbus Rev B addresses (16 bits) - not verified */
}
/* Input ports */
static INPUT_PORTS_START (mzr8105)
INPUT_PORTS_END
static void mzr8105_vme_cards(device_slot_interface &device)
{
device.option_add("mzr8300", VME_MZR8300);
}
/*
* Machine configuration
*/
void mzr8105_state::mzr8105(machine_config &config)
void vme_mzr8105_card_device::device_add_mconfig(machine_config &config)
{
M68000(config, m_maincpu, XTAL(10'000'000));
m_maincpu->set_addrmap(AS_PROGRAM, &mzr8105_state::mzr8105_mem);
VME(config, "vme", 0).use_owner_spaces();
VME_SLOT(config, "slot1", mzr8105_vme_cards, "mzr8300", 1, "vme");
m_maincpu->set_addrmap(AS_PROGRAM, &vme_mzr8105_card_device::mzr8105_mem);
}
/* ROM definitions */
@ -234,9 +222,16 @@ ROM_START (mzr8105)
ROM_LOAD16_BYTE ("mzros9hb.bin", 0x000000, 0x2000, CRC (d18e69a6) SHA1 (a00b68f4d649bcc09a29361f8692e52be12b3792))
ROM_END
} // anonymous namespace
const tiny_rom_entry *vme_mzr8105_card_device::device_rom_region() const
{
return ROM_NAME(mzr8105);
}
ioport_constructor vme_mzr8105_card_device::device_input_ports() const
{
return INPUT_PORTS_NAME(mzr8105);
}
/* Driver */
// YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS
COMP( 1987, mzr8105, 0, 0, mzr8105, mzr8105, mzr8105_state, empty_init, "Mizar Inc", "Mizar VME8105", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW )
//COMP( 1987, mzr8105, 0, 0, mzr8105, mzr8105, vme_mzr8105_card_device, empty_init, "Mizar Inc", "Mizar VME8105", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW )

32
src/devices/bus/vme/mzr8105.h Normal file
View File

@ -0,0 +1,32 @@
// license:BSD-3-Clause
// copyright-holders:Joakim Larsson Edstrom
#ifndef MAME_BUS_VME_MZR8105_H
#define MAME_BUS_VME_MZR8105_H
#pragma once
#include "bus/vme/vme.h"
class vme_mzr8105_card_device
: public device_t
, public device_vme_card_interface
{
public:
vme_mzr8105_card_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock);
protected:
virtual const tiny_rom_entry *device_rom_region() const override;
virtual void device_add_mconfig(machine_config &config) override;
virtual ioport_constructor device_input_ports() const override;
virtual void device_start() override;
virtual void device_reset() override;
private:
void mzr8105_mem(address_map &map);
required_device<cpu_device> m_maincpu;
};
DECLARE_DEVICE_TYPE(VME_MZR8105, vme_mzr8105_card_device)
#endif // MAME_BUS_VME_MZR8105_H

79
src/devices/bus/vme/vme_mzr8300.cpp → src/devices/bus/vme/mzr8300.cpp
View File

@ -82,10 +82,8 @@
****************************************************************************/
#include "emu.h"
#include "vme_mzr8300.h"
#include "mzr8300.h"
#include "machine/am9513.h"
#include "machine/z80sio.h"
#include "bus/rs232/rs232.h"
#define VERBOSE (0) // (LOG_GENERAL)
@ -104,7 +102,7 @@
// GLOBAL VARIABLES
//**************************************************************************
DEFINE_DEVICE_TYPE(VME_MZR8300, vme_mzr8300_card_device, "mzr8300", "Mizar 8300 SIO serial board")
DEFINE_DEVICE_TYPE(VME_MZR8300, vme_mzr8300_card_device, "mzr8300", "Mizar 8300")
/* These values are borrowed just to get the terminal going and should be replaced
* once a proper serial board hardware (ie MZ 8300) is found and emulated. */
@ -116,26 +114,26 @@ DEFINE_DEVICE_TYPE(VME_MZR8300, vme_mzr8300_card_device, "mzr8300", "Mizar 8300
void vme_mzr8300_card_device::device_add_mconfig(machine_config &config)
{
upd7201_device& sio0(UPD7201(config, "sio0", XTAL(4'000'000)));
sio0.out_txdb_callback().set("rs232p1", FUNC(rs232_port_device::write_txd));
sio0.out_dtrb_callback().set("rs232p1", FUNC(rs232_port_device::write_dtr));
sio0.out_rtsb_callback().set("rs232p1", FUNC(rs232_port_device::write_rts));
UPD7201(config, m_sio[0], XTAL(4'000'000));
m_sio[0]->out_txdb_callback().set("rs232p1", FUNC(rs232_port_device::write_txd));
m_sio[0]->out_dtrb_callback().set("rs232p1", FUNC(rs232_port_device::write_dtr));
m_sio[0]->out_rtsb_callback().set("rs232p1", FUNC(rs232_port_device::write_rts));
UPD7201(config, "sio1", XTAL(4'000'000));
UPD7201(config, m_sio[1], XTAL(4'000'000));
rs232_port_device &rs232p1(RS232_PORT(config, "rs232p1", default_rs232_devices, "terminal"));
rs232p1.rxd_handler().set("sio0", FUNC(upd7201_device::rxb_w));
rs232p1.cts_handler().set("sio0", FUNC(upd7201_device::ctsb_w));
rs232p1.rxd_handler().set(m_sio[0], FUNC(upd7201_device::rxb_w));
rs232p1.cts_handler().set(m_sio[0], FUNC(upd7201_device::ctsb_w));
am9513_device &stc(AM9513(config, "stc", 4_MHz_XTAL));
stc.out1_cb().set("sio0", FUNC(upd7201_device::rxca_w));
stc.out1_cb().append("sio0", FUNC(upd7201_device::txca_w));
stc.out2_cb().set("sio0", FUNC(upd7201_device::rxcb_w));
stc.out2_cb().append("sio0", FUNC(upd7201_device::txcb_w));
stc.out3_cb().set("sio1", FUNC(upd7201_device::rxca_w));
stc.out3_cb().append("sio1", FUNC(upd7201_device::txca_w));
stc.out4_cb().set("sio1", FUNC(upd7201_device::rxcb_w));
stc.out4_cb().append("sio1", FUNC(upd7201_device::txcb_w));
AM9513(config, m_stc, 4_MHz_XTAL);
m_stc->out1_cb().set(m_sio[0], FUNC(upd7201_device::rxca_w));
m_stc->out1_cb().append(m_sio[0], FUNC(upd7201_device::txca_w));
m_stc->out2_cb().set(m_sio[0], FUNC(upd7201_device::rxcb_w));
m_stc->out2_cb().append(m_sio[0], FUNC(upd7201_device::txcb_w));
m_stc->out3_cb().set(m_sio[1], FUNC(upd7201_device::rxca_w));
m_stc->out3_cb().append(m_sio[1], FUNC(upd7201_device::txca_w));
m_stc->out4_cb().set(m_sio[1], FUNC(upd7201_device::rxcb_w));
m_stc->out4_cb().append(m_sio[1], FUNC(upd7201_device::txcb_w));
}
@ -143,9 +141,11 @@ void vme_mzr8300_card_device::device_add_mconfig(machine_config &config)
// LIVE DEVICE
//**************************************************************************
vme_mzr8300_card_device::vme_mzr8300_card_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock) :
device_t(mconfig, type, tag, owner, clock),
device_vme_card_interface(mconfig, *this)
vme_mzr8300_card_device::vme_mzr8300_card_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
: device_t(mconfig, type, tag, owner, clock)
, device_vme_card_interface(mconfig, *this)
, m_sio(*this, "sio%u", 0U)
, m_stc(*this, "stc")
{
LOG("%s %s\n", tag, FUNCNAME);
}
@ -160,24 +160,21 @@ void vme_mzr8300_card_device::device_start()
LOG("%s %s\n", tag(), FUNCNAME);
/* Setup r/w handlers for first SIO in A16 */
uint32_t base = 0xFF0000;
// m_vme->static_set_custom_spaces(*this);
m_vme->install_device(vme_device::A16_SC, base + 0, base + 1, // Channel B - Data
read8smo_delegate(*subdevice<z80sio_device>("sio0"), FUNC(z80sio_device::db_r)),
write8smo_delegate(*subdevice<z80sio_device>("sio0"), FUNC(z80sio_device::db_w)), 0x00ff);
m_vme->install_device(vme_device::A16_SC, base + 2, base + 3, // Channel B - Control
read8smo_delegate(*subdevice<z80sio_device>("sio0"), FUNC(z80sio_device::cb_r)),
write8smo_delegate(*subdevice<z80sio_device>("sio0"), FUNC(z80sio_device::cb_w)), 0x00ff);
m_vme->install_device(vme_device::A16_SC, base + 4, base + 5, // Channel A - Data
read8smo_delegate(*subdevice<z80sio_device>("sio0"), FUNC(z80sio_device::da_r)),
write8smo_delegate(*subdevice<z80sio_device>("sio0"), FUNC(z80sio_device::da_w)), 0x00ff);
m_vme->install_device(vme_device::A16_SC, base + 6, base + 7, // Channel A - Control
read8smo_delegate(*subdevice<z80sio_device>("sio0"), FUNC(z80sio_device::ca_r)),
write8smo_delegate(*subdevice<z80sio_device>("sio0"), FUNC(z80sio_device::ca_w)), 0x00ff);
m_vme->install_device(vme_device::A16_SC, base + 0x10, base + 0x13, // Am9513
read8sm_delegate(*subdevice<am9513_device>("stc"), FUNC(am9513_device::read8)),
write8sm_delegate(*subdevice<am9513_device>("stc"), FUNC(am9513_device::write8)), 0x00ff);
vme_space(vme::AM_29).install_readwrite_handler(0, 1, // Channel B - Data
read8smo_delegate(m_sio[0], FUNC(z80sio_device::db_r)),
write8smo_delegate(m_sio[0], FUNC(z80sio_device::db_w)), 0x00ff);
vme_space(vme::AM_29).install_readwrite_handler(2, 3, // Channel B - Control
read8smo_delegate(m_sio[0], FUNC(z80sio_device::cb_r)),
write8smo_delegate(m_sio[0], FUNC(z80sio_device::cb_w)), 0x00ff);
vme_space(vme::AM_29).install_readwrite_handler(4, 5, // Channel A - Data
read8smo_delegate(m_sio[0], FUNC(z80sio_device::da_r)),
write8smo_delegate(m_sio[0], FUNC(z80sio_device::da_w)), 0x00ff);
vme_space(vme::AM_29).install_readwrite_handler(6, 7, // Channel A - Control
read8smo_delegate(m_sio[0], FUNC(z80sio_device::ca_r)),
write8smo_delegate(m_sio[0], FUNC(z80sio_device::ca_w)), 0x00ff);
vme_space(vme::AM_29).install_readwrite_handler(0x10, 0x13, // Am9513
read8sm_delegate(m_stc, FUNC(am9513_device::read8)),
write8sm_delegate(m_stc, FUNC(am9513_device::write8)), 0x00ff);
}
void vme_mzr8300_card_device::device_reset()

12
src/devices/bus/vme/vme_mzr8300.h → src/devices/bus/vme/mzr8300.h
View File

@ -1,11 +1,13 @@
// license:BSD-3-Clause
// copyright-holders:Joakim Larsson Edstrom
#ifndef MAME_BUS_VME_VME_MZR8300_H
#define MAME_BUS_VME_VME_MZR8300_H
#ifndef MAME_BUS_VME_MZR8300_H
#define MAME_BUS_VME_MZR8300_H
#pragma once
#include "bus/vme/vme.h"
#include "machine/am9513.h"
#include "machine/z80sio.h"
DECLARE_DEVICE_TYPE(VME_MZR8300, vme_mzr8300_card_device)
@ -25,6 +27,10 @@ protected:
// optional information overrides
virtual void device_add_mconfig(machine_config &config) override;
private:
required_device_array<upd7201_device, 2> m_sio;
required_device<am9513_device> m_stc;
};
#endif // MAME_BUS_VME_VME_MZR8300_H
#endif // MAME_BUS_VME_MZR8300_H

24
src/devices/bus/vme/vme_smvme2000.cpp → src/devices/bus/vme/smvme2000.cpp
View File

@ -16,14 +16,14 @@
*/
#include "emu.h"
#include "vme_smvme2000.h"
#include "smvme2000.h"
#define VERBOSE 0
#include "logmacro.h"
DEFINE_DEVICE_TYPE(VME_SMVME2000, vme_smvme2000_device, "smvme2000", "Signetics SMVME2000")
DEFINE_DEVICE_TYPE(VME_SMVME2000, vme_smvme2000_card_device, "smvme2000", "Signetics SMVME2000")
vme_smvme2000_device::vme_smvme2000_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock)
vme_smvme2000_card_device::vme_smvme2000_card_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock)
: device_t(mconfig, VME_SMVME2000, tag, owner, clock)
, device_vme_card_interface(mconfig, *this)
, m_cpu(*this, "cpu")
@ -49,22 +49,22 @@ ROM_END
static INPUT_PORTS_START(smvme2000)
INPUT_PORTS_END
const tiny_rom_entry *vme_smvme2000_device::device_rom_region() const
const tiny_rom_entry *vme_smvme2000_card_device::device_rom_region() const
{
return ROM_NAME(smvme2000);
}
ioport_constructor vme_smvme2000_device::device_input_ports() const
ioport_constructor vme_smvme2000_card_device::device_input_ports() const
{
return INPUT_PORTS_NAME(smvme2000);
}
void vme_smvme2000_device::device_start()
void vme_smvme2000_card_device::device_start()
{
m_fail.resolve();
}
void vme_smvme2000_device::device_reset()
void vme_smvme2000_card_device::device_reset()
{
/*
* FIXME: EPROM is mapped at the start of memory during reset to allow the
@ -87,11 +87,11 @@ void vme_smvme2000_device::device_reset()
});
}
void vme_smvme2000_device::device_add_mconfig(machine_config &config)
void vme_smvme2000_card_device::device_add_mconfig(machine_config &config)
{
M68000(config, m_cpu, 16_MHz_XTAL / 2);
m_cpu->set_addrmap(AS_PROGRAM, &vme_smvme2000_device::cpu_mem);
m_cpu->set_addrmap(m68000_base_device::AS_CPU_SPACE, &vme_smvme2000_device::cpu_int);
m_cpu->set_addrmap(AS_PROGRAM, &vme_smvme2000_card_device::cpu_mem);
m_cpu->set_addrmap(m68000_base_device::AS_CPU_SPACE, &vme_smvme2000_card_device::cpu_int);
SCN2681(config, m_duart, 3.6864_MHz_XTAL);
m_duart->irq_cb().set(m_pit, FUNC(pit68230_device::h3_w)); // TODO: verify destination
@ -114,7 +114,7 @@ void vme_smvme2000_device::device_add_mconfig(machine_config &config)
m_serial[1]->rxd_handler().set(m_duart, FUNC(scn2681_device::rx_b_w));
}
void vme_smvme2000_device::cpu_mem(address_map &map)
void vme_smvme2000_card_device::cpu_mem(address_map &map)
{
map(0x000000, 0x000fff).ram().share("ram");
@ -126,7 +126,7 @@ void vme_smvme2000_device::cpu_mem(address_map &map)
//map(0xf90000, 0xf9ffff).mirror(0x060000); // VMEbus short I/O space
}
void vme_smvme2000_device::cpu_int(address_map &map)
void vme_smvme2000_card_device::cpu_int(address_map &map)
{
map(0xfffff3, 0xfffff3).lr8(NAME([]() { return m68000_base_device::autovector(1); }));
map(0xfffff5, 0xfffff5).lr8(NAME([]() { return m68000_base_device::autovector(2); }));

6
src/devices/bus/vme/vme_smvme2000.h → src/devices/bus/vme/smvme2000.h
View File

@ -15,12 +15,12 @@
#include "bus/rs232/rs232.h"
class vme_smvme2000_device
class vme_smvme2000_card_device
: public device_t
, public device_vme_card_interface
{
public:
vme_smvme2000_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock);
vme_smvme2000_card_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock);
protected:
// device_t overrides
@ -49,6 +49,6 @@ private:
memory_passthrough_handler m_boot;
};
DECLARE_DEVICE_TYPE(VME_SMVME2000, vme_smvme2000_device)
DECLARE_DEVICE_TYPE(VME_SMVME2000, vme_smvme2000_card_device)
#endif // MAME_BUS_VME_SMVME2000_H

291
src/mame/force/force68k.cpp → src/devices/bus/vme/sys68k_cpu1.cpp
View File

@ -65,22 +65,12 @@
****************************************************************************/
#include "emu.h"
#include "sys68k_cpu1.h"
#include "bus/rs232/rs232.h"
#include "cpu/m68000/m68000.h"
#include "machine/mm58167.h"
#include "machine/68230pit.h"
#include "machine/6850acia.h"
#include "machine/mc14411.h"
#include "machine/clock.h"
#include "bus/centronics/ctronics.h"
#include "bus/generic/slot.h"
#include "bus/generic/carts.h"
#include "softlist.h"
#include "bus/vme/vme.h"
#include "bus/vme/vme_fcisio.h"
#include "bus/vme/vme_fcscsi.h"
#include "fccpu1.lh"
/*
* The baudrate on the Force68k CPU-1 to CPU-6 is generated by a Motorola 14411 bitrate generator
@ -138,118 +128,52 @@
#endif
namespace {
DEFINE_DEVICE_TYPE(VME_SYS68K_CPU1, vme_sys68k_cpu1_card_device, "sys68k_cpu1", "Force Computers SYS68K/CPU-1")
class force68k_state : public driver_device
vme_sys68k_cpu1_card_device::vme_sys68k_cpu1_card_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock)
: device_t(mconfig, VME_SYS68K_CPU1, tag, owner, clock)
, device_vme_card_interface(mconfig, *this)
, m_maincpu(*this, "maincpu")
, m_rtc(*this, "rtc")
, m_pit(*this, "pit")
, m_brg(*this, "brg")
, m_aciahost(*this, "aciahost")
, m_aciaterm(*this, "aciaterm")
, m_aciaremt(*this, "aciaremt")
, m_centronics(*this, "centronics")
, m_centronics_ack(0)
, m_centronics_busy(0)
, m_centronics_perror(0)
, m_centronics_select(0)
, m_serial_brf(*this, "SERIAL_BRF")
, m_serial_p3(*this, "SERIAL_P3")
, m_serial_p4(*this, "SERIAL_P4")
, m_serial_p5(*this, "SERIAL_P5")
, m_cart(*this, "exp_rom1")
, m_eprom(*this, "eprom")
, m_ram(*this, "ram")
{
public:
force68k_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag)
, m_maincpu(*this, "maincpu")
, m_rtc(*this, "rtc")
, m_pit(*this, "pit")
, m_brg(*this, "brg")
, m_aciahost(*this, "aciahost")
, m_aciaterm(*this, "aciaterm")
, m_aciaremt(*this, "aciaremt")
, m_centronics(*this, "centronics")
, m_centronics_ack(0)
, m_centronics_busy(0)
, m_centronics_perror(0)
, m_centronics_select(0)
, m_serial_brf(*this, "SERIAL_BRF")
, m_serial_p3(*this, "SERIAL_P3")
, m_serial_p4(*this, "SERIAL_P4")
, m_serial_p5(*this, "SERIAL_P5")
, m_cart(*this, "exp_rom1")
{
}
}
void fccpu1_eprom_sockets(machine_config &config);
void fccpu1(machine_config &config);
private:
uint16_t bootvect_r(offs_t offset);
uint16_t vme_a24_r();
void vme_a24_w(uint16_t data);
uint16_t vme_a16_r();
void vme_a16_w(uint16_t data);
virtual void machine_start() override;
virtual void machine_reset() override;
// Clocks
void write_acia_clocks(int id, int state);
void write_f1_clock(int state) { write_acia_clocks(mc14411_device::TIMER_F1, state); }
void write_f3_clock(int state) { write_acia_clocks(mc14411_device::TIMER_F3, state); }
void write_f5_clock(int state) { write_acia_clocks(mc14411_device::TIMER_F5, state); }
void write_f7_clock(int state) { write_acia_clocks(mc14411_device::TIMER_F7, state); }
void write_f8_clock(int state) { write_acia_clocks(mc14411_device::TIMER_F8, state); }
void write_f9_clock(int state) { write_acia_clocks(mc14411_device::TIMER_F9, state); }
void write_f11_clock(int state) { write_acia_clocks(mc14411_device::TIMER_F11, state); }
void write_f13_clock(int state) { write_acia_clocks(mc14411_device::TIMER_F13, state); }
void write_f15_clock(int state) { write_acia_clocks(mc14411_device::TIMER_F15, state); }
// Centronics printer interface
void centronics_ack_w(int state);
void centronics_busy_w(int state);
void centronics_perror_w(int state);
void centronics_select_w(int state);
// User EPROM/SRAM slot(s)
std::pair<std::error_condition, std::string> force68k_load_cart(device_image_interface &image, generic_slot_device *slot);
DECLARE_DEVICE_IMAGE_LOAD_MEMBER(exp1_load) { return force68k_load_cart(image, m_cart); }
uint16_t read16_rom(offs_t offset);
void force68k_mem(address_map &map);
required_device<cpu_device> m_maincpu;
required_device<mm58167_device> m_rtc;
required_device<pit68230_device> m_pit;
required_device<mc14411_device> m_brg;
required_device<acia6850_device> m_aciahost;
required_device<acia6850_device> m_aciaterm;
required_device<acia6850_device> m_aciaremt;
optional_device<centronics_device> m_centronics;
int32_t m_centronics_ack;
int32_t m_centronics_busy;
int32_t m_centronics_perror;
int32_t m_centronics_select;
// fake inputs for hardware configuration and things that need rewiring
required_ioport m_serial_brf;
required_ioport m_serial_p3;
required_ioport m_serial_p4;
required_ioport m_serial_p5;
// Pointer to System ROMs needed by bootvect_r
uint16_t *m_sysrom;
uint16_t *m_usrrom;
required_device<generic_slot_device> m_cart;
};
void force68k_state::force68k_mem(address_map &map)
void vme_sys68k_cpu1_card_device::force68k_mem(address_map &map)
{
map.unmap_value_high();
map(0x000000, 0x000007).rom().r(FUNC(force68k_state::bootvect_r)); /* Vectors mapped from System EPROM */
map(0x000008, 0x01ffff).ram(); /* DRAM CPU-1B */
map(0x000000, 0x01ffff).ram().share("ram"); /* DRAM CPU-1B */
// map(0x020000, 0x07ffff).ram(); /* Additional DRAM CPU-1D */
map(0x080000, 0x083fff).rom(); /* System EPROM Area 16Kb DEBUGGER supplied as default on CPU-1B/D */
map(0x084000, 0x09ffff).rom(); /* System EPROM Area 112Kb additional space for System ROM */
// map(0x0a0000, 0x0bffff).rom(); /* User EPROM/SRAM Area, max 128Kb mapped by a cartslot */
map(0x080000, 0x09ffff).rom().region("eprom", 0); /* System EPROM Area 128Kb DEBUGGER supplied as default on CPU-1B/D */
map(0x0a0000, 0x0bffff).rom().region("user", 0); /* User EPROM/SRAM Area, max 128Kb mapped by a cartslot */
map(0x0c0040, 0x0c0043).rw(m_aciahost, FUNC(acia6850_device::read), FUNC(acia6850_device::write)).umask16(0x00ff);
map(0x0c0080, 0x0c0083).rw(m_aciaterm, FUNC(acia6850_device::read), FUNC(acia6850_device::write)).umask16(0xff00);
map(0x0c0100, 0x0c0103).rw(m_aciaremt, FUNC(acia6850_device::read), FUNC(acia6850_device::write)).umask16(0x00ff);
map(0x0c0400, 0x0c042f).rw(m_rtc, FUNC(mm58167_device::read), FUNC(mm58167_device::write)).umask16(0x00ff);
map(0x0e0000, 0x0e0035).rw(m_pit, FUNC(pit68230_device::read), FUNC(pit68230_device::write)).umask16(0x00ff);
// map(0x0e0200, 0x0e0380).rw(FUNC(force68k_state::fpu_r), FUNC(force68k_state::fpu_w)); /* optional FPCP 68881 FPU interface */
map(0x100000, 0xfeffff).rw(FUNC(force68k_state::vme_a24_r), FUNC(force68k_state::vme_a24_w)); /* VMEbus Rev B addresses (24 bits) */
map(0xff0000, 0xffffff).rw(FUNC(force68k_state::vme_a16_r), FUNC(force68k_state::vme_a16_w)); /* VMEbus Rev B addresses (16 bits) */
// map(0x0e0200, 0x0e0380).rw(FUNC(vme_sys68k_cpu1_card_device::fpu_r), FUNC(vme_sys68k_cpu1_card_device::fpu_w)); /* optional FPCP 68881 FPU interface */
map(0x100000, 0xfeffff).rw(FUNC(vme_sys68k_cpu1_card_device::vme_a24_r), FUNC(vme_sys68k_cpu1_card_device::vme_a24_w)); /* VMEbus Rev B addresses (24 bits) */
map(0xff0000, 0xffffff).rw(FUNC(vme_sys68k_cpu1_card_device::vme_a16_r), FUNC(vme_sys68k_cpu1_card_device::vme_a16_w)); /* VMEbus Rev B addresses (16 bits) */
}
/* Input ports */
static INPUT_PORTS_START (force68k)
static INPUT_PORTS_START (sys68k_cpu1)
PORT_START("SERIAL_BRF")
PORT_CONFNAME(0x80 , 0x00 , "Baud Rate Factor") // RSA pin on MC14411
@ -334,7 +258,7 @@ INPUT_PORTS_END
/* Centronics ACK handler
* The centronics ack signal is expected by the ROM to arrive at H1 input line
*/
void force68k_state::centronics_ack_w(int state)
void vme_sys68k_cpu1_card_device::centronics_ack_w(int state)
{
LOG("%s(%d)\n", FUNCNAME, state);
m_centronics_ack = state;
@ -344,7 +268,7 @@ void force68k_state::centronics_ack_w(int state)
/* Centronics BUSY handler
* The centronics busy signal is not used by the ROM driver afaik
*/
void force68k_state::centronics_busy_w(int state)
void vme_sys68k_cpu1_card_device::centronics_busy_w(int state)
{
LOG("%s(%d)\n", FUNCNAME, state);
m_centronics_busy = state;
@ -353,7 +277,7 @@ void force68k_state::centronics_busy_w(int state)
/* Centronics PERROR handler
* The centronics perror signal is not used by the ROM driver afaik
*/
void force68k_state::centronics_perror_w(int state)
void vme_sys68k_cpu1_card_device::centronics_perror_w(int state)
{
LOG("%s(%d)\n", FUNCNAME, state);
m_centronics_perror = state;
@ -362,7 +286,7 @@ void force68k_state::centronics_perror_w(int state)
/* Centronics SELECT handler
* The centronics select signal is expected by the ROM on Port B bit 0
*/
void force68k_state::centronics_select_w(int state)
void vme_sys68k_cpu1_card_device::centronics_select_w(int state)
{
LOG("%s(%d)\n", FUNCNAME, state);
m_centronics_select = state;
@ -370,7 +294,7 @@ void force68k_state::centronics_select_w(int state)
}
/* Start it up */
void force68k_state::machine_start ()
void vme_sys68k_cpu1_card_device::device_start ()
{
LOG("%s\n", FUNCNAME);
@ -379,9 +303,6 @@ void force68k_state::machine_start ()
save_item (NAME (m_centronics_select));
save_item (NAME (m_centronics_perror));
/* Setup pointer to bootvector in ROM for bootvector handler bootvect_r */
m_sysrom = (uint16_t*)(memregion ("maincpu")->base () + 0x080000);
/* Map user ROM/RAM socket(s) */
if (m_cart->exists())
{
@ -389,13 +310,13 @@ void force68k_state::machine_start ()
#if 0 // This should be the correct way but produces odd and even bytes swapped
m_maincpu->space(AS_PROGRAM).install_read_handler(0xa0000, 0xbffff, read16sm_delegate(*m_cart, FUNC(generic_slot_device::read16_rom)));
#else // So we install a custom very inefficient handler for now until we understand how to solve the problem better
m_maincpu->space(AS_PROGRAM).install_read_handler(0xa0000, 0xbffff, read16sm_delegate(*this, FUNC(force68k_state::read16_rom)));
m_maincpu->space(AS_PROGRAM).install_read_handler(0xa0000, 0xbffff, read16sm_delegate(*this, FUNC(vme_sys68k_cpu1_card_device::read16_rom)));
#endif
}
}
/* Reset it */
void force68k_state::machine_reset ()
void vme_sys68k_cpu1_card_device::device_reset ()
{
LOG("%s\n", FUNCNAME);
@ -408,19 +329,26 @@ void force68k_state::machine_reset ()
m_brg->timer_enable((mc14411_device::timer_id) m_serial_p3->read(), true);
m_brg->timer_enable((mc14411_device::timer_id) m_serial_p4->read(), true);
m_brg->timer_enable((mc14411_device::timer_id) m_serial_p5->read(), true);
m_maincpu->space(AS_PROGRAM).install_rom(0, m_eprom->bytes() - 1, m_eprom->base());
m_boot_mph = m_maincpu->space(AS_PROGRAM).install_read_tap(0x000006, 0x000007, "boot",
[this](offs_t offset, uint16_t &data, uint16_t mem_mask)
{
if (!machine().side_effects_disabled() && ACCESSING_BITS_0_7)
{
m_maincpu->space(AS_PROGRAM).install_ram(0, m_ram.bytes() - 1, m_ram.target());
m_boot_mph.remove();
}
});
}
/* A very inefficient User cart emulation of two 8 bit sockets (odd and even) */
uint16_t force68k_state::read16_rom(offs_t offset){
uint16_t vme_sys68k_cpu1_card_device::read16_rom(offs_t offset){
offset = offset % m_cart->common_get_size("rom"); // Don't read outside buffer...
return swapendian_int16(m_usrrom [offset]);
}
/* Boot vector handler, the PCB hardwires the first 8 bytes from 0x80000 to 0x0 */
uint16_t force68k_state::bootvect_r(offs_t offset){
return m_sysrom [offset];
}
/* 10. The VMEbus (text from board documentation)
* ---------------
* The implemented VMEbus Interface includes 24 address, 16 data,
@ -440,24 +368,24 @@ uint16_t force68k_state::bootvect_r(offs_t offset){
*/
/* Dummy VME access methods until the VME bus device is ready for use */
uint16_t force68k_state::vme_a24_r()
uint16_t vme_sys68k_cpu1_card_device::vme_a24_r()
{
LOG("%s\n", FUNCNAME);
return (uint16_t) 0;
}
void force68k_state::vme_a24_w(uint16_t data)
void vme_sys68k_cpu1_card_device::vme_a24_w(uint16_t data)
{
LOG("%s\n", FUNCNAME);
}
uint16_t force68k_state::vme_a16_r()
uint16_t vme_sys68k_cpu1_card_device::vme_a16_r()
{
LOG("%s\n", FUNCNAME);
return (uint16_t) 0;
}
void force68k_state::vme_a16_w(uint16_t data)
void vme_sys68k_cpu1_card_device::vme_a16_w(uint16_t data)
{
LOG("%s\n", FUNCNAME);
}
@ -465,7 +393,7 @@ void force68k_state::vme_a16_w(uint16_t data)
/*
* Serial port clock sources can all be driven by different or the same output(s) of the MC14411
*/
void force68k_state::write_acia_clocks(int id, int state)
void vme_sys68k_cpu1_card_device::write_acia_clocks(int id, int state)
{
if (id == m_serial_p3->read())
{
@ -501,19 +429,19 @@ void force68k_state::write_acia_clocks(int id, int state)
*/
// Implementation of static 2 x 64K EPROM in sockets J10/J11 as 16 bit wide cartridge for easier
// software handling. TODO: make configurable according to table above.
void force68k_state::fccpu1_eprom_sockets(machine_config &config)
void vme_sys68k_cpu1_card_device::fccpu1_eprom_sockets(machine_config &config)
{
generic_cartslot_device &exp_rom1(GENERIC_CARTSLOT(config, "exp_rom1", generic_plain_slot, "fccpu1_cart", "bin,rom"));
exp_rom1.set_width(GENERIC_ROM16_WIDTH);
exp_rom1.set_endian(ENDIANNESS_BIG);
exp_rom1.set_device_load(FUNC(force68k_state::exp1_load));
exp_rom1.set_device_load(FUNC(vme_sys68k_cpu1_card_device::exp1_load));
// SOFTWARE_LIST(config, "cart_list").set_original("fccpu1_cart");
}
/***************************
Rom loading functions
****************************/
std::pair<std::error_condition, std::string> force68k_state::force68k_load_cart(device_image_interface &image, generic_slot_device *slot)
std::pair<std::error_condition, std::string> vme_sys68k_cpu1_card_device::force68k_load_cart(device_image_interface &image, generic_slot_device *slot)
{
uint32_t size = slot->common_get_size("rom");
@ -530,22 +458,14 @@ std::pair<std::error_condition, std::string> force68k_state::force68k_load_cart(
return std::make_pair(std::error_condition(), std::string());
}
static void fccpu1_vme_cards(device_slot_interface &device)
{
device.option_add("fcisio", VME_FCISIO1);
device.option_add("fcscsi", VME_FCSCSI1);
}
/*
* Machine configuration
*/
void force68k_state::fccpu1(machine_config &config)
void vme_sys68k_cpu1_card_device::device_add_mconfig(machine_config &config)
{
/* basic machine hardware */
M68000(config, m_maincpu, XTAL(16'000'000) / 2);
m_maincpu->set_addrmap(AS_PROGRAM, &force68k_state::force68k_mem);
config.set_default_layout(layout_fccpu1);
m_maincpu->set_addrmap(AS_PROGRAM, &vme_sys68k_cpu1_card_device::force68k_mem);
/* P3/Host Port config
* LO command causes ROM monitor to expect S-records on HOST port by default
@ -575,15 +495,15 @@ void force68k_state::fccpu1(machine_config &config)
/* Bit Rate Generator */
MC14411(config, m_brg, XTAL(1'843'200));
m_brg->out_f<1>().set(FUNC(force68k_state::write_f1_clock));
m_brg->out_f<3>().set(FUNC(force68k_state::write_f3_clock));
m_brg->out_f<5>().set(FUNC(force68k_state::write_f5_clock));
m_brg->out_f<7>().set(FUNC(force68k_state::write_f7_clock));
m_brg->out_f<8>().set(FUNC(force68k_state::write_f8_clock));
m_brg->out_f<9>().set(FUNC(force68k_state::write_f9_clock));
m_brg->out_f<11>().set(FUNC(force68k_state::write_f11_clock));
m_brg->out_f<13>().set(FUNC(force68k_state::write_f13_clock));
m_brg->out_f<15>().set(FUNC(force68k_state::write_f15_clock));
m_brg->out_f<1>().set(FUNC(vme_sys68k_cpu1_card_device::write_f1_clock));
m_brg->out_f<3>().set(FUNC(vme_sys68k_cpu1_card_device::write_f3_clock));
m_brg->out_f<5>().set(FUNC(vme_sys68k_cpu1_card_device::write_f5_clock));
m_brg->out_f<7>().set(FUNC(vme_sys68k_cpu1_card_device::write_f7_clock));
m_brg->out_f<8>().set(FUNC(vme_sys68k_cpu1_card_device::write_f8_clock));
m_brg->out_f<9>().set(FUNC(vme_sys68k_cpu1_card_device::write_f9_clock));
m_brg->out_f<11>().set(FUNC(vme_sys68k_cpu1_card_device::write_f11_clock));
m_brg->out_f<13>().set(FUNC(vme_sys68k_cpu1_card_device::write_f13_clock));
m_brg->out_f<15>().set(FUNC(vme_sys68k_cpu1_card_device::write_f15_clock));
/* RTC Real Time Clock device */
MM58167(config, m_rtc, XTAL(32'768));
@ -595,69 +515,65 @@ void force68k_state::fccpu1(machine_config &config)
// Centronics
CENTRONICS(config, m_centronics, centronics_devices, "printer");
m_centronics->ack_handler().set(FUNC(force68k_state::centronics_ack_w));
m_centronics->busy_handler().set(FUNC(force68k_state::centronics_busy_w));
m_centronics->perror_handler().set(FUNC(force68k_state::centronics_perror_w));
m_centronics->select_handler().set(FUNC(force68k_state::centronics_select_w));
m_centronics->ack_handler().set(FUNC(vme_sys68k_cpu1_card_device::centronics_ack_w));
m_centronics->busy_handler().set(FUNC(vme_sys68k_cpu1_card_device::centronics_busy_w));
m_centronics->perror_handler().set(FUNC(vme_sys68k_cpu1_card_device::centronics_perror_w));
m_centronics->select_handler().set(FUNC(vme_sys68k_cpu1_card_device::centronics_select_w));
output_latch_device &latch(OUTPUT_LATCH(config, "cent_data_out"));
m_centronics->set_output_latch(latch);
// EPROM sockets
fccpu1_eprom_sockets(config);
// VME interface
VME(config, "vme", 0);
VME_SLOT(config, "slot1", fccpu1_vme_cards, nullptr, 1, "vme");
}
#if 0 /*
* CPU-6 family is device and adressmap compatible with CPU-1 but with additions
* such as an optional 68881 FPU
*/
void force68k_state::fccpu6(machine_config &config)
void vme_sys68k_cpu1_card_device::fccpu6(machine_config &config)
{
M68000(config, m_maincpu, XTAL(8'000'000)); /* Jumper B10 Mode B */
m_maincpu->set_addrmap(AS_PROGRAM, &force68k_state::force68k_mem);
m_maincpu->set_addrmap(AS_PROGRAM, &vme_sys68k_cpu1_card_device::force68k_mem);
}
void force68k_state::fccpu6a(machine_config &config)
void vme_sys68k_cpu1_card_device::fccpu6a(machine_config &config)
{
M68000(config, m_maincpu, XTAL(12'500'000)); /* Jumper B10 Mode A */
m_maincpu->set_addrmap(AS_PROGRAM, &force68k_state::force68k_mem);
m_maincpu->set_addrmap(AS_PROGRAM, &vme_sys68k_cpu1_card_device::force68k_mem);
}
void force68k_state::fccpu6v(machine_config &config)
void vme_sys68k_cpu1_card_device::fccpu6v(machine_config &config)
{
M68010(config, m_maincpu, XTAL(8'000'000)); /* Jumper B10 Mode B */
m_maincpu->set_addrmap(AS_PROGRAM, &force68k_state::force68k_mem);
m_maincpu->set_addrmap(AS_PROGRAM, &vme_sys68k_cpu1_card_device::force68k_mem);
}
void force68k_state::fccpu6va(machine_config &config)
void vme_sys68k_cpu1_card_device::fccpu6va(machine_config &config)
{
M68010(config, m_maincpu, XTAL(12'500'000)); /* Jumper B10 Mode A */
m_maincpu->set_addrmap(AS_PROGRAM, &force68k_state::force68k_mem);
m_maincpu->set_addrmap(AS_PROGRAM, &vme_sys68k_cpu1_card_device::force68k_mem);
}
void force68k_state::fccpu6vb(machine_config &config)
void vme_sys68k_cpu1_card_device::fccpu6vb(machine_config &config)
{
M68010(config, m_maincpu, XTAL(12'500'000)); /* Jumper B10 Mode A */
m_maincpu->set_addrmap(AS_PROGRAM, &force68k_state::force68k_mem);
m_maincpu->set_addrmap(AS_PROGRAM, &vme_sys68k_cpu1_card_device::force68k_mem);
}
#endif
/* ROM definitions */
ROM_START (fccpu1)
ROM_REGION (0x1000000, "maincpu", 0)
ROM_START (sys68k_cpu1)
ROM_REGION16_BE(0x20000, "eprom", 0)
ROM_DEFAULT_BIOS("forcebug-1.1")
ROM_SYSTEM_BIOS(0, "forcemon-1.0l", "Force Computers SYS68K/CPU-1 Force Monitor 1.0L")
ROMX_LOAD ("fccpu1v1.0l.j8.bin", 0x080001, 0x2000, CRC (3ac6f08f) SHA1 (502f6547b508d8732bd68bbbb2402d8c30fefc3b), ROM_SKIP(1) | ROM_BIOS(0))
ROMX_LOAD ("fccpu1v1.0l.j9.bin", 0x080000, 0x2000, CRC (035315fb) SHA1 (90dc44d9c25d28428233e6846da6edce2d69e440), ROM_SKIP(1) | ROM_BIOS(0))
ROMX_LOAD ("fccpu1v1.0l.j8.bin", 0x0001, 0x2000, CRC (3ac6f08f) SHA1 (502f6547b508d8732bd68bbbb2402d8c30fefc3b), ROM_SKIP(1) | ROM_BIOS(0))
ROMX_LOAD ("fccpu1v1.0l.j9.bin", 0x0000, 0x2000, CRC (035315fb) SHA1 (90dc44d9c25d28428233e6846da6edce2d69e440), ROM_SKIP(1) | ROM_BIOS(0))
ROM_SYSTEM_BIOS(1, "forcebug-1.1", "Force Computers SYS68K/CPU-1 Force Debugger 1.1")
ROMX_LOAD ("fccpu1v1.1.j8.bin", 0x080001, 0x4000, CRC (116dcbf0) SHA1 (6870b71606933f84afe27ad031c651d201b93f99), ROM_SKIP(1) | ROM_BIOS(1))
ROMX_LOAD ("fccpu1v1.1.j9.bin", 0x080000, 0x4000, CRC (aefd5b0b) SHA1 (1e24530a6d5dc4fb77fde67acae08d371e59fc0f), ROM_SKIP(1) | ROM_BIOS(1))
ROMX_LOAD ("fccpu1v1.1.j8.bin", 0x0001, 0x4000, CRC (116dcbf0) SHA1 (6870b71606933f84afe27ad031c651d201b93f99), ROM_SKIP(1) | ROM_BIOS(1))
ROMX_LOAD ("fccpu1v1.1.j9.bin", 0x0000, 0x4000, CRC (aefd5b0b) SHA1 (1e24530a6d5dc4fb77fde67acae08d371e59fc0f), ROM_SKIP(1) | ROM_BIOS(1))
/*
* System ROM terminal commands
@ -734,14 +650,21 @@ ROM_START (fccpu6vb)
ROM_END
#endif
} // anonymous namespace
const tiny_rom_entry *vme_sys68k_cpu1_card_device::device_rom_region() const
{
return ROM_NAME(sys68k_cpu1);
}
ioport_constructor vme_sys68k_cpu1_card_device::device_input_ports() const
{
return INPUT_PORTS_NAME(sys68k_cpu1);
}
/* Driver */
/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS */
COMP( 1983, fccpu1, 0, 0, fccpu1, force68k, force68k_state, empty_init, "Force Computers GmbH", "SYS68K/CPU-1", MACHINE_NO_SOUND_HW )
//COMP( 1989, fccpu6, 0, 0, fccpu6, force68k, force68k_state, empty_init, "Force Computers GmbH", "SYS68K/CPU-6", MACHINE_IS_SKELETON )
//COMP( 1989, fccpu6a, 0, 0, fccpu6a, force68k, force68k_state, empty_init, "Force Computers GmbH", "SYS68K/CPU-6a", MACHINE_IS_SKELETON )
//COMP( 1989, fccpu6v, 0, 0, fccpu6v, force68k, force68k_state, empty_init, "Force Computers GmbH", "SYS68K/CPU-6v", MACHINE_IS_SKELETON )
//COMP( 1989, fccpu6va, 0, 0, fccpu6va, force68k, force68k_state, empty_init, "Force Computers GmbH", "SYS68K/CPU-6va", MACHINE_IS_SKELETON )
//COMP( 1989, fccpu6vb, 0, 0, fccpu6vb, force68k, force68k_state, empty_init, "Force Computers GmbH", "SYS68K/CPU-6vb", MACHINE_IS_SKELETON )
//COMP( 1983, fccpu1, 0, 0, fccpu1, force68k, vme_sys68k_cpu1_card_device, empty_init, "Force Computers GmbH", "SYS68K/CPU-1", MACHINE_NO_SOUND_HW )
//COMP( 1989, fccpu6, 0, 0, fccpu6, force68k, vme_sys68k_cpu1_card_device, empty_init, "Force Computers GmbH", "SYS68K/CPU-6", MACHINE_IS_SKELETON )
//COMP( 1989, fccpu6a, 0, 0, fccpu6a, force68k, vme_sys68k_cpu1_card_device, empty_init, "Force Computers GmbH", "SYS68K/CPU-6a", MACHINE_IS_SKELETON )
//COMP( 1989, fccpu6v, 0, 0, fccpu6v, force68k, vme_sys68k_cpu1_card_device, empty_init, "Force Computers GmbH", "SYS68K/CPU-6v", MACHINE_IS_SKELETON )
//COMP( 1989, fccpu6va, 0, 0, fccpu6va, force68k, vme_sys68k_cpu1_card_device, empty_init, "Force Computers GmbH", "SYS68K/CPU-6va", MACHINE_IS_SKELETON )
//COMP( 1989, fccpu6vb, 0, 0, fccpu6vb, force68k, vme_sys68k_cpu1_card_device, empty_init, "Force Computers GmbH", "SYS68K/CPU-6vb", MACHINE_IS_SKELETON )

97
src/devices/bus/vme/sys68k_cpu1.h Normal file
View File

@ -0,0 +1,97 @@
// license:BSD-3-Clause
// copyright-holders:Joakim Larsson Edstrom
#ifndef MAME_BUS_VME_SYS68K_CPU1_H
#define MAME_BUS_VME_SYS68K_CPU1_H
#pragma once
#include "bus/vme/vme.h"
#include "machine/mm58167.h"
#include "machine/68230pit.h"
#include "machine/mc14411.h"
#include "machine/6850acia.h"
#include "bus/centronics/ctronics.h"
#include "bus/generic/carts.h"
#include "bus/generic/slot.h"
class vme_sys68k_cpu1_card_device
: public device_t
, public device_vme_card_interface
{
public:
vme_sys68k_cpu1_card_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock);
protected:
virtual const tiny_rom_entry *device_rom_region() const override;
virtual void device_add_mconfig(machine_config &config) override;
virtual ioport_constructor device_input_ports() const override;
virtual void device_start() override;
virtual void device_reset() override;
private:
void fccpu1_eprom_sockets(machine_config &config);
uint16_t vme_a24_r();
void vme_a24_w(uint16_t data);
uint16_t vme_a16_r();
void vme_a16_w(uint16_t data);
// Clocks
void write_acia_clocks(int id, int state);
void write_f1_clock(int state) { write_acia_clocks(mc14411_device::TIMER_F1, state); }
void write_f3_clock(int state) { write_acia_clocks(mc14411_device::TIMER_F3, state); }
void write_f5_clock(int state) { write_acia_clocks(mc14411_device::TIMER_F5, state); }
void write_f7_clock(int state) { write_acia_clocks(mc14411_device::TIMER_F7, state); }
void write_f8_clock(int state) { write_acia_clocks(mc14411_device::TIMER_F8, state); }
void write_f9_clock(int state) { write_acia_clocks(mc14411_device::TIMER_F9, state); }
void write_f11_clock(int state) { write_acia_clocks(mc14411_device::TIMER_F11, state); }
void write_f13_clock(int state) { write_acia_clocks(mc14411_device::TIMER_F13, state); }
void write_f15_clock(int state) { write_acia_clocks(mc14411_device::TIMER_F15, state); }
// Centronics printer interface
void centronics_ack_w(int state);
void centronics_busy_w(int state);
void centronics_perror_w(int state);
void centronics_select_w(int state);
// User EPROM/SRAM slot(s)
std::pair<std::error_condition, std::string> force68k_load_cart(device_image_interface &image, generic_slot_device *slot);
DECLARE_DEVICE_IMAGE_LOAD_MEMBER(exp1_load) { return force68k_load_cart(image, m_cart); }
uint16_t read16_rom(offs_t offset);
void force68k_mem(address_map &map);
required_device<cpu_device> m_maincpu;
required_device<mm58167_device> m_rtc;
required_device<pit68230_device> m_pit;
required_device<mc14411_device> m_brg;
required_device<acia6850_device> m_aciahost;
required_device<acia6850_device> m_aciaterm;
required_device<acia6850_device> m_aciaremt;
optional_device<centronics_device> m_centronics;
int32_t m_centronics_ack;
int32_t m_centronics_busy;
int32_t m_centronics_perror;
int32_t m_centronics_select;
// fake inputs for hardware configuration and things that need rewiring
required_ioport m_serial_brf;
required_ioport m_serial_p3;
required_ioport m_serial_p4;
required_ioport m_serial_p5;
uint16_t *m_usrrom;
required_device<generic_slot_device> m_cart;
required_memory_region m_eprom;
required_shared_ptr<uint16_t> m_ram;
memory_passthrough_handler m_boot_mph;
};
DECLARE_DEVICE_TYPE(VME_SYS68K_CPU1, vme_sys68k_cpu1_card_device)
#endif // MAME_BUS_VME_SYS68K_CPU1_H

211
src/devices/bus/vme/vme_fccpu20.cpp → src/devices/bus/vme/sys68k_cpu20.cpp
View File

@ -183,7 +183,7 @@
* - VME bus arbiter as MAME always gets the bus
****************************************************************************/
#include "emu.h"
#include "vme_fccpu20.h"
#include "sys68k_cpu20.h"
#include "cpu/m68000/m68020.h"
#include "bus/rs232/rs232.h"
@ -206,27 +206,25 @@
// GLOBAL VARIABLES
//**************************************************************************
DEFINE_DEVICE_TYPE(VME_FCCPU20, vme_fccpu20_card_device, "fccpu20", "Force Computer SYS68K/CPU-20 CPU Board")
DEFINE_DEVICE_TYPE(VME_FCCPU21S, vme_fccpu21s_card_device, "fccpu21s", "Force Computer SYS68K/CPU-21S CPU Board")
DEFINE_DEVICE_TYPE(VME_FCCPU21, vme_fccpu21_card_device, "fccpu21", "Force Computer SYS68K/CPU-21 CPU Board")
DEFINE_DEVICE_TYPE(VME_FCCPU21A, vme_fccpu21a_card_device, "fccpu21a", "Force Computer SYS68K/CPU-21A CPU Board")
DEFINE_DEVICE_TYPE(VME_FCCPU21YA, vme_fccpu21ya_card_device, "fccpu21ya", "Force Computer SYS68K/CPU-21YA CPU Board")
DEFINE_DEVICE_TYPE(VME_FCCPU21B, vme_fccpu21b_card_device, "fccpu21b", "Force Computer SYS68K/CPU-21B CPU Board")
DEFINE_DEVICE_TYPE(VME_FCCPU21YB, vme_fccpu21yb_card_device, "fccpu21yb", "Force Computer SYS68K/CPU-21YB CPU Board")
DEFINE_DEVICE_TYPE(VME_SYS68K_CPU20, vme_sys68k_cpu20_card_device, "sys68k_cpu20", "Force Computers SYS68K/CPU-20")
DEFINE_DEVICE_TYPE(VME_SYS68K_CPU21S, vme_sys68k_cpu21s_card_device, "sys68k_cpu21s", "Force Computers SYS68K/CPU-21S")
DEFINE_DEVICE_TYPE(VME_SYS68K_CPU21, vme_sys68k_cpu21_card_device, "sys68k_cpu21", "Force Computers SYS68K/CPU-21")
DEFINE_DEVICE_TYPE(VME_SYS68K_CPU21A, vme_sys68k_cpu21a_card_device, "sys68k_cpu21a", "Force Computers SYS68K/CPU-21A")
DEFINE_DEVICE_TYPE(VME_SYS68K_CPU21YA, vme_sys68k_cpu21ya_card_device, "sys68k_cpu21ya", "Force Computers SYS68K/CPU-21YA")
DEFINE_DEVICE_TYPE(VME_SYS68K_CPU21B, vme_sys68k_cpu21b_card_device, "sys68k_cpu21b", "Force Computers SYS68K/CPU-21B")
DEFINE_DEVICE_TYPE(VME_SYS68K_CPU21YB, vme_sys68k_cpu21yb_card_device, "sys68k_cpu21yb", "Force Computers SYS68K/CPU-21YB")
#define CLOCK50 XTAL(50'000'000) /* HCJ */
#define CLOCK40 XTAL(40'000'000) /* HCJ */
#define CLOCK32 XTAL(32'000'000) /* HCJ */
void vme_fccpu20_device::cpu20_mem(address_map &map)
void vme_sys68k_cpu20_card_device_base::cpu20_mem(address_map &map)
{
map.unmap_value_high();
map(0x00000000, 0x00000007).ram().w(FUNC(vme_fccpu20_device::bootvect_w)); /* After first write we act as RAM */
map(0x00000000, 0x00000007).rom().r(FUNC(vme_fccpu20_device::bootvect_r)); /* ROM mirror just during reset */
map(0x00000008, 0x0007ffff).ram(); /* Local SRAM */
map(0x00000000, 0x0007ffff).ram().share("ram"); /* Local SRAM */
map(0x00080000, 0x000fffff).ram(); /* SRAM-22 installed */
map(0xff040000, 0xff04ffff).ram();
map(0xff000000, 0xff00ffff).rom().region("roms", 0x0000);
map(0xff000000, 0xff00ffff).rom().region("eprom", 0);
map(0xff800000, 0xff80001f).rw("mpcc", FUNC(mpcc68561_device::read), FUNC(mpcc68561_device::write));
map(0xff800200, 0xff80021f).rw("mpcc2", FUNC(mpcc68561_device::read), FUNC(mpcc68561_device::write));
map(0xff800600, 0xff80061f).rw("mpcc3", FUNC(mpcc68561_device::read), FUNC(mpcc68561_device::write));
@ -243,28 +241,28 @@ static DEVICE_INPUT_DEFAULTS_START( terminal )
DEVICE_INPUT_DEFAULTS( "RS232_STOPBITS", 0xff, RS232_STOPBITS_2 )
DEVICE_INPUT_DEFAULTS_END
void vme_fccpu20_device::cpu_space_map(address_map &map)
void vme_sys68k_cpu20_card_device_base::cpu_space_map(address_map &map)
{
map(0xfffffff2, 0xffffffff).lr16(NAME([this](offs_t offset) -> u16 { return m_bim->iack(offset+1); }));
}
void vme_fccpu20_device::device_add_mconfig(machine_config &config)
void vme_sys68k_cpu20_card_device_base::device_add_mconfig(machine_config &config)
{
/* basic machine hardware */
M68020(config, m_maincpu, CLOCK50 / 3); /* Crytstal verified from picture HCI */
m_maincpu->set_addrmap(AS_PROGRAM, &vme_fccpu20_device::cpu20_mem);
m_maincpu->set_addrmap(m68000_base_device::AS_CPU_SPACE, &vme_fccpu20_device::cpu_space_map);
m_maincpu->set_addrmap(AS_PROGRAM, &vme_sys68k_cpu20_card_device_base::cpu20_mem);
m_maincpu->set_addrmap(m68000_base_device::AS_CPU_SPACE, &vme_sys68k_cpu20_card_device_base::cpu_space_map);
/* PIT Parallel Interface and Timer device, assumed strapped for on board clock */
PIT68230(config, m_pit, CLOCK32 / 4); /* Crystal not verified */
m_pit->pa_in_callback().set(FUNC(vme_fccpu20_device::pita_r));
m_pit->pb_in_callback().set(FUNC(vme_fccpu20_device::pitb_r));
m_pit->pc_in_callback().set(FUNC(vme_fccpu20_device::pitc_r));
m_pit->pa_in_callback().set(FUNC(vme_sys68k_cpu20_card_device_base::pita_r));
m_pit->pb_in_callback().set(FUNC(vme_sys68k_cpu20_card_device_base::pitb_r));
m_pit->pc_in_callback().set(FUNC(vme_sys68k_cpu20_card_device_base::pitc_r));
m_pit->timer_irq_callback().set("bim", FUNC(bim68153_device::int2_w));
/* BIM */
bim68153_device &bim(MC68153(config, "bim", CLOCK32 / 8));
bim.out_int_callback().set(FUNC(vme_fccpu20_device::bim_irq_callback));
bim.out_int_callback().set(FUNC(vme_sys68k_cpu20_card_device_base::bim_irq_callback));
/*INT0 - Abort switch */
/*INT1 - MPCC@8.064 MHz aswell */
/*INT2 - PI/T timer */
@ -311,55 +309,55 @@ void vme_fccpu20_device::device_add_mconfig(machine_config &config)
rs232p3.cts_handler().set(m_mpcc3, FUNC(mpcc68561_device::cts_w));
}
void vme_fccpu20_card_device::device_add_mconfig(machine_config &config)
void vme_sys68k_cpu20_card_device::device_add_mconfig(machine_config &config)
{
vme_fccpu20_device::device_add_mconfig(config);
vme_sys68k_cpu20_card_device_base::device_add_mconfig(config);
}
// SYS68K/CPU-21S Part No.1 01 041 - 68020 CPU board + FPU 68881 at 12.5 MHz, 512 KB RAM
void vme_fccpu21s_card_device::device_add_mconfig(machine_config &config)
void vme_sys68k_cpu21s_card_device::device_add_mconfig(machine_config &config)
{
vme_fccpu20_device::device_add_mconfig(config);
vme_sys68k_cpu20_card_device_base::device_add_mconfig(config);
m_maincpu->set_clock(CLOCK50 / 4);
}
// SYS68K/CPU-21 Part No.1 01 001 - 68020 CPU board (CPU-20) + FPU 68881 at 16.7 MHz, 512 KB RAM
void vme_fccpu21_card_device::device_add_mconfig(machine_config &config)
void vme_sys68k_cpu21_card_device::device_add_mconfig(machine_config &config)
{
vme_fccpu20_device::device_add_mconfig(config);
vme_sys68k_cpu20_card_device_base::device_add_mconfig(config);
m_maincpu->set_clock(CLOCK50 / 3);
}
// SYS68K/CPU-21A Part No.1 01 011 - 68020 CPU board + FPU 68881 at 20 MHz, 512 KB RAM
void vme_fccpu21a_card_device::device_add_mconfig(machine_config &config)
void vme_sys68k_cpu21a_card_device::device_add_mconfig(machine_config &config)
{
vme_fccpu20_device::device_add_mconfig(config);
vme_sys68k_cpu20_card_device_base::device_add_mconfig(config);
m_maincpu->set_clock(CLOCK40 / 2);
}
// SYS68K/CPU-21YA Part No.1 01 061 - 68020 CPU board + FPU 68881 at 20 MHz, 2048 KB RAM
void vme_fccpu21ya_card_device::device_add_mconfig(machine_config &config)
void vme_sys68k_cpu21ya_card_device::device_add_mconfig(machine_config &config)
{
vme_fccpu20_device::device_add_mconfig(config);
vme_sys68k_cpu20_card_device_base::device_add_mconfig(config);
m_maincpu->set_clock(CLOCK40 / 2);
}
// SYS68K/CPU-21B Part No.1 01 021 - 68020 CPU board + FPU 68881 at 25 MHz, 512 KB RAM
void vme_fccpu21b_card_device::device_add_mconfig(machine_config &config)
void vme_sys68k_cpu21b_card_device::device_add_mconfig(machine_config &config)
{
vme_fccpu20_device::device_add_mconfig(config);
vme_sys68k_cpu20_card_device_base::device_add_mconfig(config);
m_maincpu->set_clock(CLOCK50 / 2);
}
// SYS68K/CPU-21YB Part No.1 01 071 - 68020 CPU board + FPU 68881 at 25 MHz, 2048 KB RAM
void vme_fccpu21yb_card_device::device_add_mconfig(machine_config &config)
void vme_sys68k_cpu21yb_card_device::device_add_mconfig(machine_config &config)
{
vme_fccpu20_device::device_add_mconfig(config);
vme_sys68k_cpu20_card_device_base::device_add_mconfig(config);
m_maincpu->set_clock(CLOCK50 / 2);
}
@ -368,7 +366,7 @@ void vme_fccpu21yb_card_device::device_add_mconfig(machine_config &config)
//**************************************************************************
// Base Device
//**************************************************************************
vme_fccpu20_device::vme_fccpu20_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, fc_board_t board_id) :
vme_sys68k_cpu20_card_device_base::vme_sys68k_cpu20_card_device_base(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, fc_board_t board_id) :
device_t(mconfig, type, tag, owner, clock)
, device_vme_card_interface(mconfig, *this)
, m_maincpu (*this, "maincpu")
@ -377,73 +375,70 @@ vme_fccpu20_device::vme_fccpu20_device(const machine_config &mconfig, device_typ
, m_mpcc (*this, "mpcc")
, m_mpcc2 (*this, "mpcc2")
, m_mpcc3 (*this, "mpcc3")
, m_eprom (*this, "eprom")
, m_ram (*this, "ram")
, m_board_id(board_id)
{
LOG("vme_fccpu20_device ctor\n");
LOG("vme_sys68k_cpu20_card_device_base ctor\n");
}
//**************************************************************************
// Card Devices
//**************************************************************************
vme_fccpu20_card_device::vme_fccpu20_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: vme_fccpu20_card_device(mconfig, VME_FCCPU20, tag, owner, clock)
vme_sys68k_cpu20_card_device::vme_sys68k_cpu20_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: vme_sys68k_cpu20_card_device(mconfig, VME_SYS68K_CPU20, tag, owner, clock)
{
LOG("vme_fccpu20_card_device ctor: %s\n", tag);
LOG("vme_sys68k_cpu20_card_device ctor: %s\n", tag);
}
vme_fccpu21s_card_device::vme_fccpu21s_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: vme_fccpu21s_card_device(mconfig, VME_FCCPU21S, tag, owner, clock)
vme_sys68k_cpu21s_card_device::vme_sys68k_cpu21s_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: vme_sys68k_cpu21s_card_device(mconfig, VME_SYS68K_CPU21S, tag, owner, clock)
{
LOG("vme_fccpu21s_card_device ctor: %s\n", tag);
LOG("vme_sys68k_cpu21s_card_device ctor: %s\n", tag);
}
vme_fccpu21_card_device::vme_fccpu21_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: vme_fccpu21_card_device(mconfig, VME_FCCPU21, tag, owner, clock)
vme_sys68k_cpu21_card_device::vme_sys68k_cpu21_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: vme_sys68k_cpu21_card_device(mconfig, VME_SYS68K_CPU21, tag, owner, clock)
{
LOG("vme_fccpu21_card_device ctor: %s\n", tag);
LOG("vme_sys68k_cpu21_card_device ctor: %s\n", tag);
}
vme_fccpu21a_card_device::vme_fccpu21a_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: vme_fccpu21a_card_device(mconfig, VME_FCCPU21A, tag, owner, clock)
vme_sys68k_cpu21a_card_device::vme_sys68k_cpu21a_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: vme_sys68k_cpu21a_card_device(mconfig, VME_SYS68K_CPU21A, tag, owner, clock)
{
LOG("vme_fccpu21a_card_device ctor: %s\n", tag);
LOG("vme_sys68k_cpu21a_card_device ctor: %s\n", tag);
}
// TODO: Change to 2MB on board RAM and move FLME memory and find/verify memory map
vme_fccpu21ya_card_device::vme_fccpu21ya_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: vme_fccpu21ya_card_device(mconfig, VME_FCCPU21YA, tag, owner, clock)
vme_sys68k_cpu21ya_card_device::vme_sys68k_cpu21ya_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: vme_sys68k_cpu21ya_card_device(mconfig, VME_SYS68K_CPU21YA, tag, owner, clock)
{
LOG("vme_fccpu21ya_card_device ctor: %s\n", tag);
LOG("vme_sys68k_cpu21ya_card_device ctor: %s\n", tag);
}
vme_fccpu21b_card_device::vme_fccpu21b_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: vme_fccpu21b_card_device(mconfig, VME_FCCPU21B, tag, owner, clock)
vme_sys68k_cpu21b_card_device::vme_sys68k_cpu21b_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: vme_sys68k_cpu21b_card_device(mconfig, VME_SYS68K_CPU21B, tag, owner, clock)
{
LOG("vme_fccpu21b_card_device ctor: %s\n", tag);
LOG("vme_sys68k_cpu21b_card_device ctor: %s\n", tag);
}
// TODO: Change to 2MB on board RAM and move FLME memory and find/verify memory map
vme_fccpu21yb_card_device::vme_fccpu21yb_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: vme_fccpu21yb_card_device(mconfig, VME_FCCPU21YB, tag, owner, clock)
vme_sys68k_cpu21yb_card_device::vme_sys68k_cpu21yb_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: vme_sys68k_cpu21yb_card_device(mconfig, VME_SYS68K_CPU21YB, tag, owner, clock)
{
LOG("vme_fccpu21yb_card_device ctor: %s\n", tag);
LOG("vme_sys68k_cpu21yb_card_device ctor: %s\n", tag);
}
void vme_fccpu20_device::device_start()
void vme_sys68k_cpu20_card_device_base::device_start()
{
LOG("vme_fccpu20_device::device_start\n");
LOG("vme_sys68k_cpu20_card_device::device_start\n");
save_pointer(NAME(m_sysrom), sizeof(m_sysrom));
save_pointer(NAME(m_sysram), sizeof(m_sysram));
// save_item(NAME(m_board_id)); // TODO: Save this "non base type" item
/* TODO: setup this RAM from (not yet) optional SRAM-2x board and also support 2MB versions */
//m_maincpu->space(AS_PROGRAM).install_ram(0x80000, m_ram->size() + 0x7ffff, m_ram->pointer());
/* Setup pointer to bootvector in ROM for bootvector handler bootvect_r */
m_sysrom = (uint32_t*)(memregion("roms")->base());
#if 0 // TODO: Setup VME access handlers for shared memory area
uint32_t base = 0xFFFF5000;
m_vme->install_device(base + 0, base + 1, // Channel B - Data
@ -451,44 +446,41 @@ void vme_fccpu20_device::device_start()
m_vme->install_device(base + 2, base + 3, // Channel B - Control
read8_delegate(*subdevice<z80sio_device>("pit"), FUNC(z80sio_device::cb_r)), write8_delegate(*subdevice<z80sio_device>("pit"), FUNC(z80sio_device::cb_w)), 0x00ff);
#endif
m_arbiter_start = timer_alloc(FUNC(vme_fccpu20_device::grant_bus), this);
m_arbiter_start = timer_alloc(FUNC(vme_sys68k_cpu20_card_device_base::grant_bus), this);
}
void vme_fccpu20_device::device_reset()
void vme_sys68k_cpu20_card_device_base::device_reset()
{
LOG("vme_fccpu20_device::device_reset\n");
LOG("vme_sys68k_cpu20_card_device::device_reset\n");
/* We need to delay the static bus grant signal until we have it from the VME interface or MAME supports bus arbitration */
m_arbiter_start->adjust(attotime::from_msec(10));
m_maincpu->space(AS_PROGRAM).install_rom(0, m_eprom->bytes() - 1, m_eprom->base());
m_boot_mph = m_maincpu->space(AS_PROGRAM).install_read_tap(0x000004, 0x000007, "boot",
[this](offs_t offset, u32 &data, u32 mem_mask)
{
if (!machine().side_effects_disabled() && ACCESSING_BITS_0_15)
{
m_maincpu->space(AS_PROGRAM).install_ram(0, m_ram.bytes() - 1, m_ram.target());
m_boot_mph.remove();
}
});
}
//-------------------------------------------------
// grant_bus
//-------------------------------------------------
TIMER_CALLBACK_MEMBER(vme_fccpu20_device::grant_bus)
TIMER_CALLBACK_MEMBER(vme_sys68k_cpu20_card_device_base::grant_bus)
{
m_pit->h1_w(ASSERT_LINE); // Grant bus always
}
/* Boot vector handler, the PCB hardwires the first 8 bytes from 0xff800000 to 0x0 at reset*/
uint32_t vme_fccpu20_device::bootvect_r(offs_t offset)
void vme_sys68k_cpu20_card_device_base::bim_irq_callback(int state)
{
LOG("vme_fccpu20_device::bootvect_r\n");
return m_sysrom[offset];
}
void vme_fccpu20_device::bootvect_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
LOG("vme_fccpu20_device::bootvect_w\n");
m_sysram[offset % std::size(m_sysram)] &= ~mem_mask;
m_sysram[offset % std::size(m_sysram)] |= (data & mem_mask);
m_sysrom = &m_sysram[0]; // redirect all upcoming accesses to masking RAM until reset.
}
void vme_fccpu20_device::bim_irq_callback(int state)
{
LOGINT("vme_fccpu20_device::bim_irq_callback(%02x)\n", state);
LOGINT("vme_sys68k_cpu20_card_device_base::bim_irq_callback(%02x)\n", state);
m_bim_irq_state = state;
m_bim_irq_level = m_bim->get_irq_level();
@ -496,9 +488,9 @@ void vme_fccpu20_device::bim_irq_callback(int state)
update_irq_to_maincpu();
}
void vme_fccpu20_device::update_irq_to_maincpu()
void vme_sys68k_cpu20_card_device_base::update_irq_to_maincpu()
{
LOGINT("vme_fccpu20_device::update_irq_to_maincpu()\n");
LOGINT("vme_sys68k_cpu20_card_device_base::update_irq_to_maincpu()\n");
LOGINT(" - m_bim_irq_level: %02x\n", m_bim_irq_level);
LOGINT(" - m_bim_irq_state: %02x\n", m_bim_irq_state);
switch (m_bim_irq_level & 0x07)
@ -510,7 +502,7 @@ void vme_fccpu20_device::update_irq_to_maincpu()
case 5: m_maincpu->set_input_line(M68K_IRQ_5, m_bim_irq_state); break;
case 6: m_maincpu->set_input_line(M68K_IRQ_6, m_bim_irq_state); break;
case 7: m_maincpu->set_input_line(M68K_IRQ_7, m_bim_irq_state); break;
default: logerror("Unsupported BIM IRQ line value 0 in vme_fccpu20_device::update_irq_to_maincpu, please report\n");
default: logerror("Unsupported BIM IRQ line value 0 in vme_sys68k_cpu20_card_device_base::update_irq_to_maincpu, please report\n");
}
}
@ -534,26 +526,26 @@ void vme_fccpu20_device::update_irq_to_maincpu()
#define BR8N38400 0x08
#define FORCEBUG 0x30
uint8_t vme_fccpu20_device::pita_r()
uint8_t vme_sys68k_cpu20_card_device_base::pita_r()
{
LOG("vme_fccpu20_device::pita_r\n");
LOG("vme_sys68k_cpu20_card_device::pita_r\n");
return FORCEBUG | BR7N9600;
}
/* Enabling/Disabling of VME IRQ 1-7 */
uint8_t vme_fccpu20_device::pitb_r()
uint8_t vme_sys68k_cpu20_card_device_base::pitb_r()
{
LOG("vme_fccpu20_device::pitb_r\n");
LOG("vme_sys68k_cpu20_card_device::pitb_r\n");
return 0xff;
}
/* VME board ID bit and bus release software settings (output) (ROR, RAT, RATAR, RATBCLR, RORAT, RORRAT */
/* Bit 4 is bus available */
uint8_t vme_fccpu20_device::pitc_r()
uint8_t vme_sys68k_cpu20_card_device_base::pitc_r()
{
uint8_t board_id = 0;
LOG("vme_fccpu20_device::pitc_r Board id:%02x\n", m_board_id);
LOG("vme_sys68k_cpu20_card_device_base::pitc_r Board id:%02x\n", m_board_id);
switch (m_board_id)
{
@ -577,38 +569,17 @@ uint8_t vme_fccpu20_device::pitc_r()
}
/* ROM definitions */
ROM_START (fccpu20) /* This is an original rom dump */
ROM_REGION32_BE(0x10000, "roms", 0)
ROM_START (sys68k_cpu20) /* This is an original rom dump */
ROM_REGION32_BE(0x10000, "eprom", 0)
ROM_LOAD32_BYTE("l.bin", 0x000002, 0x4000, CRC (174ab801) SHA1 (0d7b8ed29d5fdd4bd2073005008120c5f20128dd))
ROM_LOAD32_BYTE("ll.bin", 0x000003, 0x4000, CRC (9fd9e3e4) SHA1 (e5a7c87021e6be412dd5a8166d9f62b681169eda))
ROM_LOAD32_BYTE("u.bin", 0x000001, 0x4000, CRC (d1afe4c0) SHA1 (b5baf9798d73632f7bb843cbc4b306c8c03f4296))
ROM_LOAD32_BYTE("uu.bin", 0x000000, 0x4000, CRC (b54d623b) SHA1 (49b272184a04570b09004de71fae0ed0d1bf5929))
ROM_END
/* These cpu-21 boards are supported by the latest cpu-20 rom */
#define rom_fccpu21s rom_fccpu20
#define rom_fccpu21 rom_fccpu20
#define rom_fccpu21a rom_fccpu20
#define rom_fccpu21ya rom_fccpu20
#define rom_fccpu21b rom_fccpu20
#define rom_fccpu21yb rom_fccpu20
const tiny_rom_entry *vme_fccpu20_device::device_rom_region() const
const tiny_rom_entry *vme_sys68k_cpu20_card_device_base::device_rom_region() const
{
LOG("vme_fccpu20_device::device_rom_region\n");
switch (m_board_id)
{
case cpu20: return ROM_NAME( fccpu20 ); break;
case cpu21a: return ROM_NAME( fccpu21a ); break;
case cpu21ya: return ROM_NAME( fccpu21ya ); break;
case cpu21b: return ROM_NAME( fccpu21b ); break;
case cpu21yb: return ROM_NAME( fccpu21yb ); break;
case cpu21s: return ROM_NAME( fccpu21s ); break;
case cpu21: return ROM_NAME( fccpu21 ); break;
default: logerror("Attempted to get rom set for unknown board type %02x, defaulting to CPU20\n", m_board_id);
return ROM_NAME( fccpu20 );
}
return ROM_NAME(sys68k_cpu20);
}
/*

188
src/devices/bus/vme/sys68k_cpu20.h Normal file
View File

@ -0,0 +1,188 @@
// license:BSD-3-Clause
// copyright-holders:Joakim Larsson Edstrom
#ifndef MAME_BUS_VME_SYS68K_CPU20_H
#define MAME_BUS_VME_SYS68K_CPU20_H
#pragma once
#include "bus/vme/vme.h"
#include "machine/68561mpcc.h"
#include "machine/68230pit.h"
#include "machine/68153bim.h"
DECLARE_DEVICE_TYPE(VME_SYS68K_CPU20, vme_sys68k_cpu20_card_device)
DECLARE_DEVICE_TYPE(VME_SYS68K_CPU21S, vme_sys68k_cpu21s_card_device)
DECLARE_DEVICE_TYPE(VME_SYS68K_CPU21, vme_sys68k_cpu21_card_device)
DECLARE_DEVICE_TYPE(VME_SYS68K_CPU21A, vme_sys68k_cpu21a_card_device)
DECLARE_DEVICE_TYPE(VME_SYS68K_CPU21YA, vme_sys68k_cpu21ya_card_device)
DECLARE_DEVICE_TYPE(VME_SYS68K_CPU21B, vme_sys68k_cpu21b_card_device)
DECLARE_DEVICE_TYPE(VME_SYS68K_CPU21YB, vme_sys68k_cpu21yb_card_device)
//**************************************************************************
// Base Device declaration
//**************************************************************************
class vme_sys68k_cpu20_card_device_base : public device_t, public device_vme_card_interface
{
protected:
// PIT port C Board ID bits
static constexpr unsigned CPU20 = 0x40;
static constexpr unsigned CPU21 = 0x00;
/* Board types */
enum fc_board_t {
cpu20,
cpu21,
cpu21a,
cpu21ya,
cpu21b,
cpu21yb,
cpu21s
};
vme_sys68k_cpu20_card_device_base(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, fc_board_t board_id);
virtual void device_start() override;
virtual void device_reset() override;
// optional information overrides
virtual void device_add_mconfig(machine_config &config) override;
virtual const tiny_rom_entry *device_rom_region() const override;
TIMER_CALLBACK_MEMBER(grant_bus);
int m_bim_irq_state;
uint8_t m_bim_irq_level;
emu_timer *m_arbiter_start; // Need a startup delay because it is hooked up to the sense inputs of the PIT
required_device<cpu_device> m_maincpu;
private:
void bim_irq_callback(int state);
/* PIT callbacks */
uint8_t pita_r();
uint8_t pitb_r();
uint8_t pitc_r();
void cpu20_mem(address_map &map);
void cpu_space_map(address_map &map);
required_device<pit68230_device> m_pit;
required_device<bim68153_device> m_bim;
required_device<mpcc68561_device> m_mpcc;
required_device<mpcc68561_device> m_mpcc2;
required_device<mpcc68561_device> m_mpcc3;
required_memory_region m_eprom;
required_shared_ptr<uint32_t> m_ram;
memory_passthrough_handler m_boot_mph;
void update_irq_to_maincpu();
const fc_board_t m_board_id;
};
//**************************************************************************
// Board Device declarations
//**************************************************************************
class vme_sys68k_cpu20_card_device : public vme_sys68k_cpu20_card_device_base
{
public :
vme_sys68k_cpu20_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:
vme_sys68k_cpu20_card_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
: vme_sys68k_cpu20_card_device_base(mconfig, type, tag, owner, clock, cpu20)
{ }
// optional information overrides
virtual void device_add_mconfig(machine_config &config) override;
};
class vme_sys68k_cpu21s_card_device : public vme_sys68k_cpu20_card_device_base
{
public :
vme_sys68k_cpu21s_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:
vme_sys68k_cpu21s_card_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
: vme_sys68k_cpu20_card_device_base(mconfig, type, tag, owner, clock, cpu21s)
{ }
// optional information overrides
virtual void device_add_mconfig(machine_config &config) override;
};
class vme_sys68k_cpu21_card_device : public vme_sys68k_cpu20_card_device_base
{
public :
vme_sys68k_cpu21_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:
vme_sys68k_cpu21_card_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
: vme_sys68k_cpu20_card_device_base(mconfig, type, tag, owner, clock, cpu21)
{ }
// optional information overrides
virtual void device_add_mconfig(machine_config &config) override;
};
class vme_sys68k_cpu21a_card_device : public vme_sys68k_cpu20_card_device_base
{
public :
vme_sys68k_cpu21a_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:
vme_sys68k_cpu21a_card_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
: vme_sys68k_cpu20_card_device_base(mconfig, type, tag, owner, clock, cpu21a)
{ }
// optional information overrides
virtual void device_add_mconfig(machine_config &config) override;
};
class vme_sys68k_cpu21ya_card_device : public vme_sys68k_cpu20_card_device_base
{
public :
vme_sys68k_cpu21ya_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:
vme_sys68k_cpu21ya_card_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
: vme_sys68k_cpu20_card_device_base(mconfig, type, tag, owner, clock, cpu21ya)
{ }
// optional information overrides
virtual void device_add_mconfig(machine_config &config) override;
};
class vme_sys68k_cpu21b_card_device : public vme_sys68k_cpu20_card_device_base
{
public :
vme_sys68k_cpu21b_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:
vme_sys68k_cpu21b_card_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
: vme_sys68k_cpu20_card_device_base(mconfig, type, tag, owner, clock, cpu21b)
{ }
// optional information overrides
virtual void device_add_mconfig(machine_config &config) override;
};
class vme_sys68k_cpu21yb_card_device : public vme_sys68k_cpu20_card_device_base
{
public :
vme_sys68k_cpu21yb_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:
vme_sys68k_cpu21yb_card_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
: vme_sys68k_cpu20_card_device_base(mconfig, type, tag, owner, clock, cpu21yb)
{ }
// optional information overrides
virtual void device_add_mconfig(machine_config &config) override;
};
#endif // MAME_BUS_VME_SYS68K_CPU20_H

474
src/mame/force/fccpu30.cpp → src/devices/bus/vme/sys68k_cpu30.cpp
View File

@ -195,15 +195,8 @@
****************************************************************************/
#include "emu.h"
#include "cpu/m68000/m68030.h"
#include "bus/vme/vme.h"
#include "bus/vme/vme_fcisio.h"
#include "bus/vme/vme_fcscsi.h"
#include "machine/msm6242.h"
#include "machine/ram.h" // For variants that only differs in amount of RAM
#include "machine/scnxx562.h"
#include "machine/68230pit.h"
#include "machine/fga002.h"
#include "sys68k_cpu30.h"
#include "machine/nvram.h"
#include "bus/rs232/rs232.h"
#include "machine/clock.h"
@ -231,210 +224,137 @@
#endif
namespace {
#define DUSCC_CLOCK XTAL(14'745'600) /* Verified */
class cpu30_state : public driver_device
DEFINE_DEVICE_TYPE(VME_SYS68K_CPU30, vme_sys68k_cpu30_card_device, "sys68k_cpu30", "Force Computers SYS68K/CPU-30")
DEFINE_DEVICE_TYPE(VME_SYS68K_CPU30X, vme_sys68k_cpu30x_card_device, "sys68k_cpu30x", "Force Computers SYS68K/CPU-30X")
DEFINE_DEVICE_TYPE(VME_SYS68K_CPU30XA, vme_sys68k_cpu30xa_card_device, "sys68k_cpu30xa", "Force Computers SYS68K/CPU-30XA")
DEFINE_DEVICE_TYPE(VME_SYS68K_CPU30ZA, vme_sys68k_cpu30za_card_device, "sys68k_cpu30za", "Force Computers SYS68K/CPU-30ZA")
DEFINE_DEVICE_TYPE(VME_SYS68K_CPU30BE, vme_sys68k_cpu30be_card_device, "sys68k_cpu30be", "Force Computers SYS68K/CPU-30BE")
DEFINE_DEVICE_TYPE(VME_SYS68K_CPU30LITE, vme_sys68k_cpu30lite_card_device, "sys68k_cpu30lite", "Force Computers SYS68K/CPU-30Lite")
DEFINE_DEVICE_TYPE(VME_SYS68K_CPU33, vme_sys68k_cpu33_card_device, "sys68k_cpu33", "Force Computers SYS68K/CPU-33")
sys68k_cpu30_device_base::sys68k_cpu30_device_base(machine_config const &mconfig, device_type type, char const *tag, device_t *owner, u32 clock, uint8_t board_id)
: device_t(mconfig, type, tag, owner, clock)
, device_vme_card_interface(mconfig, *this)
, m_maincpu (*this, "maincpu")
, m_ram(*this, RAM_TAG)
, m_dusccterm(*this, "duscc")
, m_pit1 (*this, "pit1")
, m_pit2 (*this, "pit2")
, m_fga002 (*this, "fga002")
, m_rtc (*this, "rtc")
, m_boot(*this, "boot")
, m_board_id(board_id)
{
public:
cpu30_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device (mconfig, type, tag)
, m_maincpu (*this, "maincpu")
, m_ram(*this, RAM_TAG)
, m_dusccterm(*this, "duscc")
, m_pit1 (*this, "pit1")
, m_pit2 (*this, "pit2")
, m_fga002 (*this, "fga002")
, m_rtc (*this, "rtc")
, m_board_id(0x50)
{
}
}
void cpu30(machine_config &config);
void cpu30x(machine_config &config);
void cpu30zbe(machine_config &config);
void cpu30be8(machine_config &config);
void cpu30za(machine_config &config);
void cpu30lite4(machine_config &config);
void cpu30xa(machine_config &config);
void cpu33(machine_config &config);
void cpu30lite8(machine_config &config);
void cpu30be16(machine_config &config);
vme_sys68k_cpu30_card_device::vme_sys68k_cpu30_card_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock)
: sys68k_cpu30_device_base(mconfig, VME_SYS68K_CPU30, tag, owner, clock, 0x50)
{
}
vme_sys68k_cpu30x_card_device::vme_sys68k_cpu30x_card_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock)
: sys68k_cpu30_device_base(mconfig, VME_SYS68K_CPU30X, tag, owner, clock, 0x50)
{
}
vme_sys68k_cpu30xa_card_device::vme_sys68k_cpu30xa_card_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock)
: sys68k_cpu30_device_base(mconfig, VME_SYS68K_CPU30XA, tag, owner, clock, 0x50)
{
}
vme_sys68k_cpu30za_card_device::vme_sys68k_cpu30za_card_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock)
: sys68k_cpu30_device_base(mconfig, VME_SYS68K_CPU30ZA, tag, owner, clock, 0x50)
{
}
vme_sys68k_cpu30be_card_device::vme_sys68k_cpu30be_card_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock)
: sys68k_cpu30_device_base(mconfig, VME_SYS68K_CPU30BE, tag, owner, clock, 0x50)
{
}
vme_sys68k_cpu30lite_card_device::vme_sys68k_cpu30lite_card_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock)
: sys68k_cpu30_device_base(mconfig, VME_SYS68K_CPU30LITE, tag, owner, clock, 0x50)
{
}
vme_sys68k_cpu33_card_device::vme_sys68k_cpu33_card_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock)
: sys68k_cpu30_device_base(mconfig, VME_SYS68K_CPU33, tag, owner, clock, 0x68) // 0x60 skips FGA prompt
{
}
void init_cpu30x();
void init_cpu30xa();
void init_cpu30za();
void init_cpu30zbe();
void init_cpu30be8();
void init_cpu30be16();
void init_cpu30lite4();
void init_cpu30lite8();
void init_cpu33();
private:
void fdc_w(offs_t offset, uint8_t data);
uint8_t fdc_r(offs_t offset);
void scsi_w(offs_t offset, uint8_t data);
uint8_t scsi_r(offs_t offset);
uint8_t slot1_status_r();
uint32_t bootvect_r(offs_t offset);
void bootvect_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
/* Interrupt support */
void cpu_space_map(address_map &map);
void fga_irq_callback(int state);
uint8_t fga_irq_state = 0;
// int fga_irq_vector = 0;
int fga_irq_level = 0;
/* Rotary switch PIT input */
uint8_t rotary_rd();
uint8_t flop_dmac_r();
void flop_dmac_w(uint8_t data);
uint8_t pit1c_r();
void pit1c_w(uint8_t data);
uint8_t pit2a_r();
void pit2a_w(uint8_t data);
uint8_t board_mem_id_rd();
uint8_t pit2c_r();
void pit2c_w(uint8_t data);
/* VME bus accesses */
//uint16_t vme_a24_r();
//void vme_a24_w(uint16_t data);
//uint16_t vme_a16_r();
//void vme_a16_w(uint16_t data);
virtual void machine_start () override;
virtual void machine_reset () override;
void cpu30_mem(address_map &map);
required_device<m68000_musashi_device> m_maincpu;
required_device<ram_device> m_ram;
required_device<duscc68562_device> m_dusccterm;
required_device<pit68230_device> m_pit1;
required_device<pit68230_device> m_pit2;
required_device<fga002_device> m_fga002;
required_device<rtc72423_device> m_rtc;
// Helper functions
void update_irq_to_maincpu();
// Pointer to System ROMs needed by bootvect_r and masking RAM buffer for post reset accesses
uint32_t *m_sysrom = nullptr;
uint32_t m_sysram[2]{};
uint8_t m_board_id;
};
void cpu30_state::cpu30_mem(address_map &map)
void sys68k_cpu30_device_base::cpu30_mem(address_map &map)
{
map.unmap_value_high();
map(0x00000000, 0x00000007).ram().w(FUNC(cpu30_state::bootvect_w)); /* After first write we act as RAM */
map(0x00000000, 0x00000007).rom().r(FUNC(cpu30_state::bootvect_r)); /* ROM mirror just during reset */
// map(0x00000008, 0x003fffff).ram(); /* RAM installed in machine start */
map(0xff000000, 0xff7fffff).rom().region("roms", 0x000000);
map(0xff000000, 0xff7fffff).rom().region("system", 0);
map(0xff800c00, 0xff800dff).rw(m_pit1, FUNC(pit68230_device::read), FUNC(pit68230_device::write));
map(0xff800e00, 0xff800fff).rw(m_pit2, FUNC(pit68230_device::read), FUNC(pit68230_device::write));
map(0xff802000, 0xff8021ff).rw(m_dusccterm, FUNC(duscc68562_device::read), FUNC(duscc68562_device::write)); /* Port 1&2 - Dual serial port DUSCC */
map(0xff802200, 0xff8023ff).rw("duscc2", FUNC(duscc68562_device::read), FUNC(duscc68562_device::write)); /* Port 3&4 - Dual serial port DUSCC */
map(0xff803000, 0xff8031ff).rw(m_rtc, FUNC(rtc72423_device::read), FUNC(rtc72423_device::write));
// map(0xff803400, 0xff8035ff).rw("scsi", FUNC(mb87033_device::read), FUNC(mb87033_device::write)); /* TODO: implement MB87344 SCSI device */
map(0xff803400, 0xff8035ff).rw(FUNC(cpu30_state::scsi_r), FUNC(cpu30_state::scsi_w)).umask32(0x000000ff); /* mock driver to log calls to device */
map(0xff803400, 0xff8035ff).rw(FUNC(sys68k_cpu30_device_base::scsi_r), FUNC(sys68k_cpu30_device_base::scsi_w)).umask32(0x000000ff); /* mock driver to log calls to device */
// map(0xff803800, 0xff80397f).rw("fdc", FUNC(wd37c65c_device::read), FUNC(wd37c65c_device::write)); /* TODO: implement WD3/C65C fdc controller */
map(0xff803800, 0xff80397f).rw(FUNC(cpu30_state::fdc_r), FUNC(cpu30_state::fdc_w)).umask32(0x000000ff); /* mock driver to log calls to device */
map(0xff803980, 0xff8039ff).r(FUNC(cpu30_state::slot1_status_r)).umask32(0x000000ff);
map(0xff803800, 0xff80397f).rw(FUNC(sys68k_cpu30_device_base::fdc_r), FUNC(sys68k_cpu30_device_base::fdc_w)).umask32(0x000000ff); /* mock driver to log calls to device */
map(0xff803980, 0xff8039ff).r(FUNC(sys68k_cpu30_device_base::slot1_status_r)).umask32(0x000000ff);
map(0xffc00000, 0xffcfffff).ram().share("nvram"); /* On-board SRAM with battery backup (nvram) */
map(0xffd00000, 0xffdfffff).rw(m_fga002, FUNC(fga002_device::read), FUNC(fga002_device::write)); /* FGA-002 Force Gate Array */
map(0xffe00000, 0xffefffff).rom().region("roms", 0x800000);
map(0xffe00000, 0xffe0ffff).rom().region("boot", 0);
//map(0x100000, 0xfeffff).rw(FUNC(cpu30_state::vme_a24_r), FUNC(cpu30_state::vme_a24_w)); /* VMEbus Rev B addresses (24 bits) - not verified */
//map(0xff0000, 0xffffff).rw(FUNC(cpu30_state::vme_a16_r), FUNC(cpu30_state::vme_a16_w)); /* VMEbus Rev B addresses (16 bits) - not verified */
//map(0x100000, 0xfeffff).rw(FUNC(sys68k_cpu30_device_base::vme_a24_r), FUNC(sys68k_cpu30_device_base::vme_a24_w)); /* VMEbus Rev B addresses (24 bits) - not verified */
//map(0xff0000, 0xffffff).rw(FUNC(sys68k_cpu30_device_base::vme_a16_r), FUNC(sys68k_cpu30_device_base::vme_a16_w)); /* VMEbus Rev B addresses (16 bits) - not verified */
}
/* Input ports */
static INPUT_PORTS_START (cpu30)
static INPUT_PORTS_START (sys68k_cpu30)
INPUT_PORTS_END
/* Start it up */
void cpu30_state::machine_start ()
void sys68k_cpu30_device_base::device_start ()
{
LOGINIT("%s\n", FUNCNAME);
}
void sys68k_cpu30_device_base::device_reset()
{
LOGINIT("%s\n", FUNCNAME);
save_pointer (NAME (m_sysrom), sizeof(m_sysrom));
save_pointer (NAME (m_sysram), sizeof(m_sysram));
m_maincpu->space(AS_PROGRAM).install_rom(0, m_boot->bytes() - 1, m_boot->base());
/* setup ram */
m_maincpu->space(AS_PROGRAM).install_ram(0x08, m_ram->size() - 1, m_ram->pointer());
/* Setup pointer to bootvector in ROM for bootvector handler bootvect_r */
m_sysrom = (uint32_t*)(memregion ("roms")->base () + 0x800000);
m_boot_mph = m_maincpu->space(AS_PROGRAM).install_read_tap(0x000004, 0x000007, "boot",
[this](offs_t offset, u32 &data, u32 mem_mask)
{
if (!machine().side_effects_disabled() && ACCESSING_BITS_0_15)
{
m_maincpu->space(AS_PROGRAM).install_ram(0, m_ram->size() - 1, m_ram->pointer());
m_boot_mph.remove();
}
});
}
void cpu30_state::machine_reset ()
{
LOGINIT("%s\n", FUNCNAME);
/* Reset pointer to bootvector in ROM for bootvector handler bootvect_r */
if (m_sysrom == &m_sysram[0]) /* Condition needed because memory map is not setup first time */
m_sysrom = (uint32_t*)(memregion ("roms")->base () + 0x800000);
}
/* setup board ID */
void cpu30_state::init_cpu30x() { LOGINIT("%s\n", FUNCNAME); m_board_id = 0x50; }
void cpu30_state::init_cpu30xa() { LOGINIT("%s\n", FUNCNAME); m_board_id = 0x50; }
void cpu30_state::init_cpu30za() { LOGINIT("%s\n", FUNCNAME); m_board_id = 0x50; }
void cpu30_state::init_cpu30zbe() { LOGINIT("%s\n", FUNCNAME); m_board_id = 0x50; }
void cpu30_state::init_cpu30be8() { LOGINIT("%s\n", FUNCNAME); m_board_id = 0x50; }
void cpu30_state::init_cpu30be16() { LOGINIT("%s\n", FUNCNAME); m_board_id = 0x50; }
void cpu30_state::init_cpu30lite4() { LOGINIT("%s\n", FUNCNAME); m_board_id = 0x50; }
void cpu30_state::init_cpu30lite8() { LOGINIT("%s\n", FUNCNAME); m_board_id = 0x50; }
void cpu30_state::init_cpu33() { LOGINIT("%s\n", FUNCNAME); m_board_id = 0x68; } // 0x60 skips FGA prompt
/* Mock FDC driver */
uint8_t cpu30_state::fdc_r(offs_t offset){
uint8_t sys68k_cpu30_device_base::fdc_r(offs_t offset){
LOG("%s\n * FDC read Offset: %04x\n", FUNCNAME, offset);
return 1;
}
void cpu30_state::fdc_w(offs_t offset, uint8_t data){
void sys68k_cpu30_device_base::fdc_w(offs_t offset, uint8_t data){
LOG("%s\n * FDC write Offset: %04x Data: %02x\n", FUNCNAME, offset, data);
}
/* Mock SCSI driver */
uint8_t cpu30_state::scsi_r(offs_t offset){
uint8_t sys68k_cpu30_device_base::scsi_r(offs_t offset){
LOG("%s\n * SCSI read Offset: %04x\n", FUNCNAME, offset);
return 1;
}
void cpu30_state::scsi_w(offs_t offset, uint8_t data){
void sys68k_cpu30_device_base::scsi_w(offs_t offset, uint8_t data){
LOG("%s\n * SCSI write Offset: %04x Data: %02x\n", FUNCNAME, offset, data);
}
/* 1 = board is in slot 1, 0 = board is NOT in slot 1 */
uint8_t cpu30_state::slot1_status_r(){
uint8_t sys68k_cpu30_device_base::slot1_status_r(){
LOG("%s\n", FUNCNAME);
return 1;
}
/* Boot vector handler, the PCB hardwires the first 8 bytes from 0xff800000 to 0x0 at reset*/
uint32_t cpu30_state::bootvect_r(offs_t offset){
LOG("%s\n", FUNCNAME);
return m_sysrom[offset];
}
void cpu30_state::bootvect_w(offs_t offset, uint32_t data, uint32_t mem_mask){
LOG("%s\n", FUNCNAME);
m_sysram[offset % std::size(m_sysram)] &= ~mem_mask;
m_sysram[offset % std::size(m_sysram)] |= (data & mem_mask);
m_sysrom = &m_sysram[0]; // redirect all upcoming accesses to masking RAM until reset.
}
/*
* Rotary Switches - to configure the board
*
@ -489,42 +409,42 @@ void cpu30_state::bootvect_w(offs_t offset, uint32_t data, uint32_t mem_mask){
*
* "To start VMEPROM, the rotary switches must both be set to 'F':" Hmm...
*/
uint8_t cpu30_state::rotary_rd(){
uint8_t sys68k_cpu30_device_base::rotary_rd(){
LOG("%s\n", FUNCNAME);
return 0xff; // TODO: make this configurable from commandline or artwork
}
// PIT#1 Port B TODO: implement floppy and dma control
uint8_t cpu30_state::flop_dmac_r(){
uint8_t sys68k_cpu30_device_base::flop_dmac_r(){
LOG("%s\n", FUNCNAME);
return 0xff;
}
void cpu30_state::flop_dmac_w(uint8_t data){
void sys68k_cpu30_device_base::flop_dmac_w(uint8_t data){
LOG("%s(%02x)\n", FUNCNAME, data);
}
#define FPCP_SENSE 0x40 /* Port C bit 6 is low if a Floating Point Co Processor is installed */
// PIT#1 Port C TODO: implement timer+port interrupts
// TODO: Connect PC0, PC1, PC4 and PC7 to B5 and/or P2 connector
uint8_t cpu30_state::pit1c_r(){
uint8_t sys68k_cpu30_device_base::pit1c_r(){
LOG("%s\n", FUNCNAME);
m_maincpu->set_fpu_enable(1); // Lets assume the FPCP is always installed ( which is default for 68030 atm )
return 0xff & ~FPCP_SENSE; // Should really be command line for the edge cases...
}
void cpu30_state::pit1c_w(uint8_t data){
void sys68k_cpu30_device_base::pit1c_w(uint8_t data){
LOG("%s(%02x)\n", FUNCNAME, data);
}
// PIT#2 Port A TODO: Connect to B5 and /or P2 connector
uint8_t cpu30_state::pit2a_r(){
uint8_t sys68k_cpu30_device_base::pit2a_r(){
LOG("%s\n", FUNCNAME);
logerror("Unsupported user i/o on PIT2 port A detected\n");
return 0xff;
}
void cpu30_state::pit2a_w(uint8_t data){
void sys68k_cpu30_device_base::pit2a_w(uint8_t data){
LOG("%s(%02x)\n", FUNCNAME, data);
logerror("Unsupported user i/o on PIT2 port A detected\n");
}
@ -547,7 +467,7 @@ void cpu30_state::pit2a_w(uint8_t data){
* Currently this doesn't work so the wrong speed is displayed on the screen. To fix this timing needs to be more exact.
* Speed measure subroutine is at address 0xffe033c4 in the FGA-002 firmware with CRC (faa38972) (for example)
*/
uint8_t cpu30_state::board_mem_id_rd()
uint8_t sys68k_cpu30_device_base::board_mem_id_rd()
{
int sz;
LOG("%s\n", FUNCNAME);
@ -593,37 +513,37 @@ uint8_t cpu30_state::board_mem_id_rd()
}
// PIT#2 Port C TODO: implement timer interrupt, DMA i/o, memory control and Hardware ID
uint8_t cpu30_state::pit2c_r(){
uint8_t sys68k_cpu30_device_base::pit2c_r(){
LOG("%s\n", FUNCNAME);
return 0xfe;
}
void cpu30_state::pit2c_w(uint8_t data){
void sys68k_cpu30_device_base::pit2c_w(uint8_t data){
LOG("%s(%02x)\n", FUNCNAME, data);
}
#if 0
/* Dummy VME access methods until the VME bus device is ready for use */
uint16_t cpu30_state::vme_a24_r(){
uint16_t sys68k_cpu30_device_base::vme_a24_r(){
LOG("%s\n", FUNCNAME);
return (uint16_t) 0;
}
void cpu30_state::vme_a24_w(uint16_t data){
void sys68k_cpu30_device_base::vme_a24_w(uint16_t data){
LOG("%s(%02x)\n", FUNCNAME, data);
}
uint16_t cpu30_state::vme_a16_r(){
uint16_t sys68k_cpu30_device_base::vme_a16_r(){
LOG("%s\n", FUNCNAME);
return (uint16_t) 0;
}
void cpu30_state::vme_a16_w(uint16_t data){
void sys68k_cpu30_device_base::vme_a16_w(uint16_t data){
LOG("%s(%02x)\n", FUNCNAME, data);
}
#endif
void cpu30_state::fga_irq_callback(int state)
void sys68k_cpu30_device_base::fga_irq_callback(int state)
{
LOGINT("%s(%02x)\n", FUNCNAME, state);
@ -633,7 +553,7 @@ void cpu30_state::fga_irq_callback(int state)
update_irq_to_maincpu();
}
void cpu30_state::update_irq_to_maincpu()
void sys68k_cpu30_device_base::update_irq_to_maincpu()
{
LOGINT("%s()\n", FUNCNAME);
LOGINT(" - fga_irq_level: %02x\n", fga_irq_level);
@ -651,31 +571,23 @@ void cpu30_state::update_irq_to_maincpu()
}
}
static void fccpu30_vme_cards(device_slot_interface &device)
{
device.option_add("fcisio", VME_FCISIO1);
device.option_add("fcscsi", VME_FCSCSI1);
}
/*
* Machine configuration
*/
void cpu30_state::cpu_space_map(address_map &map)
void sys68k_cpu30_device_base::cpu_space_map(address_map &map)
{
map(0xfffffff2, 0xffffffff).lr16(NAME([this] (offs_t offset) -> u16 { return m_fga002->iack(); }));
}
void cpu30_state::cpu30(machine_config &config)
void sys68k_cpu30_device_base::sys68k_cpu30(machine_config &config, XTAL clock, char const *const ram_default, char const *const ram_options)
{
/* basic machine hardware */
M68030(config, m_maincpu, XTAL(25'000'000));
m_maincpu->set_addrmap(AS_PROGRAM, &cpu30_state::cpu30_mem);
m_maincpu->set_addrmap(m68000_base_device::AS_CPU_SPACE, &cpu30_state::cpu_space_map);
M68030(config, m_maincpu, clock);
m_maincpu->set_addrmap(AS_PROGRAM, &sys68k_cpu30_device_base::cpu30_mem);
m_maincpu->set_addrmap(m68000_base_device::AS_CPU_SPACE, &sys68k_cpu30_device_base::cpu_space_map);
NVRAM(config, "nvram", nvram_device::DEFAULT_ALL_0);
VME(config, "vme", 0);
VME_SLOT(config, "slot1", fccpu30_vme_cards, nullptr, 1, "vme");
/* Terminal Port config */
/* Force CPU30 series of boards has up to four serial ports, p1-p4, the FGA boot uses p4 as console and subsequent
firmware uses p1 as console and in an operating system environment there may be user login shells on the other.
@ -742,24 +654,24 @@ void cpu30_state::cpu30(machine_config &config)
/* PIT Parallel Interface and Timer device, assumed strapped for on board clock */
PIT68230(config, m_pit1, XTAL(16'000'000) / 2); // The PIT clock is not verified on schema but reversed from behaviour
m_pit1->pa_in_callback().set(FUNC(cpu30_state::rotary_rd));
m_pit1->pb_in_callback().set(FUNC(cpu30_state::flop_dmac_r));
m_pit1->pb_out_callback().set(FUNC(cpu30_state::flop_dmac_w));
m_pit1->pc_in_callback().set(FUNC(cpu30_state::pit1c_r));
m_pit1->pc_out_callback().set(FUNC(cpu30_state::pit1c_w));
m_pit1->pa_in_callback().set(FUNC(sys68k_cpu30_device_base::rotary_rd));
m_pit1->pb_in_callback().set(FUNC(sys68k_cpu30_device_base::flop_dmac_r));
m_pit1->pb_out_callback().set(FUNC(sys68k_cpu30_device_base::flop_dmac_w));
m_pit1->pc_in_callback().set(FUNC(sys68k_cpu30_device_base::pit1c_r));
m_pit1->pc_out_callback().set(FUNC(sys68k_cpu30_device_base::pit1c_w));
// m_pit1->timer_irq_callback().set(m_fga002, FUNC(fga002_device::lirq2_w)); // The timer interrupt seems to silence the terminal interrupt, needs invectigation
PIT68230(config, m_pit2, XTAL(16'000'000) / 2); // Th PIT clock is not verified on schema but reversed from behaviour
m_pit2->pb_in_callback().set(FUNC(cpu30_state::board_mem_id_rd));
m_pit2->pa_in_callback().set(FUNC(cpu30_state::pit2a_r));
m_pit2->pa_out_callback().set(FUNC(cpu30_state::pit2a_w));
m_pit2->pc_in_callback().set(FUNC(cpu30_state::pit2c_r));
m_pit2->pc_out_callback().set(FUNC(cpu30_state::pit2c_w));
m_pit2->pb_in_callback().set(FUNC(sys68k_cpu30_device_base::board_mem_id_rd));
m_pit2->pa_in_callback().set(FUNC(sys68k_cpu30_device_base::pit2a_r));
m_pit2->pa_out_callback().set(FUNC(sys68k_cpu30_device_base::pit2a_w));
m_pit2->pc_in_callback().set(FUNC(sys68k_cpu30_device_base::pit2c_r));
m_pit2->pc_out_callback().set(FUNC(sys68k_cpu30_device_base::pit2c_w));
// m_pit2->timer_irq_callback().set(m_fga002, FUNC(fga002_device::lirq3_w)); // The timer interrupt seems to silence the terminal interrupt, needs invectigation
/* FGA-002, Force Gate Array */
FGA002(config, m_fga002, 0);
m_fga002->out_int().set(FUNC(cpu30_state::fga_irq_callback));
m_fga002->out_int().set(FUNC(sys68k_cpu30_device_base::fga_irq_callback));
m_fga002->liack4().set("duscc", FUNC(duscc_device::iack));
m_fga002->liack5().set("duscc2", FUNC(duscc_device::iack));
@ -768,138 +680,106 @@ void cpu30_state::cpu30(machine_config &config)
m_rtc->out_int_handler().set(m_fga002, FUNC(fga002_device::lirq0_w));
// dual ported ram
RAM(config, m_ram).set_default_size("4M").set_extra_options("8M, 16M, 32M");
RAM(config, m_ram).set_default_size(ram_default).set_extra_options(ram_options);
}
void vme_sys68k_cpu30_card_device::device_add_mconfig(machine_config &config)
{
sys68k_cpu30(config, XTAL(25'000'000), "4M", "4M, 8M, 16M, 32M");
}
/* SYS68K/CPU-30X Part No.1 01300: 16.7 MHz 68030 based CPU board with 68882 FPCP, DMAC, 1 Mbyte Dual Ported RAM capacity and VMEPROM. */
void cpu30_state::cpu30x(machine_config &config)
void vme_sys68k_cpu30x_card_device::device_add_mconfig(machine_config &config)
{
cpu30(config);
m_maincpu->set_clock(XTAL(16'777'216)); /* 16.7 MHz from description, crystal needs verification */
// config.device_remove("");
// dual ported ram
m_ram->set_default_size("1M").set_extra_options("1M, 2M, 4M");
sys68k_cpu30(config, XTAL(16'777'216), "1M", "1M, 2M, 4M"); // 16.7 MHz from description, crystal needs verification
}
/* SYS68K/CPU-30XA Part No.1 01301: 20.0 MHz 68030 based CPU board with 68882 FPCP, DMAC, 1 Mbyte Dual Ported RAM capacity and VMEPROM. Documentation included.*/
void cpu30_state::cpu30xa(machine_config &config)
void vme_sys68k_cpu30xa_card_device::device_add_mconfig(machine_config &config)
{
cpu30x(config);
m_maincpu->set_clock(XTAL(20'000'000)); /* 20.0 MHz from description, crystal needs verification */
sys68k_cpu30(config, XTAL(20'000'000), "1M", "1M, 2M, 4M"); // 20.0 MHz from description, crystal needs verification
}
/* SYS68K/CPU-30ZA Part No.1 01302: 20.0 MHz 68030 based CPU board with 68882 FPCP, DMAC, 4 Mbyte Dual Ported RAM capacity and VMEPROM. Documentation included.*/
void cpu30_state::cpu30za(machine_config &config)
void vme_sys68k_cpu30za_card_device::device_add_mconfig(machine_config &config)
{
cpu30xa(config);
m_maincpu->set_clock(XTAL(20'000'000)); /* 20.0 MHz from description, crystal needs verification */
// dual ported ram
m_ram->set_default_size("4M").set_extra_options("1M, 2M, 4M");
sys68k_cpu30(config, XTAL(20'000'000), "4M", "1M, 2M, 4M"); // 20.0 MHz from description, crystal needs verification
}
/* SYS68K/CPU-30ZBE 68030/68882 CPU, 25 MHz, 4 Mbyte shared DRAM, 4 Mbyte Flash, SCSI, Ethernet, Floppy disk, 4 serial I/O ports, 32-bit VMEbus interface */
void cpu30_state::cpu30zbe(machine_config &config)
/* SYS68K/CPU-30ZBE 68030/68882 CPU, 25 MHz, 4/8/16 Mbyte shared DRAM, 4 Mbyte Flash, SCSI, Ethernet, Floppy disk, 4 serial I/O ports, 32-bit VMEbus interface */
void vme_sys68k_cpu30be_card_device::device_add_mconfig(machine_config &config)
{
cpu30za(config);
m_maincpu->set_clock(XTAL(25'000'000)); /* 25.0 MHz from description, crystal needs verification */
// dual ported ram
m_ram->set_default_size("4M").set_extra_options("256K, 512K, 1M, 2M, 4M, 8M, 16M, 32M");
sys68k_cpu30(config, XTAL(25'000'000), "4M", "256K, 512K, 1M, 2M, 4M, 8M, 16M, 32M"); // 25.0 MHz from description, crystal needs verification
}
/* SYS68K/CPU-33 */
void cpu30_state::cpu33(machine_config &config)
void vme_sys68k_cpu33_card_device::device_add_mconfig(machine_config &config)
{
cpu30zbe(config);
m_maincpu->set_clock(XTAL(25'000'000)); /* 25.0 MHz from description, crystal needs verification */
// dual ported ram
m_ram->set_default_size("4M").set_extra_options("256K, 512K, 1M, 2M, 4M, 8M, 16M, 32M");
sys68k_cpu30(config, XTAL(25'000'000), "4M", "256K, 512K, 1M, 2M, 4M, 8M, 16M, 32M"); // 25.0 MHz from description, crystal needs verification
}
/* SYS68K/CPU-30BE/8 68030/68882 CPU, 25 MHz, 8 Mbyte shared DRAM, 4 Mbyte Flash, SCSI, Ethernet, Floppy disk, 4 serial I/O ports, 32-bit VMEbus interface, VMEPROM firmware*/
void cpu30_state::cpu30be8(machine_config &config)
/* SYS68K/CPU-30Lite 68030 CPU, 25 MHz, 4/8 Mbyte shared DRAM, 4 Mbyte Flash, 4 serial ports, 32-bit VMEbus interface, VMEPROM firmware. */
void vme_sys68k_cpu30lite_card_device::device_add_mconfig(machine_config &config)
{
cpu30zbe(config);
// dual ported ram
m_ram->set_default_size("8M").set_extra_options("256K, 512K, 1M, 2M, 4M, 8M, 16M, 32M");
}
sys68k_cpu30(config, XTAL(25'000'000), "4M", "256K, 512K, 1M, 2M, 4M, 8M, 16M, 32M");
/* SYS68K/CPU-30BE/16 68030/68882 CPU, 25 MHz, 16 Mbyte shared DRAM, 4 Mbyte Flash, SCSI, Ethernet, Floppy disk, 4 serial I/O ports, 32-bit VMEbus interface, VMEPROM firmware*/
void cpu30_state::cpu30be16(machine_config &config)
{
cpu30zbe(config);
// dual ported ram
m_ram->set_default_size("16M").set_extra_options("256K, 512K, 1M, 2M, 4M, 8M, 16M, 32M");
}
/* SYS68K/CPU-30Lite/4 68030 CPU, 25 MHz, 4 Mbyte shared DRAM, 4 Mbyte Flash, 4 serial ports, 32-bit VMEbus interface, VMEPROM firmware. */
void cpu30_state::cpu30lite4(machine_config &config)
{
cpu30zbe(config);
// Enable these when added to main config
// config.device_remove("fpu");
// config.device_remove("scsi");
// config.device_remove("eth");
// config.device_remove("fdc");
// dual ported ram
m_ram->set_default_size("4M").set_extra_options("256K, 512K, 1M, 2M, 4M, 8M, 16M, 32M");
}
/* SYS68K/CPU-30Lite/8 68030 CPU, 25 MHz, 4 Mbyte shared DRAM, 8 Mbyte Flash, 4 serial ports, 32-bit VMEbus interface, VMEPROM firmware. */
void cpu30_state::cpu30lite8(machine_config &config)
{
cpu30lite4(config);
// dual ported ram
m_ram->set_default_size("8M").set_extra_options("256K, 512K, 1M, 2M, 4M, 8M, 16M, 32M");
}
/* ROM definitions */
ROM_START (fccpu30) /* This is an original rom dump */
ROM_REGION32_BE(0x900000, "roms", 0)
ROM_START (sys68k_cpu30) /* This is an original rom dump */
ROM_REGION32_BE(0x800000, "system", 0)
// Boots with Board ID set to: 0x36 (FGA002 BOOT on terminal P4, "Wait until harddisk is up to speed " on terminal P1)
ROM_LOAD32_BYTE("cpu30ll-ubr-v2.1.rom", 0x000003, 0x20000, CRC (a03ebf46) SHA1 (48fa0268cb10e20679c093e02574dbd9925f95d1))
ROM_LOAD32_BYTE("cpu30lo-ubr-v2.1.rom", 0x000002, 0x20000, CRC (fefa88ed) SHA1 (71a9ad807c0c2da5c6f6a6dc68c73ad8b52f3ea9))
ROM_LOAD32_BYTE("cpu30up-ubr-v2.1.rom", 0x000001, 0x20000, CRC (dfed1f68) SHA1 (71478a77d5ab5da0fabcd78e69537919b560e3b8))
ROM_LOAD32_BYTE("cpu30uu-ubr-v2.1.rom", 0x000000, 0x20000, CRC (66e95cc2) SHA1 (acdb468a3a5974295b81271d617de7f101098891))
// Same binary for many boards, attempts to detect CPU speed etc, currently failing detection but boots system roms anyway
ROM_LOAD ("fga002-3.1.rom", 0x800000, 0x10000, CRC (faa38972) SHA1 (651dfc2f9a865fc6adf49dad90f9e705f2889919) )
ROM_REGION32_BE(0x10000, "boot", 0)
ROM_LOAD ("fga002-3.1.rom", 0x000000, 0x10000, CRC (faa38972) SHA1 (651dfc2f9a865fc6adf49dad90f9e705f2889919) )
ROM_END
ROM_START (fccpu33) /* This is an original rom dump */
ROM_REGION32_BE(0x900000, "roms", 0)
ROM_START (sys68k_cpu33) /* This is an original rom dump */
ROM_REGION32_BE(0x800000, "system", 0)
// Boots with Board ID set to: 0x36 (FGA002 BOOT and VMEPROM on terminal P4)
ROM_LOAD16_BYTE("cpu33lo-ubr-v1.01.rom", 0x000001, 0x40000, CRC (49895fdf) SHA1 (733abd144c95225a2faf920490e31df2a27f8e03))
ROM_LOAD16_BYTE("cpu33up-ubr-v1.01.rom", 0x000000, 0x40000, CRC (cfe75e94) SHA1 (d40e0635a48607be25f7c58c74b53b7e58fe735d))
// Same binary for many boards, attempts to detect CPU speed etc, currently failing detection but boots system roms anyway
ROM_LOAD ("fga002-3.1.rom", 0x800000, 0x10000, CRC (faa38972) SHA1 (651dfc2f9a865fc6adf49dad90f9e705f2889919) )
ROM_REGION32_BE(0x10000, "boot", 0)
ROM_LOAD ("fga002-3.1.rom", 0x000000, 0x10000, CRC (faa38972) SHA1 (651dfc2f9a865fc6adf49dad90f9e705f2889919) )
ROM_END
ROM_START (nodump)
ROM_REGION32_BE(0x900000, "roms", 0)
ROM_LOAD("rom.bin", 0x800000, 0x10000, NO_DUMP)
ROM_REGION32_BE(0x800000, "system", 0)
ROM_LOAD("system.bin", 0x000000, 0x800000, NO_DUMP)
ROM_REGION32_BE(0x10000, "boot", 0)
ROM_LOAD("boot.bin", 0x000000, 0x10000, NO_DUMP)
ROM_END
/* These needs reality check as they has 1Mb of RAM which is not a suitable size for later CPU_30:s */
#define rom_fccpu30x rom_fccpu30
#define rom_fccpu30xa rom_fccpu30
#define rom_fccpu30za rom_fccpu30
const tiny_rom_entry *vme_sys68k_cpu30_card_device::device_rom_region() const { return ROM_NAME(sys68k_cpu30); }
#define rom_fccpu30zbe rom_fccpu30
#define rom_fccpu30be8 rom_fccpu30
#define rom_fccpu30be16 rom_fccpu30
/* These needs reality check as they has 1Mb of RAM which is not a suitable size for later CPU_30:s */
const tiny_rom_entry *vme_sys68k_cpu30x_card_device::device_rom_region() const { return ROM_NAME(sys68k_cpu30); }
const tiny_rom_entry *vme_sys68k_cpu30xa_card_device::device_rom_region() const { return ROM_NAME(sys68k_cpu30); }
const tiny_rom_entry *vme_sys68k_cpu30za_card_device::device_rom_region() const { return ROM_NAME(sys68k_cpu30); }
const tiny_rom_entry *vme_sys68k_cpu30be_card_device::device_rom_region() const { return ROM_NAME(sys68k_cpu30); }
/* These needs dumps */
#define rom_fccpu30lite4 rom_nodump
#define rom_fccpu30lite8 rom_nodump
const tiny_rom_entry *vme_sys68k_cpu30lite_card_device::device_rom_region() const { return ROM_NAME(nodump); }
/* These are most likelly wrong, needs dump */
#define rom_fccpu30senr rom_nodump
#define rom_fccpu30senr501 rom_nodump
const tiny_rom_entry *vme_sys68k_cpu33_card_device::device_rom_region() const { return ROM_NAME(sys68k_cpu33); }
ioport_constructor sys68k_cpu30_device_base::device_input_ports() const
{
return INPUT_PORTS_NAME(sys68k_cpu30);
}
/*
* System ROM information
@ -1037,38 +917,36 @@ void fga002_device::trigger_interrupt(uint8_t)(34)
Interrupt Level 4, caused by ICR 1c with vector 34
void fga002_device::check_interrupts()()
:fga002 virtual int fga002_device::z80daisy_irq_state() Level 0-7:[00][00] [00][00] [01][00] [00][00]
void cpu30_state::fga_irq_callback(int)(01)
void sys68k_cpu30_device_base::fga_irq_callback(int)(01)
void fga002_device::check_interrupts()()
*/
} // anonymous namespace
/* Driver */
/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS */
COMP( 1988, fccpu30, 0, 0, cpu30, cpu30, cpu30_state, empty_init, "Force Computers GmbH", "SYS68K/CPU-30", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW )
COMP( 1988, fccpu30x, fccpu30, 0, cpu30x, cpu30, cpu30_state, init_cpu30x, "Force Computers GmbH", "SYS68K/CPU-30X", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW )
COMP( 1988, fccpu30xa, fccpu30, 0, cpu30xa, cpu30, cpu30_state, init_cpu30xa, "Force Computers GmbH", "SYS68K/CPU-30XA", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW )
COMP( 1988, fccpu30za, fccpu30, 0, cpu30za, cpu30, cpu30_state, init_cpu30za, "Force Computers GmbH", "SYS68K/CPU-30ZA", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW )
COMP( 1996, fccpu30zbe, fccpu30, 0, cpu30zbe, cpu30, cpu30_state, init_cpu30zbe, "Force Computers GmbH", "SYS68K/CPU-30ZBE", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW )
COMP( 1996, fccpu30be8, fccpu30, 0, cpu30be8, cpu30, cpu30_state, init_cpu30be8, "Force Computers GmbH", "SYS68K/CPU-30BE/8", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW )
COMP( 1996, fccpu30be16, fccpu30, 0, cpu30be16, cpu30, cpu30_state, init_cpu30be16, "Force Computers GmbH", "SYS68K/CPU-30BE/16", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW )
COMP( 1996, fccpu30lite4, fccpu30, 0, cpu30lite4, cpu30, cpu30_state, init_cpu30lite4, "Force Computers GmbH", "SYS68K/CPU-30Lite/4", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW )
COMP( 1996, fccpu30lite8, fccpu30, 0, cpu30lite8, cpu30, cpu30_state, init_cpu30lite8, "Force Computers GmbH", "SYS68K/CPU-30Lite/8", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW )
COMP( 199?, fccpu33, fccpu30, 0, cpu33, cpu30, cpu30_state, init_cpu33, "Force Computers GmbH", "SYS68K/CPU-33", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW )
//COMP( 1988, sys68k_cpu30, 0, 0, cpu30, cpu30, sys68k_cpu30_device_base, empty_init, "Force Computers GmbH", "SYS68K/CPU-30", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW )
//COMP( 1988, sys68k_cpu30x, sys68k_cpu30, 0, cpu30x, cpu30, sys68k_cpu30_device_base, init_cpu30x, "Force Computers GmbH", "SYS68K/CPU-30X", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW )
//COMP( 1988, sys68k_cpu30xa, sys68k_cpu30, 0, cpu30xa, cpu30, sys68k_cpu30_device_base, init_cpu30xa, "Force Computers GmbH", "SYS68K/CPU-30XA", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW )
//COMP( 1988, sys68k_cpu30za, sys68k_cpu30, 0, cpu30za, cpu30, sys68k_cpu30_device_base, init_cpu30za, "Force Computers GmbH", "SYS68K/CPU-30ZA", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW )
//COMP( 1996, sys68k_cpu30zbe, sys68k_cpu30, 0, cpu30zbe, cpu30, sys68k_cpu30_device_base, init_cpu30zbe, "Force Computers GmbH", "SYS68K/CPU-30ZBE", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW )
//COMP( 1996, sys68k_cpu30be8, sys68k_cpu30, 0, cpu30be8, cpu30, sys68k_cpu30_device_base, init_cpu30be8, "Force Computers GmbH", "SYS68K/CPU-30BE/8", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW )
//COMP( 1996, sys68k_cpu30be16, sys68k_cpu30, 0, cpu30be16, cpu30, sys68k_cpu30_device_base, init_cpu30be16, "Force Computers GmbH", "SYS68K/CPU-30BE/16", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW )
//COMP( 1996, sys68k_cpu30lite4, sys68k_cpu30, 0, cpu30lite4, cpu30, sys68k_cpu30_device_base, init_cpu30lite4, "Force Computers GmbH", "SYS68K/CPU-30Lite/4", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW )
//COMP( 1996, sys68k_cpu30lite8, sys68k_cpu30, 0, cpu30lite8, cpu30, sys68k_cpu30_device_base, init_cpu30lite8, "Force Computers GmbH", "SYS68K/CPU-30Lite/8", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW )
//COMP( 199?, sys68k_cpu33, sys68k_cpu30, 0, cpu33, cpu30, sys68k_cpu30_device_base, init_cpu33, "Force Computers GmbH", "SYS68K/CPU-33", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW )
/* Below are not fully configured variants defaulting to generic cpu30 */
/* The following boards were manufactured for Ericsson to be used in their fixed network switches. They support hot swap and the Ericsson APNbus */
/* SYS68K/CPU-30SEN-R/32 assumed as generic until spec is found. 25 MHz 68030 based CPU board with DMAC, 32 MByte Shared RAM capacity and VMEPROM.
4 MByte System Flash memory, SCSI via on-board EAGLE Controller FC68165 with DMA, 2 serial I/O ports, APNbus interface, VMEPROM firmware */
COMP( 1997, fccpu30senr, 0, 0, cpu30, cpu30, cpu30_state, empty_init, "Force Computers GmbH", "SYS68K/CPU-30SEN-R", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW )
//COMP( 1997, sys68k_cpu30senr, 0, 0, cpu30, cpu30, sys68k_cpu30_device_base, empty_init, "Force Computers GmbH", "SYS68K/CPU-30SEN-R", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW )
/* SYS68K/CPU-30SEN-R-501/4 assumed as generic until spec is found. 25 MHz 68030 based CPU board with DMAC, 4 MByte Shared RAM capacity and VMEPROM.
48V DC/DC onboard, metric backplane connectors, BYB501 PCB formfactor (TVJ807). 4 MByte System Flash memory, SCSI via onboard EAGLEController
FC68165 with DMA, 2 serial I/O ports, APNbus interface, VMEPROM firmware*/
COMP( 1997, fccpu30senr501, 0, 0, cpu30, cpu30, cpu30_state, empty_init, "Force Computers GmbH", "SYS68K/CPU-30SEN-R-501", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW )
//COMP( 1997, sys68k_cpu30senr501, 0, 0, cpu30, cpu30, sys68k_cpu30_device_base, empty_init, "Force Computers GmbH", "SYS68K/CPU-30SEN-R-501", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW )
/*CPU-33XB MC68030 25MHz CPU, 68882 FPC, 1MB, 2 SERIAL, RS-232, VME BOARD*/
//COMP( 1990, cpu33xb, 0, 0, cpu30, cpu30, cpu30_state, 0, "Force Computers GmbH", "SYS68K/CPU-33XB", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW )
//COMP( 1990, cpu33xb, 0, 0, cpu30, cpu30, sys68k_cpu30_device_base, 0, "Force Computers GmbH", "SYS68K/CPU-33XB", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW )
/*CPU-33B/4 MC68030 25MHz CPU, 68882 FPC, 1MB, 2 SERIAL, RS-232, VME BOARD*/
//COMP( 1990, cpu30b4, 0, 0, cpu30, cpu30, cpu30_state, 0, "Force Computers GmbH", "SYS68K/CPU-33B/4", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW )
//COMP( 1990, cpu30b4, 0, 0, cpu30, cpu30, sys68k_cpu30_device_base, 0, "Force Computers GmbH", "SYS68K/CPU-33B/4", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW )

157
src/devices/bus/vme/sys68k_cpu30.h Normal file
View File

@ -0,0 +1,157 @@
// license:BSD-3-Clause
// copyright-holders:Joakim Larsson Edstrom
#ifndef MAME_BUS_VME_SYS68K_CPU30_H
#define MAME_BUS_VME_SYS68K_CPU30_H
#pragma once
#include "bus/vme/vme.h"
#include "cpu/m68000/m68030.h"
#include "machine/ram.h" // For variants that only differs in amount of RAM
#include "machine/scnxx562.h"
#include "machine/68230pit.h"
#include "machine/msm6242.h"
#include "machine/fga002.h"
class sys68k_cpu30_device_base
: public device_t
, public device_vme_card_interface
{
public:
sys68k_cpu30_device_base(machine_config const &mconfig, device_type type, char const *tag, device_t *owner, u32 clock, uint8_t board_id);
protected:
virtual ioport_constructor device_input_ports() const override;
virtual void device_start() override;
virtual void device_reset() override;
void sys68k_cpu30(machine_config &config, XTAL clock, char const *const ram_default, char const *const ram_options);
void fdc_w(offs_t offset, uint8_t data);
uint8_t fdc_r(offs_t offset);
void scsi_w(offs_t offset, uint8_t data);
uint8_t scsi_r(offs_t offset);
uint8_t slot1_status_r();
/* Interrupt support */
void cpu_space_map(address_map &map);
void fga_irq_callback(int state);
uint8_t fga_irq_state = 0;
// int fga_irq_vector = 0;
int fga_irq_level = 0;
/* Rotary switch PIT input */
uint8_t rotary_rd();
uint8_t flop_dmac_r();
void flop_dmac_w(uint8_t data);
uint8_t pit1c_r();
void pit1c_w(uint8_t data);
uint8_t pit2a_r();
void pit2a_w(uint8_t data);
uint8_t board_mem_id_rd();
uint8_t pit2c_r();
void pit2c_w(uint8_t data);
/* VME bus accesses */
//uint16_t vme_a24_r();
//void vme_a24_w(uint16_t data);
//uint16_t vme_a16_r();
//void vme_a16_w(uint16_t data);
void cpu30_mem(address_map &map);
required_device<m68000_musashi_device> m_maincpu;
required_device<ram_device> m_ram;
required_device<duscc68562_device> m_dusccterm;
required_device<pit68230_device> m_pit1;
required_device<pit68230_device> m_pit2;
required_device<fga002_device> m_fga002;
required_device<rtc72423_device> m_rtc;
required_memory_region m_boot;
memory_passthrough_handler m_boot_mph;
// Helper functions
void update_irq_to_maincpu();
uint8_t const m_board_id;
};
class vme_sys68k_cpu30_card_device : public sys68k_cpu30_device_base
{
public:
vme_sys68k_cpu30_card_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock);
protected:
virtual const tiny_rom_entry *device_rom_region() const override;
virtual void device_add_mconfig(machine_config &config) override;
};
class vme_sys68k_cpu30x_card_device : public sys68k_cpu30_device_base
{
public:
vme_sys68k_cpu30x_card_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock);
protected:
virtual const tiny_rom_entry *device_rom_region() const override;
virtual void device_add_mconfig(machine_config &config) override;
};
class vme_sys68k_cpu30xa_card_device : public sys68k_cpu30_device_base
{
public:
vme_sys68k_cpu30xa_card_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock);
protected:
virtual const tiny_rom_entry *device_rom_region() const override;
virtual void device_add_mconfig(machine_config &config) override;
};
class vme_sys68k_cpu30za_card_device : public sys68k_cpu30_device_base
{
public:
vme_sys68k_cpu30za_card_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock);
protected:
virtual const tiny_rom_entry *device_rom_region() const override;
virtual void device_add_mconfig(machine_config &config) override;
};
class vme_sys68k_cpu30be_card_device : public sys68k_cpu30_device_base
{
public:
vme_sys68k_cpu30be_card_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock);
protected:
virtual const tiny_rom_entry *device_rom_region() const override;
virtual void device_add_mconfig(machine_config &config) override;
};
class vme_sys68k_cpu30lite_card_device : public sys68k_cpu30_device_base
{
public:
vme_sys68k_cpu30lite_card_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock);
protected:
virtual const tiny_rom_entry *device_rom_region() const override;
virtual void device_add_mconfig(machine_config &config) override;
};
class vme_sys68k_cpu33_card_device : public sys68k_cpu30_device_base
{
public:
vme_sys68k_cpu33_card_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock);
protected:
virtual const tiny_rom_entry *device_rom_region() const override;
virtual void device_add_mconfig(machine_config &config) override;
};
DECLARE_DEVICE_TYPE(VME_SYS68K_CPU30, vme_sys68k_cpu30_card_device)
DECLARE_DEVICE_TYPE(VME_SYS68K_CPU30X, vme_sys68k_cpu30x_card_device)
DECLARE_DEVICE_TYPE(VME_SYS68K_CPU30XA, vme_sys68k_cpu30xa_card_device)
DECLARE_DEVICE_TYPE(VME_SYS68K_CPU30ZA, vme_sys68k_cpu30za_card_device)
DECLARE_DEVICE_TYPE(VME_SYS68K_CPU30BE, vme_sys68k_cpu30be_card_device)
DECLARE_DEVICE_TYPE(VME_SYS68K_CPU30LITE, vme_sys68k_cpu30lite_card_device)
DECLARE_DEVICE_TYPE(VME_SYS68K_CPU33, vme_sys68k_cpu33_card_device)
#endif // MAME_BUS_VME_SYS68K_CPU30_H

113
src/devices/bus/vme/vme_fcscsi.cpp → src/devices/bus/vme/sys68k_iscsi.cpp
View File

@ -143,7 +143,7 @@
*
****************************************************************************/
#include "emu.h"
#include "vme_fcscsi.h"
#include "sys68k_iscsi.h"
#include "cpu/m68000/m68010.h"
#include "machine/68230pit.h"
@ -169,24 +169,23 @@
// GLOBAL VARIABLES
//**************************************************************************
DEFINE_DEVICE_TYPE(VME_FCSCSI1, vme_fcscsi1_card_device, "fcscsi1", "Force Computer SYS68K/ISCSI-1 Intelligent Mass Storage Controller Board")
DEFINE_DEVICE_TYPE(VME_SYS68K_ISCSI1, vme_sys68k_iscsi1_card_device, "sys68k_iscsi1", "Force Computers SYS68K/ISCSI-1")
#define CPU_CRYSTAL 20_MHz_XTAL /* Jauch */
#define PIT_CRYSTAL 16_MHz_XTAL /* Jauch */
void vme_fcscsi1_card_device::fcscsi1_mem(address_map &map)
void vme_sys68k_iscsi1_card_device::fcscsi1_mem(address_map &map)
{
map.unmap_value_high();
map(0x000000, 0x000007).rom().r(FUNC(vme_fcscsi1_card_device::bootvect_r)); /* Vectors mapped from System EPROM */
map(0x000008, 0x001fff).ram(); /* SRAM */
map(0x002000, 0x01ffff).ram(); /* Dual Ported RAM */
map(0xe00000, 0xe7ffff).rom(); /* System EPROM Area 32Kb DEBUGGER supplied */
map(0x000000, 0x01ffff).ram(); /* SRAM */
map(0xe00000, 0xe1ffff).rom().region("eprom", 0); /* System EPROM Area 32Kb DEBUGGER supplied */
map(0xd00000, 0xd0003f).rw("pit", FUNC(pit68230_device::read), FUNC(pit68230_device::write)).umask16(0x00ff);
// map(0xc40000, 0xc4001f).rw("scsi", FUNC(ncr5386_device::read), FUNC(ncr5386_device::write)).umask16(0x00ff); /* SCSI Controller interface - device support not yet available*/
map(0xc40000, 0xc4001f).rw(FUNC(vme_fcscsi1_card_device::scsi_r), FUNC(vme_fcscsi1_card_device::scsi_w)).umask16(0x00ff);
map(0xc40000, 0xc4001f).rw(FUNC(vme_sys68k_iscsi1_card_device::scsi_r), FUNC(vme_sys68k_iscsi1_card_device::scsi_w)).umask16(0x00ff);
map(0xc80000, 0xc800ff).rw("mc68450", FUNC(hd63450_device::read), FUNC(hd63450_device::write)); /* DMA Controller interface */
map(0xcc0000, 0xcc0007).rw("fdc", FUNC(wd1772_device::read), FUNC(wd1772_device::write)).umask16(0x00ff); /* Floppy Controller interface */
map(0xcc0009, 0xcc0009).rw(FUNC(vme_fcscsi1_card_device::tcr_r), FUNC(vme_fcscsi1_card_device::tcr_w)); /* The Control Register, SCSI ID and FD drive select bits */
map(0xcc0009, 0xcc0009).rw(FUNC(vme_sys68k_iscsi1_card_device::tcr_r), FUNC(vme_sys68k_iscsi1_card_device::tcr_w)); /* The Control Register, SCSI ID and FD drive select bits */
}
/*
@ -212,7 +211,7 @@ elapses and/or if the VMEbus interrupt trigger call occurs.
/* TODO: Add configurable B41 jumper */
#define B41 0
void vme_fcscsi1_card_device::update_irq_to_maincpu() {
void vme_sys68k_iscsi1_card_device::update_irq_to_maincpu() {
if (fdc_irq_state) {
m_maincpu->set_input_line(M68K_IRQ_3, ASSERT_LINE);
m_maincpu->set_input_line(M68K_IRQ_2, CLEAR_LINE);
@ -228,10 +227,10 @@ void vme_fcscsi1_card_device::update_irq_to_maincpu() {
}
}
void vme_fcscsi1_card_device::cpu_space_map(address_map &map)
void vme_sys68k_iscsi1_card_device::cpu_space_map(address_map &map)
{
map(0xfffff0, 0xffffff).m(m_maincpu, FUNC(m68000_base_device::autovectors_map));
map(0xfffff5, 0xfffff5).r(FUNC(vme_fcscsi1_card_device::dma_iack));
map(0xfffff5, 0xfffff5).r(FUNC(vme_sys68k_iscsi1_card_device::dma_iack));
}
static void fcscsi_floppies(device_slot_interface &device)
@ -241,32 +240,32 @@ static void fcscsi_floppies(device_slot_interface &device)
/* ROM definitions */
ROM_START (fcscsi1)
ROM_REGION (0x1000000, "maincpu", 0)
ROM_START (sys68k_iscsi1)
ROM_REGION16_BE (0x20000, "eprom", 0)
/* Besta ROM:s - apparantly patched Force ROM:s */
ROM_SYSTEM_BIOS(0, "besta88", "Besta 88")
ROMX_LOAD ("besta88_scsi_lower.rom", 0xe00001, 0x4000, CRC (fb3ab364) SHA1 (d79112100f1c4beaf358e006efd4dde5e300b0ba), ROM_SKIP(1) | ROM_BIOS(0))
ROMX_LOAD ("besta88_scsi_upper.rom", 0xe00000, 0x4000, CRC (41f9cdf4) SHA1 (66b998bbf9459f0a613718260e05e97749532073), ROM_SKIP(1) | ROM_BIOS(0))
ROMX_LOAD ("besta88_scsi_lower.rom", 0x00001, 0x4000, CRC (fb3ab364) SHA1 (d79112100f1c4beaf358e006efd4dde5e300b0ba), ROM_SKIP(1) | ROM_BIOS(0))
ROMX_LOAD ("besta88_scsi_upper.rom", 0x00000, 0x4000, CRC (41f9cdf4) SHA1 (66b998bbf9459f0a613718260e05e97749532073), ROM_SKIP(1) | ROM_BIOS(0))
/* Force ROM:s */
ROM_SYSTEM_BIOS(1, "iscsi-1_v3.7", "Force Computer SYS68K/ISCSI-1 firmware v3.7")
ROMX_LOAD ("iscsi-1_v3.7_l.bin", 0xe00001, 0x4000, CRC (83d95ab7) SHA1 (bf249910bcb6cb0b04dda2a95a38a0f90b553352), ROM_SKIP(1) | ROM_BIOS(1))
ROMX_LOAD ("iscsi-1_v3.7_u.bin", 0xe00000, 0x4000, CRC (58815831) SHA1 (074085ef96e1fe2a551938bdeee6a9cab40ff09c), ROM_SKIP(1) | ROM_BIOS(1))
ROMX_LOAD ("iscsi-1_v3.7_l.bin", 0x00001, 0x4000, CRC (83d95ab7) SHA1 (bf249910bcb6cb0b04dda2a95a38a0f90b553352), ROM_SKIP(1) | ROM_BIOS(1))
ROMX_LOAD ("iscsi-1_v3.7_u.bin", 0x00000, 0x4000, CRC (58815831) SHA1 (074085ef96e1fe2a551938bdeee6a9cab40ff09c), ROM_SKIP(1) | ROM_BIOS(1))
ROM_END
void vme_fcscsi1_card_device::device_add_mconfig(machine_config &config)
void vme_sys68k_iscsi1_card_device::device_add_mconfig(machine_config &config)
{
/* basic machine hardware */
M68010(config, m_maincpu, CPU_CRYSTAL / 2); /* 7474 based frequency divide by 2 */
m_maincpu->set_addrmap(AS_PROGRAM, &vme_fcscsi1_card_device::fcscsi1_mem);
m_maincpu->set_addrmap(m68000_base_device::AS_CPU_SPACE, &vme_fcscsi1_card_device::cpu_space_map);
m_maincpu->set_addrmap(AS_PROGRAM, &vme_sys68k_iscsi1_card_device::fcscsi1_mem);
m_maincpu->set_addrmap(m68000_base_device::AS_CPU_SPACE, &vme_sys68k_iscsi1_card_device::cpu_space_map);
/* FDC */
WD1772(config, m_fdc, PIT_CRYSTAL / 2);
m_fdc->intrq_wr_callback().set(FUNC(vme_fcscsi1_card_device::fdc_irq));
m_fdc->intrq_wr_callback().set(FUNC(vme_sys68k_iscsi1_card_device::fdc_irq));
m_fdc->drq_wr_callback().set("mc68450", FUNC(hd63450_device::drq1_w));
FLOPPY_CONNECTOR(config, "fdc:0", fcscsi_floppies, "525qd", floppy_image_device::default_pc_floppy_formats);
FLOPPY_CONNECTOR(config, "fdc:1", fcscsi_floppies, "525qd", floppy_image_device::default_pc_floppy_formats);
@ -275,53 +274,52 @@ void vme_fcscsi1_card_device::device_add_mconfig(machine_config &config)
/* PIT Parallel Interface and Timer device */
PIT68230(config, m_pit, PIT_CRYSTAL / 2); /* 7474 based frequency divide by 2 */
m_pit->pb_out_callback().set(FUNC(vme_fcscsi1_card_device::led_w));
m_pit->pb_out_callback().set(FUNC(vme_sys68k_iscsi1_card_device::led_w));
/* DMAC it is really a M68450 but the HD63850 is upwards compatible */
HD63450(config, m_dmac, CPU_CRYSTAL / 2, "maincpu"); // MC68450 compatible
m_dmac->set_clocks(attotime::from_usec(32), attotime::from_nsec(450), attotime::from_usec(4), attotime::from_hz(15625/2));
m_dmac->set_burst_clocks(attotime::from_usec(32), attotime::from_nsec(450), attotime::from_nsec(50), attotime::from_nsec(50));
m_dmac->irq_callback().set(FUNC(vme_fcscsi1_card_device::dma_irq));
//m_dmac->dma_read<0>().set(FUNC(vme_fcscsi1_card_device::scsi_read_byte)); // ch 0 = SCSI
//m_dmac->dma_write<0>().set(FUNC(vme_fcscsi1_card_device::scsi_write_byte));
m_dmac->dma_read<1>().set(FUNC(vme_fcscsi1_card_device::fdc_read_byte)); // ch 1 = fdc
m_dmac->dma_write<1>().set(FUNC(vme_fcscsi1_card_device::fdc_write_byte));
m_dmac->irq_callback().set(FUNC(vme_sys68k_iscsi1_card_device::dma_irq));
//m_dmac->dma_read<0>().set(FUNC(vme_sys68k_iscsi1_card_device::scsi_read_byte)); // ch 0 = SCSI
//m_dmac->dma_write<0>().set(FUNC(vme_sys68k_iscsi1_card_device::scsi_write_byte));
m_dmac->dma_read<1>().set(FUNC(vme_sys68k_iscsi1_card_device::fdc_read_byte)); // ch 1 = fdc
m_dmac->dma_write<1>().set(FUNC(vme_sys68k_iscsi1_card_device::fdc_write_byte));
}
const tiny_rom_entry *vme_fcscsi1_card_device::device_rom_region() const
const tiny_rom_entry *vme_sys68k_iscsi1_card_device::device_rom_region() const
{
LOG("%s\n", FUNCNAME);
return ROM_NAME( fcscsi1 );
return ROM_NAME(sys68k_iscsi1);
}
//**************************************************************************
// LIVE DEVICE
//**************************************************************************
vme_fcscsi1_card_device::vme_fcscsi1_card_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
vme_sys68k_iscsi1_card_device::vme_sys68k_iscsi1_card_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
: device_t(mconfig, type, tag, owner, clock)
, device_vme_card_interface(mconfig, *this)
, m_maincpu(*this, "maincpu")
, m_fdc(*this, "fdc")
, m_pit(*this, "pit")
, m_dmac(*this, "mc68450")
, m_eprom(*this, "eprom")
, m_ram(*this, "ram")
, m_tcr(0)
{
LOG("%s\n", FUNCNAME);
}
vme_fcscsi1_card_device::vme_fcscsi1_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: vme_fcscsi1_card_device(mconfig, VME_FCSCSI1, tag, owner, clock)
vme_sys68k_iscsi1_card_device::vme_sys68k_iscsi1_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: vme_sys68k_iscsi1_card_device(mconfig, VME_SYS68K_ISCSI1, tag, owner, clock)
{
}
/* Start it up */
void vme_fcscsi1_card_device::device_start()
void vme_sys68k_iscsi1_card_device::device_start()
{
LOG("%s\n", FUNCNAME);
/* Setup pointer to bootvector in ROM for bootvector handler bootvect_r */
m_sysrom = (uint16_t*)(memregion ("maincpu")->base () + 0xe00000);
#if 0 // TODO: Setup VME access handlers for shared memory area
uint32_t base = 0x00A00000;
m_vme->install_device(base + 0, base + 1, // Channel B - Data
@ -332,14 +330,21 @@ void vme_fcscsi1_card_device::device_start()
}
void vme_fcscsi1_card_device::device_reset()
void vme_sys68k_iscsi1_card_device::device_reset()
{
LOG("%s\n", FUNCNAME);
}
/* Boot vector handler, the PCB hardwires the first 8 bytes from 0x80000 to 0x0 */
uint16_t vme_fcscsi1_card_device::bootvect_r(offs_t offset){
return m_sysrom [offset];
m_maincpu->space(AS_PROGRAM).install_rom(0, m_eprom->bytes() - 1, m_eprom->base());
m_boot_mph = m_maincpu->space(AS_PROGRAM).install_read_tap(0x000006, 0x000007, "boot",
[this](offs_t offset, uint16_t &data, uint16_t mem_mask)
{
if (!machine().side_effects_disabled() && ACCESSING_BITS_0_7)
{
m_maincpu->space(AS_PROGRAM).install_ram(0, m_ram.bytes() - 1, m_ram.target());
m_boot_mph.remove();
}
});
}
/* The Control Register - discretely implemented on the PCB
@ -354,12 +359,12 @@ Bit #: 7 6 5 4 3 2 1 0
\ ISCSI-l 1.D. Bit #2
*/
uint8_t vme_fcscsi1_card_device::tcr_r(){
uint8_t vme_sys68k_iscsi1_card_device::tcr_r(){
LOG("%s\n", FUNCNAME);
return (uint8_t) m_tcr;
}
void vme_fcscsi1_card_device::tcr_w(uint8_t data){
void vme_sys68k_iscsi1_card_device::tcr_w(uint8_t data){
floppy_image_device *floppy0 = m_fdc->subdevice<floppy_connector>("0")->get_device();
floppy_image_device *floppy1 = m_fdc->subdevice<floppy_connector>("1")->get_device();
floppy_image_device *floppy2 = m_fdc->subdevice<floppy_connector>("2")->get_device();
@ -390,7 +395,7 @@ void vme_fcscsi1_card_device::tcr_w(uint8_t data){
return;
}
void vme_fcscsi1_card_device::led_w(uint8_t data) {
void vme_sys68k_iscsi1_card_device::led_w(uint8_t data) {
LOG("%s [%02x]\n", FUNCNAME, data);
m_fdc->dden_w(BIT(data, 7));
@ -398,7 +403,7 @@ void vme_fcscsi1_card_device::led_w(uint8_t data) {
return;
}
void vme_fcscsi1_card_device::dma_irq(int state)
void vme_sys68k_iscsi1_card_device::dma_irq(int state)
{
if(state != CLEAR_LINE)
{
@ -413,7 +418,7 @@ void vme_fcscsi1_card_device::dma_irq(int state)
update_irq_to_maincpu();
}
uint8_t vme_fcscsi1_card_device::dma_iack()
uint8_t vme_sys68k_iscsi1_card_device::dma_iack()
{
if (B41)
return m_dmac->iack();
@ -421,7 +426,7 @@ uint8_t vme_fcscsi1_card_device::dma_iack()
return m68000_base_device::autovector(2);
}
void vme_fcscsi1_card_device::fdc_irq(int state)
void vme_sys68k_iscsi1_card_device::fdc_irq(int state)
{
if (state != 0)
{
@ -434,17 +439,17 @@ void vme_fcscsi1_card_device::fdc_irq(int state)
update_irq_to_maincpu();
}
uint8_t vme_fcscsi1_card_device::fdc_read_byte()
uint8_t vme_sys68k_iscsi1_card_device::fdc_read_byte()
{
return m_fdc->data_r();
}
void vme_fcscsi1_card_device::fdc_write_byte(uint8_t data)
void vme_sys68k_iscsi1_card_device::fdc_write_byte(uint8_t data)
{
m_fdc->data_w(data & 0xff);
}
uint8_t vme_fcscsi1_card_device::scsi_r(offs_t offset)
uint8_t vme_sys68k_iscsi1_card_device::scsi_r(offs_t offset)
{
uint8_t data = 0;
@ -457,12 +462,12 @@ uint8_t vme_fcscsi1_card_device::scsi_r(offs_t offset)
return data;
}
void vme_fcscsi1_card_device::scsi_w(offs_t offset, uint8_t data)
void vme_sys68k_iscsi1_card_device::scsi_w(offs_t offset, uint8_t data)
{
LOG("scsi W %02x <- %02x\n", offset, data);
}
uint8_t vme_fcscsi1_card_device::not_implemented_r(){
uint8_t vme_sys68k_iscsi1_card_device::not_implemented_r(){
static int been_here = 0;
if (!been_here++){
logerror(TODO);
@ -471,7 +476,7 @@ uint8_t vme_fcscsi1_card_device::not_implemented_r(){
return (uint8_t) 0;
}
void vme_fcscsi1_card_device::not_implemented_w(uint8_t data){
void vme_sys68k_iscsi1_card_device::not_implemented_w(uint8_t data){
static int been_here = 0;
if (!been_here++){
logerror(TODO);

22
src/devices/bus/vme/vme_fcscsi.h → src/devices/bus/vme/sys68k_iscsi.h
View File

@ -1,7 +1,7 @@
// license:BSD-3-Clause
// copyright-holders:Joakim Larsson Edstrom
#ifndef MAME_BUS_VME_VME_FCSCSI_H
#define MAME_BUS_VME_VME_FCSCSI_H
#ifndef MAME_BUS_VME_SYS68K_ISCSI_H
#define MAME_BUS_VME_SYS68K_ISCSI_H
#pragma once
@ -11,15 +11,15 @@
#include "machine/hd63450.h" // compatible with MC68450
#include "bus/vme/vme.h"
DECLARE_DEVICE_TYPE(VME_FCSCSI1, vme_fcscsi1_card_device)
DECLARE_DEVICE_TYPE(VME_SYS68K_ISCSI1, vme_sys68k_iscsi1_card_device)
class vme_fcscsi1_card_device : public device_t, public device_vme_card_interface
class vme_sys68k_iscsi1_card_device : public device_t, public device_vme_card_interface
{
public:
vme_fcscsi1_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
vme_sys68k_iscsi1_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:
vme_fcscsi1_card_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
vme_sys68k_iscsi1_card_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
virtual void device_start() override;
virtual void device_reset() override;
@ -43,7 +43,6 @@ private:
uint8_t fdc_read_byte();
void fdc_write_byte(uint8_t data);
uint16_t bootvect_r(offs_t offset);
uint8_t tcr_r();
void tcr_w(uint8_t data);
void led_w(uint8_t data);
@ -63,10 +62,11 @@ private:
required_device<pit68230_device> m_pit;
required_device<hd63450_device> m_dmac;
uint8_t m_tcr;
required_memory_region m_eprom;
required_shared_ptr<uint16_t> m_ram;
memory_passthrough_handler m_boot_mph;
// Pointer to System ROMs needed by bootvect_r
uint16_t *m_sysrom;
uint8_t m_tcr;
};
#endif // MAME_BUS_VME_VME_FCSCSI_H
#endif // MAME_BUS_VME_SYS68K_ISCSI_H

69
src/devices/bus/vme/vme_fcisio.cpp → src/devices/bus/vme/sys68k_isio.cpp
View File

@ -125,7 +125,7 @@
*
****************************************************************************/
#include "emu.h"
#include "vme_fcisio.h"
#include "sys68k_isio.h"
#include "cpu/m68000/m68010.h"
#include "machine/scnxx562.h"
@ -150,28 +150,27 @@
// GLOBAL VARIABLES
//**************************************************************************
DEFINE_DEVICE_TYPE(VME_FCISIO1, vme_fcisio1_card_device, "fcisio1", "Force Computer SYS68K/ISIO-1/2 Intelligent Serial I/O Board")
DEFINE_DEVICE_TYPE(VME_SYS68K_ISIO1, vme_sys68k_isio1_card_device, "sys68k_isio1", "Force Computers SYS68K/ISIO-1")
#define CPU_CLOCK XTAL(20'000'000) /* HCJ */
#define DUSCC_CLOCK XTAL(14'745'600) /* HCJ */
void vme_fcisio1_card_device::fcisio1_mem(address_map &map)
void vme_sys68k_isio1_card_device::fcisio1_mem(address_map &map)
{
map.unmap_value_high();
map(0x000000, 0x01ffff).ram(); /* SRAM */
map(0x000000, 0x000007).rom().r(FUNC(vme_fcisio1_card_device::bootvect_r)); /* Vectors mapped from System EPROM */
map(0x000000, 0x01ffff).ram().share("ram"); /* SRAM */
map(0xe00000, 0xe001ff).rw("duscc0", FUNC(duscc68562_device::read), FUNC(duscc68562_device::write)).umask16(0x00ff);
map(0xe20000, 0xe201ff).rw("duscc1", FUNC(duscc68562_device::read), FUNC(duscc68562_device::write)).umask16(0x00ff);
map(0xe40000, 0xe401ff).rw("duscc2", FUNC(duscc68562_device::read), FUNC(duscc68562_device::write)).umask16(0x00ff);
map(0xe60000, 0xe601ff).rw("duscc3", FUNC(duscc68562_device::read), FUNC(duscc68562_device::write)).umask16(0x00ff);
map(0xe80000, 0xe80dff).rw("pit", FUNC(pit68230_device::read), FUNC(pit68230_device::write)).umask16(0x00ff);
map(0xf00000, 0xf7ffff).rom(); /* System EPROM Area 32Kb DEBUGGER supplied */
// map(0xc40000, 0xc800ff).rw(FUNC(vme_fcisio1_card_device::not_implemented_r), FUNC(vme_fcisio1_card_device::not_implemented_w)); /* Dummy mapping af address area to display message */
map(0xf00000, 0xf1ffff).rom().region("eprom", 0); /* System EPROM Area 32Kb DEBUGGER supplied */
// map(0xc40000, 0xc800ff).rw(FUNC(vme_sys68k_isio1_card_device::not_implemented_r), FUNC(vme_sys68k_isio1_card_device::not_implemented_w)); /* Dummy mapping af address area to display message */
}
/* ROM definitions */
ROM_START (fcisio1)
ROM_REGION (0x1000000, "maincpu", 0)
ROM_START (sys68k_isio1)
ROM_REGION16_BE (0x20000, "eprom", 0)
/* ISIO ROM:s v2.1 information
* PIT setup sequence
@ -265,15 +264,15 @@ ROM_START (fcisio1)
* 1e 1a -> DUSCC2 REG_IVR
* 1e 19 -> DUSCC3 REG_IVR
*/
ROM_LOAD16_BYTE ("isio-1_v2.1_l.bin", 0xf00001, 0x4000, CRC (0d47d80f) SHA1 (541b55966f464c1cf686e36998650720950a2242))
ROM_LOAD16_BYTE ("isio-1_v2.1_u.bin", 0xf00000, 0x4000, CRC (67986768) SHA1 (215f7ff90d9dbe2bea54510e3722fb33d4e54193))
ROM_LOAD16_BYTE ("isio-1_v2.1_l.bin", 0x0001, 0x4000, CRC (0d47d80f) SHA1 (541b55966f464c1cf686e36998650720950a2242))
ROM_LOAD16_BYTE ("isio-1_v2.1_u.bin", 0x0000, 0x4000, CRC (67986768) SHA1 (215f7ff90d9dbe2bea54510e3722fb33d4e54193))
ROM_END
void vme_fcisio1_card_device::device_add_mconfig(machine_config &config)
void vme_sys68k_isio1_card_device::device_add_mconfig(machine_config &config)
{
/* basic machine hardware */
M68010(config, m_maincpu, CPU_CLOCK / 2);
m_maincpu->set_addrmap(AS_PROGRAM, &vme_fcisio1_card_device::fcisio1_mem);
m_maincpu->set_addrmap(AS_PROGRAM, &vme_sys68k_isio1_card_device::fcisio1_mem);
/* DUSCC channels */
#define RS232P1_TAG "rs232p1"
@ -362,21 +361,21 @@ void vme_fcisio1_card_device::device_add_mconfig(machine_config &config)
rs232p8.cts_handler().set(m_duscc3, FUNC(duscc68562_device::ctsb_w));
PIT68230(config, m_pit, XTAL(20'000'000) / 2);
m_pit->pb_in_callback().set(FUNC(vme_fcisio1_card_device::config_rd));
m_pit->pb_in_callback().set(FUNC(vme_sys68k_isio1_card_device::config_rd));
MC68153(config, m_bim, XTAL(20'000'000) / 2);
}
const tiny_rom_entry *vme_fcisio1_card_device::device_rom_region() const
const tiny_rom_entry *vme_sys68k_isio1_card_device::device_rom_region() const
{
LOG("%s\n", FUNCNAME);
return ROM_NAME( fcisio1 );
return ROM_NAME(sys68k_isio1);
}
//**************************************************************************
// LIVE DEVICE
//**************************************************************************
vme_fcisio1_card_device::vme_fcisio1_card_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
vme_sys68k_isio1_card_device::vme_sys68k_isio1_card_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
: device_t(mconfig, type, tag, owner, clock)
, device_vme_card_interface(mconfig, *this)
, m_maincpu (*this, "maincpu")
@ -386,23 +385,22 @@ vme_fcisio1_card_device::vme_fcisio1_card_device(const machine_config &mconfig,
, m_duscc3(*this, "duscc3")
, m_pit (*this, "pit")
, m_bim (*this, "bim")
, m_eprom (*this, "eprom")
, m_ram (*this, "ram")
{
LOG("%s\n", FUNCNAME);
}
vme_fcisio1_card_device::vme_fcisio1_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: vme_fcisio1_card_device(mconfig, VME_FCISIO1, tag, owner, clock)
vme_sys68k_isio1_card_device::vme_sys68k_isio1_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: vme_sys68k_isio1_card_device(mconfig, VME_SYS68K_ISIO1, tag, owner, clock)
{
}
/* Start it up */
void vme_fcisio1_card_device::device_start()
void vme_sys68k_isio1_card_device::device_start()
{
LOG("%s\n", FUNCNAME);
/* Setup pointer to bootvector in ROM for bootvector handler bootvect_r */
m_sysrom = (uint16_t*)(memregion ("maincpu")->base () + 0xf00000);
#if 0 // TODO: Setup VME access handlers for shared memory area
uint32_t base = 0xFFFF5000;
m_vme->install_device(base + 0, base + 1, // Channel B - Data
@ -413,17 +411,24 @@ void vme_fcisio1_card_device::device_start()
}
void vme_fcisio1_card_device::device_reset()
void vme_sys68k_isio1_card_device::device_reset()
{
LOG("%s\n", FUNCNAME);
m_maincpu->space(AS_PROGRAM).install_rom(0, m_eprom->bytes() - 1, m_eprom->base());
m_boot_mph = m_maincpu->space(AS_PROGRAM).install_read_tap(0x000006, 0x000007, "boot",
[this](offs_t offset, uint16_t &data, uint16_t mem_mask)
{
if (!machine().side_effects_disabled() && ACCESSING_BITS_0_7)
{
m_maincpu->space(AS_PROGRAM).install_ram(0, m_ram.bytes() - 1, m_ram.target());
m_boot_mph.remove();
}
});
}
/* Boot vector handler, the PCB hardwires the first 8 bytes from 0x80000 to 0x0 */
uint16_t vme_fcisio1_card_device::bootvect_r(offs_t offset){
return m_sysrom [offset];
}
uint8_t vme_fcisio1_card_device::not_implemented_r(){
uint8_t vme_sys68k_isio1_card_device::not_implemented_r(){
static int been_here = 0;
if (!been_here++){
logerror(TODO);
@ -432,7 +437,7 @@ uint8_t vme_fcisio1_card_device::not_implemented_r(){
return (uint8_t) 0;
}
void vme_fcisio1_card_device::not_implemented_w(uint8_t data){
void vme_sys68k_isio1_card_device::not_implemented_w(uint8_t data){
static int been_here = 0;
if (!been_here++){
logerror(TODO);
@ -442,7 +447,7 @@ void vme_fcisio1_card_device::not_implemented_w(uint8_t data){
}
// TODO: Get a manual to understand the config options for real
uint8_t vme_fcisio1_card_device::config_rd(){
uint8_t vme_sys68k_isio1_card_device::config_rd(){
uint8_t ret = 0;
LOG("%s\n", FUNCNAME);

21
src/devices/bus/vme/vme_fcisio.h → src/devices/bus/vme/sys68k_isio.h
View File

@ -1,7 +1,7 @@
// license:BSD-3-Clause
// copyright-holders:Joakim Larsson Edstrom
#ifndef MAME_BUS_VME_VME_FCISIO_H
#define MAME_BUS_VME_VME_FCISIO_H
#ifndef MAME_BUS_VME_SYS68K_ISIO_H
#define MAME_BUS_VME_SYS68K_ISIO_H
#pragma once
@ -10,15 +10,15 @@
#include "machine/68153bim.h"
#include "bus/vme/vme.h"
DECLARE_DEVICE_TYPE(VME_FCISIO1, vme_fcisio1_card_device)
DECLARE_DEVICE_TYPE(VME_SYS68K_ISIO1, vme_sys68k_isio1_card_device)
class vme_fcisio1_card_device : public device_t, public device_vme_card_interface
class vme_sys68k_isio1_card_device : public device_t, public device_vme_card_interface
{
public:
vme_fcisio1_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
vme_sys68k_isio1_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:
vme_fcisio1_card_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
vme_sys68k_isio1_card_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
virtual void device_start() override;
virtual void device_reset() override;
@ -30,8 +30,6 @@ protected:
private:
uint8_t config_rd();
uint16_t bootvect_r(offs_t offset);
/* Dummy driver routines */
uint8_t not_implemented_r();
void not_implemented_w(uint8_t data);
@ -47,8 +45,9 @@ private:
required_device<pit68230_device> m_pit;
required_device<bim68153_device> m_bim;
// Pointer to System ROMs needed by bootvect_r
uint16_t *m_sysrom;
required_memory_region m_eprom;
required_shared_ptr<uint16_t> m_ram;
memory_passthrough_handler m_boot_mph;
};
#endif // MAME_BUS_VME_VME_FCISIO_H
#endif // MAME_BUS_VME_SYS68K_ISIO_H

27
src/devices/bus/vme/tp881v.cpp
View File

@ -27,10 +27,10 @@
#define VERBOSE 0
#include "logmacro.h"
DEFINE_DEVICE_TYPE(TP881V, tp881v_device, "tp881v", "Tadpole Technology TP881V")
DEFINE_DEVICE_TYPE(VME_TP881V, vme_tp881v_card_device, "tp881v", "Tadpole Technology TP881V")
tp881v_device::tp881v_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock)
: device_t(mconfig, TP881V, tag, owner, clock)
vme_tp881v_card_device::vme_tp881v_card_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock)
: device_t(mconfig, VME_TP881V, tag, owner, clock)
, device_vme_card_interface(mconfig, *this)
, m_cpu(*this, "cpu")
, m_mmu(*this, "mmu%u", 0U)
@ -57,21 +57,21 @@ ROM_END
static INPUT_PORTS_START(tp881v)
INPUT_PORTS_END
const tiny_rom_entry *tp881v_device::device_rom_region() const
const tiny_rom_entry *vme_tp881v_card_device::device_rom_region() const
{
return ROM_NAME(tp881v);
}
ioport_constructor tp881v_device::device_input_ports() const
ioport_constructor vme_tp881v_card_device::device_input_ports() const
{
return INPUT_PORTS_NAME(tp881v);
}
void tp881v_device::device_start()
void vme_tp881v_card_device::device_start()
{
}
void tp881v_device::device_reset()
void vme_tp881v_card_device::device_reset()
{
}
@ -82,10 +82,10 @@ static void scsi_devices(device_slot_interface &device)
device.option_add("ncr53c90a", NCR53C90A);
}
void tp881v_device::device_add_mconfig(machine_config &config)
void vme_tp881v_card_device::device_add_mconfig(machine_config &config)
{
MC88100(config, m_cpu, 40_MHz_XTAL / 2);
m_cpu->set_addrmap(AS_PROGRAM, &tp881v_device::cpu_mem);
m_cpu->set_addrmap(AS_PROGRAM, &vme_tp881v_card_device::cpu_mem);
MC88200(config, m_mmu[0], 40_MHz_XTAL / 2, 0x00);
m_mmu[0]->set_mbus(m_cpu, AS_PROGRAM);
@ -178,7 +178,7 @@ void tp881v_device::device_add_mconfig(machine_config &config)
I82596_BE32(config, m_net, 20'000'000); // A82596DX-25
m_net->out_irq_cb().set(m_cio[0], FUNC(z8036_device::pa1_w));
m_net->set_addrmap(0, &tp881v_device::net_mem);
m_net->set_addrmap(0, &vme_tp881v_card_device::net_mem);
input_merger_any_high_device &scc_irq(INPUT_MERGER_ANY_HIGH(config, "scc_irq"));
scc_irq.output_handler().set(m_cio[0], FUNC(z8036_device::pa5_w));
@ -310,12 +310,13 @@ void tp881v_device::device_add_mconfig(machine_config &config)
NMC9306(config, m_eeprom, 0);
}
void tp881v_device::cpu_mem(address_map &map)
void vme_tp881v_card_device::cpu_mem(address_map &map)
{
map(0x0000'0000, 0x0003'ffff).rom().region("eprom", 0);
//map(0x2000'0000, 0x20ff'ffff); // vme short space (a24 d32)
map(0x4000'0000, 0x41ff'ffff).ram().share("ram");
//map(0x8000'0000, 0x80ff'ffff); // vme extended space (a32 d32)
//map(0x8000'0000, 0xbfff'ffff); // vme extended space (a32 d32)
//map(0xc000'0000, 0xc0ff'ffff); // vsb space
map(0xfff3'0000, 0xfff3'003f).m(m_scsi[0], FUNC(ncr53c90a_device::map)).umask32(0x000000ff);
@ -342,7 +343,7 @@ void tp881v_device::cpu_mem(address_map &map)
map(0xfff9'0c00, 0xfff9'0cbf).rw(m_cio[7], FUNC(z8036_device::read), FUNC(z8036_device::write)).umask32(0x000000ff);
}
void tp881v_device::net_mem(address_map &map)
void vme_tp881v_card_device::net_mem(address_map &map)
{
map(0x4000'0000, 0x41ff'ffff).ram().share("ram");
}

6
src/devices/bus/vme/tp881v.h
View File

@ -19,12 +19,12 @@
#include "bus/vme/vme.h"
#include "bus/rs232/rs232.h"
class tp881v_device
class vme_tp881v_card_device
: public device_t
, public device_vme_card_interface
{
public:
tp881v_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock);
vme_tp881v_card_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock);
protected:
virtual const tiny_rom_entry *device_rom_region() const override;
@ -54,6 +54,6 @@ private:
required_device_array<rs232_port_device, 4> m_serial;
};
DECLARE_DEVICE_TYPE(TP881V, tp881v_device)
DECLARE_DEVICE_TYPE(VME_TP881V, vme_tp881v_card_device)
#endif // MAME_BUS_VME_TP881V_H

537
src/devices/bus/vme/vme.cpp
View File

@ -66,404 +66,275 @@
interfaced to the incoming AC power source and may also be located remotely.
*/
/*
* TODO:
* - bus arbitration
* - block, rmw and address-only cycles
* - utility bus (serial clock/data, acfail, sysreset, sysfail)
* - variants (16-bit backplanes, VME64)
* - location monitors
*/
#include "emu.h"
#include "vme.h"
//#include "bus/vme/vme_mzr8105.h"
#include "bus/vme/vme_mzr8300.h"
#include "bus/vme/vme_mvme350.h"
#include "bus/vme/vme_fcisio.h"
#include "bus/vme/vme_fcscsi.h"
#define LOG_SETUP (1U << 1)
//#define VERBOSE (LOG_SETUP | LOG_GENERAL)
#define LOG_OUTPUT_FUNC printf // logerror is not available here
#define VERBOSE 0
#include "logmacro.h"
#define LOGSETUP(...) LOGMASKED(LOG_SETUP, __VA_ARGS__)
#ifdef _MSC_VER
#define FUNCNAME __func__
#else
#define FUNCNAME __PRETTY_FUNCTION__
#endif
//**************************************************************************
// GLOBAL VARIABLES
//**************************************************************************
DEFINE_DEVICE_TYPE(VME, vme_bus_device, "vme", "VME bus")
DEFINE_DEVICE_TYPE(VME_SLOT, vme_slot_device, "vme_slot", "VME slot")
//-------------------------------------------------
// vme_slot_device - constructor
//-------------------------------------------------
vme_slot_device::vme_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: vme_slot_device(mconfig, VME_SLOT, tag, owner, clock)
{
}
vme_slot_device::vme_slot_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
: device_t(mconfig, type, tag, owner, clock)
, device_slot_interface(mconfig, *this)
, m_vme(*this, finder_base::DUMMY_TAG)
, m_slot_nbr(0)
, m_vme_j1_callback(*this)
{
LOG("%s %s\n", tag, FUNCNAME);
}
//-------------------------------------------------
// device_start - device-specific startup
//-------------------------------------------------
void vme_slot_device::device_start()
{
// m_card = dynamic_cast<device_vme_card_interface *>(get_card_device());
}
//-------------------------------------------------
// device_resolve_objects - resolve objects that
// may be needed for other devices to set
// initial conditions at start time
//-------------------------------------------------
void vme_slot_device::device_resolve_objects()
{
device_vme_card_interface *dev = dynamic_cast<device_vme_card_interface *>(get_card_device());
LOG("%s %s - %s\n", tag(), FUNCNAME, m_vme.finder_tag());
if (dev)
vme_bus_device::vme_bus_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock, u8 datawidth)
: device_t(mconfig, VME, tag, owner, clock)
, device_memory_interface(mconfig, *this)
, m_asc
{
dev->set_vme_bus(*m_vme, m_slot_nbr);
{ "iack", ENDIANNESS_BIG, datawidth, 4, -2, address_map_constructor(FUNC(vme_bus_device::iack), this) },
{}, {}, {}, {}, {}, {}, {}, {},
{ "a32_09", ENDIANNESS_BIG, datawidth, 32, 0, address_map_constructor(FUNC(vme_bus_device::a32), this) },
{ "a32_0a", ENDIANNESS_BIG, datawidth, 32, 0, address_map_constructor(FUNC(vme_bus_device::a32), this) },
{ "a32_0b", ENDIANNESS_BIG, datawidth, 32, 0, address_map_constructor(FUNC(vme_bus_device::a32), this) },
{},
{ "a32_0d", ENDIANNESS_BIG, datawidth, 32, 0, address_map_constructor(FUNC(vme_bus_device::a32), this) },
{ "a32_0e", ENDIANNESS_BIG, datawidth, 32, 0, address_map_constructor(FUNC(vme_bus_device::a32), this) },
{ "a32_0f", ENDIANNESS_BIG, datawidth, 32, 0, address_map_constructor(FUNC(vme_bus_device::a32), this) },
{}, {}, {}, {}, {}, {}, {}, {},
{}, {}, {}, {}, {}, {}, {}, {},
{}, {}, {}, {}, {}, {}, {}, {},
{},
{ "a16_29", ENDIANNESS_BIG, datawidth, 16, 0, address_map_constructor(FUNC(vme_bus_device::a16), this) },
{}, {}, {},
{ "a16_2d", ENDIANNESS_BIG, datawidth, 16, 0, address_map_constructor(FUNC(vme_bus_device::a16), this) },
{}, {},
{}, {}, {}, {}, {}, {}, {}, {},
{},
{ "a24_39", ENDIANNESS_BIG, datawidth, 24, 0, address_map_constructor(FUNC(vme_bus_device::a24), this) },
{ "a24_3a", ENDIANNESS_BIG, datawidth, 24, 0, address_map_constructor(FUNC(vme_bus_device::a24), this) },
{ "a24_3b", ENDIANNESS_BIG, datawidth, 24, 0, address_map_constructor(FUNC(vme_bus_device::a24), this) },
{},
{ "a24_3d", ENDIANNESS_BIG, datawidth, 24, 0, address_map_constructor(FUNC(vme_bus_device::a24), this) },
{ "a24_3e", ENDIANNESS_BIG, datawidth, 24, 0, address_map_constructor(FUNC(vme_bus_device::a24), this) },
{ "a24_3f", ENDIANNESS_BIG, datawidth, 24, 0, address_map_constructor(FUNC(vme_bus_device::a24), this) },
}
, m_irq(*this)
, m_berr(*this)
, m_irq_count{}
, m_iack(false)
{
}
//-------------------------------------------------
// P1 D8 read
//-------------------------------------------------
uint8_t vme_slot_device::read8(offs_t offset)
void vme_bus_device::device_start()
{
uint16_t result = 0x00;
LOG("%s %s\n", tag(), FUNCNAME);
// printf("%s %s\n", tag(), FUNCNAME);
// if (m_card) result = m_card->read8(offset);
return result;
save_item(NAME(m_irq_count));
save_item(NAME(m_iack));
}
//-------------------------------------------------
// P1 D8 write
//-------------------------------------------------
void vme_slot_device::write8(offs_t offset, uint8_t data)
device_memory_interface::space_config_vector vme_bus_device::memory_space_config() const
{
LOG("%s %s\n", tag(), FUNCNAME);
// printf("%s %s\n", tag(), FUNCNAME);
// if (m_card) m_card->write8(offset, data);
}
return space_config_vector{
std::make_pair(vme::IACK, &m_asc[vme::IACK]),
#if 0 // Disabled until we know how to make a board driver also a slot device
/* The following two slot collections be combined once we intriduce capabilities for each board */
/* Usually a VME firmware supports only a few boards so it will have its own slot collection defined */
// Controller capable boards that can go into slot1 ( or has an embedded VME bus )
void vme_slot1(device_slot_interface &device)
{
// device.option_add("mzr8105", VME_MZR8105);
}
#endif
std::make_pair(vme::AM_09, &m_asc[vme::AM_09]),
std::make_pair(vme::AM_0a, &m_asc[vme::AM_0a]),
std::make_pair(vme::AM_0b, &m_asc[vme::AM_0b]),
std::make_pair(vme::AM_0d, &m_asc[vme::AM_0d]),
std::make_pair(vme::AM_0e, &m_asc[vme::AM_0e]),
std::make_pair(vme::AM_0f, &m_asc[vme::AM_0f]),
// All boards that can be non-controller boards, eg not driving the VME CLK etc
void vme_slots(device_slot_interface &device)
{
device.option_add("mzr8300", VME_MZR8300);
device.option_add("mvme350", VME_MVME350);
device.option_add("fcisio1", VME_FCISIO1);
device.option_add("fcscsi1", VME_FCSCSI1);
}
std::make_pair(vme::AM_29, &m_asc[vme::AM_29]),
std::make_pair(vme::AM_2d, &m_asc[vme::AM_2d]),
//
// VME device P1
//
DEFINE_DEVICE_TYPE(VME, vme_device, "vme", "VME bus")
device_memory_interface::space_config_vector vme_device::memory_space_config() const
{
return space_config_vector {
std::make_pair(AS_PROGRAM, &m_a32_config)
std::make_pair(vme::AM_39, &m_asc[vme::AM_39]),
std::make_pair(vme::AM_3a, &m_asc[vme::AM_3a]),
std::make_pair(vme::AM_3b, &m_asc[vme::AM_3b]),
std::make_pair(vme::AM_3d, &m_asc[vme::AM_3d]),
std::make_pair(vme::AM_3e, &m_asc[vme::AM_3e]),
std::make_pair(vme::AM_3f, &m_asc[vme::AM_3f]),
};
}
// set_use_owner_spaces - disables use of the memory interface and use the address spaces
// of the owner instead. This is useful for VME buses where no address modifiers or arbitration is
// being used and gives some gain in performance.
void vme_device::use_owner_spaces()
u32 vme_bus_device::read_iack(address_space &space, offs_t offset, u32 mem_mask)
{
LOG("%s %s\n", tag(), FUNCNAME);
m_allocspaces = false;
}
vme_device::vme_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: vme_device(mconfig, VME, tag, owner, clock)
{
}
vme_device::vme_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
: device_t(mconfig, type, tag, owner, clock)
, device_memory_interface(mconfig, *this)
, m_a32_config("a32", ENDIANNESS_BIG, 32, 32, 0, address_map_constructor())
, m_allocspaces(true)
, m_cputag("maincpu")
{
LOG("%s %s\n", tag, FUNCNAME);
}
vme_device::~vme_device()
{
LOG("%s %s\n", tag(), FUNCNAME);
}
void vme_device::device_start()
{
LOG("%s %s %s\n", owner()->tag(), tag(), FUNCNAME);
if (m_allocspaces)
if (!device().machine().side_effects_disabled())
{
LOG(" - using my own memory spaces\n");
m_prgspace = &space(AS_PROGRAM);
m_prgwidth = m_prgspace->data_width();
LOG(" - Done at %d width\n", m_prgwidth);
LOG("read_iack 0x%08x mem_mask 0x%08x (%s)\n", offset, mem_mask, machine().describe_context());
// enable interrupt acknowledge daisy chain
m_iack = true;
}
else // use host CPU's spaces directly
return space.unmap();
}
// generate bus errors on unmapped read cycles
u32 vme_bus_device::read_berr(address_space &space, offs_t offset, u32 mem_mask)
{
if (!device().machine().side_effects_disabled())
{
LOG(" - using owner memory spaces for %s\n", m_cputag);
m_maincpu = owner()->subdevice<cpu_device>(m_cputag);
m_prgspace = &m_maincpu->space(AS_PROGRAM);
m_prgwidth = m_maincpu->space_config(AS_PROGRAM)->data_width();
LOG(" - Done at %d width\n", m_prgwidth);
LOG("read_berr 0x%08x mem_mask 0x%08x (%s)\n", offset << 2, mem_mask, machine().describe_context());
m_berr(0);
}
return space.unmap();
}
// generate bus errors on unmapped write cycles
void vme_bus_device::write_berr(offs_t offset, u32 data, u32 mem_mask)
{
if (!device().machine().side_effects_disabled())
{
LOG("write_berr 0x%08x data 0x%08x mem_mask 0x%08x (%s)\n", offset << 2, data, mem_mask, machine().describe_context());
m_berr(0);
}
}
void vme_device::device_reset()
void vme_bus_device::iack(address_map &map)
{
LOG("%s %s\n", tag(), FUNCNAME);
map(0x0, 0xf).r(FUNC(vme_bus_device::read_iack));
}
void vme_device::add_vme_card(device_vme_card_interface *card)
void vme_bus_device::a16(address_map &map)
{
LOG("%s %s\n", tag(), FUNCNAME);
m_device_list.emplace_back(*card);
map(0x0000, 0xffff).rw(FUNC(vme_bus_device::read_berr), FUNC(vme_bus_device::write_berr));
}
#if 0
/*
* Install UB (Utility Bus) handlers for this board
*
* The Utility Bus signal lines
*------------------------------
* System Clock (SYSCLK)
* Serial Clock (SERCLK)
* Serial Data (SERDAT*)
* AC Fail (ACFAIL*)
* System Reset (SYSRESET*)
* System Failure (SYSFAIL*)
*------------------------------
*/
void vme_device::install_ub_handler(offs_t start, offs_t end, read8_delegate rhandler, write8_delegate whandler, uint32_t mask)
void vme_bus_device::a24(address_map &map)
{
map(0x00'0000, 0xff'ffff).rw(FUNC(vme_bus_device::read_berr), FUNC(vme_bus_device::write_berr));
}
#endif
/*
* Install DTB (Data Transfer Bus) handlers for this board
*/
// D8 bit devices in A16, A24 and A32
void vme_device::install_device(vme_amod_t amod, offs_t start, offs_t end, read8_delegate rhandler, write8_delegate whandler, uint32_t mask)
void vme_bus_device::a32(address_map &map)
{
LOG("%s %s AM%d D%02x\n", tag(), FUNCNAME, amod, m_prgwidth);
map(0x0000'0000, 0xffff'ffff).rw(FUNC(vme_bus_device::read_berr), FUNC(vme_bus_device::write_berr));
}
LOG(" - width:%d\n", m_prgwidth);
template <unsigned I> void vme_bus_device::irq_w(int state)
{
bool const irq_active = m_irq_count[I - 1];
// TODO: support address modifiers and buscycles other than single access cycles
switch(amod)
// count assertions
if (!state)
m_irq_count[I - 1]++;
else if (irq_active)
m_irq_count[I - 1]--;
// update line state
if (irq_active ^ bool(m_irq_count[I - 1]))
{
case A16_SC: break;
case A24_SC: break;
case A32_SC: break;
default: fatalerror("VME D8: Non supported Address modifier: AM%02x\n", amod);
}
switch(m_prgwidth)
{
case 16:
m_prgspace->install_readwrite_handler(start, end, rhandler, whandler, (uint16_t)(mask & 0x0000ffff));
break;
case 24:
m_prgspace->install_readwrite_handler(start, end, rhandler, whandler, (uint32_t)(mask & 0x00ffffff));
break;
case 32:
m_prgspace->install_readwrite_handler(start, end, rhandler, whandler, mask);
break;
default: fatalerror("VME D8: Bus width %d not supported\n", m_prgwidth);
LOG("irq %d state %d\n", I, state);
m_irq[I - 1](state);
}
}
void vme_device::install_device(vme_amod_t amod, offs_t start, offs_t end, read8sm_delegate rhandler, write8sm_delegate whandler, uint32_t mask)
template void vme_bus_device::irq_w<1>(int state);
template void vme_bus_device::irq_w<2>(int state);
template void vme_bus_device::irq_w<3>(int state);
template void vme_bus_device::irq_w<4>(int state);
template void vme_bus_device::irq_w<5>(int state);
template void vme_bus_device::irq_w<6>(int state);
template void vme_bus_device::irq_w<7>(int state);
vme_slot_device::vme_slot_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock)
: device_t(mconfig, VME_SLOT, tag, owner, clock)
, device_slot_interface(mconfig, *this)
, m_bus(*this, owner->tag())
{
LOG("%s %s AM%d D%02x\n", tag(), FUNCNAME, amod, m_prgwidth);
LOG(" - width:%d\n", m_prgwidth);
// TODO: support address modifiers and buscycles other than single access cycles
switch(amod)
{
case A16_SC: break;
case A24_SC: break;
case A32_SC: break;
default: fatalerror("VME D8: Non supported Address modifier: AM%02x\n", amod);
}
switch(m_prgwidth)
{
case 16:
m_prgspace->install_readwrite_handler(start, end, rhandler, whandler, (uint16_t)(mask & 0x0000ffff));
break;
case 24:
m_prgspace->install_readwrite_handler(start, end, rhandler, whandler, (uint32_t)(mask & 0x00ffffff));
break;
case 32:
m_prgspace->install_readwrite_handler(start, end, rhandler, whandler, mask);
break;
default: fatalerror("VME D8: Bus width %d not supported\n", m_prgwidth);
}
}
void vme_device::install_device(vme_amod_t amod, offs_t start, offs_t end, read8smo_delegate rhandler, write8smo_delegate whandler, uint32_t mask)
void vme_slot_device::device_start()
{
LOG("%s %s AM%d D%02x\n", tag(), FUNCNAME, amod, m_prgwidth);
LOG(" - width:%d\n", m_prgwidth);
// TODO: support address modifiers and buscycles other than single access cycles
switch(amod)
{
case A16_SC: break;
case A24_SC: break;
case A32_SC: break;
default: fatalerror("VME D8: Non supported Address modifier: AM%02x\n", amod);
}
switch(m_prgwidth)
{
case 16:
m_prgspace->install_readwrite_handler(start, end, rhandler, whandler, (uint16_t)(mask & 0x0000ffff));
break;
case 24:
m_prgspace->install_readwrite_handler(start, end, rhandler, whandler, (uint32_t)(mask & 0x00ffffff));
break;
case 32:
m_prgspace->install_readwrite_handler(start, end, rhandler, whandler, mask);
break;
default: fatalerror("VME D8: Bus width %d not supported\n", m_prgwidth);
}
}
// D16 bit devices in A16, A24 and A32
void vme_device::install_device(vme_amod_t amod, offs_t start, offs_t end, read16_delegate rhandler, write16_delegate whandler, uint32_t mask)
{
LOG("%s %s AM%d D%02x\n", tag(), FUNCNAME, amod, m_prgwidth);
#undef LOG_OUTPUT_FUNC
#define LOG_OUTPUT_FUNC device().logerror
LOG(" - width:%d\n", m_prgwidth);
// TODO: support address modifiers and buscycles other than single access cycles
switch(amod)
{
case A16_SC: break;
case A24_SC: break;
case A32_SC: break;
default: fatalerror("VME D16: Non supported Address modifier: %02x\n", amod);
}
switch(m_prgwidth)
{
case 16:
m_prgspace->install_readwrite_handler(start, end, rhandler, whandler, (uint16_t)(mask & 0x0000ffff));
break;
case 24:
m_prgspace->install_readwrite_handler(start, end, rhandler, whandler, (uint32_t)(mask & 0x00ffffff));
break;
case 32:
m_prgspace->install_readwrite_handler(start, end, rhandler, whandler, mask);
break;
default: fatalerror("VME D16: Bus width %d not supported\n", m_prgwidth);
}
}
// D32 bit devices in A16, A24 and A32
void vme_device::install_device(vme_amod_t amod, offs_t start, offs_t end, read32_delegate rhandler, write32_delegate whandler, uint32_t mask)
{
LOG("%s %s AM%d D%02x\n", tag(), FUNCNAME, amod, m_prgwidth);
LOG(" - width:%d\n", m_prgwidth);
// TODO: support address modifiers and buscycles other than single access cycles
switch(amod)
{
case A16_SC: break;
case A24_SC: break;
case A32_SC: break;
default: fatalerror("VME D32: Non supported Address modifier: %02x\n", amod);
}
switch(m_prgwidth)
{
case 16:
m_prgspace->install_readwrite_handler(start, end, rhandler, whandler, (uint16_t)(mask & 0x0000ffff));
break;
case 24:
m_prgspace->install_readwrite_handler(start, end, rhandler, whandler, (uint32_t)(mask & 0x00ffffff));
break;
case 32:
m_prgspace->install_readwrite_handler(start, end, rhandler, whandler, mask);
break;
default: fatalerror("VME D32: Bus width %d not supported\n", m_prgwidth);
}
}
//
// Card interface
//
device_vme_card_interface::device_vme_card_interface(const machine_config &mconfig, device_t &device)
device_vme_card_interface::device_vme_card_interface(machine_config const &mconfig, device_t &device)
: device_interface(device, "vme")
, m_vme(nullptr)
, m_slot(0)
, m_slot(dynamic_cast<vme_slot_device *>(device.owner()))
, m_berr(*this)
, m_iack(*this, 0)
, m_irq_active(0)
, m_master(false)
{
m_device = &device;
LOG("%s %s\n", m_device->tag(), FUNCNAME);
}
device_vme_card_interface::~device_vme_card_interface()
void device_vme_card_interface::interface_config_complete()
{
LOG("%s %s\n", m_device->tag(), FUNCNAME);
// route bus errors to the card when it is the bus master
m_slot->berr().append(
[this](int state)
{
if (m_master)
{
LOG("vme berr %d\n", state);
m_berr(state);
}
});
}
void device_vme_card_interface::interface_post_start()
{
LOG("%s %s\n", m_device->tag(), FUNCNAME);
// printf("*** %s %sfound\n", m_vme_tag, m_vme ? "" : "not ");
if (m_vme) m_vme->add_vme_card(this);
device().save_item(NAME(m_irq_active));
device().save_item(NAME(m_master));
/*
* Install a read tap into the bus interrupt acknowledge address space,
* simulating a daisy chain and giving each card an opportunity to respond
* to the interrupt acknowledge cycle in slot sequence. Empty slots do not
* respond, acting as if they have /IACKIN jumpered to /IACKOUT.
*/
vme_space(vme::IACK).install_read_tap(0x0, 0xf, "iack",
[this](offs_t offset, u32 &data, u32 mem_mask)
{
// decode the interrupt number from address lines A03-A01
unsigned const irq = BIT(offset, 1, 3);
/*
* An interrupt acknowledge cycle is being asserted. This device
* will only respond if the upstream interrupt acknowledge daisy
* chain input (/IACKIN) is asserted and this device is asserting
* the interrupt number being acknowledged.
*/
if (m_slot->iackin_r() && BIT(m_irq_active, irq))
{
// deassert interrupt acknowledge daisy chain output
m_slot->iackout_w(1);
// read and return the interrupting device status/ID
data = m_iack(irq);
LOG("vme iack irq %d status 0x%08x (%s)\n", irq, data, device().machine().describe_context());
}
});
}
/* VME D8 accesses */
uint8_t device_vme_card_interface::read8(offs_t offset)
template <unsigned I> void device_vme_card_interface::vme_irq_w(int state)
{
uint8_t result = 0x00;
LOG("%s %s Offset:%08x\n", m_device->tag(), FUNCNAME, offset);
return result;
// check whether the interrupt state has changed
if (BIT(m_irq_active, I) == state)
{
LOG("vme irq %d state %d\n", I, state);
// record device interrupt state
if (!state)
m_irq_active |= 1U << I;
else
m_irq_active &= ~(1U << I);
// update the bus irq state
m_slot->irq_w<I>(state);
}
}
void device_vme_card_interface::write8(offs_t offset, uint8_t data)
{
LOG("%s %s Offset:%08x\n", m_device->tag(), FUNCNAME, offset);
}
template void device_vme_card_interface::vme_irq_w<1>(int state);
template void device_vme_card_interface::vme_irq_w<2>(int state);
template void device_vme_card_interface::vme_irq_w<3>(int state);
template void device_vme_card_interface::vme_irq_w<4>(int state);
template void device_vme_card_interface::vme_irq_w<5>(int state);
template void device_vme_card_interface::vme_irq_w<6>(int state);
template void device_vme_card_interface::vme_irq_w<7>(int state);
//--------------- P2 connector below--------------------------
/*

287
src/devices/bus/vme/vme.h
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@ -50,192 +50,175 @@
#pragma once
#include <functional>
#include <utility>
#include <vector>
namespace vme
{
enum address_modifier : u8
{
IACK = 0x00, // interrupt acknowledge
AM_09 = 0x09, // a32, non-privileged, data
AM_0a = 0x0a, // a32, non-privileged, instruction
AM_0b = 0x0b, // a32, non-privileged, block transfer
AM_0d = 0x0d, // a32, privileged, data
AM_0e = 0x0e, // a32, privileged, instruction
AM_0f = 0x0f, // a32, privileged, block transfer
//**************************************************************************
// CONSTANTS
//**************************************************************************
AM_29 = 0x29, // a16, non-privileged
AM_2d = 0x2d, // a16, privileged
//void vme_slot1(device_slot_interface &device); // Disabled until we know how to combine a board driver and a slot device.
void vme_slots(device_slot_interface &device);
AM_39 = 0x39, // a24, non-privileged, data
AM_3a = 0x3a, // a24, non-privileged, instruction
AM_3b = 0x3b, // a24, non-privileged, block transfer
AM_3d = 0x3d, // a24, privileged, data
AM_3e = 0x3e, // a24, privileged, instruction
AM_3f = 0x3f, // a24, privileged, block transfer
};
}
class device_vme_card_interface; // This interface is standardized
class vme_device;
class vme_slot_device : public device_t,
public device_slot_interface
class vme_bus_device
: public device_t
, public device_memory_interface
{
public:
// VME BUS signals driven to or drived by the VME bus
enum class control
{
AS,
DS0,
DS1,
BERR,
DTACK,
WRITE
};
enum class address
{
DS0,
DS1,
LWORD
};
// construction/destruction
template <typename T, typename U>
vme_slot_device(machine_config const &mconfig, char const *tag, device_t *owner, T &&opts, char const *dflt, uint32_t slot_nbr, U &&bus_tag)
: vme_slot_device(mconfig, tag, owner, 0)
{
option_reset();
opts(*this);
set_default_option(dflt);
set_fixed(false);
set_vme_slot(std::forward<U>(bus_tag), slot_nbr);
}
vme_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
// Callbacks to the board from the VME bus comes through here
auto vme_j1_callback() { return m_vme_j1_callback.bind(); }
template <typename T> void set_vme_slot(T &&tag, uint32_t slot_nbr) { m_vme.set_tag(std::forward<T>(tag)); m_slot_nbr = slot_nbr; }
virtual uint8_t read8(offs_t offset);
virtual void write8(offs_t offset, uint8_t data);
protected:
vme_slot_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
// device-level overrides
virtual void device_start() override;
virtual void device_resolve_objects() override;
vme_bus_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock = 16'000'000, u8 datawidth = 32);
// configuration
required_device<vme_device> m_vme;
uint32_t m_slot_nbr;
auto berr() { return m_berr.bind(); }
template <unsigned I> auto irq() { return m_irq[I - 1].bind(); }
// callbacks
devcb_write_line m_vme_j1_callback;
device_vme_card_interface *m_card;
};
DECLARE_DEVICE_TYPE(VME, vme_device)
class vme_card_interface;
class vme_device : public device_t,
public device_memory_interface
{
public:
vme_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
~vme_device();
// inline configuration
void set_cputag(const char *tag) { m_cputag = tag; }
void use_owner_spaces();
const address_space_config m_a32_config;
void add_vme_card(device_vme_card_interface *card);
//
// Address Modifiers
//
/* There are 6 address modifier lines. They allow the MASTER to pass additional binary
information to the SLAVE during data transfers. Table 2-3 lists all of the 64 possible
address modifier (AM) codes and classifies each into one of three categories:
- Defined
- Reserved
- User defined
The defined address modifier codes can be further classified into three categories:
Short addressing AM codes indicate that address lines A02-A15 are being used to select a BYTE(0-3) group.
Standard addressing AM codes ,indicate that address lines A02-A23 are being used to select a BYTE(0-3) group.
Extended addressing AM codes indicate that address lines A02-A31 are being used to select a BYTE(0-3) group.*/
enum vme_amod_t
{ // Defined and User Defined Address Modifier Values (long bnames from VME standard text. please use short)
AMOD_EXTENDED_NON_PRIV_DATA = 0x09, //A32 SC (Single Cycle)
A32_SC = 0x09, //A32 SC (Single Cycle)
AMOD_EXTENDED_NON_PRIV_PRG = 0x0A,
AMOD_EXTENDED_NON_PRIV_BLK = 0x0B,
AMOD_EXTENDED_SUPERVIS_DATA = 0x0D,
AMOD_EXTENDED_SUPERVIS_PRG = 0x0E,
AMOD_EXTENDED_SUPERVIS_BLK = 0x0F,
AMOD_USER_DEFINED_FIRST = 0x10,
AMOD_USER_DEFINED_LAST = 0x1F,
AMOD_SHORT_NON_PRIV_ACCESS = 0x29, //A16 SC
A16_SC = 0x29, //A16 SC
AMOD_SHORT_SUPERVIS_ACCESS = 0x2D,
AMOD_STANDARD_NON_PRIV_DATA = 0x39, //A24 SC
A24_SC = 0x39, //A24 SC
AMOD_STANDARD_NON_PRIV_PRG = 0x3A,
AMOD_STANDARD_NON_PRIV_BLK = 0x3B, //A24 BLT
AMOD_STANDARD_SUPERVIS_DATA = 0x3D,
AMOD_STANDARD_SUPERVIS_PRG = 0x3E,
AMOD_STANDARD_SUPERVIS_BLK = 0x3F
};
void install_device(vme_amod_t amod, offs_t start, offs_t end, read8_delegate rhandler, write8_delegate whandler, uint32_t mask);
void install_device(vme_amod_t amod, offs_t start, offs_t end, read8sm_delegate rhandler, write8sm_delegate whandler, uint32_t mask);
void install_device(vme_amod_t amod, offs_t start, offs_t end, read8smo_delegate rhandler, write8smo_delegate whandler, uint32_t mask);
// void install_device(vme_amod_t amod, offs_t start, offs_t end, read8_delegate rhandler, write8_delegate whandler);
void install_device(vme_amod_t amod, offs_t start, offs_t end, read16_delegate rhandler, write16_delegate whandler, uint32_t mask);
void install_device(vme_amod_t amod, offs_t start, offs_t end, read32_delegate rhandler, write32_delegate whandler, uint32_t mask);
// runtime
void berr_w(int state) { m_berr(state); }
int iackin_r() { return m_iack; }
void iackout_w(int state) { m_iack = !state; }
template <unsigned I> void irq_w(int state);
protected:
vme_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
// device-level overrides
// device_t implementation
virtual void device_start() override;
virtual void device_reset() override;
std::vector<std::reference_wrapper<device_vme_card_interface> > m_device_list;
// device_memory_interface implementation
virtual space_config_vector memory_space_config() const override;
// internal state
cpu_device *m_maincpu;
private:
void iack(address_map &map);
void a16(address_map &map);
void a24(address_map &map);
void a32(address_map &map);
// address spaces
address_space *m_prgspace;
int m_prgwidth;
bool m_allocspaces;
u32 read_iack(address_space &space, offs_t offset, u32 mem_mask);
u32 read_berr(address_space &space, offs_t offset, u32 mem_mask);
void write_berr(offs_t offset, u32 data, u32 mem_mask);
const char *m_cputag;
address_space_config const m_asc[64];
devcb_write_line::array<7> m_irq;
devcb_write_line m_berr;
u8 m_irq_count[7];
bool m_iack;
};
class vme_slot_device
: public device_t
, public device_slot_interface
{
public:
vme_slot_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock = DERIVED_CLOCK(1, 1));
template <typename T>
vme_slot_device(machine_config const &mconfig, char const *tag, device_t *owner, T &&slot_options, char const *default_option, bool const fixed = false)
: vme_slot_device(mconfig, tag, owner, DERIVED_CLOCK(1, 1))
{
option_reset();
slot_options(*this);
set_default_option(default_option);
set_fixed(fixed);
}
// device type definition
DECLARE_DEVICE_TYPE(VME_SLOT, vme_slot_device)
// configuration
template <unsigned I> auto irq() { return m_bus.lookup()->irq<I>(); }
auto berr() { return m_bus.lookup()->berr(); }
// runtime
void berr_w(int state) { m_bus->berr_w(state); }
int iackin_r() { return m_bus->iackin_r(); }
void iackout_w(int state) { m_bus->iackout_w(state); }
template <unsigned I> void irq_w(int state) { m_bus->irq_w<I>(state); }
address_space &space(vme::address_modifier am) const { return m_bus->space(am); }
protected:
// device_t implementation
virtual void device_start() override;
private:
required_device<vme_bus_device> m_bus;
};
class device_vme_card_interface : public device_interface
{
public:
// inline configuration
void set_vme_bus(vme_device &vme, int slot) { m_vme = &vme; m_slot = slot; }
template <vme::address_modifier AM, offs_t base = 0> u32 vme_read32(offs_t offset, u32 mem_mask)
{
m_master = true;
u32 const data = m_slot->space(AM).read_dword(base + (offset << 2), mem_mask);
m_master = false;
// construction/destruction
virtual ~device_vme_card_interface();
return data;
}
template <vme::address_modifier AM, offs_t base = 0> u16 vme_read16(offs_t offset, u16 mem_mask)
{
m_master = true;
u16 const data = m_slot->space(AM).read_word(base + (offset << 1), mem_mask);
m_master = false;
virtual uint8_t read8(offs_t offset);
virtual void write8(offs_t offset, uint8_t data);
return data;
}
template <vme::address_modifier AM, offs_t base = 0> void vme_write32(offs_t offset, u32 data, u32 mem_mask)
{
m_master = true;
m_slot->space(AM).write_dword(base + (offset << 2), data, mem_mask);
m_master = false;
}
template <vme::address_modifier AM, offs_t base = 0> void vme_write16(offs_t offset, u16 data, u16 mem_mask)
{
m_master = true;
m_slot->space(AM).write_word(base + (offset << 1), data, mem_mask);
m_master = false;
}
u32 vme_iack_r(offs_t offset)
{
return m_slot->space(vme::IACK).read_dword(offset);
}
protected:
device_vme_card_interface(const machine_config &mconfig, device_t &device);
device_vme_card_interface(machine_config const &mconfig, device_t &device);
// configuration
template <unsigned I> auto vme_irq() { return m_slot->irq<I>(); }
auto vme_berr() { return m_berr.bind(); }
auto vme_iack() { return m_iack.bind(); }
// device_interface implementation
virtual void interface_config_complete() override;
virtual void interface_post_start() override;
device_t *m_device;
// runtime
template <unsigned I> void vme_irq_w(int state);
void vme_berr_w(int state) { m_slot->berr_w(state); }
vme_device *m_vme;
int m_slot;
address_space &vme_space(vme::address_modifier am) const { return m_slot->space(am); }
private:
vme_slot_device *m_slot;
devcb_write_line m_berr;
devcb_read32 m_iack;
u8 m_irq_active;
bool m_master;
};
DECLARE_DEVICE_TYPE(VME, vme_bus_device)
DECLARE_DEVICE_TYPE(VME_SLOT, vme_slot_device)
#endif // MAME_BUS_VME_VME_H

64
src/devices/bus/vme/vme_cards.cpp Normal file
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// license:BSD-3-Clause
// copyright-holders:Patrick Mackinlay
#include "emu.h"
#include "vme_cards.h"
#include "cp31.h"
#include "enp10.h"
#include "hcpu30.h"
#include "hk68v10.h"
#include "mvme120.h"
#include "mvme147.h"
#include "mvme180.h"
#include "mvme181.h"
#include "mvme187.h"
#include "mvme327a.h"
#include "mvme350.h"
#include "mzr8105.h"
#include "mzr8300.h"
#include "smvme2000.h"
#include "sys68k_cpu1.h"
#include "sys68k_cpu20.h"
#include "sys68k_cpu30.h"
#include "sys68k_iscsi.h"
#include "sys68k_isio.h"
#include "tp881v.h"
void vme_cards(device_slot_interface &device)
{
device.option_add("cp31", VME_CP31);
device.option_add("enp10", VME_ENP10);
device.option_add("hcpu30", VME_HCPU30);
device.option_add("hk68v10", VME_HK68V10);
device.option_add("mvme120", VME_MVME120);
device.option_add("mvme121", VME_MVME121);
device.option_add("mvme122", VME_MVME122);
device.option_add("mvme123", VME_MVME123);
device.option_add("mvme147", VME_MVME147);
device.option_add("mvme180", VME_MVME180);
device.option_add("mvme181", VME_MVME181);
device.option_add("mvme187", VME_MVME187);
device.option_add("mvme327a", VME_MVME327A);
device.option_add("mzr8105", VME_MZR8105);
device.option_add("mzr8300", VME_MZR8300);
device.option_add("smvme2000", VME_SMVME2000);
device.option_add("sys68k_cpu1", VME_SYS68K_CPU1);
device.option_add("sys68k_cpu20", VME_SYS68K_CPU20);
device.option_add("sys68k_cpu21", VME_SYS68K_CPU21);
device.option_add("sys68k_cpu21a", VME_SYS68K_CPU21A);
device.option_add("sys68k_cpu21b", VME_SYS68K_CPU21B);
device.option_add("sys68k_cpu21s", VME_SYS68K_CPU21S);
device.option_add("sys68k_cpu21ya", VME_SYS68K_CPU21YA);
device.option_add("sys68k_cpu21yb", VME_SYS68K_CPU21YB);
device.option_add("sys68k_cpu30", VME_SYS68K_CPU30);
device.option_add("sys68k_cpu30x", VME_SYS68K_CPU30X);
device.option_add("sys68k_cpu30xa", VME_SYS68K_CPU30XA);
device.option_add("sys68k_cpu30za", VME_SYS68K_CPU30ZA);
device.option_add("sys68k_cpu30be", VME_SYS68K_CPU30BE);
device.option_add("sys68k_cpu30lite", VME_SYS68K_CPU30LITE);
device.option_add("sys68k_cpu33", VME_SYS68K_CPU33);
device.option_add("sys68k_iscsi1", VME_SYS68K_ISCSI1),
device.option_add("sys68k_isio1", VME_SYS68K_ISIO1),
device.option_add("tp881v", VME_TP881V);
}

11
src/devices/bus/vme/vme_cards.h Normal file
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// license:BSD-3-Clause
// copyright-holders:Patrick Mackinlay
#ifndef MAME_BUS_VME_CARDS_H
#define MAME_BUS_VME_CARDS_H
#pragma once
void vme_cards(device_slot_interface &device);
#endif // MAME_BUS_VME_CARDS_H

191
src/devices/bus/vme/vme_fccpu20.h
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@ -1,191 +0,0 @@
// license:BSD-3-Clause
// copyright-holders:Joakim Larsson Edstrom
#ifndef MAME_BUS_VME_VME_FCCPU20_H
#define MAME_BUS_VME_VME_FCCPU20_H
#pragma once
#include "bus/vme/vme.h"
#include "machine/68561mpcc.h"
#include "machine/68230pit.h"
#include "machine/68153bim.h"
DECLARE_DEVICE_TYPE(VME_FCCPU20, vme_fccpu20_card_device)
DECLARE_DEVICE_TYPE(VME_FCCPU21S, vme_fccpu21s_card_device)
DECLARE_DEVICE_TYPE(VME_FCCPU21, vme_fccpu21_card_device)
DECLARE_DEVICE_TYPE(VME_FCCPU21A, vme_fccpu21a_card_device)
DECLARE_DEVICE_TYPE(VME_FCCPU21YA, vme_fccpu21ya_card_device)
DECLARE_DEVICE_TYPE(VME_FCCPU21B, vme_fccpu21b_card_device)
DECLARE_DEVICE_TYPE(VME_FCCPU21YB, vme_fccpu21yb_card_device)
//**************************************************************************
// Base Device declaration
//**************************************************************************
class vme_fccpu20_device : public device_t, public device_vme_card_interface
{
protected:
// PIT port C Board ID bits
static constexpr unsigned CPU20 = 0x40;
static constexpr unsigned CPU21 = 0x00;
/* Board types */
enum fc_board_t {
cpu20,
cpu21,
cpu21a,
cpu21ya,
cpu21b,
cpu21yb,
cpu21s
};
vme_fccpu20_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, fc_board_t board_id);
virtual void device_start() override;
virtual void device_reset() override;
// optional information overrides
virtual void device_add_mconfig(machine_config &config) override;
virtual const tiny_rom_entry *device_rom_region() const override;
TIMER_CALLBACK_MEMBER(grant_bus);
int m_bim_irq_state;
uint8_t m_bim_irq_level;
emu_timer *m_arbiter_start; // Need a startup delay because it is hooked up to the sense inputs of the PIT
required_device<cpu_device> m_maincpu;
private:
void bim_irq_callback(int state);
/* PIT callbacks */
uint8_t pita_r();
uint8_t pitb_r();
uint8_t pitc_r();
// Below are duplicated declarations from src/mame/drivers/fccpu20.cpp
uint32_t bootvect_r(offs_t offset);
void bootvect_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
void cpu20_mem(address_map &map);
void cpu_space_map(address_map &map);
required_device<pit68230_device> m_pit;
required_device<bim68153_device> m_bim;
required_device<mpcc68561_device> m_mpcc;
required_device<mpcc68561_device> m_mpcc2;
required_device<mpcc68561_device> m_mpcc3;
// Pointer to System ROMs needed by bootvect_r and masking RAM buffer for post reset accesses
uint32_t *m_sysrom;
uint32_t m_sysram[2];
void update_irq_to_maincpu();
const fc_board_t m_board_id;
};
//**************************************************************************
// Board Device declarations
//**************************************************************************
class vme_fccpu20_card_device : public vme_fccpu20_device
{
public :
vme_fccpu20_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:
vme_fccpu20_card_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
: vme_fccpu20_device(mconfig, type, tag, owner, clock, cpu20)
{ }
// optional information overrides
virtual void device_add_mconfig(machine_config &config) override;
};
class vme_fccpu21s_card_device : public vme_fccpu20_device
{
public :
vme_fccpu21s_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:
vme_fccpu21s_card_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
: vme_fccpu20_device(mconfig, type, tag, owner, clock, cpu21s)
{ }
// optional information overrides
virtual void device_add_mconfig(machine_config &config) override;
};
class vme_fccpu21_card_device : public vme_fccpu20_device
{
public :
vme_fccpu21_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:
vme_fccpu21_card_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
: vme_fccpu20_device(mconfig, type, tag, owner, clock, cpu21)
{ }
// optional information overrides
virtual void device_add_mconfig(machine_config &config) override;
};
class vme_fccpu21a_card_device : public vme_fccpu20_device
{
public :
vme_fccpu21a_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:
vme_fccpu21a_card_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
: vme_fccpu20_device(mconfig, type, tag, owner, clock, cpu21a)
{ }
// optional information overrides
virtual void device_add_mconfig(machine_config &config) override;
};
class vme_fccpu21ya_card_device : public vme_fccpu20_device
{
public :
vme_fccpu21ya_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:
vme_fccpu21ya_card_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
: vme_fccpu20_device(mconfig, type, tag, owner, clock, cpu21ya)
{ }
// optional information overrides
virtual void device_add_mconfig(machine_config &config) override;
};
class vme_fccpu21b_card_device : public vme_fccpu20_device
{
public :
vme_fccpu21b_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:
vme_fccpu21b_card_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
: vme_fccpu20_device(mconfig, type, tag, owner, clock, cpu21b)
{ }
// optional information overrides
virtual void device_add_mconfig(machine_config &config) override;
};
class vme_fccpu21yb_card_device : public vme_fccpu20_device
{
public :
vme_fccpu21yb_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:
vme_fccpu21yb_card_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
: vme_fccpu20_device(mconfig, type, tag, owner, clock, cpu21yb)
{ }
// optional information overrides
virtual void device_add_mconfig(machine_config &config) override;
};
#endif // MAME_BUS_VME_VME_FCCPU20_H

60
src/devices/bus/vme/vme_mzr8105.cpp
View File

@ -1,60 +0,0 @@
// license:BSD-3-Clause
// copyright-holders:Joakim Larsson Edstrom
#include "emu.h"
#include "vme_mzr8105.h"
#define VERBOSE (0) // (LOG_GENERAL)
//#define LOG_OUTPUT_FUNC osd_printf_info
#include "logmacro.h"
#ifdef _MSC_VER
#define FUNCNAME __func__
#else
#define FUNCNAME __PRETTY_FUNCTION__
#endif
//**************************************************************************
// GLOBAL VARIABLES
//**************************************************************************
DEFINE_DEVICE_TYPE(VME_MZR8105, vme_mzr8105_card_device, "mzr8105", "Mizar 8105 68K CPU board")
//-------------------------------------------------
// device_add_mconfig - add device configuration
//-------------------------------------------------
void vme_mzr8105_card_device::device_add_mconfig(machine_config &config)
{
M68000(config, m_maincpu, XTAL(10'000'000))
m_maincpu->set_addrmap(AS_PROGRAM, &vme_mzr8105_card_device::mzr8105_mem);
VME(config, "vme", 0).use_owner_spaces();
VME_SLOT(config, "slot1", mzr8105_vme_cards, "mzr8300", 1, "vme");
}
vme_mzr8105_card_device::vme_mzr8105_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
vme_mzr8105_card_device(mconfig, VME_MZR8105, tag, owner, clock)
{
m_slot = 1;
LOG("%s %s\n", tag, FUNCNAME);
}
vme_mzr8105_card_device::vme_mzr8105_card_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock) :
device_t(mconfig, type, tag, owner, clock),
device_vme_card_interface(mconfig, *this)
{
LOG("%s %s\n", tag, FUNCNAME);
}
void vme_mzr8105_card_device::device_start()
{
LOG("%s %s\n", tag(), FUNCNAME);
}
void vme_mzr8105_card_device::device_reset()
{
LOG("%s %s\n", tag(), FUNCNAME);
}

27
src/devices/bus/vme/vme_mzr8105.h
View File

@ -1,27 +0,0 @@
// license:BSD-3-Clause
// copyright-holders:Joakim Larsson Edstrom
#ifndef MAME_BUS_VME_VME_MZR8105_H
#define MAME_BUS_VME_VME_MZR8105_H
#pragma once
#include "bus/vme/vme.h"
DECLARE_DEVICE_TYPE(VME_MZR8105, vme_mzr8105_card_device)
class vme_mzr8105_card_device : public device_t, public device_vme_card_interface
{
public:
vme_mzr8105_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:
vme_mzr8105_card_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
virtual void device_start() override;
virtual void device_reset() override;
// optional information overrides
virtual void device_add_mconfig(machine_config &config) override;
};
#endif // MAME_BUS_VME_VME_MZR8105_H

223
src/mame/force/fccpu20.cpp
View File

@ -1,223 +0,0 @@
// license:BSD-3-Clause
// copyright-holders:Joakim Larsson Edstrom
/***************************************************************************
*
* Force SYS68K CPU-20 and CPU-21 VME SBC drivers
*
* The only purpose of this driver is to be able to start the VME board as
* a single board computer and not as a slot device. It allows the board to
* have a layout and number of other goodies as board driver too but the chassi
* emulated here is really imaginary representing any chassi that provides power
* and used without any other VME board installed.
*
* This board occupies two mechanical slots but is only using one slot.
*
* If you want to combine multiple VME boards there are a few multi VME slot chassi
* board drivers which will allow you to do that, such as the 'miniforce' driver.
*
* +=============================+
* | CPU-20 | SYS68K/PWR-09A |
* | | |
* | RST | |
* | ABT |O +5v |
* | |O +12v |
* |O RUN O RUN|O -12v |
* |O HLT |O ON |
* |O BM | |
* | | |
* |O FLM O SL0| |
* |O EPR O SL1| |
* |O 2WS | +-------+ |
* |O 4WS | | o |PWR |
* |O 6WS | | | |
* |O 8WS | +-------+ |
* |O12WS | |
* |O14WS | |
* | | |
* | CSH | |
* | R/M | |
* | | |
* | o | |
* | o | |
* | o | |
* | o | |
* | RS232/422 | |
* | P4 P3 | |
* | | |
* |SLOT1| 1U | |
* +=============================+
*
* History of Force Computers
*---------------------------
* see fccpu30.cpp
*
* Misc links about Force Computes and this board:
*------------------------------------------------
* See the CPU-20 slot device code in vme_fccpu20.cpp
*
*---------------------------------------------------------------------------
* TODO:
* - Add front layout
****************************************************************************/
#include "emu.h"
#include "bus/vme/vme.h"
#include "bus/vme/vme_fccpu20.h"
//**************************************************************************
// CONFIGURABLE LOGGING
//**************************************************************************
#define LOG_SETUP (1U << 1)
//#define VERBOSE (LOG_GENERAL | LOG_SETUP)
//#define LOG_OUTPUT_FUNC printf
#include "logmacro.h"
#define LOGSETUP(...) LOGMASKED(LOG_SETUP, __VA_ARGS__)
//**************************************************************************
// MACROS / CONSTANTS
//**************************************************************************
#ifdef _MSC_VER
#define FUNCNAME __func__
#else
#define FUNCNAME __PRETTY_FUNCTION__
#endif
namespace {
class cpu20_state : public driver_device
{
public:
cpu20_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device (mconfig, type, tag)
{
}
virtual void machine_start () override { LOGSETUP("%s\n", FUNCNAME); }
// virtual void machine_reset () override;
void init_cpu20() { LOGSETUP("%s\n", FUNCNAME); }
void init_cpu21s() { LOGSETUP("%s\n", FUNCNAME); }
void init_cpu21() { LOGSETUP("%s\n", FUNCNAME); }
void init_cpu21a() { LOGSETUP("%s\n", FUNCNAME); }
void init_cpu21ya() { LOGSETUP("%s\n", FUNCNAME); }
void init_cpu21b() { LOGSETUP("%s\n", FUNCNAME); }
void init_cpu21yb() { LOGSETUP("%s\n", FUNCNAME); }
void cpu21(machine_config &config);
void cpu20(machine_config &config);
void cpu21yb(machine_config &config);
void cpu21s(machine_config &config);
void cpu21b(machine_config &config);
void cpu21ya(machine_config &config);
void cpu21a(machine_config &config);
};
/* Input ports */
static INPUT_PORTS_START (cpu20)
INPUT_PORTS_END
/* Slot interfaces */
static void cpu20_vme_cards(device_slot_interface &device)
{
device.option_add("fccpu20", VME_FCCPU20);
}
static void cpu21s_vme_cards(device_slot_interface &device)
{
device.option_add("fccpu21s", VME_FCCPU21S);
}
static void cpu21_vme_cards(device_slot_interface &device)
{
device.option_add("fccpu21", VME_FCCPU21);
}
static void cpu21a_vme_cards(device_slot_interface &device)
{
device.option_add("fccpu21a", VME_FCCPU21A);
}
static void cpu21ya_vme_cards(device_slot_interface &device)
{
device.option_add("fccpu21ya", VME_FCCPU21YA);
}
static void cpu21b_vme_cards(device_slot_interface &device)
{
device.option_add("fccpu21b", VME_FCCPU21B);
}
static void cpu21yb_vme_cards(device_slot_interface &device)
{
device.option_add("fccpu21yb", VME_FCCPU21YB);
}
/* Machine configurations */
void cpu20_state::cpu20(machine_config &config)
{
VME(config, "vme", 0);
VME_SLOT(config, "slot1", cpu20_vme_cards, "fccpu20", 1, "vme");
}
void cpu20_state::cpu21s(machine_config &config)
{
VME(config, "vme", 0);
VME_SLOT(config, "slot1", cpu21s_vme_cards, "fccpu21s", 1, "vme");
}
void cpu20_state::cpu21(machine_config &config)
{
VME(config, "vme", 0);
VME_SLOT(config, "slot1", cpu21_vme_cards, "fccpu21", 1, "vme");
}
void cpu20_state::cpu21a(machine_config &config)
{
VME(config, "vme", 0);
VME_SLOT(config, "slot1", cpu21a_vme_cards, "fccpu21a", 1, "vme");
}
void cpu20_state::cpu21ya(machine_config &config)
{
VME(config, "vme", 0);
VME_SLOT(config, "slot1", cpu21ya_vme_cards, "fccpu21ya", 1, "vme");
}
void cpu20_state::cpu21b(machine_config &config)
{
VME(config, "vme", 0);
VME_SLOT(config, "slot1", cpu21b_vme_cards, "fccpu21b", 1, "vme");
}
void cpu20_state::cpu21yb(machine_config &config)
{
VME(config, "vme", 0);
VME_SLOT(config, "slot1", cpu21yb_vme_cards, "fccpu21yb", 1, "vme");
}
/* ROM configurations */
ROM_START(fccpu20sbc) ROM_END
/* Boards supported by same rom set, need to do like this to avoid need for multi named rom sets */
#define rom_fccpu21ssbc rom_fccpu20sbc
#define rom_fccpu21sbc rom_fccpu20sbc
#define rom_fccpu21asbc rom_fccpu20sbc
#define rom_fccpu21yasbc rom_fccpu20sbc
#define rom_fccpu21bsbc rom_fccpu20sbc
#define rom_fccpu21ybsbc rom_fccpu20sbc
} // anonymous namespace
/* Driver */
/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS */
COMP( 1986, fccpu20sbc, 0, 0, cpu20, cpu20, cpu20_state, empty_init, "Force Computers GmbH", "SYS68K/CPU-20", MACHINE_NO_SOUND_HW )
COMP( 1986, fccpu21ssbc, fccpu20sbc, 0, cpu21s, cpu20, cpu20_state, init_cpu21s, "Force Computers GmbH", "SYS68K/CPU-21S", MACHINE_NO_SOUND_HW )
COMP( 1986, fccpu21sbc, fccpu20sbc, 0, cpu21, cpu20, cpu20_state, init_cpu21, "Force Computers GmbH", "SYS68K/CPU-21", MACHINE_NO_SOUND_HW )
COMP( 1986, fccpu21asbc, fccpu20sbc, 0, cpu21a, cpu20, cpu20_state, init_cpu21a, "Force Computers GmbH", "SYS68K/CPU-21A", MACHINE_NO_SOUND_HW )
COMP( 1986, fccpu21yasbc, fccpu20sbc, 0, cpu21ya, cpu20, cpu20_state, init_cpu21ya, "Force Computers GmbH", "SYS68K/CPU-21YA", MACHINE_NO_SOUND_HW )
COMP( 1986, fccpu21bsbc, fccpu20sbc, 0, cpu21b, cpu20, cpu20_state, init_cpu21b, "Force Computers GmbH", "SYS68K/CPU-21B", MACHINE_NO_SOUND_HW )
COMP( 1986, fccpu21ybsbc, fccpu20sbc, 0, cpu21yb, cpu20, cpu20_state, init_cpu21yb, "Force Computers GmbH", "SYS68K/CPU-21YB", MACHINE_NO_SOUND_HW )

54
src/mame/force/miniforce.cpp
View File

@ -97,13 +97,11 @@
*/
#include "emu.h"
#include "bus/vme/vme.h"
#include "bus/vme/vme_cp31.h"
#include "bus/vme/vme_fccpu20.h"
#include "bus/vme/vme_fcisio.h"
#include "bus/vme/vme_fcscsi.h"
#include "bus/vme/vme_mzr8300.h"
#include "bus/vme/vme_hcpu30.h"
#include "machine/clock.h"
#include "bus/vme/cp31.h"
#include "bus/vme/hcpu30.h"
#include "bus/vme/sys68k_cpu20.h"
#include "bus/vme/sys68k_iscsi.h"
#include "bus/vme/sys68k_isio.h"
#define VERBOSE (0) // (LOG_GENERAL)
//#define LOG_OUTPUT_FUNC printf
@ -132,22 +130,8 @@ public:
private:
virtual void machine_start() override;
virtual void machine_reset() override;
void miniforce_mem(address_map &map);
};
#if 0
void miniforce_state::miniforce_mem(address_map &map)
{
map.unmap_value_high();
/* The ROMs contains an OS9 bootloader. It is position independent but reset vector suggests that it sits flat on adress 0 (zero) */
// map(0x000000, 0x003fff).rom().region("roms", 0x000000); /* System EPROM Area 16Kb OS9 DEBUG - not verified */
// map(0x004000, 0x01ffff).rom().region("roms", 0x004000);/* System EPROM Area 112Kb for System ROM - not verified */
// map(0x020000, 0x03ffff).ram(); /* Not verified */
// map(0x100000, 0xfeffff).rw(FUNC(miniforce_state::vme_a24_r), FUNC(miniforce_state::vme_a24_w)); /* VMEbus Rev B addresses (24 bits) - not verified */
// map(0xff0000, 0xffffff).rw(FUNC(miniforce_state::vme_a16_r), FUNC(miniforce_state::vme_a16_w)); /* VMEbus Rev B addresses (16 bits) - not verified */
}
#endif
/* Start it up */
void miniforce_state::machine_start()
{
@ -166,10 +150,10 @@ INPUT_PORTS_END
static void miniforce_vme_cards(device_slot_interface &device)
{
device.option_add("cp31", VME_CP31);
device.option_add("fccpu21", VME_FCCPU21);
device.option_add("fcisio", VME_FCISIO1);
device.option_add("fcscsi", VME_FCSCSI1);
device.option_add("cp31", VME_CP31);
device.option_add("cpu21", VME_SYS68K_CPU21);
device.option_add("isio", VME_SYS68K_ISIO1);
device.option_add("iscsi", VME_SYS68K_ISCSI1);
device.option_add("hcpu30", VME_HCPU30);
}
@ -179,16 +163,16 @@ static void miniforce_vme_cards(device_slot_interface &device)
void miniforce_state::miniforce(machine_config &config)
{
// ->set_addrmap(AS_PROGRAM, &miniforce_state::miniforce_mem);
VME(config, "vme", 0);
VME_SLOT(config, "slot1", miniforce_vme_cards, "fccpu21", 1, "vme");
VME_SLOT(config, "slot2", miniforce_vme_cards, nullptr, 2, "vme");
VME_SLOT(config, "slot3", miniforce_vme_cards, nullptr, 3, "vme");
VME_SLOT(config, "slot4", miniforce_vme_cards, nullptr, 4, "vme");
VME_SLOT(config, "slot5", miniforce_vme_cards, nullptr, 5, "vme");
VME_SLOT(config, "slot6", miniforce_vme_cards, nullptr, 6, "vme");
VME_SLOT(config, "slot7", miniforce_vme_cards, nullptr, 7, "vme");
VME_SLOT(config, "slot8", miniforce_vme_cards, nullptr, 8, "vme");
VME_SLOT(config, "slot9", miniforce_vme_cards, nullptr, 9, "vme");
VME(config, "vme");
VME_SLOT(config, "vme:slot1", miniforce_vme_cards, "cpu21");
VME_SLOT(config, "vme:slot2", miniforce_vme_cards, nullptr);
VME_SLOT(config, "vme:slot3", miniforce_vme_cards, nullptr);
VME_SLOT(config, "vme:slot4", miniforce_vme_cards, nullptr);
VME_SLOT(config, "vme:slot5", miniforce_vme_cards, nullptr);
VME_SLOT(config, "vme:slot6", miniforce_vme_cards, nullptr);
VME_SLOT(config, "vme:slot7", miniforce_vme_cards, nullptr);
VME_SLOT(config, "vme:slot8", miniforce_vme_cards, nullptr);
VME_SLOT(config, "vme:slot9", miniforce_vme_cards, nullptr);
}
ROM_START(miniforce)

42
src/mame/mame.lst
View File

@ -17872,32 +17872,6 @@ vcc //
@source:fidelity/vsc.cpp
vsc //
@source:force/fccpu20.cpp
fccpu20sbc
fccpu21ssbc
fccpu21sbc
fccpu21asbc
fccpu21yasbc
fccpu21bsbc
fccpu21ybsbc
@source:force/fccpu30.cpp
fccpu30
fccpu30x
fccpu30xa
fccpu30za
fccpu30zbe
fccpu30be8
fccpu30be16
fccpu30lite4
fccpu30lite8
fccpu30senr
fccpu30senr501
fccpu33
@source:force/force68k.cpp
fccpu1 //
@source:force/miniforce.cpp
miniforce // D26 cabinet test board
@ -19346,9 +19320,6 @@ smondialab // 1986 Mephisto Super Mondial (Ver AB)
smondialb // 1986 Mephisto Super Mondial (Ver B)
smondial2 // 1989 Mephisto Super Mondial II
@source:heurikon/hk68v10.cpp
hk68v10 //
@source:hitachi/b16.cpp
b16 //
@ -31978,9 +31949,6 @@ multi16 //
@source:mitsubishi/trium.cpp
triumec //
@source:mizar/mzr8105.cpp
mzr8105 //
@source:morrow/microdec.cpp
md2 //
md3 //
@ -32027,9 +31995,6 @@ mekd4 // 1980 Motorola Evaluation Kit
@source:motorola/mekd5.cpp
mekd5 // 1980 Motorola Evaluation Kit
@source:motorola/mvme147.cpp
mvme147 // (c) 1989 Motorola
@source:motorola/mvme162.cpp
mvme162 // (c) 1993 Motorola
@ -40825,9 +40790,6 @@ indy_4613 // IP22: Indy, R4600, 133MHz
indy_5015 // IP22: Indy, R5000, 150MHz
indigo2_4415 // IP24: Indigo 2, R4400, 150MHz
@source:sgi/ip4.cpp
pi4d50 // Professional IRIS 4D/50 (R2000 @ 8MHz)
@source:sgi/ip6.cpp
pi4d20 // Personal IRIS 4D/20 (R2000 @ 12.5MHz)
pi4d25 // Personal IRIS 4D/25 (R3000 @ 20MHz)
@ -40853,6 +40815,10 @@ o2 // (c) 1996 SGI
@source:sgi/octane.cpp
octane // (c) 1997 SGI
@source:sgi/tt.cpp
pi4d50 // Professional IRIS 4D/50 (R2000 @ 8MHz)
pi4d70 // Professional IRIS 4D/70 (R2000 @ 12.5MHz)
@source:sharp/fontwriter.cpp
fw600 // (c) Sharp
fw700ger // (c) Sharp

7
src/mame/motorola/m8120.cpp
View File

@ -7,6 +7,7 @@
#include "emu.h"
#include "bus/vme/vme.h"
#include "bus/vme/mvme187.h"
namespace {
@ -24,11 +25,9 @@ public:
void m8120_state::m8120(machine_config &config)
{
VME(config, "vme", 0);
VME(config, "vme");
vme_slot_device &slot(VME_SLOT(config, "vme:0", 0));
slot.set_vme_slot("vme", 0);
slot.option_set("mvme187", MVME187);
VME_SLOT(config, "vme:slot1").option_set("mvme187", VME_MVME187);
}
ROM_START(m8120)

39
src/mame/motorola/sys1121.cpp
View File

@ -10,12 +10,8 @@
#include "emu.h"
#include "bus/vme/tp881v.h"
#include "bus/vme/vme_mvme120.h"
#include "bus/vme/vme_mvme180.h"
#include "bus/vme/vme_mvme181.h"
#include "bus/vme/vme_mvme327a.h"
#include "bus/vme/vme_smvme2000.h"
#include "bus/vme/vme.h"
#include "bus/vme/vme_cards.h"
namespace {
@ -35,30 +31,17 @@ public:
INPUT_PORTS_START(sys1121)
INPUT_PORTS_END
void sys1121_vme_cards(device_slot_interface &device)
{
device.option_add("mvme120", VME_MVME120);
device.option_add("mvme121", VME_MVME121);
device.option_add("mvme122", VME_MVME122);
device.option_add("mvme123", VME_MVME123);
device.option_add("smvme2000", VME_SMVME2000);
device.option_add("mvme180", VME_MVME180);
device.option_add("mvme181", VME_MVME181);
device.option_add("mvme327a", VME_MVME327A);
device.option_add("tp881v", TP881V);
}
void sys1121_state::sys1121(machine_config &config)
{
VME(config, "vme", 0);
VME_SLOT(config, "slot1", sys1121_vme_cards, "mvme120", 1, "vme");
VME_SLOT(config, "slot2", sys1121_vme_cards, nullptr, 2, "vme");
VME_SLOT(config, "slot3", sys1121_vme_cards, nullptr, 3, "vme");
VME_SLOT(config, "slot4", sys1121_vme_cards, nullptr, 4, "vme");
VME_SLOT(config, "slot5", sys1121_vme_cards, nullptr, 5, "vme");
VME_SLOT(config, "slot6", sys1121_vme_cards, nullptr, 6, "vme");
VME_SLOT(config, "slot7", sys1121_vme_cards, nullptr, 7, "vme");
VME_SLOT(config, "slot8", sys1121_vme_cards, nullptr, 8, "vme");
VME(config, "vme");
VME_SLOT(config, "vme:slot1", vme_cards, "mvme120");
VME_SLOT(config, "vme:slot2", vme_cards, nullptr);
VME_SLOT(config, "vme:slot3", vme_cards, nullptr);
VME_SLOT(config, "vme:slot4", vme_cards, nullptr);
VME_SLOT(config, "vme:slot5", vme_cards, nullptr);
VME_SLOT(config, "vme:slot6", vme_cards, nullptr);
VME_SLOT(config, "vme:slot7", vme_cards, nullptr);
VME_SLOT(config, "vme:slot8", vme_cards, nullptr);
}
// This is a VME chassis so any ROMs are contained in the cards.

389
src/mame/sgi/ip4.cpp
View File

@ -2,198 +2,110 @@
// copyright-holders:Patrick Mackinlay
/*
* Silicon Graphics Professional IRIS 4D/50 and 4D/70.
*
* Year Model Board CPU Clock I/D Cache Code Name
* 1987 4D/50 IP4 R2000 8MHz 64KiB/32KiB Twin Tower
* 1987 4D/70 IP4 R2000 12.5MHz 64KiB/32KiB Twin Tower
*
* Sources:
* - VME-Eclipse CPU (VIP10) Specification, Silicon Graphics, Inc.
*
* TODO:
* - configurable ram size
* - diagnostics
* - VME bus
* - graphics
*
* WIP:
* - can boot to monitor
* - failing diagnostics: VME, duarts, lio interrupts, fpu
*/
/*
* SCN2681AC1N40 x 2
* SCN2681AC1N24
* P8254
* CXK5816PN-15L 2,048x8 SRAM
* WD33C93-PL
* DS1216? SmartWatch RAM
* SAA1099
*
* 16MHz
* 10MHz
* 8MHz
* 3.6864MHz
* Silicon Graphics Professional IRIS 4D/50 and 4D/70 CPU board.
*/
#include "emu.h"
#include "ip4.h"
#include "kbd.h"
// cpu and memory
#include "cpu/mips/mips1.h"
// other devices
#include "machine/ds1315.h"
#include "machine/mc68681.h"
#include "machine/nvram.h"
#include "machine/pit8253.h"
#include "machine/wd33c9x.h"
#include "sound/saa1099.h"
// buses and connectors
#include "machine/nscsi_bus.h"
#include "machine/nvram.h"
#include "bus/nscsi/hd.h"
#include "bus/nscsi/cd.h"
#include "bus/rs232/rs232.h"
#include "bus/rs232/hlemouse.h"
#include "kbd.h"
#include "speaker.h"
#define LOG_PARITY (1U << 1)
#define LOG_VME (1U << 2)
//#define VERBOSE (LOG_PARITY)
#define VERBOSE (0)
#include "logmacro.h"
namespace {
DEFINE_DEVICE_TYPE(SGI_IP4, sgi_ip4_device, "sgi_ip4", "SGI IP4")
class ip4_state : public driver_device
sgi_ip4_device::sgi_ip4_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock)
: device_t(mconfig, SGI_IP4, tag, owner, clock)
, device_vme_card_interface(mconfig, *this)
, m_cpu(*this, "cpu")
, m_rtc(*this, "rtc")
, m_pit(*this, "pit")
, m_scsi(*this, "scsi:0:wd33c93")
, m_duart(*this, "duart%u", 0U)
, m_serial(*this, "serial%u", 0U)
, m_saa(*this, "saa")
, m_nvram(*this, "nvram", 0x800, ENDIANNESS_BIG)
, m_ram(*this, "ram")
, m_leds(*this, "led%u", 0U)
{
public:
ip4_state(machine_config const &mconfig, device_type type, char const *tag)
: driver_device(mconfig, type, tag)
, m_cpu(*this, "cpu")
, m_rtc(*this, "rtc")
, m_pit(*this, "pit")
, m_scsi(*this, "scsi:0:wd33c93")
, m_duart(*this, "duart%u", 0U)
, m_serial(*this, "serial%u", 0U)
, m_saa(*this, "saa")
, m_nvram(*this, "nvram", 0x800, ENDIANNESS_BIG)
, m_leds(*this, "led%u", 0U)
{
}
}
void pi4d50(machine_config &config);
protected:
virtual void machine_start() override;
virtual void machine_reset() override;
void common(machine_config &config);
void map(address_map &map);
template <unsigned N> void lio_interrupt(int state) { lio_interrupt(N, state); }
void lio_interrupt(unsigned number, int state);
void scsi_drq(int state);
u16 cpucfg_r() { return m_cpucfg; }
void cpucfg_w(u16 data);
void parity_r(offs_t offset, u32 &data, u32 mem_mask);
void parity_w(offs_t offset, u32 &data, u32 mem_mask);
enum cpucfg_mask : u16
{
CPUCFG_LEDS = 0x001f,
CPUCFG_S01 = 0x0040, // enable serial ports 0,1
CPUCFG_S23 = 0x0080, // enable serial ports 2,3
CPUCFG_MAIL = 0x0100, // enable mailbox interrupts
CPUCFG_SIN = 0x0200, // VME sysreset (reset)
CPUCFG_RPAR = 0x0400, // enable parity checking
CPUCFG_SLA = 0x0800, // enable slave accesses
CPUCFG_ARB = 0x1000, // enable VME arbiter
CPUCFG_BAD = 0x2000, // write bad parity
CPUCFG_DOG = 0x4000, // enable watchdog timout
CPUCFG_AUX2 = 0x8000, // unused
};
enum parerr_mask : u8
{
PAR_LAN = 0x01,
PAR_DMA = 0x02,
PAR_CPU = 0x04,
PAR_VME = 0x08,
PAR_B3 = 0x10, // parity errory byte 3
PAR_B2 = 0x20, // parity errory byte 2
PAR_B1 = 0x40, // parity errory byte 1
PAR_B0 = 0x80, // parity errory byte 0
PAR_ALL = 0xf0, // parity errory all bytes
};
enum lio_int_number : unsigned
{
LIO_D0 = 0, // duart 0
LIO_D1 = 1, // duart 1
LIO_D2 = 2, // duart 2
// unused
LIO_SCSI = 4, // scsi
// unused
LIO_MAIL = 6, // VME mailbox
LIO_AC = 7, // VME AC fail
};
private:
required_device<mips1_device_base> m_cpu;
required_device<ds1315_device> m_rtc;
required_device<pit8254_device> m_pit;
required_device<wd33c9x_base_device> m_scsi;
required_device_array<scn2681_device, 3> m_duart;
required_device_array<rs232_port_device, 4> m_serial;
required_device<saa1099_device> m_saa;
memory_share_creator<u8> m_nvram;
output_finder<5> m_leds;
// machine registers
u16 m_cpucfg;
u16 m_dmalo;
u16 m_dmahi;
u8 m_lio_isr;
u8 m_parerr;
u32 m_erradr;
// other machine state
std::unique_ptr<u8[]> m_parity;
memory_passthrough_handler m_parity_mph;
u32 m_parity_bad;
bool m_lio_int;
enum cpucfg_mask : u16
{
CPUCFG_LEDS = 0x001f,
CPUCFG_S01 = 0x0040, // enable serial ports 0,1
CPUCFG_S23 = 0x0080, // enable serial ports 2,3
CPUCFG_MAIL = 0x0100, // enable mailbox interrupts
CPUCFG_SIN = 0x0200, // VME sysreset (reset)
CPUCFG_RPAR = 0x0400, // enable parity checking
CPUCFG_SLA = 0x0800, // enable slave accesses
CPUCFG_ARB = 0x1000, // enable VME arbiter
CPUCFG_BAD = 0x2000, // write bad parity
CPUCFG_DOG = 0x4000, // enable watchdog timout
CPUCFG_AUX2 = 0x8000, // unused
};
void ip4_state::map(address_map &map)
enum parerr_mask : u8
{
//map(0x1c00'0000, 0x1cff'ffff); // vme a24 modifier 0x3d privileged
//map(0x1d00'0000, 0x1d00'ffff); // vme a16 modifier 0x2d privileged
//map(0x1d10'0000, 0x1d10'ffff); // vme a16 modifier 0x29 non-privileged
//map(0x1df0'0000, 0x1dff'ffff).umask32(0x0000'ff00); // VME_IACK: vme interrupt acknowledge
//map(0x1e00'0000, 0x1eff'ffff); // vme a24 modifier 0x39 non-privileged
PAR_LAN = 0x01,
PAR_DMA = 0x02,
PAR_CPU = 0x04,
PAR_VME = 0x08,
PAR_B3 = 0x10, // parity error byte 3
PAR_B2 = 0x20, // parity error byte 2
PAR_B1 = 0x40, // parity error byte 1
PAR_B0 = 0x80, // parity error byte 0
PAR_ALL = 0xf0, // parity error all bytes
};
enum lio_int_number : unsigned
{
LIO_D0 = 0, // duart 0
LIO_D1 = 1, // duart 1
LIO_D2 = 2, // duart 2
// unused
LIO_SCSI = 4, // scsi
// unused
LIO_MAIL = 6, // VME mailbox
LIO_AC = 7, // VME acfail
};
void sgi_ip4_device::map(address_map &map)
{
// TODO: 4 banks of 4 SIMMs with parity
map(0x0000'0000, 0x007f'ffff).ram();
map(0x0000'0000, 0x007f'ffff).ram().share("ram");
map(0x1000'0000, 0x1bff'ffff).rw(&device_vme_card_interface::vme_read32<vme::AM_09,0x1000'0000>, "read", &device_vme_card_interface::vme_write32<vme::AM_09,0x1000'0000>, "write");
map(0x1c00'0000, 0x1cff'ffff).rw(FUNC(device_vme_card_interface::vme_read32<vme::AM_3d>), FUNC(device_vme_card_interface::vme_write32<vme::AM_3d>));
map(0x1d00'0000, 0x1d00'ffff).rw(FUNC(device_vme_card_interface::vme_read32<vme::AM_2d>), FUNC(device_vme_card_interface::vme_write32<vme::AM_2d>));
map(0x1d10'0000, 0x1d10'ffff).rw(FUNC(device_vme_card_interface::vme_read32<vme::AM_29>), FUNC(device_vme_card_interface::vme_write32<vme::AM_29>));
map(0x1df0'0000, 0x1df0'000f).lr16(NAME([this](offs_t offset) { return vme_iack_r(offset << 1); })).mirror(0xf'fff0);
map(0x1e00'0000, 0x1eff'ffff).rw(FUNC(device_vme_card_interface::vme_read32<vme::AM_39>), FUNC(device_vme_card_interface::vme_write32<vme::AM_39>));
map(0x2000'0000, 0x2fff'ffff).rw(FUNC(device_vme_card_interface::vme_read32<vme::AM_09>), FUNC(device_vme_card_interface::vme_write32<vme::AM_09>));
map(0x1f60'0000, 0x1f60'0003).umask32(0xff00'0000).w(m_saa, FUNC(saa1099_device::data_w));
map(0x1f60'0010, 0x1f60'0013).umask32(0xff00'0000).w(m_saa, FUNC(saa1099_device::control_w));
map(0x1f80'0000, 0x1f80'0003).umask32(0x00ff'0000).lr8(NAME([]() { return 0; })); // system id prom/coprocessor present
map(0x1f80'0000, 0x1f80'0003).umask32(0x00ff'0000).lr8(NAME([]() { return 0; })); // TODO: system id prom/coprocessor present
//map(0x1f840000, 0x1f840003).umask32(0x0000'00ff).lrw8(NAME([this]() { return m_vme_isr; }), NAME([this](u8 data) { m_vme_isr = data; }));
//map(0x1f840008, 0x1f84000b).umask32(0x0000'00ff).lrw8(NAME([this]() { return m_vme_imr; }), NAME([this](u8 data) { m_vme_imr = data; }));
map(0x1f84'0000, 0x1f84'0003).umask32(0x0000'00ff).lrw8(NAME([this]() { LOG("vme_isr_r 0x%02x\n", m_vme_isr); return m_vme_isr; }), NAME([this](u8 data) { LOG("vme_isr_w 0x%02x\n", data); m_vme_isr = data; }));
map(0x1f84'0008, 0x1f84'000b).umask32(0x0000'00ff).lrw8(NAME([this]() { LOG("vme_imr_r 0x%02x\n", m_vme_imr); return m_vme_imr; }), NAME([this](u8 data) { LOG("vme_imr_w 0x%02x\n", data); m_vme_imr = data; }));
map(0x1f88'0000, 0x1f88'0003).umask32(0x0000'ffff).rw(FUNC(ip4_state::cpucfg_r), FUNC(ip4_state::cpucfg_w));
map(0x1f88'0000, 0x1f88'0003).umask32(0x0000'ffff).rw(FUNC(sgi_ip4_device::cpucfg_r), FUNC(sgi_ip4_device::cpucfg_w));
map(0x1f90'0000, 0x1f90'0003).umask32(0x0000'ffff).lw16(NAME([this](u16 data) { m_dmalo = data; }));
map(0x1f92'0000, 0x1f92'0003).umask32(0x0000'ffff).lw16(NAME([this](u16 data) { m_dmahi = data; }));
@ -201,15 +113,15 @@ void ip4_state::map(address_map &map)
map(0x1f98'0000, 0x1f98'0003).umask32(0x0000'00ff).lr8(NAME([this]() { return m_lio_isr; }));
map(0x1f9a'0000, 0x1f9a'0003).nopr(); // switches
map(0x1f9a'0000, 0x1f9a'0003).nopr(); // TODO: switches
map(0x1fa0'0000, 0x1fa0'0003).umask32(0xff00'0000).lr8(NAME([this]() { m_cpu->set_input_line(INPUT_LINE_IRQ4, 0); return 0; }));
map(0x1fa2'0000, 0x1fa2'0003).umask32(0xff00'0000).lr8(NAME([this]() { m_cpu->set_input_line(INPUT_LINE_IRQ2, 0); return 0; }));
map(0x1fa4'0000, 0x1fa4'0003).lr32([this]() { return m_erradr; }, "sbe");
map(0x1fa4'0000, 0x1fa4'0003).lr32(NAME([this]() { m_cpu->set_input_line(INPUT_LINE_IRQ5, 0); return m_erradr; }));
map(0x1fa8'0000, 0x1fa8'0003).umask32(0xff00'0000).lr8(NAME([this]() { m_scsi->reset_w(0); return 0; }));
map(0x1fa8'0004, 0x1fa8'0007).umask32(0xff00'0000).lr8(NAME([this]() { m_scsi->reset_w(1); return 0; }));
//map(0x1fa60000, 0x1fa60003).umask32(0xff00'0000); // vme rmw
//map(0x1fa60000, 0x1fa60003).umask32(0xff00'0000); // TODO: vme rmw
map(0x1faa0000, 0x1faa0003).lrw8(
NAME([this](offs_t offset) { m_parerr &= ~(PAR_ALL | (1U << offset)); return 0; }),
NAME([this](offs_t offset, u8 data) { m_parerr &= ~(PAR_ALL | (1U << offset)); }));
@ -246,17 +158,11 @@ static void scsi_devices(device_slot_interface &device)
device.option_add("harddisk", NSCSI_HARDDISK);
}
void ip4_state::pi4d50(machine_config &config)
void sgi_ip4_device::device_add_mconfig(machine_config &config)
{
R2000(config, m_cpu, 16_MHz_XTAL / 2, 65536, 32768);
R2000(config, m_cpu, clock() / 2, 65536, 32768);
m_cpu->set_fpu(mips1_device_base::MIPS_R2010);
common(config);
}
void ip4_state::common(machine_config &config)
{
m_cpu->set_addrmap(AS_PROGRAM, &ip4_state::map);
m_cpu->set_addrmap(AS_PROGRAM, &sgi_ip4_device::map);
m_cpu->in_brcond<0>().set([]() { return 1; }); // writeback complete
DS1315(config, m_rtc, 0); // DS1216?
@ -277,8 +183,8 @@ void ip4_state::common(machine_config &config)
wd33c9x_base_device &wd33c93(downcast<wd33c9x_base_device &>(*device));
wd33c93.set_clock(10'000'000);
wd33c93.irq_cb().set(*this, FUNC(ip4_state::lio_interrupt<LIO_SCSI>)).invert();
wd33c93.drq_cb().set(*this, FUNC(ip4_state::scsi_drq));
wd33c93.irq_cb().set(*this, FUNC(sgi_ip4_device::lio_irq<LIO_SCSI>)).invert();
wd33c93.drq_cb().set(*this, FUNC(sgi_ip4_device::scsi_drq));
});
NSCSI_CONNECTOR(config, "scsi:1", scsi_devices, "harddisk", false);
NSCSI_CONNECTOR(config, "scsi:2", scsi_devices, nullptr, false);
@ -290,6 +196,7 @@ void ip4_state::common(machine_config &config)
// duart 0 (keyboard/mouse)
SCN2681(config, m_duart[0], 3.6864_MHz_XTAL); // SCN2681AC1N24
sgi_kbd_port_device &keyboard_port(SGI_KBD_PORT(config, "keyboard_port", default_sgi_kbd_devices, nullptr));
rs232_port_device &mouse_port(RS232_PORT(config, "mouse_port",
[](device_slot_interface &device)
@ -299,7 +206,7 @@ void ip4_state::common(machine_config &config)
nullptr));
// duart 0 outputs
m_duart[0]->irq_cb().set(FUNC(ip4_state::lio_interrupt<LIO_D0>)).invert();
m_duart[0]->irq_cb().set(FUNC(sgi_ip4_device::lio_irq<LIO_D0>)).invert();
m_duart[0]->a_tx_cb().set(keyboard_port, FUNC(sgi_kbd_port_device::write_txd));
m_duart[0]->b_tx_cb().set(mouse_port, FUNC(rs232_port_device::write_txd));
@ -313,7 +220,7 @@ void ip4_state::common(machine_config &config)
RS232_PORT(config, m_serial[1], default_rs232_devices, nullptr);
// duart 1 outputs
m_duart[1]->irq_cb().set(FUNC(ip4_state::lio_interrupt<LIO_D1>)).invert();
m_duart[1]->irq_cb().set(FUNC(sgi_ip4_device::lio_irq<LIO_D1>)).invert();
m_duart[1]->a_tx_cb().set(m_serial[0], FUNC(rs232_port_device::write_txd));
m_duart[1]->b_tx_cb().set(m_serial[1], FUNC(rs232_port_device::write_txd));
m_duart[1]->outport_cb().set(
@ -342,7 +249,7 @@ void ip4_state::common(machine_config &config)
RS232_PORT(config, m_serial[3], default_rs232_devices, nullptr);
// duart 2 outputs
m_duart[2]->irq_cb().set(FUNC(ip4_state::lio_interrupt<LIO_D2>)).invert();
m_duart[2]->irq_cb().set(FUNC(sgi_ip4_device::lio_irq<LIO_D2>)).invert();
m_duart[2]->a_tx_cb().set(m_serial[2], FUNC(rs232_port_device::write_txd));
m_duart[2]->b_tx_cb().set(m_serial[3], FUNC(rs232_port_device::write_txd));
m_duart[2]->outport_cb().set(
@ -365,6 +272,7 @@ void ip4_state::common(machine_config &config)
m_serial[3]->cts_handler().set(m_duart[2], FUNC(scn2681_device::ip1_w));
m_serial[3]->dcd_handler().set(m_duart[2], FUNC(scn2681_device::ip2_w));
// TODO: move speakers to host
SPEAKER(config, "lspeaker").front_left();
SPEAKER(config, "rspeaker").front_right();
@ -373,24 +281,45 @@ void ip4_state::common(machine_config &config)
m_saa->add_route(1, "rspeaker", 0.5);
}
void ip4_state::machine_start()
void sgi_ip4_device::device_config_complete()
{
// TODO: ACFAIL -> vme_irq<0>
device_vme_card_interface::vme_irq<1>().append(*this, FUNC(sgi_ip4_device::vme_irq<1>));
device_vme_card_interface::vme_irq<2>().append(*this, FUNC(sgi_ip4_device::vme_irq<2>));
device_vme_card_interface::vme_irq<3>().append(*this, FUNC(sgi_ip4_device::vme_irq<3>));
device_vme_card_interface::vme_irq<4>().append(*this, FUNC(sgi_ip4_device::vme_irq<4>));
device_vme_card_interface::vme_irq<5>().append(*this, FUNC(sgi_ip4_device::vme_irq<5>));
device_vme_card_interface::vme_irq<6>().append(*this, FUNC(sgi_ip4_device::vme_irq<6>));
device_vme_card_interface::vme_irq<7>().append(*this, FUNC(sgi_ip4_device::vme_irq<7>));
vme_berr().set_inputline(m_cpu, INPUT_LINE_IRQ5).invert();
}
void sgi_ip4_device::device_start()
{
m_leds.resolve();
save_item(NAME(m_cpucfg));
save_item(NAME(m_lio_isr));
save_item(NAME(m_lio_int));
save_item(NAME(m_dmalo));
save_item(NAME(m_dmahi));
save_item(NAME(m_erradr));
save_item(NAME(m_lio_isr));
save_item(NAME(m_vme_isr));
save_item(NAME(m_vme_imr));
save_item(NAME(m_parerr));
save_item(NAME(m_erradr));
save_item(NAME(m_lio_irq));
save_item(NAME(m_vme_irq));
m_cpucfg = 0;
m_lio_isr = 0xff;
m_lio_int = false;
m_dmalo = 0;
m_dmahi = 0;
m_lio_isr = 0xff;
m_vme_isr = 0;
m_vme_imr = 0;
m_lio_irq = false;
m_vme_irq = false;
// install phantom rtc with a memory tap
m_cpu->space(AS_PROGRAM).install_readwrite_tap(0x1fbc'1ffc, 0x1fbc'1fff, "rtc",
@ -415,13 +344,13 @@ void ip4_state::machine_start()
m_parity_bad = 0;
}
void ip4_state::machine_reset()
void sgi_ip4_device::device_reset()
{
m_erradr = 0;
m_parerr = 0;
m_erradr = 0;
}
void ip4_state::lio_interrupt(unsigned number, int state)
void sgi_ip4_device::lio_irq(unsigned number, int state)
{
// record interrupt state
if (state)
@ -430,15 +359,32 @@ void ip4_state::lio_interrupt(unsigned number, int state)
m_lio_isr &= ~(1U << number);
// update interrupt line
bool const lio_int = !m_lio_isr;
if (m_lio_int ^ lio_int)
bool const lio_irq = (m_lio_isr ^ 0xff);
if (m_lio_irq ^ lio_irq)
{
m_lio_int = lio_int;
m_cpu->set_input_line(INPUT_LINE_IRQ1, m_lio_int);
m_lio_irq = lio_irq;
m_cpu->set_input_line(INPUT_LINE_IRQ1, m_lio_irq);
}
}
void ip4_state::scsi_drq(int state)
void sgi_ip4_device::vme_irq(unsigned number, int state)
{
// record interrupt state
if (!state)
m_vme_isr |= 1U << number;
else
m_vme_isr &= ~(1U << number);
// update interrupt line
bool const vme_irq = m_vme_isr;// &m_vme_imr;
if (m_vme_irq ^ vme_irq)
{
m_vme_irq = vme_irq;
m_cpu->set_input_line(INPUT_LINE_IRQ0, m_vme_irq);
}
}
void sgi_ip4_device::scsi_drq(int state)
{
if (state)
{
@ -456,7 +402,7 @@ void ip4_state::scsi_drq(int state)
}
}
void ip4_state::cpucfg_w(u16 data)
void sgi_ip4_device::cpucfg_w(u16 data)
{
LOG("cpucfg_w 0x%04x\n", data);
@ -464,12 +410,31 @@ void ip4_state::cpucfg_w(u16 data)
for (unsigned i = 0; i < 5; i++)
m_leds[i] = BIT(data, i);
if ((m_cpucfg & CPUCFG_MAIL) && !BIT(data, 8))
lio_irq<LIO_MAIL>(1);
if (BIT(data, 9))
machine().schedule_soft_reset();
if ((m_cpucfg ^ data) & CPUCFG_RPAR)
LOGMASKED(LOG_PARITY, "parity checking %d\n", BIT(data, 10));
if (!(m_cpucfg & CPUCFG_SLA) && (data & CPUCFG_SLA))
{
LOGMASKED(LOG_VME, "vme slave access enabled\n");
vme_space(vme::AM_29).install_write_handler(0x1000, 0x13ff, emu::rw_delegate(*this, FUNC(sgi_ip4_device::mailbox_w)));
vme_space(vme::AM_39).install_ram(0x0000'0000, 0x007f'ffff, m_ram.target());
vme_space(vme::AM_3a).install_ram(0x0000'0000, 0x007f'ffff, m_ram.target());
vme_space(vme::AM_3b).install_ram(0x0000'0000, 0x007f'ffff, m_ram.target());
vme_space(vme::AM_3d).install_ram(0x0000'0000, 0x007f'ffff, m_ram.target());
vme_space(vme::AM_3e).install_ram(0x0000'0000, 0x007f'ffff, m_ram.target());
vme_space(vme::AM_3f).install_ram(0x0000'0000, 0x007f'ffff, m_ram.target());
vme_space(vme::AM_09).install_ram(0x0000'0000, m_ram.bytes() - 1, m_ram.target());
vme_space(vme::AM_0a).install_ram(0x0000'0000, m_ram.bytes() - 1, m_ram.target());
}
if ((m_cpucfg ^ data) & CPUCFG_BAD)
{
LOGMASKED(LOG_PARITY, "write bad parity %d\n", BIT(data, 13));
@ -482,15 +447,15 @@ void ip4_state::cpucfg_w(u16 data)
m_parity = std::make_unique<u8[]>(ram_size << (20 - 3));
m_parity_mph = m_cpu->space(0).install_readwrite_tap(0, (ram_size << 20) - 1, "parity",
std::bind(&ip4_state::parity_r, this, std::placeholders::_1, std::placeholders::_2, std::placeholders::_3),
std::bind(&ip4_state::parity_w, this, std::placeholders::_1, std::placeholders::_2, std::placeholders::_3));
std::bind(&sgi_ip4_device::parity_r, this, std::placeholders::_1, std::placeholders::_2, std::placeholders::_3),
std::bind(&sgi_ip4_device::parity_w, this, std::placeholders::_1, std::placeholders::_2, std::placeholders::_3));
}
}
m_cpucfg = data;
}
void ip4_state::parity_r(offs_t offset, u32 &data, u32 mem_mask)
void sgi_ip4_device::parity_r(offs_t offset, u32 &data, u32 mem_mask)
{
if (m_cpucfg & CPUCFG_RPAR)
{
@ -514,7 +479,7 @@ void ip4_state::parity_r(offs_t offset, u32 &data, u32 mem_mask)
}
}
void ip4_state::parity_w(offs_t offset, u32 &data, u32 mem_mask)
void sgi_ip4_device::parity_w(offs_t offset, u32 &data, u32 mem_mask)
{
if (m_cpucfg & CPUCFG_BAD)
{
@ -552,7 +517,17 @@ void ip4_state::parity_w(offs_t offset, u32 &data, u32 mem_mask)
}
}
ROM_START(pi4d50)
void sgi_ip4_device::mailbox_w(offs_t offset, u8 data)
{
if (m_cpucfg & CPUCFG_MAIL)
{
LOGMASKED(LOG_VME, "vme mailbox interrupt (%s)\n", machine().describe_context());
lio_irq<LIO_MAIL>(0);
}
}
ROM_START(ip4)
ROM_REGION32_BE(0x40000, "boot", 0)
ROM_SYSTEM_BIOS(0, "4d1v3", "Version 4D1-3.0 PROM IP4 Mon Jan 4 20:29:51 PST 1988 SGI")
ROMX_LOAD("070-0093-009.bin", 0x000000, 0x010000, CRC(261b0a4c) SHA1(59f73d0e022a502dc5528289e388700b51b308da), ROM_BIOS(0) | ROM_SKIP(3))
@ -564,7 +539,15 @@ ROM_START(pi4d50)
ROM_LOAD("idprom.bin", 0, 0x20, NO_DUMP)
ROM_END
} // anonymous namespace
static INPUT_PORTS_START(ip4)
INPUT_PORTS_END
// YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS
COMP(1987, pi4d50, 0, 0, pi4d50, 0, ip4_state, empty_init, "Silicon Graphics", "Professional IRIS 4D/50", MACHINE_NOT_WORKING)
tiny_rom_entry const *sgi_ip4_device::device_rom_region() const
{
return ROM_NAME(ip4);
}
ioport_constructor sgi_ip4_device::device_input_ports() const
{
return INPUT_PORTS_NAME(ip4);
}

85
src/mame/sgi/ip4.h Normal file
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@ -0,0 +1,85 @@
// license:BSD-3-Clause
// copyright-holders:Patrick Mackinlay
#ifndef MAME_BUS_VME_IP4_H
#define MAME_BUS_VME_IP4_H
#pragma once
#include "cpu/mips/mips1.h"
#include "machine/ds1315.h"
#include "machine/mc68681.h"
#include "machine/pit8253.h"
#include "machine/wd33c9x.h"
#include "sound/saa1099.h"
#include "bus/rs232/rs232.h"
#include "bus/vme/vme.h"
class sgi_ip4_device
: public device_t
, public device_vme_card_interface
{
public:
sgi_ip4_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock);
protected:
virtual tiny_rom_entry const *device_rom_region() const override;
virtual void device_add_mconfig(machine_config &config) override;
virtual void device_config_complete() override;
virtual ioport_constructor device_input_ports() const override;
virtual void device_start() override;
virtual void device_reset() override;
void map(address_map &map);
template <unsigned N> void lio_irq(int state) { lio_irq(N, state); }
void lio_irq(unsigned number, int state);
template <unsigned N> void vme_irq(int state) { vme_irq(N, state); }
void vme_irq(unsigned number, int state);
void scsi_drq(int state);
u16 cpucfg_r() { return m_cpucfg; }
void cpucfg_w(u16 data);
void parity_r(offs_t offset, u32 &data, u32 mem_mask);
void parity_w(offs_t offset, u32 &data, u32 mem_mask);
void mailbox_w(offs_t offset, u8 data);
private:
required_device<mips1_device_base> m_cpu;
required_device<ds1315_device> m_rtc;
required_device<pit8254_device> m_pit;
required_device<wd33c9x_base_device> m_scsi;
required_device_array<scn2681_device, 3> m_duart;
required_device_array<rs232_port_device, 4> m_serial;
required_device<saa1099_device> m_saa;
memory_share_creator<u8> m_nvram;
required_shared_ptr<u32> m_ram;
output_finder<5> m_leds;
// machine registers
u16 m_cpucfg;
u16 m_dmalo;
u16 m_dmahi;
u8 m_lio_isr;
u8 m_vme_isr;
u8 m_vme_imr;
u8 m_parerr;
u32 m_erradr;
// other machine state
std::unique_ptr<u8[]> m_parity;
memory_passthrough_handler m_parity_mph;
u32 m_parity_bad;
bool m_lio_irq;
bool m_vme_irq;
};
DECLARE_DEVICE_TYPE(SGI_IP4, sgi_ip4_device)
#endif // MAME_BUS_VME_IP4_H

109
src/mame/sgi/tt.cpp Normal file
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@ -0,0 +1,109 @@
// license:BSD-3-Clause
// copyright-holders:Patrick Mackinlay
/*
* Silicon Graphics Professional IRIS/PowerSeries "Twin Tower" systems.
*
* Year Model Board CPU Clock I/D Cache Code Name
* 1987 4D/50 IP4 R2000 8MHz 64KiB/32KiB Twin Tower
* 1987 4D/70 IP4 R2000 12.5MHz 64KiB/32KiB Twin Tower
*
* Sources:
* - VME-Eclipse CPU (VIP10) Specification, Silicon Graphics, Inc.
*
* TODO:
* - graphics
* - IP4.5, IP5, IP7
* - 15 slot version (IP5, IP7)
*
*/
#include "emu.h"
#include "bus/vme/vme.h"
#include "bus/vme/enp10.h"
#include "ip4.h"
//#define VERBOSE (0)
#include "logmacro.h"
namespace {
class ip4_state : public driver_device
{
public:
ip4_state(machine_config const &mconfig, device_type type, char const *tag)
: driver_device(mconfig, type, tag)
, m_vme(*this, "vme")
, m_slot(*this, "vme:slot%u", 1U)
{
}
void pi4d50(machine_config &config);
void pi4d70(machine_config &config);
protected:
virtual void machine_start() override;
virtual void machine_reset() override;
void tt12(machine_config &config, XTAL clock);
private:
required_device<vme_bus_device> m_vme;
required_device_array<vme_slot_device, 12> m_slot;
};
void ip4_state::pi4d50(machine_config &config)
{
tt12(config, 16_MHz_XTAL);
}
void ip4_state::pi4d70(machine_config &config)
{
tt12(config, 25_MHz_XTAL);
}
static void vme_cards(device_slot_interface &device)
{
device.option_add("enp10", VME_ENP10);
}
void ip4_state::tt12(machine_config &config, XTAL clock)
{
VME(config, m_vme);
VME_SLOT(config, m_slot[0]).option_set("ip4", SGI_IP4).clock(clock);
VME_SLOT(config, m_slot[1], vme_cards, "enp10", false);
VME_SLOT(config, m_slot[2], vme_cards, nullptr, false);
VME_SLOT(config, m_slot[3], vme_cards, nullptr, false);
VME_SLOT(config, m_slot[4], vme_cards, nullptr, false);
VME_SLOT(config, m_slot[5], vme_cards, nullptr, false);
VME_SLOT(config, m_slot[6], vme_cards, nullptr, false);
VME_SLOT(config, m_slot[7], vme_cards, nullptr, false);
VME_SLOT(config, m_slot[8], vme_cards, nullptr, false);
VME_SLOT(config, m_slot[9], vme_cards, nullptr, false);
VME_SLOT(config, m_slot[10], vme_cards, nullptr, false);
VME_SLOT(config, m_slot[11], vme_cards, nullptr, false);
}
void ip4_state::machine_start()
{
}
void ip4_state::machine_reset()
{
}
ROM_START(pi4d50)
ROM_END
#define rom_pi4d70 rom_pi4d50
} // anonymous namespace
// YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS
COMP(1987, pi4d50, 0, 0, pi4d50, 0, ip4_state, empty_init, "Silicon Graphics", "Professional IRIS 4D/50", MACHINE_NOT_WORKING)
COMP(1987, pi4d70, 0, 0, pi4d70, 0, ip4_state, empty_init, "Silicon Graphics", "Professional IRIS 4D/70", MACHINE_NOT_WORKING)

18
src/mame/vme.flt Normal file
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@ -0,0 +1,18 @@
// drivers which are actually vme cards:
// ffcpu30: sys68k/cpu-30 card
// force68k: card -> done -> working
// hk68v10: card -> done -> working
// mzr8105: card -> done -> no serial?
// mvme147: card -> done
// clxvme186: card (not vme yet)
//
// ffcpu20: driver for fccpu2* cards - should be deleted?
// miniforce: vme backplane (fccpu21)
// m8120: computer (mvme187)
// sys1121: backplane
//
force/miniforce.cpp
motorola/m8120.cpp
motorola/sys1121.cpp
sgi/tt.cpp
skeleton/clxvme186.cpp