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applepic: Add device files missing from 918da8411d
This commit is contained in:
AJR
parent
918da8411d
commit
aa78efa47f
406
src/devices/machine/applepic.cpp
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406
src/devices/machine/applepic.cpp
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// license:BSD-3-Clause
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// copyright-holders:AJR
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/**********************************************************************
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Apple Computer 343S1021 PIC (Peripheral Interface Controller)
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NCR standard cell ASIC, 65CX02 CPU core
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**********************************************************************/
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#include "emu.h"
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#include "applepic.h"
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// device type definition
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DEFINE_DEVICE_TYPE(APPLEPIC, applepic_device, "applepic", "Apple 343S1021 PIC")
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const std::string_view applepic_device::s_interrupt_names[8] = { "0", "DMA 1", "DMA 2", "peripheral", "host", "timer", "6", "7" };
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applepic_device::applepic_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
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: device_t(mconfig, APPLEPIC, tag, owner, clock)
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, m_iopcpu(*this, "iopcpu")
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, m_prd_callback(*this)
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, m_pwr_callback(*this)
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, m_hint_callback(*this)
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, m_gpout_callback(*this)
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, m_ram_address(0)
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, m_status_reg(0x80)
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, m_timer_counter(0)
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, m_timer_latch(0)
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, m_scc_control(0)
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, m_io_control(0)
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, m_timer_dpll_control(0)
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, m_int_mask(0)
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, m_int_reg(0)
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{
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for (dma_channel &channel : m_dma_channel)
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{
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channel.control = 0;
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channel.map = 0;
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channel.tc = 0;
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}
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}
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void applepic_device::internal_map(address_map &map)
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{
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map(0x0000, 0x6fff).mirror(0x8000).ram();
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map(0x7000, 0x77ff).ram();
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map(0x7800, 0x7fff).mirror(0x8000).ram();
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map(0xf010, 0xf013).rw(FUNC(applepic_device::timer_r), FUNC(applepic_device::timer_w));
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map(0xf020, 0xf02f).rw(FUNC(applepic_device::dma_channel_r), FUNC(applepic_device::dma_channel_w));
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map(0xf030, 0xf030).rw(FUNC(applepic_device::scc_control_r), FUNC(applepic_device::scc_control_w));
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map(0xf031, 0xf031).rw(FUNC(applepic_device::io_control_r), FUNC(applepic_device::io_control_w));
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map(0xf032, 0xf032).rw(FUNC(applepic_device::timer_dpll_control_r), FUNC(applepic_device::timer_dpll_control_w));
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map(0xf033, 0xf033).rw(FUNC(applepic_device::int_mask_r), FUNC(applepic_device::int_mask_w));
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map(0xf034, 0xf034).rw(FUNC(applepic_device::int_reg_r), FUNC(applepic_device::int_reg_w));
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map(0xf035, 0xf035).rw(FUNC(applepic_device::host_reg_r), FUNC(applepic_device::host_reg_w));
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map(0xf040, 0xf04f).rw(FUNC(applepic_device::device_reg_r), FUNC(applepic_device::device_reg_w));
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}
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void applepic_device::device_add_mconfig(machine_config &config)
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{
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R65C02(config, m_iopcpu, DERIVED_CLOCK(1, 8));
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m_iopcpu->set_addrmap(AS_PROGRAM, &applepic_device::internal_map);
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}
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void applepic_device::device_resolve_objects()
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{
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// Resolve callbacks
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m_prd_callback.resolve_safe(0);
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m_pwr_callback.resolve_safe();
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m_hint_callback.resolve_safe();
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m_gpout_callback.resolve_all_safe();
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}
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void applepic_device::device_start()
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{
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// Save internal state
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save_item(NAME(m_ram_address));
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save_item(NAME(m_status_reg));
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save_item(NAME(m_timer_counter));
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save_item(NAME(m_timer_latch));
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save_item(STRUCT_MEMBER(m_dma_channel, control));
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save_item(STRUCT_MEMBER(m_dma_channel, map));
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save_item(STRUCT_MEMBER(m_dma_channel, tc));
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save_item(NAME(m_scc_control));
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save_item(NAME(m_io_control));
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save_item(NAME(m_timer_dpll_control));
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save_item(NAME(m_int_mask));
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save_item(NAME(m_int_reg));
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}
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void applepic_device::device_reset()
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{
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m_status_reg &= 0xc3;
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m_int_mask = 0;
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m_iopcpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
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m_iopcpu->set_input_line(r65c02_device::IRQ_LINE, CLEAR_LINE);
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m_hint_callback(CLEAR_LINE);
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}
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u8 applepic_device::host_r(offs_t offset)
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{
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if (BIT(offset, 4))
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{
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if (BIT(m_scc_control, 0))
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return m_prd_callback(offset & 0x0f);
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else
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{
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if (!machine().side_effects_disabled())
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logerror("%s: Read from device register $%X in non-bypass mode\n", machine().describe_context(), offset & 0x0f);
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return 0;
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}
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}
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else if (BIT(offset, 2))
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{
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// Shared RAM read access
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u8 data = m_iopcpu->space(AS_PROGRAM).read_byte(m_ram_address);
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if (BIT(m_status_reg, 1) && !machine().side_effects_disabled())
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++m_ram_address;
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return data;
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}
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else if (BIT(offset, 1))
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{
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// PINT (D6) and /REQ (D7) are used in bypass mode only
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return BIT(m_scc_control, 0) ? m_status_reg | 0x01 : (m_status_reg & 0x3f) | 0x80;
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}
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else if (BIT(offset, 0))
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return m_ram_address & 0x00ff;
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else
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return (m_ram_address & 0xff00) >> 8;
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}
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void applepic_device::host_w(offs_t offset, u8 data)
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{
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if (BIT(offset, 4))
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{
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if (BIT(m_scc_control, 0))
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m_pwr_callback(offset & 0x0f, data);
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else
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logerror("%s: Write $%02X to device register $%X in non-bypass mode\n", machine().describe_context(), data, offset & 0x0f);
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}
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else if (BIT(offset, 2))
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{
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// Shared RAM write access
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m_iopcpu->space(AS_PROGRAM).write_byte(m_ram_address, data);
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if (BIT(m_status_reg, 1))
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++m_ram_address;
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}
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else if (BIT(offset, 1))
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{
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if (BIT(m_status_reg, 2) != BIT(data, 2))
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{
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logerror("%s: /RSTPIC %dactive\n", machine().describe_context(), BIT(data, 2) ? "in" : "");
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m_iopcpu->set_input_line(INPUT_LINE_RESET, BIT(data, 2) ? CLEAR_LINE : ASSERT_LINE);
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}
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if (BIT(data, 3))
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set_interrupt(4);
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if ((m_status_reg & data & 0x30) != 0)
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{
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m_status_reg &= ~(data & 0x30);
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if ((m_status_reg & 0x30) == 0)
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{
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logerror("%s: Host interrupts acknowledged\n", machine().describe_context());
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m_hint_callback(CLEAR_LINE);
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}
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}
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m_status_reg = (data & 0x06) | (m_status_reg & 0xf0);
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}
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else if (BIT(offset, 0))
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m_ram_address = (m_ram_address & 0xff00) | data;
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else
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m_ram_address = u16(data) << 8 | (m_ram_address & 0x00ff);
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}
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WRITE_LINE_MEMBER(applepic_device::pint_w)
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{
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if (state == ASSERT_LINE)
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{
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m_status_reg |= 0x40;
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if (!BIT(m_scc_control, 0))
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set_interrupt(3);
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}
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else
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{
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m_status_reg &= 0xbf;
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if (!BIT(m_scc_control, 0))
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reset_interrupt(3);
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}
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}
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WRITE_LINE_MEMBER(applepic_device::reqa_w)
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{
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}
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WRITE_LINE_MEMBER(applepic_device::reqb_w)
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{
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}
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u8 applepic_device::timer_r(offs_t offset)
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{
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u16 reg = BIT(offset, 1) ? m_timer_latch : m_timer_counter;
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if (BIT(offset, 0))
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return (reg & 0xff00) >> 8;
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else
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{
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if (offset == 0 && !machine().side_effects_disabled())
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reset_interrupt(5);
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return reg & 0x00ff;
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}
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}
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void applepic_device::timer_w(offs_t offset, u8 data)
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{
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if (BIT(offset, 0))
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{
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m_timer_latch = u16(data) << 8 | (m_timer_latch & 0xff00);
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if (offset == 1)
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reset_interrupt(5);
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}
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else
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m_timer_latch = (m_timer_latch & 0xff00) | data;
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}
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u8 applepic_device::dma_channel_r(offs_t offset)
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{
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dma_channel &channel = m_dma_channel[BIT(offset, 3)];
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switch (offset & 7)
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{
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case 0:
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return channel.control;
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case 1:
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return channel.map & 0x00ff;
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case 2:
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return (channel.map & 0xff00) >> 8;
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case 3:
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return channel.tc & 0x0ff;
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case 4:
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return (channel.tc & 0x700) >> 8;
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default:
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if (!machine().side_effects_disabled())
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logerror("%s: Read from undefined DMA register $%02X\n", machine().describe_context(), 0x20 + offset);
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return 0;
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}
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}
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void applepic_device::dma_channel_w(offs_t offset, u8 data)
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{
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dma_channel &channel = m_dma_channel[BIT(offset, 3)];
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switch (offset & 7)
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{
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case 0:
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channel.control = data;
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break;
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case 1:
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channel.map = (channel.map & 0xff00) | data;
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break;
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case 2:
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channel.map = u16(data) << 8 | (channel.map & 0x00ff);
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break;
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case 3:
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channel.tc = (channel.tc & 0x700) | data;
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break;
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case 4:
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channel.tc = (data & 0x07) | (channel.tc & 0x0ff);
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break;
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default:
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logerror("%s: Write $%02X to undefined DMA register $%02X\n", machine().describe_context(), data, 0x20 + offset);
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break;
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}
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}
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u8 applepic_device::scc_control_r()
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{
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return m_scc_control;
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}
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void applepic_device::scc_control_w(u8 data)
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{
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m_scc_control = data;
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if (!BIT(data, 0) && BIT(m_status_reg, 6))
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set_interrupt(3);
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else
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reset_interrupt(3);
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m_gpout_callback[1](BIT(data, 7));
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}
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u8 applepic_device::io_control_r()
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{
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return m_io_control;
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}
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void applepic_device::io_control_w(u8 data)
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{
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m_io_control = data;
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}
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u8 applepic_device::timer_dpll_control_r()
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{
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return m_timer_dpll_control;
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}
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void applepic_device::timer_dpll_control_w(u8 data)
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{
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m_timer_dpll_control = data;
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}
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u8 applepic_device::int_mask_r()
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{
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return m_int_mask;
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}
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void applepic_device::int_mask_w(u8 data)
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{
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for (int which = 1; which <= 5; which++)
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if (BIT(m_int_mask, which) != BIT(data, which))
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logerror("%s: %sabling %s interrupt\n", machine().describe_context(), BIT(data, which) ? "En" : "Dis", s_interrupt_names[which]);
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m_int_mask = data & 0x3e;
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m_iopcpu->set_input_line(r65c02_device::IRQ_LINE, (m_int_mask & m_int_reg) != 0 ? ASSERT_LINE : CLEAR_LINE);
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}
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u8 applepic_device::int_reg_r()
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{
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return m_int_reg;
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}
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void applepic_device::int_reg_w(u8 data)
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{
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if ((m_int_reg & data) != 0)
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{
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m_int_reg &= ~data;
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if ((m_int_mask & m_int_reg) == 0)
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{
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logerror("%s: 6502 interrupts acknowledged\n", machine().describe_context());
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m_iopcpu->set_input_line(r65c02_device::IRQ_LINE, CLEAR_LINE);
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}
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}
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}
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void applepic_device::set_interrupt(int which)
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{
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if (!BIT(m_int_reg, which))
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{
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logerror("%s: Setting %s interrupt\n", machine().describe_context(), s_interrupt_names[which]);
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m_int_reg |= (1 << which);
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if ((m_int_reg & m_int_mask) == (1 << which))
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m_iopcpu->set_input_line(r65c02_device::IRQ_LINE, ASSERT_LINE);
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}
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}
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void applepic_device::reset_interrupt(int which)
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{
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if (BIT(m_int_reg, which))
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{
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logerror("%s: Resetting %s interrupt\n", machine().describe_context(), s_interrupt_names[which]);
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if ((m_int_reg & m_int_mask) == (1 << which))
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m_iopcpu->set_input_line(r65c02_device::IRQ_LINE, CLEAR_LINE);
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m_int_reg &= ~(1 << which);
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}
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}
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u8 applepic_device::host_reg_r()
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{
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return (m_status_reg & 0x30) >> 2;
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}
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void applepic_device::host_reg_w(u8 data)
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{
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logerror("%s: INTHST0 %srequested, INTHST1 %srequested\n", machine().describe_context(), BIT(data, 2) ? "" : "not ", BIT(data, 3) ? "" : "not ");
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m_status_reg |= (data & 0x0c) << 2;
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if ((data & 0x0c) != 0)
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m_hint_callback(ASSERT_LINE);
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}
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u8 applepic_device::device_reg_r(offs_t offset)
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{
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if (BIT(m_scc_control, 0))
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{
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if (!machine().side_effects_disabled())
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logerror("%s: Read from device register $%X in bypass mode\n", machine().describe_context(), offset & 0x0f);
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return 0;
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}
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else
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return m_prd_callback(offset & 0x0f);
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}
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void applepic_device::device_reg_w(offs_t offset, u8 data)
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{
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if (BIT(m_scc_control, 0))
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logerror("%s: Read from device register $%X in bypass mode\n", machine().describe_context(), offset & 0x0f);
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else
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m_pwr_callback(offset & 0x0f, data);
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}
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105
src/devices/machine/applepic.h
Normal file
105
src/devices/machine/applepic.h
Normal file
@ -0,0 +1,105 @@
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// license:BSD-3-Clause
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// copyright-holders:AJR
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#ifndef MAME_DEVICES_MACHINE_APPLEPIC_H
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#define MAME_DEVICES_MACHINE_APPLEPIC_H
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#pragma once
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#include "cpu/m6502/r65c02.h"
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//**************************************************************************
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// TYPE DEFINITIONS
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//**************************************************************************
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// ======================> applepic_device
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class applepic_device : public device_t
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{
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public:
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// construction/destruction
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applepic_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
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// callback configuration
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auto prd_callback() { return m_prd_callback.bind(); }
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auto pwr_callback() { return m_pwr_callback.bind(); }
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auto hint_callback() { return m_hint_callback.bind(); }
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auto gpout0_callback() { return m_gpout_callback[0].bind(); }
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auto gpout1_callback() { return m_gpout_callback[1].bind(); }
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// host interface
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u8 host_r(offs_t offset);
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void host_w(offs_t offset, u8 data);
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// peripheral device requests
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DECLARE_WRITE_LINE_MEMBER(pint_w);
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DECLARE_WRITE_LINE_MEMBER(reqa_w);
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DECLARE_WRITE_LINE_MEMBER(reqb_w);
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protected:
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// device-level overrides
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virtual void device_add_mconfig(machine_config &config) override;
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virtual void device_resolve_objects() override;
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virtual void device_start() override;
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virtual void device_reset() override;
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private:
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static const std::string_view s_interrupt_names[8];
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||||
struct dma_channel
|
||||
{
|
||||
u8 control;
|
||||
u16 map;
|
||||
u16 tc;
|
||||
};
|
||||
|
||||
u8 timer_r(offs_t offset);
|
||||
void timer_w(offs_t offset, u8 data);
|
||||
void reset_timer_interrupt();
|
||||
u8 dma_channel_r(offs_t offset);
|
||||
void dma_channel_w(offs_t offset, u8 data);
|
||||
u8 scc_control_r();
|
||||
void scc_control_w(u8 data);
|
||||
u8 io_control_r();
|
||||
void io_control_w(u8 data);
|
||||
u8 timer_dpll_control_r();
|
||||
void timer_dpll_control_w(u8 data);
|
||||
u8 int_mask_r();
|
||||
void int_mask_w(u8 data);
|
||||
u8 int_reg_r();
|
||||
void int_reg_w(u8 data);
|
||||
void set_interrupt(int which);
|
||||
void reset_interrupt(int which);
|
||||
u8 host_reg_r();
|
||||
void host_reg_w(u8 data);
|
||||
u8 device_reg_r(offs_t offset);
|
||||
void device_reg_w(offs_t offset, u8 data);
|
||||
|
||||
void internal_map(address_map &map);
|
||||
|
||||
// internal CPU
|
||||
required_device<r65c02_device> m_iopcpu;
|
||||
|
||||
// callbacks for peripheral and host
|
||||
devcb_read8 m_prd_callback;
|
||||
devcb_write8 m_pwr_callback;
|
||||
devcb_write_line m_hint_callback;
|
||||
devcb_write_line::array<2> m_gpout_callback;
|
||||
|
||||
// internal state
|
||||
u16 m_ram_address;
|
||||
u8 m_status_reg;
|
||||
u16 m_timer_counter;
|
||||
u16 m_timer_latch;
|
||||
dma_channel m_dma_channel[2];
|
||||
u8 m_scc_control;
|
||||
u8 m_io_control;
|
||||
u8 m_timer_dpll_control;
|
||||
u8 m_int_mask;
|
||||
u8 m_int_reg;
|
||||
};
|
||||
|
||||
// device type declaration
|
||||
DECLARE_DEVICE_TYPE(APPLEPIC, applepic_device)
|
||||
|
||||
#endif // MAME_DEVICES_MACHINE_APPLEPIC_H
|
||||
Loading…
Reference in New Issue
Block a user