cdicdic: Explicitly configure second clock (nw)

src/mame/drivers/cdi.cpp

@@ -850,9 +850,10 @@ void cdi_state::cdimono1_base(machine_config &config)
 
 	config.set_default_layout(layout_cdi);
 
-	// IMS66490 CDIC input clocks are 22.5792 MHz and 19.3536 MHz (latter is generated by PLL circuit incorporating 19.3575 MHz XTAL)
+	// IMS66490 CDIC input clocks are 22.5792 MHz and 19.3536 MHz
 	// DSP input clock is 7.5264 MHz
 	CDI_CDIC(config, m_cdic, 45.1584_MHz_XTAL / 2);
+	m_cdic->set_clock2(45.1584_MHz_XTAL * 3 / 7); // generated by PLL circuit incorporating 19.3575 MHz XTAL
 	m_cdic->intreq_callback().set(m_maincpu, FUNC(scc68070_device::in4_w));
 
 	CDI_SLAVE(config, m_slave_hle, 0);

src/mame/machine/cdicdic.cpp

@@ -106,9 +106,9 @@ const int32_t cdicdic_device::s_cdic_adpcm_filter_coef[5][2] =
 //  INLINES
 //**************************************************************************
 
-static inline int CDIC_IS_VALID_SAMPLE_BUF(uint16_t *cdram, uint16_t addr)
+int cdicdic_device::is_valid_sample_buf(uint16_t addr) const
 {
-	uint8_t *cdram8 = ((uint8_t*)cdram) + addr + 8;
+	const uint8_t *cdram8 = ((uint8_t*)m_ram.get()) + addr + 8;
 	if(cdram8[2] != 0xff)
 	{
 		return 1;
@@ -116,29 +116,29 @@ static inline int CDIC_IS_VALID_SAMPLE_BUF(uint16_t *cdram, uint16_t addr)
 	return 0;
 }
 
-static inline double CDIC_SAMPLE_BUF_FREQ(uint16_t *cdram, uint16_t addr)
+double cdicdic_device::sample_buf_freq(uint16_t addr) const
 {
-	uint8_t *cdram8 = ((uint8_t*)cdram) + addr + 8;
+	const uint8_t *cdram8 = ((uint8_t*)m_ram.get()) + addr + 8;
 	switch(cdram8[2] & 0x3f)
 	{
 		case 0:
 		case 1:
 		case 16:
 		case 17:
-			return 37800.0f;
+			return clock2() / 512.0f;
 
 		case 4:
 		case 5:
-			return 18900.0f;
+			return clock2() / 1024.0f;
 
 		default:
-			return 18900.0f;
+			return clock2() / 1024.0f;
 	}
 }
 
-static inline int CDIC_SAMPLE_BUF_SIZE(uint16_t *cdram, uint16_t addr)
+int cdicdic_device::sample_buf_size(uint16_t addr) const
 {
-	uint8_t *cdram8 = ((uint8_t*)cdram) + addr + 8;
+	const uint8_t *cdram8 = ((uint8_t*)m_ram.get()) + addr + 8;
 	switch(cdram8[2] & 0x3f)
 	{
 		case 0:
@@ -440,44 +440,44 @@ void cdicdic_device::decode_audio_sector(const uint8_t *xa, int32_t triggered)
 	{
 		case 0:
 			channels = 1;
-			m_audio_sample_freq = 37800.0f; //18900.0f;
+			m_audio_sample_freq = clock2() / 512.0f; // / 1024.0f;
 			bits = 4;
 			m_audio_sample_size = 4;
 			break;
 
 		case 1:
-			channels=2;
+			channels = 2;
-			m_audio_sample_freq=37800.0f;
+			m_audio_sample_freq = clock2() / 512.0f;
-			bits=4;
+			bits = 4;
-			m_audio_sample_size=2;
+			m_audio_sample_size = 2;
 			break;
 
 		case 4:
-			channels=1;
+			channels = 1;
-			m_audio_sample_freq=18900.0f;   ///2.0f;
+			m_audio_sample_freq = clock2() / 1024.0f;   ///2.0f;
-			bits=4;
+			bits = 4;
-			m_audio_sample_size=4;
+			m_audio_sample_size = 4;
 			break;
 
 		case 5:
-			channels=2;
+			channels = 2;
-			m_audio_sample_freq=18900.0f;   //37800.0f/2.0f;
+			m_audio_sample_freq = clock2() / 1024.0f;   //37800.0f/2.0f;
-			bits=4;
+			bits = 4;
-			m_audio_sample_size=2;
+			m_audio_sample_size = 2;
 			break;
 
 		case 16:
-			channels=1;
+			channels = 1;
-			m_audio_sample_freq=37800.0f;
+			m_audio_sample_freq = clock2() / 512.0f;
-			bits=8;
+			bits = 8;
-			m_audio_sample_size=2;
+			m_audio_sample_size = 2;
 			break;
 
 		case 17:
-			channels=2;
+			channels = 2;
-			m_audio_sample_freq=37800.0f;
+			m_audio_sample_freq = clock2() / 512.0f;
-			bits=8;
+			bits = 8;
-			m_audio_sample_size=1;
+			m_audio_sample_size = 1;
 			break;
 
 		default:
@@ -572,7 +572,7 @@ void cdicdic_device::sample_trigger()
 		m_decode_delay = 0;
 	}
 
-	if(CDIC_IS_VALID_SAMPLE_BUF(m_ram.get(), m_decode_addr & 0x3ffe))
+	if(is_valid_sample_buf(m_decode_addr & 0x3ffe))
 	{
 		verboselog(*this, 0, "Hit audio_sample_trigger, with m_decode_addr == %04x, calling decode_audio_sector\n", m_decode_addr );
 
@@ -586,7 +586,7 @@ void cdicdic_device::sample_trigger()
 
 		//// Delay for Frequency * (18*28*2*size in bytes) before requesting more data
 		verboselog(*this, 0, "%s", "Data is valid, setting up a new callback\n" );
-		m_decode_period = attotime::from_hz(CDIC_SAMPLE_BUF_FREQ(m_ram.get(), m_decode_addr & 0x3ffe)) * (18*28*2*CDIC_SAMPLE_BUF_SIZE(m_ram.get(), m_decode_addr & 0x3ffe));
+		m_decode_period = attotime::from_hz(sample_buf_freq(m_decode_addr & 0x3ffe)) * (18*28*2*sample_buf_size(m_decode_addr & 0x3ffe));
 		m_audio_sample_timer->adjust(m_decode_period);
 		//dmadac_enable(&dmadac[0], 2, 0);
 	}
@@ -1163,6 +1163,7 @@ cdicdic_device::cdicdic_device(const machine_config &mconfig, const char *tag, d
 	, m_scc(*this, ":maincpu")
 	, m_cdda(*this, ":cdda")
 	, m_cdrom_dev(*this, ":cdrom")
+	, m_clock2(clock)
 {
 }
 

src/mame/machine/cdicdic.h

@@ -45,6 +45,10 @@ public:
 	// construction/destruction
 	cdicdic_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
 
+	void set_clock2(uint32_t clock) { m_clock2 = clock; }
+	void set_clock2(const XTAL &xtal) { set_clock2(xtal.value()); }
+	uint32_t clock2() const { return m_clock2; }
+
 	auto intreq_callback() { return m_intreq_callback.bind(); }
 
 	// non-static internal members
@@ -69,6 +73,10 @@ protected:
 	TIMER_CALLBACK_MEMBER( trigger_readback_int );
 
 private:
+	int is_valid_sample_buf(uint16_t addr) const;
+	double sample_buf_freq(uint16_t addr) const;
+	int sample_buf_size(uint16_t addr) const;
+
 	devcb_write_line m_intreq_callback;
 
 	required_address_space m_memory_space;
@@ -77,6 +85,8 @@ private:
 	required_device<cdda_device> m_cdda;
 	optional_device<cdrom_image_device> m_cdrom_dev;
 
+	uint32_t m_clock2;
+
 	// internal state
 	uint16_t m_command;           // CDIC Command Register            (0x303c00)
 	uint32_t m_time;              // CDIC Time Register               (0x303c02)