mirror of
https://github.com/holub/mame
synced 2025-07-04 09:28:51 +03:00
(nw) small cleanups in my drivers
This commit is contained in:
Robbbert
parent
02c0a7f4f3
commit
aafd1b7225
@ -107,54 +107,52 @@ public:
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void init_applix();
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protected:
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private:
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virtual void machine_reset() override;
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virtual void video_start() override;
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private:
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uint8_t applix_inputs_r();
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void palette_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
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void analog_latch_w(uint16_t data);
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void dac_latch_w(uint16_t data);
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void video_latch_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
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uint8_t applix_pb_r();
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void applix_pa_w(uint8_t data);
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void applix_pb_w(uint8_t data);
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u8 applix_inputs_r();
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void palette_w(offs_t offset, u16 data, u16 mem_mask = ~0);
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void analog_latch_w(u16 data);
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void dac_latch_w(u16 data);
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void video_latch_w(offs_t offset, u16 data, u16 mem_mask = ~0);
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u8 applix_pb_r();
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void applix_pa_w(u8 data);
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void applix_pb_w(u8 data);
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DECLARE_WRITE_LINE_MEMBER(vsync_w);
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uint8_t port00_r();
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uint8_t port08_r();
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uint8_t port10_r();
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uint8_t port18_r();
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uint8_t port20_r();
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uint8_t port60_r();
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void port08_w(uint8_t data);
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void port10_w(uint8_t data);
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void port18_w(offs_t offset, uint8_t data);
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void port20_w(uint8_t data);
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void port60_w(uint8_t data);
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uint16_t fdc_data_r();
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uint16_t fdc_stat_r(offs_t offset);
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void fdc_data_w(uint16_t data);
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void fdc_cmd_w(uint16_t data);
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u8 port00_r();
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u8 port08_r();
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u8 port10_r();
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u8 port18_r();
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u8 port20_r();
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u8 port60_r();
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void port08_w(u8 data);
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void port10_w(u8 data);
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void port18_w(offs_t offset, u8 data);
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void port20_w(u8 data);
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void port60_w(u8 data);
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u16 fdc_data_r();
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u16 fdc_stat_r(offs_t offset);
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void fdc_data_w(u16 data);
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void fdc_cmd_w(u16 data);
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DECLARE_FLOPPY_FORMATS(floppy_formats);
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uint8_t internal_data_read(offs_t offset);
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void internal_data_write(offs_t offset, uint8_t data);
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uint8_t p1_read();
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void p1_write(uint8_t data);
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uint8_t p2_read();
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void p2_write(uint8_t data);
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uint8_t p3_read();
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void p3_write(uint8_t data);
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u8 internal_data_read(offs_t offset);
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void internal_data_write(offs_t offset, u8 data);
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u8 p1_read();
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void p1_write(u8 data);
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u8 p2_read();
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void p2_write(u8 data);
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u8 p3_read();
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void p3_write(u8 data);
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TIMER_DEVICE_CALLBACK_MEMBER(cass_timer);
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MC6845_UPDATE_ROW(crtc_update_row);
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MC6845_BEGIN_UPDATE(crtc_update_border);
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void applix_palette(palette_device &palette) const;
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uint8_t m_video_latch;
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uint8_t m_pa;
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uint8_t m_palette_latch[4];
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required_shared_ptr<uint16_t> m_base;
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u8 m_video_latch;
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u8 m_pa;
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u8 m_palette_latch[4];
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required_shared_ptr<u16> m_base;
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void applix_mem(address_map &map);
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void keytronic_pc3270_io(address_map &map);
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@ -162,24 +160,24 @@ private:
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void subcpu_io(address_map &map);
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void subcpu_mem(address_map &map);
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uint8_t m_pb;
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uint8_t m_analog_latch;
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uint8_t m_dac_latch;
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uint8_t m_port08;
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uint8_t m_data_to_fdc;
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uint8_t m_data_from_fdc;
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u8 m_pb;
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u8 m_analog_latch;
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u8 m_dac_latch;
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u8 m_port08;
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u8 m_data_to_fdc;
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u8 m_data_from_fdc;
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bool m_data;
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bool m_data_or_cmd;
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bool m_buffer_empty;
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bool m_fdc_cmd;
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uint8_t m_clock_count;
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u8 m_clock_count;
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bool m_cp;
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uint8_t m_p1;
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uint8_t m_p1_data;
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uint8_t m_p2;
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uint8_t m_p3;
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uint16_t m_last_write_addr;
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uint8_t m_cass_data[4];
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u8 m_p1;
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u8 m_p1_data;
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u8 m_p2;
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u8 m_p3;
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u16 m_last_write_addr;
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u8 m_cass_data[4];
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required_device<cpu_device> m_maincpu;
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required_device<mc6845_device> m_crtc;
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required_device<via6522_device> m_via;
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@ -215,7 +213,7 @@ private:
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required_ioport m_io_k3a0;
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required_ioport m_io_k3b0;
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required_ioport m_io_k0b;
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required_shared_ptr<uint16_t> m_expansion;
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required_shared_ptr<u16> m_expansion;
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required_device<palette_device> m_palette;
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};
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@ -226,7 +224,7 @@ d3 = cassette LED, low=on
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d4,5,6 = audio select
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d7 = cassette relay, low=on
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*/
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void applix_state::analog_latch_w(uint16_t data)
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void applix_state::analog_latch_w(u16 data)
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{
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data &= 0xff;
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if (data != m_analog_latch)
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@ -238,7 +236,7 @@ void applix_state::analog_latch_w(uint16_t data)
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}
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}
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void applix_state::dac_latch_w(uint16_t data)
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void applix_state::dac_latch_w(u16 data)
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{
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data &= 0xff;
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m_dac_latch = data;
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@ -251,7 +249,7 @@ void applix_state::dac_latch_w(uint16_t data)
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}
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//cent = odd, video = even
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void applix_state::palette_w(offs_t offset, uint16_t data, uint16_t mem_mask)
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void applix_state::palette_w(offs_t offset, u16 data, u16 mem_mask)
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{
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offset >>= 4;
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if (ACCESSING_BITS_0_7)
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@ -262,7 +260,7 @@ void applix_state::palette_w(offs_t offset, uint16_t data, uint16_t mem_mask)
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m_palette_latch[offset] = (data >> 8) & 15;
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}
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void applix_state::video_latch_w(offs_t offset, uint16_t data, uint16_t mem_mask)
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void applix_state::video_latch_w(offs_t offset, u16 data, u16 mem_mask)
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{
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if (ACCESSING_BITS_0_7)
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m_video_latch = data;
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@ -274,12 +272,12 @@ d1 = cassette in
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d2,3 = joystick in
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d4-7 = SW2 dipswitch block
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*/
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uint8_t applix_state::applix_inputs_r()
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u8 applix_state::applix_inputs_r()
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{
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return m_io_dsw->read() | m_cass_data[2];
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}
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uint8_t applix_state::applix_pb_r()
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u8 applix_state::applix_pb_r()
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{
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return m_pb;
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}
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@ -294,7 +292,7 @@ d5 = /(out) clear cass IRQ and output line
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d6 = /(out) reset keyboard by pulling kbd clock low
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d7 = /(out) reset keyboard flipflop
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*/
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void applix_state::applix_pa_w(uint8_t data)
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void applix_state::applix_pa_w(u8 data)
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{
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// Reset flipflop counter
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if (!BIT(data, 7))
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@ -325,7 +323,7 @@ void applix_state::applix_pa_w(uint8_t data)
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d0-6 = user
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d7 = square wave output for cassette IRQ
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*/
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void applix_state::applix_pb_w(uint8_t data)
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void applix_state::applix_pb_w(u8 data)
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{
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// low-to-high of PB7 when writing cassette - CLK on IC49
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if (!BIT(m_pb, 7) && BIT(data, 7))
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@ -341,9 +339,9 @@ d1 = H if 68000 sent a byte
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d2 = H if 68000 has read last byte
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d3 = test switch
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*/
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uint8_t applix_state::port00_r()
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u8 applix_state::port00_r()
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{
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return (uint8_t)m_data_or_cmd | ((uint8_t)m_data << 1) | ((uint8_t)m_buffer_empty << 2) | m_io_fdc->read();
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return (u8)m_data_or_cmd | ((u8)m_data << 1) | ((u8)m_buffer_empty << 2) | m_io_fdc->read();
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}
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/*
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@ -356,7 +354,7 @@ d5 = SIDE
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d6 = BANK
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d7 = MAP
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*/
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uint8_t applix_state::port08_r()
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u8 applix_state::port08_r()
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{
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return m_port08 | 3;
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}
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@ -366,7 +364,7 @@ d0 = /INUSE
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d1 = /EJECT
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d2-7 same as for port08_r
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*/
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void applix_state::port08_w(uint8_t data)
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void applix_state::port08_w(u8 data)
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{
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m_port08 = data;
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membank("bank1")->set_entry(BIT(data, 6));
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@ -384,72 +382,72 @@ void applix_state::port08_w(uint8_t data)
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}
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}
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uint8_t applix_state::port10_r()
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u8 applix_state::port10_r()
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{
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return 0;
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}
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void applix_state::port10_w(uint8_t data)
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void applix_state::port10_w(u8 data)
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{
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}
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uint8_t applix_state::port18_r()
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u8 applix_state::port18_r()
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{
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m_data = 0;
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return m_data_to_fdc;
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}
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void applix_state::port18_w(offs_t offset, uint8_t data)
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void applix_state::port18_w(offs_t offset, u8 data)
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{
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m_data_from_fdc = data;
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m_buffer_empty = 0;
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m_fdc_cmd = BIT(offset, 2);
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}
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uint8_t applix_state::port20_r()
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u8 applix_state::port20_r()
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{
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return 0;
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}
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void applix_state::port20_w(uint8_t data)
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void applix_state::port20_w(u8 data)
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{
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}
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uint8_t applix_state::port60_r()
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u8 applix_state::port60_r()
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{
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return 0;
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}
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void applix_state::port60_w(uint8_t data)
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void applix_state::port60_w(u8 data)
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{
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}
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uint16_t applix_state::fdc_stat_r(offs_t offset)
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u16 applix_state::fdc_stat_r(offs_t offset)
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{
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uint8_t data = 0;
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u8 data = 0;
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switch (offset)
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{
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case 0: data = (uint8_t)m_buffer_empty^1; break;
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case 1: data = (uint8_t)m_data^1; break;
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default: data = (uint8_t)m_fdc_cmd; // case 2
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case 0: data = (u8)m_buffer_empty^1; break;
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case 1: data = (u8)m_data^1; break;
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default: data = (u8)m_fdc_cmd; // case 2
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}
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return data << 7;
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}
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uint16_t applix_state::fdc_data_r()
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u16 applix_state::fdc_data_r()
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{
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m_buffer_empty = 1;
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return m_data_from_fdc;
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}
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void applix_state::fdc_data_w(uint16_t data)
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void applix_state::fdc_data_w(u16 data)
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{
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m_data_to_fdc = data;
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m_data = 1;
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m_data_or_cmd = 0;
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}
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void applix_state::fdc_cmd_w(uint16_t data)
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void applix_state::fdc_cmd_w(u16 data)
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{
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m_data_to_fdc = data;
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m_data = 1;
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@ -743,7 +741,7 @@ INPUT_PORTS_END
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void applix_state::machine_reset()
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{
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uint8_t* ROM = memregion("maincpu")->base();
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u8* ROM = memregion("maincpu")->base();
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memcpy(m_expansion, ROM, 8);
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membank("bank1")->set_entry(0);
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m_p3 = 0xff;
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@ -798,13 +796,13 @@ MC6845_UPDATE_ROW( applix_state::crtc_update_row )
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// There is a monochrome mode, but no info found as yet.
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// The 6845 cursor signal is not used at all.
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rgb_t const *const palette = m_palette->palette()->entry_list_raw();
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uint32_t const vidbase = (m_video_latch & 15) << 14 | (ra & 7) << 12;
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uint32_t *p = &bitmap.pix32(y + vbp, hbp);
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u32 const vidbase = (m_video_latch & 15) << 14 | (ra & 7) << 12;
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u32 *p = &bitmap.pix32(y + vbp, hbp);
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for (uint16_t x = 0; x < x_count; x++)
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for (u16 x = 0; x < x_count; x++)
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{
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uint32_t const mem = vidbase | ((ma + x) & 0xfff);
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uint16_t chr = m_base[mem];
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u32 const mem = vidbase | ((ma + x) & 0xfff);
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u16 chr = m_base[mem];
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if (BIT(m_pa, 3))
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{
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@ -842,7 +840,7 @@ TIMER_DEVICE_CALLBACK_MEMBER(applix_state::cass_timer)
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{
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/* cassette - turn 2500/5000Hz to a bit */
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m_cass_data[1]++;
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uint8_t cass_ws = (m_cass->input() > +0.03) ? 1 : 0;
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u8 cass_ws = (m_cass->input() > +0.03) ? 1 : 0;
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if (cass_ws != m_cass_data[0])
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{
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@ -985,7 +983,7 @@ ROM_END
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void applix_state::init_applix()
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{
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uint8_t *RAM = memregion("subcpu")->base();
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u8 *RAM = memregion("subcpu")->base();
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membank("bank1")->configure_entries(0, 2, &RAM[0x8000], 0x8000);
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}
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@ -999,7 +997,7 @@ COMP( 1986, applix, 0, 0, applix, applix, applix_state, init_applix,
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/**************************************************** KEYBOARD MODULE *****************************************/
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uint8_t applix_state::internal_data_read(offs_t offset)
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u8 applix_state::internal_data_read(offs_t offset)
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{
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m_via->write_cb2( BIT(offset, 8) ); // data
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bool cp = !BIT(offset, 9);
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@ -1016,7 +1014,7 @@ uint8_t applix_state::internal_data_read(offs_t offset)
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}
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void applix_state::internal_data_write(offs_t offset, uint8_t data)
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void applix_state::internal_data_write(offs_t offset, u8 data)
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{
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/* Check for low->high transition on AD8 */
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if ( ! ( m_last_write_addr & 0x0100 ) && ( offset & 0x0100 ) )
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@ -1115,33 +1113,33 @@ void applix_state::internal_data_write(offs_t offset, uint8_t data)
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}
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uint8_t applix_state::p1_read()
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u8 applix_state::p1_read()
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{
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return m_p1 & m_p1_data;
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}
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void applix_state::p1_write(uint8_t data)
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void applix_state::p1_write(u8 data)
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{
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m_p1 = data;
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}
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uint8_t applix_state::p2_read()
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u8 applix_state::p2_read()
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{
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return m_p2;
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}
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void applix_state::p2_write(uint8_t data)
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void applix_state::p2_write(u8 data)
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{
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m_p2 = data;
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}
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uint8_t applix_state::p3_read()
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u8 applix_state::p3_read()
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{
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uint8_t data = m_p3;
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u8 data = m_p3;
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data &= ~0x14;
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|
||||
@ -1155,7 +1153,7 @@ uint8_t applix_state::p3_read()
|
||||
}
|
||||
|
||||
|
||||
void applix_state::p3_write(uint8_t data)
|
||||
void applix_state::p3_write(u8 data)
|
||||
{
|
||||
m_p3 = data;
|
||||
}
|
||||
|
||||
@ -64,13 +64,13 @@ private:
|
||||
TIMER_BOOT
|
||||
};
|
||||
|
||||
void argo_videoram_w(offs_t offset, uint8_t data);
|
||||
uint8_t argo_io_r(offs_t offset);
|
||||
void argo_io_w(offs_t offset, uint8_t data);
|
||||
void argo_videoram_w(offs_t offset, u8 data);
|
||||
u8 argo_io_r(offs_t offset);
|
||||
void argo_io_w(offs_t offset, u8 data);
|
||||
DECLARE_WRITE_LINE_MEMBER(z0_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(hrq_w);
|
||||
void argo_palette(palette_device &palette) const;
|
||||
uint8_t dma_r(offs_t offset);
|
||||
u8 dma_r(offs_t offset);
|
||||
I8275_DRAW_CHARACTER_MEMBER(display_pixels);
|
||||
TIMER_DEVICE_CALLBACK_MEMBER(kansas_r);
|
||||
|
||||
@ -87,9 +87,9 @@ private:
|
||||
required_device<cassette_image_device> m_cass;
|
||||
required_device<palette_device> m_palette;
|
||||
required_ioport_array<11> m_io_keyboard;
|
||||
uint8_t m_framecnt;
|
||||
u8 m_framecnt;
|
||||
bool m_ram_ctrl;
|
||||
uint8_t m_scroll_ctrl;
|
||||
u8 m_scroll_ctrl;
|
||||
bool m_txe, m_txd, m_rts, m_casspol;
|
||||
u8 m_cass_data[4];
|
||||
virtual void machine_reset() override;
|
||||
@ -97,9 +97,9 @@ private:
|
||||
};
|
||||
|
||||
// write to videoram if following 'out b9,61' otherwise write to the unknown 'extra' ram
|
||||
void argo_state::argo_videoram_w(offs_t offset, uint8_t data)
|
||||
void argo_state::argo_videoram_w(offs_t offset, u8 data)
|
||||
{
|
||||
uint8_t *RAM;
|
||||
u8 *RAM;
|
||||
if (m_ram_ctrl)
|
||||
m_p_videoram[offset] = data;
|
||||
else
|
||||
@ -109,9 +109,9 @@ void argo_state::argo_videoram_w(offs_t offset, uint8_t data)
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t argo_state::argo_io_r(offs_t offset)
|
||||
u8 argo_state::argo_io_r(offs_t offset)
|
||||
{
|
||||
uint8_t low_io = offset;
|
||||
u8 low_io = offset;
|
||||
|
||||
switch (low_io)
|
||||
{
|
||||
@ -147,7 +147,7 @@ uint8_t argo_state::argo_io_r(offs_t offset)
|
||||
}
|
||||
}
|
||||
|
||||
void argo_state::argo_io_w(offs_t offset, uint8_t data)
|
||||
void argo_state::argo_io_w(offs_t offset, u8 data)
|
||||
{
|
||||
switch (offset)
|
||||
{
|
||||
@ -204,7 +204,7 @@ TIMER_DEVICE_CALLBACK_MEMBER( argo_state::kansas_r )
|
||||
m_cass_data[1]++;
|
||||
m_cass_data[2]++;
|
||||
|
||||
uint8_t cass_ws = (m_cass->input() > +0.04) ? 1 : 0;
|
||||
u8 cass_ws = (m_cass->input() > +0.04) ? 1 : 0;
|
||||
|
||||
if (cass_ws != m_cass_data[0])
|
||||
{
|
||||
@ -234,7 +234,7 @@ WRITE_LINE_MEMBER(argo_state::z0_w)
|
||||
// read - incoming 2514Hz
|
||||
}
|
||||
|
||||
uint8_t argo_state::dma_r(offs_t offset)
|
||||
u8 argo_state::dma_r(offs_t offset)
|
||||
{
|
||||
if (offset < 0xf800)
|
||||
return m_maincpu->space(AS_PROGRAM).read_byte(offset);
|
||||
@ -254,7 +254,7 @@ I8275_DRAW_CHARACTER_MEMBER(argo_state::display_pixels)
|
||||
m_framecnt++;
|
||||
|
||||
const rgb_t *palette = m_palette->palette()->entry_list_raw();
|
||||
uint8_t gfx = m_p_chargen[(linecount & 15) | (charcode << 4)];
|
||||
u8 gfx = m_p_chargen[(linecount & 15) | (charcode << 4)];
|
||||
|
||||
if (vsp)
|
||||
gfx = 0;
|
||||
@ -269,7 +269,7 @@ I8275_DRAW_CHARACTER_MEMBER(argo_state::display_pixels)
|
||||
if (rvv)
|
||||
gfx ^= 0xff;
|
||||
|
||||
for(uint8_t i=0;i<7;i++)
|
||||
for(u8 i=0;i<7;i++)
|
||||
bitmap.pix32(y, x + i) = palette[BIT(gfx, 6-i) ? (hlgt ? 2 : 1) : 0];
|
||||
}
|
||||
|
||||
@ -446,7 +446,7 @@ void argo_state::machine_reset()
|
||||
|
||||
void argo_state::init_argo()
|
||||
{
|
||||
uint8_t *RAM = memregion("maincpu")->base();
|
||||
u8 *RAM = memregion("maincpu")->base();
|
||||
membank("boot")->configure_entries(0, 2, &RAM[0x0000], 0xf800);
|
||||
}
|
||||
|
||||
|
||||
@ -36,22 +36,22 @@ public:
|
||||
, m_p_chargen(*this, "chargen")
|
||||
{ }
|
||||
|
||||
uint8_t beehive_60_r();
|
||||
void beehive_62_w(uint8_t data);
|
||||
uint32_t screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
|
||||
|
||||
void beehive(machine_config &config);
|
||||
|
||||
private:
|
||||
void beehive_io(address_map &map);
|
||||
void beehive_mem(address_map &map);
|
||||
private:
|
||||
u8 beehive_60_r();
|
||||
void beehive_62_w(u8 data);
|
||||
u32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
|
||||
required_device<cpu_device> m_maincpu;
|
||||
required_shared_ptr<uint8_t> m_p_videoram;
|
||||
required_shared_ptr<u8> m_p_videoram;
|
||||
required_region_ptr<u8> m_p_chargen;
|
||||
uint8_t m_keyline;
|
||||
u8 m_keyline;
|
||||
virtual void machine_reset() override;
|
||||
};
|
||||
|
||||
uint8_t beehive_state::beehive_60_r()
|
||||
u8 beehive_state::beehive_60_r()
|
||||
{
|
||||
if (BIT(m_keyline, 4))
|
||||
{
|
||||
@ -63,7 +63,7 @@ uint8_t beehive_state::beehive_60_r()
|
||||
return 0xff;
|
||||
}
|
||||
|
||||
void beehive_state::beehive_62_w(uint8_t data)
|
||||
void beehive_state::beehive_62_w(u8 data)
|
||||
{
|
||||
m_keyline = data;
|
||||
}
|
||||
@ -241,12 +241,12 @@ void beehive_state::machine_reset()
|
||||
|
||||
/* This system appears to have inline attribute bytes of unknown meaning.
|
||||
Currently they are ignored. */
|
||||
uint32_t beehive_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
|
||||
u32 beehive_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
|
||||
{
|
||||
uint16_t cursor_pos = (m_p_videoram[0xcaf] | (m_p_videoram[0xcb0] << 8)) & 0xfff;
|
||||
uint16_t p_linelist;
|
||||
uint8_t line_length;
|
||||
uint8_t y,ra,chr,gfx,inv;
|
||||
u8 line_length;
|
||||
u8 y,ra,chr,gfx,inv;
|
||||
uint16_t sy=0,ma,x;
|
||||
|
||||
for (y = 0; y < 25; y++)
|
||||
@ -258,7 +258,7 @@ uint32_t beehive_state::screen_update(screen_device &screen, bitmap_ind16 &bitma
|
||||
for (ra = 0; ra < 10; ra++)
|
||||
{
|
||||
uint16_t *p = &bitmap.pix16(sy++);
|
||||
uint8_t chars = 0;
|
||||
u8 chars = 0;
|
||||
|
||||
for (x = ma; x < ma + line_length; x++)
|
||||
{
|
||||
|
||||
@ -109,9 +109,12 @@ public:
|
||||
, m_bankr(*this, "bankr")
|
||||
, m_bankv(*this, "bankv")
|
||||
, m_banka(*this, "banka")
|
||||
{
|
||||
}
|
||||
{ }
|
||||
|
||||
void bigbord2(machine_config &config);
|
||||
void init_bigbord2();
|
||||
|
||||
private:
|
||||
DECLARE_WRITE_LINE_MEMBER(side_select_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(smc1_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(smc2_w);
|
||||
@ -127,17 +130,13 @@ public:
|
||||
DECLARE_WRITE_LINE_MEMBER(sio_wrdya_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(sio_wrdyb_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(fdc_drq_w);
|
||||
void init_bigbord2();
|
||||
uint8_t memory_read_byte(offs_t offset);
|
||||
void memory_write_byte(offs_t offset, uint8_t data);
|
||||
uint8_t io_read_byte(offs_t offset);
|
||||
void io_write_byte(offs_t offset, uint8_t data);
|
||||
MC6845_UPDATE_ROW(crtc_update_row);
|
||||
|
||||
void bigbord2(machine_config &config);
|
||||
void bigbord2_io(address_map &map);
|
||||
void bigbord2_mem(address_map &map);
|
||||
private:
|
||||
u8 crt8002(u8 ac_ra, u8 ac_chr, u8 ac_attr, uint16_t ac_cnt, bool ac_curs);
|
||||
u8 m_term_data;
|
||||
u8 m_term_status;
|
||||
|
||||
@ -191,41 +191,42 @@ public:
|
||||
, m_floppy1(*this, "fdc:1")
|
||||
{ }
|
||||
|
||||
void bank1_w(offs_t offset, uint8_t data);
|
||||
void bank6_w(offs_t offset, uint8_t data);
|
||||
void port58_w(uint8_t data); // drive select etc
|
||||
void port7f_w(uint8_t data); // banking 48k
|
||||
uint8_t port80_r(); // cassin for 48k
|
||||
void port80_w(uint8_t data); // control port 48k
|
||||
uint8_t port82_r(); // cassin for 128k
|
||||
void port82_w(uint8_t data); // banking 128k
|
||||
void port84_w(uint8_t data); // dac port 48k
|
||||
DECLARE_INPUT_CHANGED_MEMBER(brk_key);
|
||||
DECLARE_MACHINE_RESET(lynx48k);
|
||||
DECLARE_MACHINE_RESET(lynx128k);
|
||||
void init_lynx48k();
|
||||
void init_lynx128k();
|
||||
DECLARE_FLOPPY_FORMATS(camplynx_floppy_formats);
|
||||
MC6845_UPDATE_ROW(lynx48k_update_row);
|
||||
MC6845_UPDATE_ROW(lynx128k_update_row);
|
||||
required_device<palette_device> m_palette;
|
||||
void lynx_common(machine_config &config);
|
||||
void lynx_disk(machine_config &config);
|
||||
void lynx128k(machine_config &config);
|
||||
void lynx48k(machine_config &config);
|
||||
void lynx96k(machine_config &config);
|
||||
void init_lynx48k();
|
||||
void init_lynx128k();
|
||||
DECLARE_INPUT_CHANGED_MEMBER(brk_key);
|
||||
|
||||
private:
|
||||
void bank1_w(offs_t offset, u8 data);
|
||||
void bank6_w(offs_t offset, u8 data);
|
||||
void port58_w(u8 data); // drive select etc
|
||||
void port7f_w(u8 data); // banking 48k
|
||||
u8 port80_r(); // cassin for 48k
|
||||
void port80_w(u8 data); // control port 48k
|
||||
u8 port82_r(); // cassin for 128k
|
||||
void port82_w(u8 data); // banking 128k
|
||||
void port84_w(u8 data); // dac port 48k
|
||||
DECLARE_MACHINE_RESET(lynx48k);
|
||||
DECLARE_MACHINE_RESET(lynx128k);
|
||||
DECLARE_FLOPPY_FORMATS(camplynx_floppy_formats);
|
||||
MC6845_UPDATE_ROW(lynx48k_update_row);
|
||||
MC6845_UPDATE_ROW(lynx128k_update_row);
|
||||
void lynx128k_io(address_map &map);
|
||||
void lynx128k_mem(address_map &map);
|
||||
void lynx48k_io(address_map &map);
|
||||
void lynx48k_mem(address_map &map);
|
||||
void lynx96k_io(address_map &map);
|
||||
private:
|
||||
uint8_t m_port58;
|
||||
uint8_t m_port80;
|
||||
uint8_t m_bankdata;
|
||||
uint8_t m_wbyte;
|
||||
uint8_t *m_p_ram;
|
||||
u8 m_port58;
|
||||
u8 m_port80;
|
||||
u8 m_bankdata;
|
||||
u8 m_wbyte;
|
||||
u8 *m_p_ram;
|
||||
bool m_is_128k;
|
||||
required_device<palette_device> m_palette;
|
||||
required_device<z80_device> m_maincpu;
|
||||
required_device<cassette_image_device> m_cass;
|
||||
//required_device<> m_printer;
|
||||
@ -236,7 +237,7 @@ private:
|
||||
optional_device<floppy_connector> m_floppy1;
|
||||
};
|
||||
|
||||
void camplynx_state::port7f_w(uint8_t data)
|
||||
void camplynx_state::port7f_w(u8 data)
|
||||
{
|
||||
/*
|
||||
d0 = write to bank 1
|
||||
@ -254,7 +255,7 @@ d7 = read from bank 4 */
|
||||
// do writes
|
||||
m_wbyte = (data & 0x0f) | ((m_port80 & 0x0c) << 3);
|
||||
// do reads
|
||||
uint8_t rbyte = (data & 0x70) | (m_port80 & 0x0c);
|
||||
u8 rbyte = (data & 0x70) | (m_port80 & 0x0c);
|
||||
switch (rbyte)
|
||||
{
|
||||
case 0x00:
|
||||
@ -357,7 +358,7 @@ d7 = read from bank 4 */
|
||||
}
|
||||
}
|
||||
|
||||
void camplynx_state::port82_w(uint8_t data)
|
||||
void camplynx_state::port82_w(u8 data)
|
||||
{
|
||||
/* Almost the same as the 48k, except the bit order is reversed.
|
||||
d7 = write to bank 1
|
||||
@ -373,7 +374,7 @@ d0 = read from bank 4 */
|
||||
// do writes
|
||||
m_wbyte = bitswap<8>(data, 0, 0, 0, 0, 4, 5, 6, 7) & 0x0f; // rearrange to 1,2,3,4
|
||||
// do reads
|
||||
uint8_t rbyte = bitswap<8>(data, 0, 0, 0, 0, 0, 1, 2, 3) & 0x0f; // rearrange to 0,1,2,4
|
||||
u8 rbyte = bitswap<8>(data, 0, 0, 0, 0, 0, 1, 2, 3) & 0x0f; // rearrange to 0,1,2,4
|
||||
if (BIT(rbyte, 1))
|
||||
rbyte &= 0x07; // remove 4 if 1 selected (AND gate in IC82)
|
||||
//printf("%s:%X:%X:%X\n", machine().describe_context().c_str(), data, rbyte, m_wbyte);
|
||||
@ -631,7 +632,7 @@ INPUT_CHANGED_MEMBER( camplynx_state::brk_key )
|
||||
m_maincpu->set_input_line(0, newval ? CLEAR_LINE : ASSERT_LINE);
|
||||
}
|
||||
|
||||
void camplynx_state::bank1_w(offs_t offset, uint8_t data)
|
||||
void camplynx_state::bank1_w(offs_t offset, u8 data)
|
||||
{
|
||||
if (BIT(m_wbyte, 0))
|
||||
m_p_ram[offset+0x10000] = data;
|
||||
@ -643,7 +644,7 @@ void camplynx_state::bank1_w(offs_t offset, uint8_t data)
|
||||
m_p_ram[offset+0x40000] = data;
|
||||
}
|
||||
|
||||
void camplynx_state::bank6_w(offs_t offset, uint8_t data)
|
||||
void camplynx_state::bank6_w(offs_t offset, u8 data)
|
||||
{
|
||||
if (BIT(m_wbyte, 0))
|
||||
m_p_ram[offset+0x10000] = data;
|
||||
@ -667,9 +668,9 @@ void camplynx_state::bank6_w(offs_t offset, uint8_t data)
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t camplynx_state::port80_r()
|
||||
u8 camplynx_state::port80_r()
|
||||
{
|
||||
uint8_t data = ioport("LINE0")->read();
|
||||
u8 data = ioport("LINE0")->read();
|
||||
// when reading tape, bit 0 becomes cass-in signal
|
||||
if (BIT(m_port80, 1))
|
||||
{
|
||||
@ -688,7 +689,7 @@ d3 = cass motor on
|
||||
d2 = cass enable
|
||||
d1 = serial h/s out
|
||||
d0 = speaker */
|
||||
void camplynx_state::port80_w(uint8_t data)
|
||||
void camplynx_state::port80_w(u8 data)
|
||||
{
|
||||
m_port80 = data;
|
||||
m_cass->change_state( BIT(data, (m_is_128k) ? 3 : 1) ? CASSETTE_MOTOR_ENABLED : CASSETTE_MOTOR_DISABLED, CASSETTE_MASK_MOTOR);
|
||||
@ -702,7 +703,7 @@ void camplynx_state::port80_w(uint8_t data)
|
||||
MESS can load PALE's wav files though.
|
||||
Currently square wave output is selected. */
|
||||
|
||||
void camplynx_state::port84_w(uint8_t data)
|
||||
void camplynx_state::port84_w(u8 data)
|
||||
{
|
||||
if (BIT(m_port80, (m_is_128k) ? 3 : 1)) // for 128k, bit 2 might be ok too
|
||||
{
|
||||
@ -722,9 +723,9 @@ d7 = clock
|
||||
d2 = cass-in
|
||||
d1 = serial data in
|
||||
d0 = serial h/s in */
|
||||
uint8_t camplynx_state::port82_r()
|
||||
u8 camplynx_state::port82_r()
|
||||
{
|
||||
uint8_t data = 0xfb; // guess
|
||||
u8 data = 0xfb; // guess
|
||||
data |= (m_cass->input() > +0.02) ? 4 : 0;
|
||||
return data;
|
||||
}
|
||||
@ -747,7 +748,7 @@ MACHINE_RESET_MEMBER(camplynx_state, lynx128k)
|
||||
|
||||
MC6845_UPDATE_ROW( camplynx_state::lynx48k_update_row )
|
||||
{
|
||||
uint8_t r,g,b,x;
|
||||
u8 r,g,b,x;
|
||||
uint32_t green_bank, *p = &bitmap.pix32(y);
|
||||
uint16_t mem = ((ma << 2) + (ra << 5)) & 0x1fff;
|
||||
|
||||
@ -776,7 +777,7 @@ MC6845_UPDATE_ROW( camplynx_state::lynx48k_update_row )
|
||||
|
||||
MC6845_UPDATE_ROW( camplynx_state::lynx128k_update_row )
|
||||
{
|
||||
uint8_t r,g,b,x;
|
||||
u8 r,g,b,x;
|
||||
uint32_t green_bank, *p = &bitmap.pix32(y);
|
||||
uint16_t mem = ((ma << 2) + (ra << 6)) & 0x3fff;
|
||||
// determine green bank
|
||||
@ -802,7 +803,7 @@ MC6845_UPDATE_ROW( camplynx_state::lynx128k_update_row )
|
||||
}
|
||||
}
|
||||
|
||||
void camplynx_state::port58_w(uint8_t data)
|
||||
void camplynx_state::port58_w(u8 data)
|
||||
{
|
||||
/*
|
||||
d0,d1 = drive select
|
||||
|
||||
@ -74,21 +74,20 @@ ToDo:
|
||||
class ccs_state : public driver_device
|
||||
{
|
||||
public:
|
||||
ccs_state(const machine_config &mconfig, device_type type, const char *tag) :
|
||||
driver_device(mconfig, type, tag),
|
||||
m_maincpu(*this, "maincpu"),
|
||||
m_ram(*this, RAM_TAG),
|
||||
m_rom(*this, "maincpu"),
|
||||
m_ins8250(*this, "ins8250"),
|
||||
m_fdc(*this, "fdc"),
|
||||
m_floppy0(*this, "fdc:0"),
|
||||
m_jump_addr_sel(*this, {"ADDRLO", "ADDRHI"}),
|
||||
m_ser_addr_sel(*this, "SERADDR"),
|
||||
m_jump_en(*this, "JMPEN"),
|
||||
m_rom_en(*this, "ROMEN"),
|
||||
m_ser_en(*this, "SEREN")
|
||||
{
|
||||
}
|
||||
ccs_state(const machine_config &mconfig, device_type type, const char *tag)
|
||||
: driver_device(mconfig, type, tag)
|
||||
, m_maincpu(*this, "maincpu")
|
||||
, m_ram(*this, RAM_TAG)
|
||||
, m_rom(*this, "maincpu")
|
||||
, m_ins8250(*this, "ins8250")
|
||||
, m_fdc(*this, "fdc")
|
||||
, m_floppy0(*this, "fdc:0")
|
||||
, m_jump_addr_sel(*this, {"ADDRLO", "ADDRHI"})
|
||||
, m_ser_addr_sel(*this, "SERADDR")
|
||||
, m_jump_en(*this, "JMPEN")
|
||||
, m_rom_en(*this, "ROMEN")
|
||||
, m_ser_en(*this, "SEREN")
|
||||
{ }
|
||||
|
||||
void init_ccs2810();
|
||||
void init_ccs2422();
|
||||
@ -96,29 +95,28 @@ public:
|
||||
void ccs2810(machine_config &config);
|
||||
void ccs2422(machine_config &config);
|
||||
|
||||
protected:
|
||||
uint8_t memory_read(offs_t offset);
|
||||
void memory_write(offs_t offset, uint8_t data);
|
||||
uint8_t io_read(offs_t offset);
|
||||
void io_write(offs_t offset, uint8_t data);
|
||||
private:
|
||||
u8 memory_read(offs_t offset);
|
||||
void memory_write(offs_t offset, u8 data);
|
||||
u8 io_read(offs_t offset);
|
||||
void io_write(offs_t offset, u8 data);
|
||||
|
||||
virtual void machine_start() override;
|
||||
virtual void machine_reset() override;
|
||||
|
||||
uint8_t port04_r();
|
||||
uint8_t port34_r();
|
||||
void port04_w(uint8_t data);
|
||||
void port34_w(uint8_t data);
|
||||
void port40_w(uint8_t data);
|
||||
u8 port04_r();
|
||||
u8 port34_r();
|
||||
void port04_w(u8 data);
|
||||
void port34_w(u8 data);
|
||||
void port40_w(u8 data);
|
||||
|
||||
void ccs2422_io(address_map &map);
|
||||
void ccs2810_io(address_map &map);
|
||||
void ccs2810_mem(address_map &map);
|
||||
|
||||
private:
|
||||
required_device<cpu_device> m_maincpu;
|
||||
required_device<ram_device> m_ram;
|
||||
required_region_ptr<uint8_t> m_rom;
|
||||
required_region_ptr<u8> m_rom;
|
||||
required_device<ins8250_device> m_ins8250;
|
||||
optional_device<mb8877_device> m_fdc;
|
||||
optional_device<floppy_connector> m_floppy0;
|
||||
@ -129,18 +127,18 @@ private:
|
||||
required_ioport m_rom_en;
|
||||
required_ioport m_ser_en;
|
||||
|
||||
uint8_t m_power_on_status;
|
||||
u8 m_power_on_status;
|
||||
|
||||
bool m_ss;
|
||||
bool m_dden;
|
||||
bool m_dsize;
|
||||
uint8_t m_ds;
|
||||
u8 m_ds;
|
||||
floppy_image_device *m_floppy;
|
||||
};
|
||||
|
||||
uint8_t ccs_state::memory_read(offs_t offset)
|
||||
u8 ccs_state::memory_read(offs_t offset)
|
||||
{
|
||||
uint8_t result = m_ram->read(offset);
|
||||
u8 result = m_ram->read(offset);
|
||||
|
||||
if (!BIT(m_power_on_status, 0))
|
||||
{
|
||||
@ -164,12 +162,12 @@ uint8_t ccs_state::memory_read(offs_t offset)
|
||||
return result;
|
||||
}
|
||||
|
||||
void ccs_state::memory_write(offs_t offset, uint8_t data)
|
||||
void ccs_state::memory_write(offs_t offset, u8 data)
|
||||
{
|
||||
m_ram->write(offset, data);
|
||||
}
|
||||
|
||||
uint8_t ccs_state::io_read(offs_t offset)
|
||||
u8 ccs_state::io_read(offs_t offset)
|
||||
{
|
||||
// A7-A3 are compared against jumper settings
|
||||
if (m_ser_en->read() && (offset & 0x00f8) == m_ser_addr_sel->read())
|
||||
@ -178,7 +176,7 @@ uint8_t ccs_state::io_read(offs_t offset)
|
||||
return 0xff;
|
||||
}
|
||||
|
||||
void ccs_state::io_write(offs_t offset, uint8_t data)
|
||||
void ccs_state::io_write(offs_t offset, u8 data)
|
||||
{
|
||||
// A7-A3 are compared against jumper settings
|
||||
if (m_ser_en->read() && (offset & 0x00f8) == m_ser_addr_sel->read())
|
||||
@ -792,10 +790,10 @@ d6 : autoboot (1=go to monitor)
|
||||
d7 : drq
|
||||
*/
|
||||
|
||||
uint8_t ccs_state::port34_r()
|
||||
u8 ccs_state::port34_r()
|
||||
{
|
||||
//return (uint8_t)m_drq | (m_ds << 1) | ((uint8_t)fdc->hld_r() << 5) | 0x40 | ((uint8_t)m_intrq << 7);
|
||||
return (uint8_t)m_fdc->drq_r() | (m_ds << 1) | 0x20 | 0x40 | ((uint8_t)m_fdc->intrq_r() << 7); // hld_r doesn't do anything
|
||||
//return (u8)m_drq | (m_ds << 1) | ((u8)fdc->hld_r() << 5) | 0x40 | ((u8)m_intrq << 7);
|
||||
return (u8)m_fdc->drq_r() | (m_ds << 1) | 0x20 | 0x40 | ((u8)m_fdc->intrq_r() << 7); // hld_r doesn't do anything
|
||||
}
|
||||
|
||||
/* Status 2
|
||||
@ -809,7 +807,7 @@ d6 : double (0 = a double-sided 20cm disk is in the drive)
|
||||
d7 : drq
|
||||
*/
|
||||
|
||||
uint8_t ccs_state::port04_r()
|
||||
u8 ccs_state::port04_r()
|
||||
{
|
||||
bool trk00=1,wprt=0,dside=1;
|
||||
int idx=1;
|
||||
@ -820,8 +818,8 @@ uint8_t ccs_state::port04_r()
|
||||
idx = m_floppy->idx_r()^1;
|
||||
dside = m_floppy->twosid_r();
|
||||
}
|
||||
return (uint8_t)trk00 | 0 | ((uint8_t)wprt << 2) | ((uint8_t)m_ss << 3) |
|
||||
idx << 4 | ((uint8_t)m_dden << 5) | ((uint8_t)dside << 6) | ((uint8_t)m_fdc->drq_r() << 7);
|
||||
return (u8)trk00 | 0 | ((u8)wprt << 2) | ((u8)m_ss << 3) |
|
||||
idx << 4 | ((u8)m_dden << 5) | ((u8)dside << 6) | ((u8)m_fdc->drq_r() << 7);
|
||||
}
|
||||
|
||||
/* Control 1
|
||||
@ -835,7 +833,7 @@ d6 : dden
|
||||
d7 : autowait (0=ignore drq)
|
||||
*/
|
||||
|
||||
void ccs_state::port34_w(uint8_t data)
|
||||
void ccs_state::port34_w(u8 data)
|
||||
{
|
||||
m_ds = data & 15;
|
||||
m_dsize = BIT(data, 4);
|
||||
@ -860,7 +858,7 @@ d7 : rom enable (1=firmware enabled)
|
||||
other bits not used
|
||||
*/
|
||||
|
||||
void ccs_state::port04_w(uint8_t data)
|
||||
void ccs_state::port04_w(u8 data)
|
||||
{
|
||||
m_ss = BIT(data, 6);
|
||||
if (m_floppy)
|
||||
@ -873,7 +871,7 @@ void ccs_state::port04_w(uint8_t data)
|
||||
// Machine
|
||||
//
|
||||
//*************************************
|
||||
void ccs_state::port40_w(uint8_t data)
|
||||
void ccs_state::port40_w(u8 data)
|
||||
{
|
||||
//membank("bankr0")->set_entry( (data) ? 1 : 0);
|
||||
}
|
||||
|
||||
@ -39,17 +39,16 @@ public:
|
||||
|
||||
void ccs300(machine_config &config);
|
||||
|
||||
protected:
|
||||
private:
|
||||
virtual void machine_start() override;
|
||||
virtual void machine_reset() override;
|
||||
|
||||
private:
|
||||
required_device<z80_device> m_maincpu;
|
||||
|
||||
void ccs300_io(address_map &map);
|
||||
void ccs300_mem(address_map &map);
|
||||
|
||||
void port40_w(uint8_t data);
|
||||
void port40_w(u8 data);
|
||||
};
|
||||
|
||||
void ccs300_state::ccs300_mem(address_map &map)
|
||||
@ -91,7 +90,7 @@ static const z80_daisy_config daisy_chain[] =
|
||||
// Machine
|
||||
//
|
||||
//*************************************
|
||||
void ccs300_state::port40_w(uint8_t data)
|
||||
void ccs300_state::port40_w(u8 data)
|
||||
{
|
||||
membank("bankr0")->set_entry( (data) ? 1 : 0);
|
||||
}
|
||||
@ -104,7 +103,7 @@ void ccs300_state::machine_reset()
|
||||
|
||||
void ccs300_state::machine_start()
|
||||
{
|
||||
uint8_t *main = memregion("maincpu")->base();
|
||||
u8 *main = memregion("maincpu")->base();
|
||||
|
||||
membank("bankr0")->configure_entry(1, &main[0x0000]);
|
||||
membank("bankr0")->configure_entry(0, &main[0x10000]);
|
||||
|
||||
@ -78,7 +78,7 @@ private:
|
||||
void cd2650_data(address_map &map);
|
||||
void cd2650_io(address_map &map);
|
||||
void cd2650_mem(address_map &map);
|
||||
uint8_t keyin_r();
|
||||
u8 keyin_r();
|
||||
void kbd_put(u8 data);
|
||||
DECLARE_WRITE_LINE_MEMBER(tape_deck_on_w);
|
||||
DECLARE_READ_LINE_MEMBER(cass_r);
|
||||
@ -86,13 +86,13 @@ private:
|
||||
TIMER_DEVICE_CALLBACK_MEMBER(kansas_r);
|
||||
DECLARE_QUICKLOAD_LOAD_MEMBER(quickload_cb);
|
||||
uint32_t screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
|
||||
uint8_t m_term_data;
|
||||
u8 m_term_data;
|
||||
bool m_cassbit;
|
||||
bool m_cassold;
|
||||
uint8_t m_cass_data[4];
|
||||
u8 m_cass_data[4];
|
||||
virtual void machine_reset() override;
|
||||
required_device<s2650_device> m_maincpu;
|
||||
required_shared_ptr<uint8_t> m_p_videoram;
|
||||
required_shared_ptr<u8> m_p_videoram;
|
||||
required_region_ptr<u8> m_p_chargen;
|
||||
required_device<cassette_image_device> m_cass;
|
||||
};
|
||||
@ -118,7 +118,7 @@ TIMER_DEVICE_CALLBACK_MEMBER(cd2650_state::kansas_r)
|
||||
{
|
||||
/* cassette - turn 1200/2400Hz to a bit */
|
||||
m_cass_data[1]++;
|
||||
uint8_t cass_ws = (m_cass->input() > +0.03) ? 1 : 0;
|
||||
u8 cass_ws = (m_cass->input() > +0.03) ? 1 : 0;
|
||||
|
||||
if (cass_ws != m_cass_data[0])
|
||||
{
|
||||
@ -138,9 +138,9 @@ READ_LINE_MEMBER(cd2650_state::cass_r)
|
||||
return m_cass_data[2];
|
||||
}
|
||||
|
||||
uint8_t cd2650_state::keyin_r()
|
||||
u8 cd2650_state::keyin_r()
|
||||
{
|
||||
uint8_t ret = m_term_data;
|
||||
u8 ret = m_term_data;
|
||||
m_term_data = ret | 0x80;
|
||||
return ret;
|
||||
}
|
||||
@ -181,7 +181,7 @@ uint32_t cd2650_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap
|
||||
When the bottom of the screen is reached, it does not scroll, it just wraps around. */
|
||||
|
||||
uint16_t offset = 0;
|
||||
uint8_t y,ra,chr,gfx;
|
||||
u8 y,ra,chr,gfx;
|
||||
uint16_t sy=0,x,mem;
|
||||
|
||||
for (y = 0; y < 16; y++)
|
||||
@ -263,7 +263,7 @@ QUICKLOAD_LOAD_MEMBER(cd2650_state::quickload_cb)
|
||||
}
|
||||
else
|
||||
{
|
||||
std::vector<uint8_t> quick_data(quick_length);
|
||||
std::vector<u8> quick_data(quick_length);
|
||||
int read_ = image.fread( &quick_data[0], quick_length);
|
||||
if (read_ != quick_length)
|
||||
{
|
||||
|
||||
@ -43,23 +43,23 @@ public:
|
||||
, m_terminal(*this, "terminal")
|
||||
, m_p_ram(*this, "ram")
|
||||
, m_maincpu(*this, "maincpu")
|
||||
{
|
||||
}
|
||||
{ }
|
||||
|
||||
uint8_t port1e_r();
|
||||
void port1f_w(uint8_t data);
|
||||
uint8_t port90_r();
|
||||
uint8_t port91_r();
|
||||
void kbd_put(u8 data);
|
||||
void chaos(machine_config &config);
|
||||
|
||||
private:
|
||||
u8 port1e_r();
|
||||
void port1f_w(u8 data);
|
||||
u8 port90_r();
|
||||
u8 port91_r();
|
||||
void kbd_put(u8 data);
|
||||
void data_map(address_map &map);
|
||||
void io_map(address_map &map);
|
||||
void mem_map(address_map &map);
|
||||
private:
|
||||
uint8_t m_term_data;
|
||||
u8 m_term_data;
|
||||
virtual void machine_reset() override;
|
||||
required_device<generic_terminal_device> m_terminal;
|
||||
required_shared_ptr<uint8_t> m_p_ram;
|
||||
required_shared_ptr<u8> m_p_ram;
|
||||
required_device<cpu_device> m_maincpu;
|
||||
};
|
||||
|
||||
@ -96,12 +96,12 @@ INPUT_PORTS_END
|
||||
|
||||
// Port 1E - Bit 0 indicates key pressed, Bit 1 indicates ok to output
|
||||
|
||||
uint8_t chaos_state::port1e_r()
|
||||
u8 chaos_state::port1e_r()
|
||||
{
|
||||
return (m_term_data) ? 1 : 0;
|
||||
}
|
||||
|
||||
void chaos_state::port1f_w(uint8_t data)
|
||||
void chaos_state::port1f_w(u8 data)
|
||||
{
|
||||
// make the output readable on our terminal
|
||||
if (data == 0x09)
|
||||
@ -116,9 +116,9 @@ void chaos_state::port1f_w(uint8_t data)
|
||||
m_terminal->write(0x0a);
|
||||
}
|
||||
|
||||
uint8_t chaos_state::port90_r()
|
||||
u8 chaos_state::port90_r()
|
||||
{
|
||||
uint8_t ret = m_term_data;
|
||||
u8 ret = m_term_data;
|
||||
m_term_data = 0;
|
||||
return ret;
|
||||
}
|
||||
@ -128,9 +128,9 @@ uint8_t chaos_state::port90_r()
|
||||
// Bit 3 = key pressed
|
||||
// Bit 7 = ok to output
|
||||
|
||||
uint8_t chaos_state::port91_r()
|
||||
u8 chaos_state::port91_r()
|
||||
{
|
||||
uint8_t ret = 0x80 | ioport("CONFIG")->read();
|
||||
u8 ret = 0x80 | ioport("CONFIG")->read();
|
||||
ret |= (m_term_data) ? 8 : 0;
|
||||
return ret;
|
||||
}
|
||||
@ -143,7 +143,7 @@ void chaos_state::kbd_put(u8 data)
|
||||
void chaos_state::machine_reset()
|
||||
{
|
||||
// copy the roms into ram
|
||||
uint8_t* ROM = memregion("roms")->base();
|
||||
u8* ROM = memregion("roms")->base();
|
||||
memcpy(m_p_ram, ROM, 0x3000);
|
||||
memcpy(m_p_ram+0x7000, ROM+0x3000, 0x1000);
|
||||
}
|
||||
|
||||
@ -49,18 +49,18 @@ public:
|
||||
, m_uart(*this, "uart")
|
||||
{ }
|
||||
|
||||
uint8_t uart_status_r();
|
||||
|
||||
void cm1800(machine_config &config);
|
||||
|
||||
private:
|
||||
void io_map(address_map &map);
|
||||
void mem_map(address_map &map);
|
||||
private:
|
||||
virtual void machine_reset() override;
|
||||
u8 uart_status_r();
|
||||
required_device<cpu_device> m_maincpu;
|
||||
required_device<ay31015_device> m_uart;
|
||||
};
|
||||
|
||||
uint8_t cm1800_state::uart_status_r()
|
||||
u8 cm1800_state::uart_status_r()
|
||||
{
|
||||
return (m_uart->dav_r()) | (m_uart->tbmt_r() << 2);
|
||||
}
|
||||
|
||||
@ -64,21 +64,21 @@ public:
|
||||
, m_io_dsw(*this, "DSW")
|
||||
{ }
|
||||
|
||||
void cortex(machine_config &config);
|
||||
void init_init();
|
||||
|
||||
private:
|
||||
void kbd_put(u8 data);
|
||||
DECLARE_WRITE_LINE_MEMBER(keyboard_ack_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(romsw_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(vdp_int_w);
|
||||
uint8_t pio_r(offs_t offset);
|
||||
uint8_t keyboard_r(offs_t offset);
|
||||
void init_init();
|
||||
|
||||
void cortex(machine_config &config);
|
||||
u8 pio_r(offs_t offset);
|
||||
u8 keyboard_r(offs_t offset);
|
||||
void io_map(address_map &map);
|
||||
void mem_map(address_map &map);
|
||||
private:
|
||||
bool m_kbd_ack;
|
||||
bool m_vdp_int;
|
||||
uint8_t m_term_data;
|
||||
u8 m_term_data;
|
||||
virtual void machine_reset() override;
|
||||
required_device<tms9995_device> m_maincpu;
|
||||
required_device<beep_device> m_beep;
|
||||
@ -119,7 +119,7 @@ static INPUT_PORTS_START( cortex )
|
||||
PORT_DIPSETTING( 0x00, "Single")
|
||||
INPUT_PORTS_END
|
||||
|
||||
uint8_t cortex_state::pio_r(offs_t offset)
|
||||
u8 cortex_state::pio_r(offs_t offset)
|
||||
{
|
||||
switch (offset)
|
||||
{
|
||||
@ -138,7 +138,7 @@ uint8_t cortex_state::pio_r(offs_t offset)
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t cortex_state::keyboard_r(offs_t offset)
|
||||
u8 cortex_state::keyboard_r(offs_t offset)
|
||||
{
|
||||
return BIT(m_term_data, offset);
|
||||
}
|
||||
@ -182,7 +182,7 @@ void cortex_state::machine_reset()
|
||||
|
||||
void cortex_state::init_init()
|
||||
{
|
||||
uint8_t *main = memregion("maincpu")->base();
|
||||
u8 *main = memregion("maincpu")->base();
|
||||
|
||||
membank("bankr0")->configure_entry(1, &main[0x10000]);
|
||||
membank("bankr0")->configure_entry(0, &main[0x00000]);
|
||||
|
||||
@ -45,36 +45,44 @@ public:
|
||||
{ }
|
||||
|
||||
void cvicny(machine_config &config);
|
||||
void cvicny_mem(address_map &map);
|
||||
uint8_t key_r();
|
||||
void digit_w(uint8_t data);
|
||||
void segment_w(uint8_t data);
|
||||
|
||||
private:
|
||||
uint8_t m_digit;
|
||||
uint8_t m_seg;
|
||||
void cvicny_mem(address_map &map);
|
||||
virtual void machine_start() override;
|
||||
u8 key_r();
|
||||
void digit_w(u8 data);
|
||||
void segment_w(u8 data);
|
||||
u8 m_digit;
|
||||
u8 m_seg;
|
||||
required_device<cpu_device> m_maincpu;
|
||||
required_device<pwm_display_device> m_display;
|
||||
required_ioport_array<8> m_io_keyboard;
|
||||
};
|
||||
|
||||
void cvicny_state::segment_w(uint8_t data) // output segments on the selected digit
|
||||
void cvicny_state::segment_w(u8 data) // output segments on the selected digit
|
||||
{
|
||||
m_seg = data;
|
||||
m_display->matrix(1<<m_digit, m_seg);
|
||||
}
|
||||
|
||||
void cvicny_state::digit_w(uint8_t data) // set keyboard scanning row; set digit to display
|
||||
void cvicny_state::digit_w(u8 data) // set keyboard scanning row; set digit to display
|
||||
{
|
||||
m_digit = data & 7;
|
||||
m_display->matrix(1<<m_digit, m_seg);
|
||||
}
|
||||
|
||||
uint8_t cvicny_state::key_r()
|
||||
u8 cvicny_state::key_r()
|
||||
{
|
||||
u8 data = m_io_keyboard[m_digit]->read();
|
||||
return ((data << 4) ^ 0xf0) | data;
|
||||
}
|
||||
|
||||
void cvicny_state::machine_start()
|
||||
{
|
||||
save_item(NAME(m_digit));
|
||||
save_item(NAME(m_seg));
|
||||
}
|
||||
|
||||
void cvicny_state::cvicny_mem(address_map &map)
|
||||
{
|
||||
map.unmap_value_high();
|
||||
@ -150,4 +158,4 @@ ROM_END
|
||||
/* Driver */
|
||||
|
||||
// YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS
|
||||
COMP( 1984, cvicny, 0, 0, cvicny, cvicny, cvicny_state, empty_init, "<unknown>", "Practice-z80", MACHINE_NO_SOUND_HW)
|
||||
COMP( 1984, cvicny, 0, 0, cvicny, cvicny, cvicny_state, empty_init, "<unknown>", "Practice-z80", MACHINE_NO_SOUND_HW | MACHINE_SUPPORTS_SAVE )
|
||||
|
||||
@ -62,40 +62,38 @@ public:
|
||||
void czk80(machine_config &config);
|
||||
void init_czk80();
|
||||
|
||||
protected:
|
||||
virtual void machine_reset() override;
|
||||
|
||||
private:
|
||||
virtual void machine_reset() override;
|
||||
TIMER_CALLBACK_MEMBER(czk80_reset);
|
||||
uint8_t port80_r();
|
||||
uint8_t port81_r();
|
||||
void port40_w(uint8_t data);
|
||||
u8 port80_r();
|
||||
u8 port81_r();
|
||||
void port40_w(u8 data);
|
||||
void kbd_put(u8 data);
|
||||
DECLARE_WRITE_LINE_MEMBER(ctc_z0_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(ctc_z1_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(ctc_z2_w);
|
||||
void czk80_io(address_map &map);
|
||||
void czk80_mem(address_map &map);
|
||||
uint8_t m_term_data;
|
||||
u8 m_term_data;
|
||||
required_device<z80_device> m_maincpu;
|
||||
required_device<generic_terminal_device> m_terminal;
|
||||
required_device<upd765a_device> m_fdc;
|
||||
};
|
||||
|
||||
|
||||
void czk80_state::port40_w(uint8_t data)
|
||||
void czk80_state::port40_w(u8 data)
|
||||
{
|
||||
membank("bankr1")->set_entry(BIT(data, 1));
|
||||
}
|
||||
|
||||
uint8_t czk80_state::port80_r()
|
||||
u8 czk80_state::port80_r()
|
||||
{
|
||||
uint8_t ret = m_term_data;
|
||||
u8 ret = m_term_data;
|
||||
m_term_data = 0;
|
||||
return ret;
|
||||
}
|
||||
|
||||
uint8_t czk80_state::port81_r()
|
||||
u8 czk80_state::port81_r()
|
||||
{
|
||||
return (m_term_data) ? 3 : 1;
|
||||
}
|
||||
@ -166,7 +164,7 @@ void czk80_state::machine_reset()
|
||||
|
||||
void czk80_state::init_czk80()
|
||||
{
|
||||
uint8_t *main = memregion("maincpu")->base();
|
||||
u8 *main = memregion("maincpu")->base();
|
||||
|
||||
membank("bankr0")->configure_entry(1, &main[0x0000]);
|
||||
membank("bankr0")->configure_entry(0, &main[0x10000]);
|
||||
|
||||
@ -121,13 +121,13 @@ public:
|
||||
void d6809(machine_config &config);
|
||||
|
||||
private:
|
||||
uint8_t term_r();
|
||||
void term_w(uint8_t data);
|
||||
u8 term_r();
|
||||
void term_w(u8 data);
|
||||
void kbd_put(u8 data);
|
||||
|
||||
void mem_map(address_map &map);
|
||||
|
||||
uint8_t m_term_data;
|
||||
u8 m_term_data;
|
||||
virtual void machine_reset() override;
|
||||
required_device<cpu_device> m_maincpu;
|
||||
required_device<generic_terminal_device> m_terminal;
|
||||
@ -135,14 +135,14 @@ private:
|
||||
required_device<floppy_connector> m_floppy0;
|
||||
};
|
||||
|
||||
uint8_t d6809_state::term_r()
|
||||
u8 d6809_state::term_r()
|
||||
{
|
||||
uint8_t ret = m_term_data;
|
||||
u8 ret = m_term_data;
|
||||
m_term_data = 0;
|
||||
return ret;
|
||||
}
|
||||
|
||||
void d6809_state::term_w(uint8_t data)
|
||||
void d6809_state::term_w(u8 data)
|
||||
{
|
||||
if ((data > 0) && (data < 0x80))
|
||||
m_terminal->write(data);
|
||||
|
||||
@ -50,7 +50,6 @@ public:
|
||||
{ }
|
||||
|
||||
void dms86(machine_config &config);
|
||||
|
||||
DECLARE_WRITE_LINE_MEMBER(nmi_w);
|
||||
|
||||
private:
|
||||
@ -145,14 +144,7 @@ void dms86_state::dms86(machine_config &config)
|
||||
m_maincpu->set_addrmap(AS_PROGRAM, &dms86_state::mem_map);
|
||||
m_maincpu->set_addrmap(AS_IO, &dms86_state::io_map);
|
||||
|
||||
// According to the manual the clock is 14,765,600 / 4 but that couldn't possibly work.
|
||||
// By maths, clock should be 9600*32*4*16 = 19,660,800 but not working either
|
||||
// So, commented out because it makes the whole thing crawl, only get 18% on my machine
|
||||
//clock_device &ctc_clock(CLOCK(config, "ctc_clock", 19660800)); //XTAL(14'745'600) / 4
|
||||
//ctc_clock.signal_handler().set(m_ctc, FUNC(z80ctc_device::trg0));
|
||||
//ctc_clock.signal_handler().append(m_ctc, FUNC(z80ctc_device::trg1));
|
||||
//ctc_clock.signal_handler().append(m_ctc, FUNC(z80ctc_device::trg2));
|
||||
|
||||
// According to the manual the clock is 14,765,600 / 4 but that's wrong
|
||||
Z80CTC(config, m_ctc, XTAL(14'745'600) / 3);
|
||||
//m_ctc->intr_callback().set_inputline(m_maincpu, INPUT_LINE_IRQ0); // frame rate interrupt to maincpu
|
||||
m_ctc->zc_callback<0>().set(m_sio[0], FUNC(z80sio_device::rxtxcb_w)); // SIO1 Ch B
|
||||
@ -188,4 +180,4 @@ ROM_END
|
||||
/* Driver */
|
||||
|
||||
/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS */
|
||||
COMP( 1982, dms86, 0, 0, dms86, dms86, dms86_state, empty_init, "Digital Microsystems", "DMS-86", MACHINE_NOT_WORKING | MACHINE_NO_SOUND)
|
||||
COMP( 1982, dms86, 0, 0, dms86, dms86, dms86_state, empty_init, "Digital Microsystems", "DMS-86", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW )
|
||||
|
||||
@ -106,15 +106,15 @@ public:
|
||||
|
||||
private:
|
||||
DECLARE_READ_LINE_MEMBER(cass_r);
|
||||
uint8_t port07_r();
|
||||
void port00_w(offs_t offset, uint8_t data);
|
||||
void port06_w(uint8_t data);
|
||||
u8 port07_r();
|
||||
void port00_w(offs_t offset, u8 data);
|
||||
void port06_w(u8 data);
|
||||
TIMER_DEVICE_CALLBACK_MEMBER(kansas_w);
|
||||
void dauphin_io(address_map &map);
|
||||
void dauphin_mem(address_map &map);
|
||||
|
||||
uint8_t m_cass_data;
|
||||
uint8_t m_last_key;
|
||||
u8 m_cass_data;
|
||||
u8 m_last_key;
|
||||
bool m_cassbit;
|
||||
bool m_cassold;
|
||||
bool m_speaker_state;
|
||||
@ -129,20 +129,20 @@ READ_LINE_MEMBER( dauphin_state::cass_r )
|
||||
return (m_cass->input() > 0.03) ? 1 : 0;
|
||||
}
|
||||
|
||||
void dauphin_state::port00_w(offs_t offset, uint8_t data)
|
||||
void dauphin_state::port00_w(offs_t offset, u8 data)
|
||||
{
|
||||
m_display->matrix(1<<offset, data);
|
||||
}
|
||||
|
||||
void dauphin_state::port06_w(uint8_t data)
|
||||
void dauphin_state::port06_w(u8 data)
|
||||
{
|
||||
m_speaker_state ^=1;
|
||||
m_speaker->level_w(m_speaker_state);
|
||||
}
|
||||
|
||||
uint8_t dauphin_state::port07_r()
|
||||
u8 dauphin_state::port07_r()
|
||||
{
|
||||
uint8_t keyin, i, data = 0x40;
|
||||
u8 keyin, i, data = 0x40;
|
||||
|
||||
keyin = ioport("X0")->read();
|
||||
if (keyin != 0xff)
|
||||
|
||||
@ -35,28 +35,25 @@ public:
|
||||
{ }
|
||||
|
||||
void dps1(machine_config &config);
|
||||
|
||||
void init_dps1();
|
||||
|
||||
protected:
|
||||
virtual void machine_reset() override;
|
||||
|
||||
private:
|
||||
void portb2_w(uint8_t data);
|
||||
void portb4_w(uint8_t data);
|
||||
void portb6_w(uint8_t data);
|
||||
void portb8_w(uint8_t data);
|
||||
void portba_w(uint8_t data);
|
||||
void portbc_w(uint8_t data);
|
||||
void portbe_w(uint8_t data);
|
||||
uint8_t portff_r();
|
||||
void portff_w(uint8_t data);
|
||||
virtual void machine_reset() override;
|
||||
void portb2_w(u8 data);
|
||||
void portb4_w(u8 data);
|
||||
void portb6_w(u8 data);
|
||||
void portb8_w(u8 data);
|
||||
void portba_w(u8 data);
|
||||
void portbc_w(u8 data);
|
||||
void portbe_w(u8 data);
|
||||
u8 portff_r();
|
||||
void portff_w(u8 data);
|
||||
DECLARE_WRITE_LINE_MEMBER(fdc_drq_w);
|
||||
|
||||
void io_map(address_map &map);
|
||||
void mem_map(address_map &map);
|
||||
bool m_dma_dir;
|
||||
uint16_t m_dma_adr;
|
||||
u16 m_dma_adr;
|
||||
required_device<cpu_device> m_maincpu;
|
||||
required_device<upd765_family_device> m_fdc;
|
||||
required_device<floppy_connector> m_floppy0;
|
||||
@ -97,54 +94,54 @@ void dps1_state::io_map(address_map &map)
|
||||
|
||||
|
||||
// read from disk, to memory
|
||||
void dps1_state::portb2_w(uint8_t data)
|
||||
void dps1_state::portb2_w(u8 data)
|
||||
{
|
||||
m_dma_dir = 1;
|
||||
}
|
||||
|
||||
// write to disk, from memory
|
||||
void dps1_state::portb4_w(uint8_t data)
|
||||
void dps1_state::portb4_w(u8 data)
|
||||
{
|
||||
m_dma_dir = 0;
|
||||
}
|
||||
|
||||
// enable eprom
|
||||
void dps1_state::portb6_w(uint8_t data)
|
||||
void dps1_state::portb6_w(u8 data)
|
||||
{
|
||||
membank("bankr0")->set_entry(1); // point at rom
|
||||
}
|
||||
|
||||
// set A16-23
|
||||
void dps1_state::portb8_w(uint8_t data)
|
||||
void dps1_state::portb8_w(u8 data)
|
||||
{
|
||||
}
|
||||
|
||||
// set A8-15
|
||||
void dps1_state::portba_w(uint8_t data)
|
||||
void dps1_state::portba_w(u8 data)
|
||||
{
|
||||
m_dma_adr = (data << 8) | (m_dma_adr & 0xff);
|
||||
}
|
||||
|
||||
// set A0-7
|
||||
void dps1_state::portbc_w(uint8_t data)
|
||||
void dps1_state::portbc_w(u8 data)
|
||||
{
|
||||
m_dma_adr = (m_dma_adr & 0xff00) | data;
|
||||
}
|
||||
|
||||
// disable eprom
|
||||
void dps1_state::portbe_w(uint8_t data)
|
||||
void dps1_state::portbe_w(u8 data)
|
||||
{
|
||||
membank("bankr0")->set_entry(0); // point at ram
|
||||
}
|
||||
|
||||
// read 8 front-panel switches
|
||||
uint8_t dps1_state::portff_r()
|
||||
u8 dps1_state::portff_r()
|
||||
{
|
||||
return 0x0e;
|
||||
}
|
||||
|
||||
// write to 8 leds
|
||||
void dps1_state::portff_w(uint8_t data)
|
||||
void dps1_state::portff_w(u8 data)
|
||||
{
|
||||
}
|
||||
|
||||
@ -183,7 +180,7 @@ void dps1_state::machine_reset()
|
||||
|
||||
void dps1_state::init_dps1()
|
||||
{
|
||||
uint8_t *main = memregion("maincpu")->base();
|
||||
u8 *main = memregion("maincpu")->base();
|
||||
|
||||
membank("bankr0")->configure_entry(1, &main[0x0000]);
|
||||
membank("bankr0")->configure_entry(0, &main[0x0400]);
|
||||
|
||||
@ -43,14 +43,11 @@ public:
|
||||
{ }
|
||||
|
||||
void dsb46(machine_config &config);
|
||||
|
||||
void init_dsb46();
|
||||
|
||||
protected:
|
||||
virtual void machine_reset() override;
|
||||
|
||||
private:
|
||||
void port1a_w(uint8_t data);
|
||||
virtual void machine_reset() override;
|
||||
void port1a_w(u8 data);
|
||||
void dsb46_io(address_map &map);
|
||||
void dsb46_mem(address_map &map);
|
||||
required_device<z80_device> m_maincpu;
|
||||
@ -81,7 +78,7 @@ INPUT_PORTS_END
|
||||
|
||||
void dsb46_state::init_dsb46()
|
||||
{
|
||||
uint8_t *RAM = memregion("maincpu")->base();
|
||||
u8 *RAM = memregion("maincpu")->base();
|
||||
membank("read")->configure_entry(0, &RAM[0x10000]);
|
||||
membank("read")->configure_entry(1, &RAM[0x00000]);
|
||||
membank("write")->configure_entry(0, &RAM[0x00000]);
|
||||
@ -94,7 +91,7 @@ void dsb46_state::machine_reset()
|
||||
m_maincpu->reset();
|
||||
}
|
||||
|
||||
void dsb46_state::port1a_w(uint8_t data)
|
||||
void dsb46_state::port1a_w(u8 data)
|
||||
{
|
||||
membank("read")->set_entry(data & 1);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user