diff --git a/src/devices/sound/ay8910.cpp b/src/devices/sound/ay8910.cpp index bc1cf3bffef..ce513c89303 100644 --- a/src/devices/sound/ay8910.cpp +++ b/src/devices/sound/ay8910.cpp @@ -252,95 +252,242 @@ has twice the steps, happening twice as fast. ***************************************************************************/ /** -AY-3-8910/8914/YM2149 (YM3439? others?) - _______ _______ - _|* \__/ |_ - [4] VSS (GND) -- |_|1 40|_| -- VCC (+5v) - _| |_ - [5] NC |_|2 39|_| <- TEST 1 [1] - _| |_ - ANALOG CHANNEL B <- |_|3 38|_| -> ANALOG CHANNEL C - _| |_ - ANALOG CHANNEL A <- |_|4 37|_| <> DA0 - _| |_ - [5] NC |_|5 36|_| <> DA1 - _| |_ - IOB7 <> |_|6 35|_| <> DA2 - _| |_ - IOB6 <> |_|7 34|_| <> DA3 - _| /---\ |_ - IOB5 <> |_|8 \-/ | A 33|_| <> DA4 - _| . . Y |_ - IOB4 <> |_|9 |---| - S 32|_| <> DA5 - _| ' ' 3 O |_ - IOB3 <> |_|10 8 - U 31|_| <> DA6 - _| 3 8 N |_ - IOB2 <> |_|11 0 9 D 30|_| <> DA7 - _| 8 1 |_ - IOB1 <> |_|12 0 29|_| <- BC1 - _| P |_ - IOB0 <> |_|13 28|_| <- BC2 - _| |_ - IOA7 <> |_|14 27|_| <- BDIR - _| |_ - IOA6 <> |_|15 26|_| <- TEST 2 [2] - _| |_ - IOA5 <> |_|16 25|_| <- A8 [3] - _| |_ - IOA4 <> |_|17 24|_| <- /A9 [3] - _| |_ - IOA3 <> |_|18 23|_| <- /RESET - _| |_ - IOA2 <> |_|19 22|_| == CLOCK - _| |_ - IOA1 <> |_|20 21|_| <> IOA0 - |__________________| +AY-3-8910(A)/8914/8916/8917/8930/YM2149 (others?): + _______ _______ + _| \__/ |_ + [4] VSS (GND) -- |_|1 * 40|_| -- VCC (+5v) + _| |_ + [5] NC |_|2 39|_| <- TEST 1 [1] + _| |_ +ANALOG CHANNEL B <- |_|3 38|_| -> ANALOG CHANNEL C + _| |_ +ANALOG CHANNEL A <- |_|4 37|_| <> DA0 + _| |_ + [5] NC |_|5 36|_| <> DA1 + _| |_ + IOB7 <> |_|6 35|_| <> DA2 + _| |_ + IOB6 <> |_|7 34|_| <> DA3 + _| /---\ |_ + IOB5 <> |_|8 \-/ | A 33|_| <> DA4 + _| . . Y |_ + IOB4 <> |_|9 |---| - S 32|_| <> DA5 + _| ' ' 3 O |_ + IOB3 <> |_|10 8 - U 31|_| <> DA6 + _| 3 8 N |_ + IOB2 <> |_|11 0 9 D 30|_| <> DA7 + _| 8 1 |_ + IOB1 <> |_|12 0 29|_| <- BC1 + _| P |_ + IOB0 <> |_|13 28|_| <- BC2 + _| |_ + IOA7 <> |_|14 27|_| <- BDIR + _| |_ Prelim. DS: YM2149/8930: + IOA6 <> |_|15 26|_| <- TEST 2 [2,3] CS2 /SEL + _| |_ + IOA5 <> |_|16 25|_| <- A8 [3] CS1 + _| |_ + IOA4 <> |_|17 24|_| <- /A9 [3] /CS0 + _| |_ + IOA3 <> |_|18 23|_| <- /RESET + _| |_ + IOA2 <> |_|19 22|_| == CLOCK + _| |_ + IOA1 <> |_|20 21|_| <> IOA0 + |__________________| -[1] Based on the decap, TEST 1 affects the Envelope Generator and/or the - frequency divider somehow. +[1] Based on the decap, TEST 1 connects to the Envelope Generator and/or the + frequency divider somehow. Is this an input or an output? [2] The TEST 2 input connects to the same selector as A8 and /A9 do on the 8910 - and appears to act as just another active high enable like A8(pin 25) and - has an internal pull-up so if left NC the chip remains enabled. + and acts as just another active high enable like A8(pin 25). + The preliminary datasheet calls this pin CS2. On the 8914, it performs the same above function but additionally ?disables? the DA0-7 bus if pulled low/active. This additional function was removed on the 8910. - on YM2149 and YM3439 this pin is /SEL, if low, clock input is /2 -[3] It is possible for A8 and /A9 pins to be mask programmed to have different - active polarities. This might be true on the AY-3-8916/17 parts used on the - Intellivision ECS module? (not the Keyboard module?) -[4] The bond wire for the VSS pin goes to the substrate frame, and then a - separate bond wire connects it to a pad between pins 21 and 22 + This pin has an internal pullup. + On the AY8930 and YM2149, this pin is /SEL; if low, clock input is halved. +[3] These 3 pins are technically enables, and have pullups/pulldowns such that + if the pins are left floating, the chip remains enabled. +[4] On the AY-3-8910 the bond wire for the VSS pin goes to the substrate frame, + and then a separate bond wire connects it to a pad between pins 21 and 22. [5] These pins lack internal bond wires entirely. + +AY-3-8912(A): + _______ _______ + _| \__/ |_ +ANALOG CHANNEL C <- |_|1 * 28|_| <> DA0 + _| |_ + TEST 1 -> |_|2 27|_| <> DA1 + _| |_ + VCC (+5V) -- |_|3 26|_| <> DA2 + _| |_ +ANALOG CHANNEL B <- |_|4 25|_| <> DA3 + _| /---\ |_ +ANALOG CHANNEL A <- |_|5 \-/ | A 24|_| <> DA4 + _| . . Y |_ + VSS (GND) -- |_|6 |---| - S 23|_| <> DA5 + _| ' ' 3 O |_ + IOA7 <> |_|7 T 8 - U 22|_| <> DA6 + _| A 3 8 N |_ + IOA6 <> |_|8 I 1 9 D 21|_| <> DA7 + _| W 1 1 |_ + IOA5 <> |_|9 A C 2 20|_| <- BC1 + _| N D |_ + IOA4 <> |_|10 A 19|_| <- BC2 + _| |_ + IOA3 <> |_|11 18|_| <- BDIR + _| |_ + IOA2 <> |_|12 17|_| <- A8 + _| |_ + IOA1 <> |_|13 16|_| <- /RESET + _| |_ + IOA0 <> |_|14 15|_| == CLOCK + |__________________| + + AY-3-8910/A: 2 I/O ports -AY-3-8912/A: 1 I/O port; /A9 doesn't exist and is considered pulled low. -AY-3-8913/A: 0 I/O port; BC2 pin doesn't exist and is considered pulled high. - Factory default for these three types when writing address data to them is: - /A9 must be low, A8 must be high, A7 thru A4 must be low. - A7 thru A4 enable state can be changed with a factory mask adjustment but - default was 0000 for the "common" part shipped. - The 'A' version of the 3 above have a re-laid out die, unclear if there are - any behavior changes vs the non-'A' version. -AY-3-8914: same as 8910 except for different register mapping and two bit - envelope enable / volume field. - Factory default for these three types when writing address data to them is: - /A9 must be low, A8 must be high, A7 thru A4 must be low. - A7 thru A4 enable state can be changed with a factory mask adjustment but - are unknown for the one known part shipped, used in the Intellivision. -AY8930: mostly backwards compatible with 8910, except like the AY-3-8913, the - BC2 pin is considered tied high/permanently '1'. + A7 thru A4 enable state for selecting a register can be changed with a + factory mask adjustment but default was 0000 for the "common" part shipped + (probably die "-100"). + Pins 24, 25, and 26 are /A9, A8, and TEST2, which are an active low, high + and high chip enable, respectively. + AY-3-8910: Unused bits in registers have unknown behavior. + AY-3-8910A: Unused bits in registers have unknown behavior. + I/O current source/sink behavior is unknown. + AY-3-8910 die is labeled "90-32033" with a 1979 copyright and a "-100" die + code. + AY-3-8910A die is labeled "90-32128" with a 1983 copyright. +AY-3-8912/A: 1 I/O port + /A9 pin doesn't exist and is considered pulled low. + TEST2 pin doesn't exist and is considered pulled high. + IOB pins do not exist and have unknown behavior if driven high/low and read + back. + A7 thru A4 enable state for selecting a register can be changed with a + factory mask adjustment but default was 0000 for the "common" part shipped + AY-3-8912: Unused bits in registers have unknown behavior. + AY-3-8912A: Unused bits in registers have unknown behavior. + I/O current source/sink behavior is unknown. + AY-3-8912 die is unknown. + AY-3-8912A or A/P die is unknown. +AY-3-8913: 0 I/O ports + BC2 pin doesn't exist and is considered pulled high. + IOA/B pins do not exist and have unknown behavior if driven high/low and read back. + A7 thru A4 enable state for selecting a register can be changed with a + factory mask adjustment but default was 0000 for the "common" part shipped + AY-3-8913: Unused bits in registers have unknown behavior. + AY-3-8913 die is unknown. +AY-3-8914/A: 2 I/O ports + A7 thru A4 enable state for selecting a register can be changed with a + factory mask adjustment but was 0000 for the part shipped with the + Intellivision. + Pins 24, 25, and 26 are /A9, A8, and TEST2, which are an active low, high + and high chip enable, respectively. + TEST2 additionally ?disables? the data bus if pulled low. + The register mapping is different from the AY-3-8910, the AY-3-8914 register + mapping matches the "preliminary" 1978 AY-3-8910 datasheet. + The Envelope/Volume control register is 6 bits wide instead of 5 bits, and + the additional bit combines with the M bit to form a bit pair C0 and C1, + which shift the volume output of the Envelope generator right by 0, 1 or 2 + bits on a given channel, or allow the low 4 bits to drive the channel + volume. + AY-3-8914: Unused bits in registers have unknown behavior. + AY-3-8914A: Unused bits in registers have unknown behavior. + I/O current source/sink behavior is unknown. + AY-3-8914 die is labeled "90-32022" with a 1978 copyright. + AY-3-8914A die is unknown. +AY-3-8916: 2 I/O ports + A7 thru A4 enable state for selecting a register can be changed with a + factory mask adjustment but was 1111 for the part shipped with the + Intellivision ECS module. + Pins 24, 25, and 26 are /A9, /A8(!), and TEST2, which are an active low, + low(!) and high chip enable, respectively. + NOTE: the /A8 enable polarity may be mixed up with AY-3-8917 below. + AY-3-8916: Unused bits in registers have unknown behavior. + I/O current source/sink behavior is unknown. + AY-3-8916 die is unknown. +AY-3-8917: 2 I/O ports + A7 thru A4 enable state for selecting a register can be changed with a + factory mask adjustment but was 1111 for the part shipped with the + Intellivision ECS module. + Pins 24, 25, and 26 are /A9, A8, and TEST2, which are an active low, high + and high chip enable, respectively. + NOTE: the A8 enable polarity may be mixed up with AY-3-8916 above. + AY-3-8917: Unused bits in registers have unknown behavior. + I/O current source/sink behavior is unknown. + AY-3-8917 die is unknown. +AY8930: 2 I/O ports + BC2 pin exists but is always considered pulled high. The pin might have no + bond wire at all. + Pins 2 and 5 might be additional test pins rather than being NC. + A7 thru A4 enable state for selecting a register are 0000 for all? parts + shipped. + Pins 24 and 25 are /A9, A8 which are an active low and high chip enable. + Pin 26 is /SELECT which if driven low divides the input clock by 2. + Writing 0xAn or 0xBn to register 0x0D turns on extended mode, which enables + an additional 16 registers (banked using 0x0D bit 0), and clears the + contents of all of the registers except the high 3 bits of register 0x0D + (according to the datasheet). If the AY8930's extended mode is enabled, it gains higher resolution - frequency and volume control, separate volume per-channel, and the duty - cycle can be adjusted for the 3 channels. If the mode is not enabled, it - behaves exactly(?) like an AY-3-8910. -YM2149: The envelope register has 5 bits of resolution internally, allowing for - smoother volume ramping, though the register for setting its direct value - remains 4 bits wide. The chip also has a selectable clock divider on pin 26 - (/SEL), which was /TEST2 on the AY-3-8910. If low, the input clock is halved. + frequency and volume control, separate volume per-channel, and the duty + cycle can be adjusted for the 3 channels. + If the mode is not enabled, it behaves almost exactly like an AY-3-8910(A?), + barring the BC2 and /SELECT differences. + AY8930: Unused bits in registers have unknown behavior, but the datasheet + explicitly states that unused bits always read as 0. + I/O current source/sink behavior is unknown. + AY8930 die is unknown. +YM2149: 2 I/O ports + A7 thru A4 enable state for selecting a register are 0000 for all? parts + shipped. + Pins 24 and 25 are /A9, A8 which are an active low and high chip enable. + Pin 26 is /SEL which if driven low divides the input clock by 2. + The YM2149 envelope register has 5 bits of resolution internally, allowing + for smoother volume ramping, though the register for setting its direct + value remains 4 bits wide. + YM2149: Unused bits in registers have unknown behavior. + I/O current source/sink behavior is unknown. + YM2149 die is unknown; only one die revision, 'G', has been observed + from Yamaha chip/datecode silkscreen surface markings. +YM2203: 2 I/O ports + The pinout of this chip is completely different from the AY-3-8910. + The entire way this chip is accessed is completely different from the usual + AY-3-8910 selection of chips, so there is a /CS and a /RD and a /WR and + an A0 pin; The chip status can be read back by reading the register + select address. + The chip has a 3-channel, 4-op FM synthesis sound core in it, not discussed + in this source file. + The first 16 registers are the same(?) as the YM2149. + YM2203: Unused bits in registers have unknown behavior. + I/O current source/sink behavior is unknown. + YM2203 die is unknown; two die revisions, 'F' and 'H', have been observed + from Yamaha chip/datecode silkscreen surface markings. It is unknown + what behavioral differences exist between these two revisions. + The 'F' revision only appears during the first year of production. YM3439: limited info: CMOS version of YM2149? YMZ284: limited info: 0 I/O port, different clock divider YMZ294: limited info: 0 I/O port OKI M5255, Winbond WF19054, JFC 95101, File KC89C72, Toshiba T7766A : differences to be listed + +Decaps: +AY-3-8914 - http://siliconpr0n.org/map/gi/ay-3-8914/mz_mit20x/ +AY-3-8910 - http://privatfrickler.de/blick-auf-den-chip-soundchip-general-instruments-ay-3-8910/ +AY-3-8910A - https://seanriddledecap.blogspot.com/2017/01/gi-ay-3-8910-ay-3-8910a-gi-8705-cba.html (TODO: update this link when it has its own page at seanriddle.com) + +Links: +AY-3-8910 'preliminary' datasheet (which actually describes the AY-3-8914) from 1978: + http://spatula-city.org/~im14u2c/intv/gi_micro_programmable_tv_games/page_7_100.png + http://spatula-city.org/~im14u2c/intv/gi_micro_programmable_tv_games/page_7_101.png + http://spatula-city.org/~im14u2c/intv/gi_micro_programmable_tv_games/page_7_102.png + http://spatula-city.org/~im14u2c/intv/gi_micro_programmable_tv_games/page_7_103.png + http://spatula-city.org/~im14u2c/intv/gi_micro_programmable_tv_games/page_7_104.png + http://spatula-city.org/~im14u2c/intv/gi_micro_programmable_tv_games/page_7_105.png +AY-3-8910/8912 Feb 1979 manual: http://dev-docs.atariforge.org/files/GI_AY-3-8910_Feb-1979.pdf +AY-3-8910/8912/8913 post-1983 manual: http://map.grauw.nl/resources/sound/generalinstrument_ay-3-8910.pdf or http://www.ym2149.com/ay8910.pdf +AY-8930 datasheet: http://www.ym2149.com/ay8930.pdf +YM2149 datasheet: http://www.ym2149.com/ym2149.pdf +YM2203 English datasheet: http://www.appleii-box.de/APPLE2/JonasCard/YM2203%20datasheet.pdf +YM2203 Japanese datasheet contents, translated: http://www.larwe.com/technical/chip_ym2203.html */ #include "emu.h" diff --git a/src/devices/sound/ay8910.h b/src/devices/sound/ay8910.h index cf910729a69..d62d838e14a 100644 --- a/src/devices/sound/ay8910.h +++ b/src/devices/sound/ay8910.h @@ -14,20 +14,20 @@ /* * The following is used by all drivers not reviewed yet. - * This will like the old behaviour, output between + * This will like the old behavior, output between * 0 and 7FFF */ #define AY8910_LEGACY_OUTPUT (0x01) /* - * Specifing the next define will simulate the special + * Specifying the next define will simulate the special * cross channel mixing if outputs are tied together. * The driver will only provide one stream in this case. */ #define AY8910_SINGLE_OUTPUT (0x02) /* - * The following define is the default behaviour. + * The following define is the default behavior. * Output level 0 is 0V and 7ffff corresponds to 5V. * Use this to specify that a discrete mixing stage * follows.