jazz: wip (nw)

The driver is able to launch the Windows NT setup program, but hangs part-way through copying tga.dll to the hard disk.
This commit is contained in:
Patrick Mackinlay 2019-05-16 16:04:24 +07:00
parent e50efb8f59
commit ab303f68c2
4 changed files with 43 additions and 28 deletions

View File

@ -68,12 +68,15 @@ void jazz_state::machine_start()
void jazz_state::machine_reset()
{
// HACK: make sure the RTC is running
m_rtc->write_direct(0x0a, 0x20);
}
void jazz_state::init_common()
{
// map the configured ram and vram
m_cpu->space(0).install_ram(0x00000000, 0x00000000 | m_ram->mask(), m_ram->pointer());
// FIXME: video ram must be written in emulated cpu order
m_cpu->space(0).install_ram(0x40000000, 0x40000000 | m_vram->mask(), m_vram->pointer());
}
@ -81,7 +84,7 @@ void jazz_state::jazz_common_map(address_map &map)
{
map(0x1fc00000, 0x1fc3ffff).r(m_flash, FUNC(amd_28f020_device::read));
map(0x40000000, 0x407fffff).ram().share("vram"); // local video memory
// NOTE: defaults to console on serial1 if no video rom found
map(0x60000000, 0x6000013f).lr8("video_rom",
[](offs_t offset)
{
@ -113,6 +116,9 @@ void jazz_state::jazz_common_map(address_map &map)
};
*/
// FIXME: this is the MIPS G364 with the PROM fields zeroed to
// avoid a startup error, and should be replaced with the real
// signature above when an actual PROM dump is located.
static u8 const bogus_g364[] =
{
0x10, 0x00, 0x00, 0x00, 'J', 'a', 'z', 'z',
@ -125,15 +131,18 @@ void jazz_state::jazz_common_map(address_map &map)
return bogus_g364[offset];
}).umask64(0xff);
map(0x60080000, 0x60081fff).m(m_ramdac, FUNC(g364_device::map)); // local video control
map(0x60180000, 0x60180007).lw32("g364_reset", [this](u32 data) { m_ramdac->reset(); });
map(0x60080000, 0x60081fff).m(m_cvc, FUNC(g364_device::map));
map(0x60180000, 0x60180007).lw32("g364_reset", [this](u32 data) { m_cvc->reset(); });
map(0x80000000, 0x80000fff).m(m_mct_adr, FUNC(jazz_mct_adr_device::map));
map(0x80001000, 0x800010ff).m(m_network, FUNC(dp83932c_device::map)).umask32(0x0000ffff);
map(0x80001000, 0x800010ff).m(m_net, FUNC(dp83932c_device::map)).umask32(0x0000ffff);
map(0x80002000, 0x8000200f).m(m_scsi, FUNC(ncr53c94_device::map));
map(0x80003000, 0x8000300f).m(m_fdc, FUNC(n82077aa_device::map));
map(0x80004000, 0x80004007).lrw8("rtc",
// LE: only reads 4000
// BE: read 400d, write 400d, write 400c
map(0x80004000, 0x8000400f).lrw8("rtc",
[this](offs_t offset) { return m_rtc->read(1); },
[this](offs_t offset, u8 data) { m_rtc->write(1, data); }).umask64(0xff);
map(0x80005000, 0x80005007).rw(m_kbdc, FUNC(at_keyboard_controller_device::data_r), FUNC(at_keyboard_controller_device::data_w)).umask64(0x00ff);
@ -142,13 +151,14 @@ void jazz_state::jazz_common_map(address_map &map)
map(0x80007000, 0x80007007).rw(m_ace[1], FUNC(ns16550_device::ins8250_r), FUNC(ns16550_device::ins8250_w));
map(0x80008000, 0x80008007).rw(m_lpt, FUNC(pc_lpt_device::read), FUNC(pc_lpt_device::write)).umask64(0xffffffff);
map(0x80009000, 0x8000afff).ram().share("nvram"); // 9000-9fff unprotected/a000-afff protected?
map(0x8000b000, 0x8000b007).lr8("mac", [](offs_t offset)
{
// mac address and checksum
static u8 const mac[] = { 0x00, 0x00, 0x6b, 0x12, 0x34, 0x56, 0x00, 0xf7 };
map(0x8000b000, 0x8000b007).lr8("mac",
[](offs_t offset)
{
// mac address and checksum
static u8 const mac[] = { 0x00, 0x00, 0x6b, 0x12, 0x34, 0x56, 0x00, 0xf7 };
return mac[offset];
});
return mac[offset];
});
// 3 4k pages of nvram: read/write, protected, read-only
// last page holds ethernet mac and checksum in bytes 0-7
@ -192,7 +202,8 @@ FLOPPY_FORMATS_END
void jazz_state::jazz(machine_config &config)
{
R4000(config, m_cpu, 50_MHz_XTAL);
// FIXME: slow the cpu clock to get past session manager bugcheck
R4000(config, m_cpu, 50_MHz_XTAL / 5);
m_cpu->set_addrmap(0, &jazz_state::jazz_common_map);
RAM(config, m_ram);
@ -244,6 +255,7 @@ void jazz_state::jazz(machine_config &config)
m_mct_adr->dma_w_cb<1>().set(m_fdc, FUNC(n82077aa_device::dma_w));
MC146818(config, m_rtc, 32.768_kHz_XTAL);
m_rtc->set_epoch(1980);
NVRAM(config, m_nvram, nvram_device::DEFAULT_ALL_0);
@ -262,8 +274,8 @@ void jazz_state::jazz(machine_config &config)
// keyboard controller
PS2_KEYBOARD_CONTROLLER(config, m_kbdc, 12_MHz_XTAL);
//m_kbdc->hot_res().set_inputline(m_cpu, INPUT_LINE_RESET);
m_kbdc->hot_res().set([this](int state) { if (!state) m_cpu->reset(); });
// FIXME: reset is probably routed through the MCT-ADR
m_kbdc->hot_res().set([this](int state) { logerror("reset %d\n", state); });
m_kbdc->kbd_clk().set(kbdc, FUNC(pc_kbdc_device::clock_write_from_mb));
m_kbdc->kbd_data().set(kbdc, FUNC(pc_kbdc_device::data_write_from_mb));
m_kbdc->kbd_irq().set(m_mct_adr, FUNC(jazz_mct_adr_device::irq<6>));;
@ -277,9 +289,9 @@ void jazz_state::jazz(machine_config &config)
m_screen->set_screen_update("g364", FUNC(g364_device::screen_update));
m_screen->screen_vblank().set(m_mct_adr, FUNC(jazz_mct_adr_device::irq<3>)); // maybe?
G364(config, m_ramdac, 5_MHz_XTAL); // FIXME: guessed clock
m_ramdac->set_screen(m_screen);
m_ramdac->set_vram(m_vram);
G364(config, m_cvc, 5_MHz_XTAL); // FIXME: guessed clock
m_cvc->set_screen(m_screen);
m_cvc->set_vram(m_vram);
// WD16C552 (two 16550 + pc_lpt)
NS16550(config, m_ace[0], 4233600);
@ -320,9 +332,9 @@ void jazz_state::jazz(machine_config &config)
SPEAKER_SOUND(config, m_buzzer);
m_buzzer->add_route(ALL_OUTPUTS, "mono", 0.50);
DP83932C(config, m_network, 20_MHz_XTAL);
m_network->out_int_cb().set(m_mct_adr, FUNC(jazz_mct_adr_device::irq<4>));
m_network->set_ram(RAM_TAG);
DP83932C(config, m_net, 20_MHz_XTAL);
m_net->out_int_cb().set(m_mct_adr, FUNC(jazz_mct_adr_device::irq<4>));
m_net->set_ram(RAM_TAG);
I82357(config, m_isp, 14.318181_MHz_XTAL);
m_isp->out_rtc_cb().set(m_rtc, FUNC(mc146818_device::write));

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@ -59,9 +59,9 @@ public:
, m_nvram(*this, "nvram")
, m_flash(*this, "flash")
, m_kbdc(*this, "kbdc")
, m_network(*this, "net")
, m_net(*this, "net")
, m_screen(*this, "screen")
, m_ramdac(*this, "g364")
, m_cvc(*this, "g364")
, m_ace(*this, "ace%u", 0)
, m_lpt(*this, "lpt")
, m_isp(*this, "isp")
@ -101,9 +101,9 @@ protected:
required_device<nvram_device> m_nvram;
required_device<amd_28f020_device> m_flash;
required_device<ps2_keyboard_controller_device> m_kbdc;
required_device<dp83932c_device> m_network;
required_device<dp83932c_device> m_net;
required_device<screen_device> m_screen;
required_device<g364_device> m_ramdac;
required_device<g364_device> m_cvc;
required_device_array<ns16550_device, 2> m_ace;
required_device<pc_lpt_device> m_lpt;
required_device<i82357_device> m_isp;

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@ -50,13 +50,13 @@ void jazz_mct_adr_device::map(address_map &map)
{
map(0x000, 0x007).lrw32("configuration", [this](){ return m_config; }, [this](u32 data) { m_config = data; });
map(0x008, 0x00f).lr32("revision_level", [](){ return 1; });
map(0x010, 0x017).lr32("invalid_address", []() { return 0; });
map(0x010, 0x017).lr32("dma_invalid_address", [this]() { m_dma_interrupt_source &= ~DMA_ADDRESS_ERROR; return m_dma_invalid_address; });
map(0x018, 0x01f).lrw32("translation_base", [this]() { return m_trans_tbl_base; }, [this](u32 data) { LOG("tbl base 0x%08x\n", data); m_trans_tbl_base = data; });
map(0x020, 0x027).lrw32("translation_limit", [this]() { return m_trans_tbl_limit; }, [this](u32 data) { LOG("tbl limit 0x%08x\n", data); m_trans_tbl_limit = data; });
map(0x028, 0x02f).lrw32("translation_invalidate", []() { return 0; }, [](u32 data) { });
map(0x030, 0x037).lw32("cache_maintenance", [this](u32 data) { m_ioc_maint = data; });
map(0x038, 0x03f).lr32("remote_failed_address", []() { return 0; });
map(0x040, 0x047).lr32("memory_failed_address", []() { return 0; });
map(0x040, 0x047).lr32("dma_memory_failed_address", [this]() { m_dma_interrupt_source &= ~DMA_PARITY_ERROR; return m_dma_memory_failed_address; });
map(0x048, 0x04f).lw32("io_cache_physical_tag", [this](u32 data) { m_ioc_physical_tag = data; });
map(0x050, 0x057).lw32("io_cache_logical_tag", [this](u32 data) { m_ioc_logical_tag = data; });
map(0x058, 0x05f).lrw32("io_cache_byte_mask",
@ -99,7 +99,7 @@ void jazz_mct_adr_device::map(address_map &map)
if ((reg == REG_ENABLE) && (data & DMA_ENABLE))
LOG("dma started address 0x%08x count %d\n", translate_address(m_dma_reg[(0 << 2) + REG_ADDRESS]), m_dma_reg[(0 << 2) + REG_COUNT]);
});
map(0x200, 0x207).lr32("interrupt_source", []() { return 0; });
map(0x200, 0x207).lr32("interrupt_source", [this]() { return m_dma_interrupt_source; });
map(0x208, 0x20f).lr32("error_type", []() { return 0; });
map(0x210, 0x217).lrw32("refresh_rate", [this]() { return m_memory_refresh_rate; }, [this](u32 data) { m_memory_refresh_rate = data; });
// refresh_counter
@ -112,7 +112,7 @@ void jazz_mct_adr_device::map(address_map &map)
m_interval_timer->adjust(interval, 0, interval);
});
map(0x230, 0x237).lr32("interval_timer", [this]() { if (m_out_int_timer_asserted) { m_out_int_timer_asserted = false; m_out_int_timer(0); } return 0; });
map(0x230, 0x237).lr32("interval_timer", [this]() { if (m_out_int_timer_asserted) { m_out_int_timer_asserted = false; m_out_int_timer(0); } return m_interval_timer->remaining().as_ticks(1000); });
map(0x238, 0x23b).lr32("interrupt_acknowledge", [this]() { return m_eisa_iack(); });
}

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@ -127,14 +127,17 @@ private:
DMA_CACHE_FLUSH_ERROR = 0x00000400,
};
u32 m_dma_invalid_address;
u32 m_trans_tbl_base;
u32 m_trans_tbl_limit;
u32 m_ioc_maint;
u32 m_dma_memory_failed_address;
u32 m_ioc_physical_tag;
u32 m_ioc_logical_tag;
u32 m_ioc_byte_mask;
u32 m_remote_speed[16];
u32 m_dma_reg[32];
u32 m_dma_interrupt_source;
u32 m_memory_refresh_rate;
u32 m_nvram_protect;