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Added "Read and Branch" code to tms5110 and tms6100. No possibility to test, though. No whatsnew.

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Couriersud 2010-05-31 21:20:06 +00:00
parent 690f98e05b
commit ab48f63b71
2 changed files with 21 additions and 0 deletions
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11
src/emu/machine/tms6100.c
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@ -230,6 +230,17 @@ WRITE_LINE_DEVICE_HANDLER( tms6100_romclock_w )
break;
case 0x03:
/* READ AND BRANCH */
if (tms->state & TMS6100_NEXT_READ_IS_DUMMY)
{
tms->state &= ~TMS6100_NEXT_READ_IS_DUMMY; // clear - no dummy read according to datasheet
LOG(("loaded address latch %08x\n", tms->address_latch));
tms->address = tms->rom[tms->address_latch] | (tms->rom[tms->address_latch+1]<<8);
tms->address &= 0x3fff; // 14 bits
LOG(("loaded indirect address %04x\n", tms->address));
tms->address = (tms->address << 3);
tms->address_latch = 0;
tms->loadptr = 0;
}
break;
}
}

10
src/emu/sound/tms5110.c
View File

@ -801,6 +801,16 @@ void tms5110_PDC_set(tms5110_state *tms, int data)
tms->next_is_address = TRUE;
break;
case TMS5110_CMD_READ_BRANCH:
new_int_write(tms, 0,1,1,0);
new_int_write(tms, 1,1,1,0);
new_int_write(tms, 0,1,1,0);
new_int_write(tms, 0,0,0,0);
new_int_write(tms, 1,0,0,0);
new_int_write(tms, 0,0,0,0);
tms->schedule_dummy_read = FALSE;
break;
case TMS5110_CMD_TEST_TALK:
tms->state = CTL_STATE_NEXT_OUTPUT;
break;