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First pass at modernizing struct definitions.

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This commit is contained in:
Aaron Giles 2012-09-15 21:47:30 +00:00
parent d1da89cc78
commit ab97dc30ef
547 changed files with 1137 additions and 1945 deletions
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4
.gitattributes vendored
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@ -405,7 +405,7 @@ src/emu/cpu/i86/host.h svneol=native#text/plain
src/emu/cpu/i86/i286.c svneol=native#text/plain
src/emu/cpu/i86/i286.h svneol=native#text/plain
src/emu/cpu/i86/i86.c svneol=native#text/plain
src/emu/cpu/i86/i86.h -text svneol=native#text/plain
src/emu/cpu/i86/i86.h svneol=native#text/plain
src/emu/cpu/i86/i86.txt svneol=native#text/plain
src/emu/cpu/i86/i86priv.h svneol=native#text/plain
src/emu/cpu/i86/i86time.c svneol=native#text/plain
@ -561,7 +561,7 @@ src/emu/cpu/mn10200/mn10200.c svneol=native#text/plain
src/emu/cpu/mn10200/mn10200.h svneol=native#text/plain
src/emu/cpu/mn10200/mn102dis.c svneol=native#text/plain
src/emu/cpu/nec/nec.c svneol=native#text/plain
src/emu/cpu/nec/nec.h -text svneol=native#text/plain
src/emu/cpu/nec/nec.h svneol=native#text/plain
src/emu/cpu/nec/necdasm.c svneol=native#text/plain
src/emu/cpu/nec/necea.h svneol=native#text/plain
src/emu/cpu/nec/necinstr.c svneol=native#text/plain

6
src/build/png2bdc.c
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@ -68,8 +68,7 @@
***************************************************************************/
/* a render_font contains information about a single character in a font */
typedef struct _render_font_char render_font_char;
struct _render_font_char
struct render_font_char
{
INT32 width; /* width from this character to the next */
INT32 xoffs, yoffs; /* X and Y offset from baseline to top,left of bitmap */
@ -79,8 +78,7 @@ struct _render_font_char
/* a render_font contains information about a font */
typedef struct _render_font render_font;
struct _render_font
struct render_font
{
int height; /* height of the font, from ascent to descent */
int yoffs; /* y offset from baseline to descent */

3
src/build/verinfo.c
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@ -24,8 +24,7 @@ typedef unsigned char UINT8;
// TYPE DEFINITIONS
//============================================================
typedef struct _version_info version_info;
struct _version_info
struct version_info
{
int version_major;
int version_minor;

5
src/emu/config.c
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@ -24,10 +24,9 @@
TYPE DEFINITIONS
***************************************************************************/
typedef struct _config_type config_type;
struct _config_type
struct config_type
{
struct _config_type * next; /* next in line */
config_type * next; /* next in line */
const char * name; /* node name */
config_saveload_delegate load; /* load callback */
config_saveload_delegate save; /* save callback */

3
src/emu/cpu/alph8201/alph8201.c
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@ -170,8 +170,7 @@ Timming
#define M_RDOP(A) cpustate->direct->read_decrypted_byte(A)
#define M_RDOP_ARG(A) cpustate->direct->read_raw_byte(A)
typedef struct _alpha8201_state alpha8201_state;
struct _alpha8201_state
struct alpha8201_state
{
UINT8 RAM[8*8]; /* internal GP register 8 * 8bank */
unsigned PREVPC;

3
src/emu/cpu/apexc/apexc.c
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@ -343,8 +343,7 @@ without danger */
#define apexc_readop(address) apexc_readmem(address)
typedef struct _apexc_state apexc_state;
struct _apexc_state
struct apexc_state
{
UINT32 a; /* accumulator */
UINT32 r; /* register */

3
src/emu/cpu/avr8/avr8.c
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@ -21,8 +21,7 @@
#include "debugger.h"
#include "avr8.h"
typedef struct _avr8_state avr8_state;
struct _avr8_state
struct avr8_state
{
UINT32 pc;

3
src/emu/cpu/ccpu/ccpu.c
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@ -17,8 +17,7 @@
STRUCTURES & TYPEDEFS
***************************************************************************/
typedef struct _ccpu_state ccpu_state;
struct _ccpu_state
struct ccpu_state
{
UINT16 PC;
UINT16 A;

3
src/emu/cpu/ccpu/ccpu.h
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@ -41,8 +41,7 @@ enum
typedef UINT8 (*ccpu_input_func)(device_t *device);
typedef void (*ccpu_vector_func)(device_t *device, INT16 sx, INT16 sy, INT16 ex, INT16 ey, UINT8 shift);
typedef struct _ccpu_config ccpu_config;
struct _ccpu_config
struct ccpu_config
{
ccpu_input_func external_input; /* if NULL, assume JMI jumper is present */
ccpu_vector_func vector_callback;

3
src/emu/cpu/cop400/cop400.c
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@ -84,8 +84,7 @@
typedef struct _cop400_opcode_map cop400_opcode_map;
typedef struct _cop400_state cop400_state;
struct _cop400_state
struct cop400_state
{
const cop400_interface *intf;

3
src/emu/cpu/cop400/cop400.h
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@ -99,8 +99,7 @@ enum _cop400_microbus {
typedef enum _cop400_microbus cop400_microbus;
/* interface */
typedef struct _cop400_interface cop400_interface;
struct _cop400_interface
struct cop400_interface
{
cop400_cki_bond cki; /* CKI bonding option */
cop400_cko_bond cko; /* CKO bonding option */

3
src/emu/cpu/cp1610/cp1610.c
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@ -30,8 +30,7 @@
#define OV 0x20
#define C 0x10
typedef struct _cp1610_state cp1610_state;
struct _cp1610_state
struct cp1610_state
{
UINT16 r[8]; /* registers */
UINT8 flags; /* flags */

9
src/emu/cpu/cubeqcpu/cubeqcpu.h
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@ -118,22 +118,19 @@ enum
typedef void (*cubeqst_dac_w_func)(device_t *, UINT16);
typedef struct _cubeqst_snd_config cubeqst_snd_config;
struct _cubeqst_snd_config
struct cubeqst_snd_config
{
cubeqst_dac_w_func dac_w;
const char * sound_data_region;
};
typedef struct _cubeqst_lin_config cubeqst_lin_config;
struct _cubeqst_lin_config
struct cubeqst_lin_config
{
const char * rot_cpu_tag;
};
typedef struct _cubeqst_rot_config cubeqst_rot_config;
struct _cubeqst_rot_config
struct cubeqst_rot_config
{
const char * lin_cpu_tag;
};

3
src/emu/cpu/e132xs/e132xs.c
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@ -292,8 +292,7 @@ struct _delay
};
/* Internal registers */
typedef struct _hyperstone_state hyperstone_state;
struct _hyperstone_state
struct hyperstone_state
{
UINT32 global_regs[32];
UINT32 local_regs[64];

3
src/emu/cpu/esrip/esrip.h
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@ -80,8 +80,7 @@ enum
/***************************************************************************
CONFIGURATION STRUCTURE
***************************************************************************/
typedef struct _esrip_config_ esrip_config;
struct _esrip_config_
struct esrip_config
{
read16_device_func fdt_r;
write16_device_func fdt_w;

3
src/emu/cpu/g65816/g65816cm.h
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@ -67,8 +67,7 @@ INLINE int MAKE_INT_8(int A) {return (A & 0x80) ? A | ~0xff : A & 0xff;}
/* ======================================================================== */
/* CPU Structure */
typedef struct _g65816i_cpu_struct g65816i_cpu_struct;
struct _g65816i_cpu_struct
struct g65816i_cpu_struct
{
uint a; /* Accumulator */
uint b; /* holds high byte of accumulator */

3
src/emu/cpu/h83002/h8priv.h
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@ -36,8 +36,7 @@ typedef struct
UINT64 timer_cycles;
} H8S2XXX_TMR;
typedef struct _h83xx_state h83xx_state;
struct _h83xx_state
struct h83xx_state
{
// main CPU stuff
UINT32 h8err;

3
src/emu/cpu/hd6309/hd6309.c
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@ -113,8 +113,7 @@
#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
/* 6309 Registers */
typedef struct _m68_state_t m68_state_t;
struct _m68_state_t
struct m68_state_t
{
PAIR pc; /* Program counter */
PAIR ppc; /* Previous program counter */

3
src/emu/cpu/i386/i386priv.h
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@ -250,8 +250,7 @@ typedef union {
float f[4];
} XMM_REG;
typedef struct _i386_state i386_state;
struct _i386_state
struct i386_state
{
I386_GPR reg;
I386_SREG sreg[6];

3
src/emu/cpu/i4004/i4004.c
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@ -21,8 +21,7 @@ static const UINT8 kbp_table[] = { 0x00,0x01,0x02,0x0f,0x03,0x0f,0x0f,0x0f,0x04,
TYPE DEFINITIONS
***************************************************************************/
typedef struct _i4004_state i4004_state;
struct _i4004_state
struct i4004_state
{
UINT8 A; // Accumulator
UINT8 R[8];

3
src/emu/cpu/i8085/i8085.c
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@ -157,8 +157,7 @@
TYPE DEFINITIONS
***************************************************************************/
typedef struct _i8085_state i8085_state;
struct _i8085_state
struct i8085_state
{
i8085_config config;

3
src/emu/cpu/i8085/i8085.h
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@ -36,8 +36,7 @@ enum
TYPE DEFINITIONS
***************************************************************************/
typedef struct _i8085_config i8085_config;
struct _i8085_config
struct i8085_config
{
devcb_write8 out_status_func; /* STATUS changed callback */
devcb_write_line out_inte_func; /* INTE changed callback */

3
src/emu/cpu/i86/i286.c
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@ -32,8 +32,7 @@ typedef union
UINT8 b[16]; /* or as 8 bit registers */
} i80286basicregs;
typedef struct _i80286_state i80286_state;
struct _i80286_state
struct i80286_state
{
i80286basicregs regs;
offs_t fetch_xor;

3
src/emu/cpu/i86/i86.c
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@ -29,8 +29,7 @@ typedef union
}
i8086basicregs;
typedef struct _i8086_state i8086_state;
struct _i8086_state
struct i8086_state
{
i8086basicregs regs;
offs_t fetch_xor;

129
src/emu/cpu/i86/i86.h
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@ -1,65 +1,64 @@
/* ASG 971222 -- rewrote this interface */
#pragma once
#ifndef __I86INTF_H__
#define __I86INTF_H__
#define INPUT_LINE_INT0 INPUT_LINE_IRQ0
#define INPUT_LINE_INT1 INPUT_LINE_IRQ1
#define INPUT_LINE_INT2 INPUT_LINE_IRQ2
#define INPUT_LINE_INT3 INPUT_LINE_IRQ3
#define INPUT_LINE_TEST 20 /* PJB 03/05 */
#define INPUT_LINE_DRQ0 21
#define INPUT_LINE_DRQ1 22
#define INPUT_LINE_TMRIN0 23
#define INPUT_LINE_TMRIN1 24
typedef struct _i80186_interface i80186_interface;
struct _i80186_interface
{
devcb_write_line out_tmrout0_func;
devcb_write_line out_tmrout1_func;
};
#define I80186_INTERFACE(name) const i80186_interface (name) =
enum
{
I8086_IP,
I8086_AX,
I8086_CX,
I8086_DX,
I8086_BX,
I8086_SP,
I8086_BP,
I8086_SI,
I8086_DI,
I8086_AL,
I8086_CL,
I8086_DL,
I8086_BL,
I8086_AH,
I8086_CH,
I8086_DH,
I8086_BH,
I8086_FLAGS,
I8086_ES,
I8086_CS,
I8086_SS,
I8086_DS,
I8086_VECTOR,
I8086_GENPC = STATE_GENPC,
I8086_GENSP = STATE_GENSP,
I8086_GENPCBASE = STATE_GENPCBASE
};
/* Public functions */
DECLARE_LEGACY_CPU_DEVICE(I8086, i8086);
DECLARE_LEGACY_CPU_DEVICE(I8088, i8088);
DECLARE_LEGACY_CPU_DEVICE(I80186, i80186);
DECLARE_LEGACY_CPU_DEVICE(I80188, i80188);
#endif /* __I86INTF_H__ */
/* ASG 971222 -- rewrote this interface */
#pragma once
#ifndef __I86INTF_H__
#define __I86INTF_H__
#define INPUT_LINE_INT0 INPUT_LINE_IRQ0
#define INPUT_LINE_INT1 INPUT_LINE_IRQ1
#define INPUT_LINE_INT2 INPUT_LINE_IRQ2
#define INPUT_LINE_INT3 INPUT_LINE_IRQ3
#define INPUT_LINE_TEST 20 /* PJB 03/05 */
#define INPUT_LINE_DRQ0 21
#define INPUT_LINE_DRQ1 22
#define INPUT_LINE_TMRIN0 23
#define INPUT_LINE_TMRIN1 24
struct i80186_interface
{
devcb_write_line out_tmrout0_func;
devcb_write_line out_tmrout1_func;
};
#define I80186_INTERFACE(name) const i80186_interface (name) =
enum
{
I8086_IP,
I8086_AX,
I8086_CX,
I8086_DX,
I8086_BX,
I8086_SP,
I8086_BP,
I8086_SI,
I8086_DI,
I8086_AL,
I8086_CL,
I8086_DL,
I8086_BL,
I8086_AH,
I8086_CH,
I8086_DH,
I8086_BH,
I8086_FLAGS,
I8086_ES,
I8086_CS,
I8086_SS,
I8086_DS,
I8086_VECTOR,
I8086_GENPC = STATE_GENPC,
I8086_GENSP = STATE_GENSP,
I8086_GENPCBASE = STATE_GENPCBASE
};
/* Public functions */
DECLARE_LEGACY_CPU_DEVICE(I8086, i8086);
DECLARE_LEGACY_CPU_DEVICE(I8088, i8088);
DECLARE_LEGACY_CPU_DEVICE(I80186, i80186);
DECLARE_LEGACY_CPU_DEVICE(I80188, i80188);
#endif /* __I86INTF_H__ */

3
src/emu/cpu/i960/i960.c
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@ -16,8 +16,7 @@ CPU_DISASSEMBLE( i960 );
enum { RCACHE_SIZE = 4 };
typedef struct _i960_state_t i960_state_t;
struct _i960_state_t {
struct i960_state_t {
UINT32 r[0x20];
UINT32 rcache[RCACHE_SIZE][0x10];
UINT32 rcache_frame_addr[RCACHE_SIZE];

3
src/emu/cpu/i960/i960dis.h
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@ -1,8 +1,7 @@
#ifndef __I960DIS_H__
#define __I960DIS_H__
typedef struct _disassemble_t disassemble_t;
struct _disassemble_t
struct disassemble_t
{
char *buffer; // output buffer
unsigned long IP;

327
src/emu/cpu/jaguar/jaguar.c
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@ -79,8 +79,7 @@ CPU_DISASSEMBLE( jaguardsp );
***************************************************************************/
/* Jaguar Registers */
typedef struct _jaguar_state jaguar_state;
struct _jaguar_state
struct jaguar_cpu_state
{
/* core registers */
UINT32 r[32];
@ -97,7 +96,7 @@ struct _jaguar_state
int isdsp;
int icount;
int bankswitch_icount;
void (*const *table)(jaguar_state *jaguar, UINT16 op);
void (*const *table)(jaguar_cpu_state *jaguar, UINT16 op);
device_irq_acknowledge_callback irq_callback;
jaguar_int_func cpu_interrupt;
legacy_cpu_device *device;
@ -124,78 +123,78 @@ static const UINT32 convert_zero[32] =
FUNCTION TABLES
***************************************************************************/
static void abs_rn(jaguar_state *jaguar, UINT16 op);
static void add_rn_rn(jaguar_state *jaguar, UINT16 op);
static void addc_rn_rn(jaguar_state *jaguar, UINT16 op);
static void addq_n_rn(jaguar_state *jaguar, UINT16 op);
static void addqmod_n_rn(jaguar_state *jaguar, UINT16 op); /* DSP only */
static void addqt_n_rn(jaguar_state *jaguar, UINT16 op);
static void and_rn_rn(jaguar_state *jaguar, UINT16 op);
static void bclr_n_rn(jaguar_state *jaguar, UINT16 op);
static void bset_n_rn(jaguar_state *jaguar, UINT16 op);
static void btst_n_rn(jaguar_state *jaguar, UINT16 op);
static void cmp_rn_rn(jaguar_state *jaguar, UINT16 op);
static void cmpq_n_rn(jaguar_state *jaguar, UINT16 op);
static void div_rn_rn(jaguar_state *jaguar, UINT16 op);
static void illegal(jaguar_state *jaguar, UINT16 op);
static void imacn_rn_rn(jaguar_state *jaguar, UINT16 op);
static void imult_rn_rn(jaguar_state *jaguar, UINT16 op);
static void imultn_rn_rn(jaguar_state *jaguar, UINT16 op);
static void jr_cc_n(jaguar_state *jaguar, UINT16 op);
static void jump_cc_rn(jaguar_state *jaguar, UINT16 op);
static void load_rn_rn(jaguar_state *jaguar, UINT16 op);
static void load_r14n_rn(jaguar_state *jaguar, UINT16 op);
static void load_r15n_rn(jaguar_state *jaguar, UINT16 op);
static void load_r14rn_rn(jaguar_state *jaguar, UINT16 op);
static void load_r15rn_rn(jaguar_state *jaguar, UINT16 op);
static void loadb_rn_rn(jaguar_state *jaguar, UINT16 op);
static void loadw_rn_rn(jaguar_state *jaguar, UINT16 op);
static void loadp_rn_rn(jaguar_state *jaguar, UINT16 op); /* GPU only */
static void mirror_rn(jaguar_state *jaguar, UINT16 op); /* DSP only */
static void mmult_rn_rn(jaguar_state *jaguar, UINT16 op);
static void move_rn_rn(jaguar_state *jaguar, UINT16 op);
static void move_pc_rn(jaguar_state *jaguar, UINT16 op);
static void movefa_rn_rn(jaguar_state *jaguar, UINT16 op);
static void movei_n_rn(jaguar_state *jaguar, UINT16 op);
static void moveq_n_rn(jaguar_state *jaguar, UINT16 op);
static void moveta_rn_rn(jaguar_state *jaguar, UINT16 op);
static void mtoi_rn_rn(jaguar_state *jaguar, UINT16 op);
static void mult_rn_rn(jaguar_state *jaguar, UINT16 op);
static void neg_rn(jaguar_state *jaguar, UINT16 op);
static void nop(jaguar_state *jaguar, UINT16 op);
static void normi_rn_rn(jaguar_state *jaguar, UINT16 op);
static void not_rn(jaguar_state *jaguar, UINT16 op);
static void or_rn_rn(jaguar_state *jaguar, UINT16 op);
static void pack_rn(jaguar_state *jaguar, UINT16 op); /* GPU only */
static void resmac_rn(jaguar_state *jaguar, UINT16 op);
static void ror_rn_rn(jaguar_state *jaguar, UINT16 op);
static void rorq_n_rn(jaguar_state *jaguar, UINT16 op);
static void sat8_rn(jaguar_state *jaguar, UINT16 op); /* GPU only */
static void sat16_rn(jaguar_state *jaguar, UINT16 op); /* GPU only */
static void sat16s_rn(jaguar_state *jaguar, UINT16 op); /* DSP only */
static void sat24_rn(jaguar_state *jaguar, UINT16 op); /* GPU only */
static void sat32s_rn(jaguar_state *jaguar, UINT16 op); /* DSP only */
static void sh_rn_rn(jaguar_state *jaguar, UINT16 op);
static void sha_rn_rn(jaguar_state *jaguar, UINT16 op);
static void sharq_n_rn(jaguar_state *jaguar, UINT16 op);
static void shlq_n_rn(jaguar_state *jaguar, UINT16 op);
static void shrq_n_rn(jaguar_state *jaguar, UINT16 op);
static void store_rn_rn(jaguar_state *jaguar, UINT16 op);
static void store_rn_r14n(jaguar_state *jaguar, UINT16 op);
static void store_rn_r15n(jaguar_state *jaguar, UINT16 op);
static void store_rn_r14rn(jaguar_state *jaguar, UINT16 op);
static void store_rn_r15rn(jaguar_state *jaguar, UINT16 op);
static void storeb_rn_rn(jaguar_state *jaguar, UINT16 op);
static void storew_rn_rn(jaguar_state *jaguar, UINT16 op);
static void storep_rn_rn(jaguar_state *jaguar, UINT16 op); /* GPU only */
static void sub_rn_rn(jaguar_state *jaguar, UINT16 op);
static void subc_rn_rn(jaguar_state *jaguar, UINT16 op);
static void subq_n_rn(jaguar_state *jaguar, UINT16 op);
static void subqmod_n_rn(jaguar_state *jaguar, UINT16 op); /* DSP only */
static void subqt_n_rn(jaguar_state *jaguar, UINT16 op);
static void xor_rn_rn(jaguar_state *jaguar, UINT16 op);
static void abs_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void add_rn_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void addc_rn_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void addq_n_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void addqmod_n_rn(jaguar_cpu_state *jaguar, UINT16 op); /* DSP only */
static void addqt_n_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void and_rn_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void bclr_n_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void bset_n_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void btst_n_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void cmp_rn_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void cmpq_n_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void div_rn_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void illegal(jaguar_cpu_state *jaguar, UINT16 op);
static void imacn_rn_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void imult_rn_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void imultn_rn_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void jr_cc_n(jaguar_cpu_state *jaguar, UINT16 op);
static void jump_cc_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void load_rn_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void load_r14n_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void load_r15n_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void load_r14rn_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void load_r15rn_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void loadb_rn_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void loadw_rn_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void loadp_rn_rn(jaguar_cpu_state *jaguar, UINT16 op); /* GPU only */
static void mirror_rn(jaguar_cpu_state *jaguar, UINT16 op); /* DSP only */
static void mmult_rn_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void move_rn_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void move_pc_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void movefa_rn_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void movei_n_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void moveq_n_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void moveta_rn_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void mtoi_rn_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void mult_rn_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void neg_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void nop(jaguar_cpu_state *jaguar, UINT16 op);
static void normi_rn_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void not_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void or_rn_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void pack_rn(jaguar_cpu_state *jaguar, UINT16 op); /* GPU only */
static void resmac_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void ror_rn_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void rorq_n_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void sat8_rn(jaguar_cpu_state *jaguar, UINT16 op); /* GPU only */
static void sat16_rn(jaguar_cpu_state *jaguar, UINT16 op); /* GPU only */
static void sat16s_rn(jaguar_cpu_state *jaguar, UINT16 op); /* DSP only */
static void sat24_rn(jaguar_cpu_state *jaguar, UINT16 op); /* GPU only */
static void sat32s_rn(jaguar_cpu_state *jaguar, UINT16 op); /* DSP only */
static void sh_rn_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void sha_rn_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void sharq_n_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void shlq_n_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void shrq_n_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void store_rn_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void store_rn_r14n(jaguar_cpu_state *jaguar, UINT16 op);
static void store_rn_r15n(jaguar_cpu_state *jaguar, UINT16 op);
static void store_rn_r14rn(jaguar_cpu_state *jaguar, UINT16 op);
static void store_rn_r15rn(jaguar_cpu_state *jaguar, UINT16 op);
static void storeb_rn_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void storew_rn_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void storep_rn_rn(jaguar_cpu_state *jaguar, UINT16 op); /* GPU only */
static void sub_rn_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void subc_rn_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void subq_n_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void subqmod_n_rn(jaguar_cpu_state *jaguar, UINT16 op); /* DSP only */
static void subqt_n_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void xor_rn_rn(jaguar_cpu_state *jaguar, UINT16 op);
static void (*const gpu_op_table[64])(jaguar_state *jaguar, UINT16 op) =
static void (*const gpu_op_table[64])(jaguar_cpu_state *jaguar, UINT16 op) =
{
/* 00-03 */ add_rn_rn, addc_rn_rn, addq_n_rn, addqt_n_rn,
/* 04-07 */ sub_rn_rn, subc_rn_rn, subq_n_rn, subqt_n_rn,
@ -215,7 +214,7 @@ static void (*const gpu_op_table[64])(jaguar_state *jaguar, UINT16 op) =
/* 60-63 */ store_rn_r14rn, store_rn_r15rn, sat24_rn, pack_rn
};
static void (*const dsp_op_table[64])(jaguar_state *jaguar, UINT16 op) =
static void (*const dsp_op_table[64])(jaguar_cpu_state *jaguar, UINT16 op) =
{
/* 00-03 */ add_rn_rn, addc_rn_rn, addq_n_rn, addqt_n_rn,
/* 04-07 */ sub_rn_rn, subc_rn_rn, subq_n_rn, subqt_n_rn,
@ -249,15 +248,15 @@ static void (*const dsp_op_table[64])(jaguar_state *jaguar, UINT16 op) =
INLINE FUNCTIONS
***************************************************************************/
INLINE jaguar_state *get_safe_token(device_t *device)
INLINE jaguar_cpu_state *get_safe_token(device_t *device)
{
assert(device != NULL);
assert(device->type() == JAGUARGPU ||
device->type() == JAGUARDSP);
return (jaguar_state *)downcast<legacy_cpu_device *>(device)->token();
return (jaguar_cpu_state *)downcast<legacy_cpu_device *>(device)->token();
}
INLINE void update_register_banks(jaguar_state *jaguar)
INLINE void update_register_banks(jaguar_cpu_state *jaguar)
{
UINT32 temp;
int i, bank;
@ -296,7 +295,7 @@ INLINE void update_register_banks(jaguar_state *jaguar)
IRQ HANDLING
***************************************************************************/
static void check_irqs(jaguar_state *jaguar)
static void check_irqs(jaguar_cpu_state *jaguar)
{
int bits, mask, which = 0;
@ -339,7 +338,7 @@ static void check_irqs(jaguar_state *jaguar)
}
static void set_irq_line(jaguar_state *jaguar, int irqline, int state)
static void set_irq_line(jaguar_cpu_state *jaguar, int irqline, int state)
{
int mask = (irqline < 5) ? (0x40 << irqline) : 0x10000;
jaguar->ctrl[G_CTRL] &= ~mask;
@ -399,7 +398,7 @@ static void init_tables(void)
}
static void jaguar_postload(jaguar_state *jaguar)
static void jaguar_postload(jaguar_cpu_state *jaguar)
{
update_register_banks(jaguar);
check_irqs(jaguar);
@ -409,7 +408,7 @@ static void jaguar_postload(jaguar_state *jaguar)
static void init_common(int isdsp, legacy_cpu_device *device, device_irq_acknowledge_callback irqcallback)
{
const jaguar_cpu_config *configdata = (const jaguar_cpu_config *)device->static_config();
jaguar_state *jaguar = get_safe_token(device);
jaguar_cpu_state *jaguar = get_safe_token(device);
init_tables();
@ -445,7 +444,7 @@ static CPU_INIT( jaguardsp )
static CPU_RESET( jaguar )
{
jaguar_state *jaguar = get_safe_token(device);
jaguar_cpu_state *jaguar = get_safe_token(device);
jaguar->b0 = jaguar->r;
jaguar->b1 = jaguar->a;
@ -474,7 +473,7 @@ static CPU_EXIT( jaguar )
static CPU_EXECUTE( jaguargpu )
{
jaguar_state *jaguar = get_safe_token(device);
jaguar_cpu_state *jaguar = get_safe_token(device);
/* if we're halted, we shouldn't be here */
if (!(jaguar->ctrl[G_CTRL] & 1))
@ -513,7 +512,7 @@ static CPU_EXECUTE( jaguargpu )
static CPU_EXECUTE( jaguardsp )
{
jaguar_state *jaguar = get_safe_token(device);
jaguar_cpu_state *jaguar = get_safe_token(device);
/* if we're halted, we shouldn't be here */
if (!(jaguar->ctrl[G_CTRL] & 1))
@ -556,7 +555,7 @@ static CPU_EXECUTE( jaguardsp )
OPCODES
***************************************************************************/
void abs_rn(jaguar_state *jaguar, UINT16 op)
void abs_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
int dreg = op & 31;
UINT32 res = jaguar->r[dreg];
@ -569,7 +568,7 @@ void abs_rn(jaguar_state *jaguar, UINT16 op)
SET_Z(jaguar, res);
}
void add_rn_rn(jaguar_state *jaguar, UINT16 op)
void add_rn_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
int dreg = op & 31;
UINT32 r1 = jaguar->r[(op >> 5) & 31];
@ -579,7 +578,7 @@ void add_rn_rn(jaguar_state *jaguar, UINT16 op)
CLR_ZNC(jaguar); SET_ZNC_ADD(jaguar, r2, r1, res);
}
void addc_rn_rn(jaguar_state *jaguar, UINT16 op)
void addc_rn_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
int dreg = op & 31;
UINT32 r1 = jaguar->r[(op >> 5) & 31];
@ -589,7 +588,7 @@ void addc_rn_rn(jaguar_state *jaguar, UINT16 op)
CLR_ZNC(jaguar); SET_ZNC_ADD(jaguar, r2, r1, res);
}
void addq_n_rn(jaguar_state *jaguar, UINT16 op)
void addq_n_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
int dreg = op & 31;
UINT32 r1 = convert_zero[(op >> 5) & 31];
@ -599,7 +598,7 @@ void addq_n_rn(jaguar_state *jaguar, UINT16 op)
CLR_ZNC(jaguar); SET_ZNC_ADD(jaguar, r2, r1, res);
}
void addqmod_n_rn(jaguar_state *jaguar, UINT16 op) /* DSP only */
void addqmod_n_rn(jaguar_cpu_state *jaguar, UINT16 op) /* DSP only */
{
int dreg = op & 31;
UINT32 r1 = convert_zero[(op >> 5) & 31];
@ -610,7 +609,7 @@ void addqmod_n_rn(jaguar_state *jaguar, UINT16 op) /* DSP only */
CLR_ZNC(jaguar); SET_ZNC_ADD(jaguar, r2, r1, res);
}
void addqt_n_rn(jaguar_state *jaguar, UINT16 op)
void addqt_n_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
int dreg = op & 31;
UINT32 r1 = convert_zero[(op >> 5) & 31];
@ -619,7 +618,7 @@ void addqt_n_rn(jaguar_state *jaguar, UINT16 op)
jaguar->r[dreg] = res;
}
void and_rn_rn(jaguar_state *jaguar, UINT16 op)
void and_rn_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
int dreg = op & 31;
UINT32 r1 = jaguar->r[(op >> 5) & 31];
@ -629,7 +628,7 @@ void and_rn_rn(jaguar_state *jaguar, UINT16 op)
CLR_ZN(jaguar); SET_ZN(jaguar, res);
}
void bclr_n_rn(jaguar_state *jaguar, UINT16 op)
void bclr_n_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
int dreg = op & 31;
UINT32 r1 = (op >> 5) & 31;
@ -639,7 +638,7 @@ void bclr_n_rn(jaguar_state *jaguar, UINT16 op)
CLR_ZN(jaguar); SET_ZN(jaguar, res);
}
void bset_n_rn(jaguar_state *jaguar, UINT16 op)
void bset_n_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
int dreg = op & 31;
UINT32 r1 = (op >> 5) & 31;
@ -649,14 +648,14 @@ void bset_n_rn(jaguar_state *jaguar, UINT16 op)
CLR_ZN(jaguar); SET_ZN(jaguar, res);
}
void btst_n_rn(jaguar_state *jaguar, UINT16 op)
void btst_n_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
UINT32 r1 = (op >> 5) & 31;
UINT32 r2 = jaguar->r[op & 31];
CLR_Z(jaguar); jaguar->FLAGS |= (~r2 >> r1) & 1;
}
void cmp_rn_rn(jaguar_state *jaguar, UINT16 op)
void cmp_rn_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
UINT32 r1 = jaguar->r[(op >> 5) & 31];
UINT32 r2 = jaguar->r[op & 31];
@ -664,7 +663,7 @@ void cmp_rn_rn(jaguar_state *jaguar, UINT16 op)
CLR_ZNC(jaguar); SET_ZNC_SUB(jaguar, r2, r1, res);
}
void cmpq_n_rn(jaguar_state *jaguar, UINT16 op)
void cmpq_n_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
UINT32 r1 = (INT8)(op >> 2) >> 3;
UINT32 r2 = jaguar->r[op & 31];
@ -672,7 +671,7 @@ void cmpq_n_rn(jaguar_state *jaguar, UINT16 op)
CLR_ZNC(jaguar); SET_ZNC_SUB(jaguar, r2, r1, res);
}
void div_rn_rn(jaguar_state *jaguar, UINT16 op)
void div_rn_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
int dreg = op & 31;
UINT32 r1 = jaguar->r[(op >> 5) & 31];
@ -694,11 +693,11 @@ void div_rn_rn(jaguar_state *jaguar, UINT16 op)
jaguar->r[dreg] = 0xffffffff;
}
void illegal(jaguar_state *jaguar, UINT16 op)
void illegal(jaguar_cpu_state *jaguar, UINT16 op)
{
}
void imacn_rn_rn(jaguar_state *jaguar, UINT16 op)
void imacn_rn_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
UINT32 r1 = jaguar->r[(op >> 5) & 31];
UINT32 r2 = jaguar->r[op & 31];
@ -706,7 +705,7 @@ void imacn_rn_rn(jaguar_state *jaguar, UINT16 op)
logerror("Unexpected IMACN instruction!\n");
}
void imult_rn_rn(jaguar_state *jaguar, UINT16 op)
void imult_rn_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
int dreg = op & 31;
UINT32 r1 = jaguar->r[(op >> 5) & 31];
@ -716,7 +715,7 @@ void imult_rn_rn(jaguar_state *jaguar, UINT16 op)
CLR_ZN(jaguar); SET_ZN(jaguar, res);
}
void imultn_rn_rn(jaguar_state *jaguar, UINT16 op)
void imultn_rn_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
int dreg = op & 31;
UINT32 r1 = jaguar->r[(op >> 5) & 31];
@ -741,7 +740,7 @@ void imultn_rn_rn(jaguar_state *jaguar, UINT16 op)
}
}
void jr_cc_n(jaguar_state *jaguar, UINT16 op)
void jr_cc_n(jaguar_cpu_state *jaguar, UINT16 op)
{
if (CONDITION(op & 31))
{
@ -756,7 +755,7 @@ void jr_cc_n(jaguar_state *jaguar, UINT16 op)
}
}
void jump_cc_rn(jaguar_state *jaguar, UINT16 op)
void jump_cc_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
if (CONDITION(op & 31))
{
@ -773,56 +772,56 @@ void jump_cc_rn(jaguar_state *jaguar, UINT16 op)
}
}
void load_rn_rn(jaguar_state *jaguar, UINT16 op)
void load_rn_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
UINT32 r1 = jaguar->r[(op >> 5) & 31];
jaguar->r[op & 31] = READLONG(jaguar, r1);
}
void load_r14n_rn(jaguar_state *jaguar, UINT16 op)
void load_r14n_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
UINT32 r1 = convert_zero[(op >> 5) & 31];
jaguar->r[op & 31] = READLONG(jaguar, jaguar->r[14] + 4 * r1);
}
void load_r15n_rn(jaguar_state *jaguar, UINT16 op)
void load_r15n_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
UINT32 r1 = convert_zero[(op >> 5) & 31];
jaguar->r[op & 31] = READLONG(jaguar, jaguar->r[15] + 4 * r1);
}
void load_r14rn_rn(jaguar_state *jaguar, UINT16 op)
void load_r14rn_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
UINT32 r1 = jaguar->r[(op >> 5) & 31];
jaguar->r[op & 31] = READLONG(jaguar, jaguar->r[14] + r1);
}
void load_r15rn_rn(jaguar_state *jaguar, UINT16 op)
void load_r15rn_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
UINT32 r1 = jaguar->r[(op >> 5) & 31];
jaguar->r[op & 31] = READLONG(jaguar, jaguar->r[15] + r1);
}
void loadb_rn_rn(jaguar_state *jaguar, UINT16 op)
void loadb_rn_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
UINT32 r1 = jaguar->r[(op >> 5) & 31];
jaguar->r[op & 31] = READBYTE(jaguar, r1);
}
void loadw_rn_rn(jaguar_state *jaguar, UINT16 op)
void loadw_rn_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
UINT32 r1 = jaguar->r[(op >> 5) & 31];
jaguar->r[op & 31] = READWORD(jaguar, r1);
}
void loadp_rn_rn(jaguar_state *jaguar, UINT16 op) /* GPU only */
void loadp_rn_rn(jaguar_cpu_state *jaguar, UINT16 op) /* GPU only */
{
UINT32 r1 = jaguar->r[(op >> 5) & 31];
jaguar->ctrl[G_HIDATA] = READWORD(jaguar, r1);
jaguar->r[op & 31] = READWORD(jaguar, r1+4);
}
void mirror_rn(jaguar_state *jaguar, UINT16 op) /* DSP only */
void mirror_rn(jaguar_cpu_state *jaguar, UINT16 op) /* DSP only */
{
int dreg = op & 31;
UINT32 r1 = jaguar->r[dreg];
@ -831,7 +830,7 @@ void mirror_rn(jaguar_state *jaguar, UINT16 op) /* DSP only */
CLR_ZN(jaguar); SET_ZN(jaguar, res);
}
void mmult_rn_rn(jaguar_state *jaguar, UINT16 op)
void mmult_rn_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
int count = jaguar->ctrl[G_MTXC] & 15, i;
int sreg = (op >> 5) & 31;
@ -860,45 +859,45 @@ void mmult_rn_rn(jaguar_state *jaguar, UINT16 op)
CLR_ZN(jaguar); SET_ZN(jaguar, res);
}
void move_rn_rn(jaguar_state *jaguar, UINT16 op)
void move_rn_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
jaguar->r[op & 31] = jaguar->r[(op >> 5) & 31];
}
void move_pc_rn(jaguar_state *jaguar, UINT16 op)
void move_pc_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
jaguar->r[op & 31] = jaguar->ppc;
}
void movefa_rn_rn(jaguar_state *jaguar, UINT16 op)
void movefa_rn_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
jaguar->r[op & 31] = jaguar->a[(op >> 5) & 31];
}
void movei_n_rn(jaguar_state *jaguar, UINT16 op)
void movei_n_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
UINT32 res = ROPCODE(jaguar, jaguar->PC) | (ROPCODE(jaguar, jaguar->PC + 2) << 16);
jaguar->PC += 4;
jaguar->r[op & 31] = res;
}
void moveq_n_rn(jaguar_state *jaguar, UINT16 op)
void moveq_n_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
jaguar->r[op & 31] = (op >> 5) & 31;
}
void moveta_rn_rn(jaguar_state *jaguar, UINT16 op)
void moveta_rn_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
jaguar->a[op & 31] = jaguar->r[(op >> 5) & 31];
}
void mtoi_rn_rn(jaguar_state *jaguar, UINT16 op)
void mtoi_rn_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
UINT32 r1 = jaguar->r[(op >> 5) & 31];
jaguar->r[op & 31] = (((INT32)r1 >> 8) & 0xff800000) | (r1 & 0x007fffff);
}
void mult_rn_rn(jaguar_state *jaguar, UINT16 op)
void mult_rn_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
int dreg = op & 31;
UINT32 r1 = jaguar->r[(op >> 5) & 31];
@ -908,7 +907,7 @@ void mult_rn_rn(jaguar_state *jaguar, UINT16 op)
CLR_ZN(jaguar); SET_ZN(jaguar, res);
}
void neg_rn(jaguar_state *jaguar, UINT16 op)
void neg_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
int dreg = op & 31;
UINT32 r2 = jaguar->r[dreg];
@ -917,11 +916,11 @@ void neg_rn(jaguar_state *jaguar, UINT16 op)
CLR_ZNC(jaguar); SET_ZNC_SUB(jaguar, 0, r2, res);
}
void nop(jaguar_state *jaguar, UINT16 op)
void nop(jaguar_cpu_state *jaguar, UINT16 op)
{
}
void normi_rn_rn(jaguar_state *jaguar, UINT16 op)
void normi_rn_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
UINT32 r1 = jaguar->r[(op >> 5) & 31];
UINT32 res = 0;
@ -942,7 +941,7 @@ void normi_rn_rn(jaguar_state *jaguar, UINT16 op)
CLR_ZN(jaguar); SET_ZN(jaguar, res);
}
void not_rn(jaguar_state *jaguar, UINT16 op)
void not_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
int dreg = op & 31;
UINT32 res = ~jaguar->r[dreg];
@ -950,7 +949,7 @@ void not_rn(jaguar_state *jaguar, UINT16 op)
CLR_ZN(jaguar); SET_ZN(jaguar, res);
}
void or_rn_rn(jaguar_state *jaguar, UINT16 op)
void or_rn_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
int dreg = op & 31;
UINT32 r1 = jaguar->r[(op >> 5) & 31];
@ -960,7 +959,7 @@ void or_rn_rn(jaguar_state *jaguar, UINT16 op)
CLR_ZN(jaguar); SET_ZN(jaguar, res);
}
void pack_rn(jaguar_state *jaguar, UINT16 op) /* GPU only */
void pack_rn(jaguar_cpu_state *jaguar, UINT16 op) /* GPU only */
{
int dreg = op & 31;
UINT32 r1 = jaguar->r[(op >> 5) & 31];
@ -974,12 +973,12 @@ void pack_rn(jaguar_state *jaguar, UINT16 op) /* GPU only */
CLR_ZN(jaguar); SET_ZN(jaguar, res);
}
void resmac_rn(jaguar_state *jaguar, UINT16 op)
void resmac_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
jaguar->r[op & 31] = (UINT32)jaguar->accum;
}
void ror_rn_rn(jaguar_state *jaguar, UINT16 op)
void ror_rn_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
int dreg = op & 31;
UINT32 r1 = jaguar->r[(op >> 5) & 31] & 31;
@ -989,7 +988,7 @@ void ror_rn_rn(jaguar_state *jaguar, UINT16 op)
CLR_ZNC(jaguar); SET_ZN(jaguar, res); jaguar->FLAGS |= (r2 >> 30) & 2;
}
void rorq_n_rn(jaguar_state *jaguar, UINT16 op)
void rorq_n_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
int dreg = op & 31;
UINT32 r1 = convert_zero[(op >> 5) & 31];
@ -999,7 +998,7 @@ void rorq_n_rn(jaguar_state *jaguar, UINT16 op)
CLR_ZNC(jaguar); SET_ZN(jaguar, res); jaguar->FLAGS |= (r2 >> 30) & 2;
}
void sat8_rn(jaguar_state *jaguar, UINT16 op) /* GPU only */
void sat8_rn(jaguar_cpu_state *jaguar, UINT16 op) /* GPU only */
{
int dreg = op & 31;
INT32 r2 = jaguar->r[dreg];
@ -1008,7 +1007,7 @@ void sat8_rn(jaguar_state *jaguar, UINT16 op) /* GPU only */
CLR_ZN(jaguar); SET_ZN(jaguar, res);
}
void sat16_rn(jaguar_state *jaguar, UINT16 op) /* GPU only */
void sat16_rn(jaguar_cpu_state *jaguar, UINT16 op) /* GPU only */
{
int dreg = op & 31;
INT32 r2 = jaguar->r[dreg];
@ -1017,7 +1016,7 @@ void sat16_rn(jaguar_state *jaguar, UINT16 op) /* GPU only */
CLR_ZN(jaguar); SET_ZN(jaguar, res);
}
void sat16s_rn(jaguar_state *jaguar, UINT16 op) /* DSP only */
void sat16s_rn(jaguar_cpu_state *jaguar, UINT16 op) /* DSP only */
{
int dreg = op & 31;
INT32 r2 = jaguar->r[dreg];
@ -1026,7 +1025,7 @@ void sat16s_rn(jaguar_state *jaguar, UINT16 op) /* DSP only */
CLR_ZN(jaguar); SET_ZN(jaguar, res);
}
void sat24_rn(jaguar_state *jaguar, UINT16 op) /* GPU only */
void sat24_rn(jaguar_cpu_state *jaguar, UINT16 op) /* GPU only */
{
int dreg = op & 31;
INT32 r2 = jaguar->r[dreg];
@ -1035,7 +1034,7 @@ void sat24_rn(jaguar_state *jaguar, UINT16 op) /* GPU only */
CLR_ZN(jaguar); SET_ZN(jaguar, res);
}
void sat32s_rn(jaguar_state *jaguar, UINT16 op) /* DSP only */
void sat32s_rn(jaguar_cpu_state *jaguar, UINT16 op) /* DSP only */
{
int dreg = op & 31;
INT32 r2 = (UINT32)jaguar->r[dreg];
@ -1045,7 +1044,7 @@ void sat32s_rn(jaguar_state *jaguar, UINT16 op) /* DSP only */
CLR_ZN(jaguar); SET_ZN(jaguar, res);
}
void sh_rn_rn(jaguar_state *jaguar, UINT16 op)
void sh_rn_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
int dreg = op & 31;
INT32 r1 = (INT32)jaguar->r[(op >> 5) & 31];
@ -1067,7 +1066,7 @@ void sh_rn_rn(jaguar_state *jaguar, UINT16 op)
SET_ZN(jaguar, res);
}
void sha_rn_rn(jaguar_state *jaguar, UINT16 op)
void sha_rn_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
int dreg = op & 31;
INT32 r1 = (INT32)jaguar->r[(op >> 5) & 31];
@ -1089,7 +1088,7 @@ void sha_rn_rn(jaguar_state *jaguar, UINT16 op)
SET_ZN(jaguar, res);
}
void sharq_n_rn(jaguar_state *jaguar, UINT16 op)
void sharq_n_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
int dreg = op & 31;
INT32 r1 = convert_zero[(op >> 5) & 31];
@ -1099,7 +1098,7 @@ void sharq_n_rn(jaguar_state *jaguar, UINT16 op)
CLR_ZNC(jaguar); SET_ZN(jaguar, res); jaguar->FLAGS |= (r2 << 1) & 2;
}
void shlq_n_rn(jaguar_state *jaguar, UINT16 op)
void shlq_n_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
int dreg = op & 31;
INT32 r1 = convert_zero[(op >> 5) & 31];
@ -1109,7 +1108,7 @@ void shlq_n_rn(jaguar_state *jaguar, UINT16 op)
CLR_ZNC(jaguar); SET_ZN(jaguar, res); jaguar->FLAGS |= (r2 >> 30) & 2;
}
void shrq_n_rn(jaguar_state *jaguar, UINT16 op)
void shrq_n_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
int dreg = op & 31;
INT32 r1 = convert_zero[(op >> 5) & 31];
@ -1119,56 +1118,56 @@ void shrq_n_rn(jaguar_state *jaguar, UINT16 op)
CLR_ZNC(jaguar); SET_ZN(jaguar, res); jaguar->FLAGS |= (r2 << 1) & 2;
}
void store_rn_rn(jaguar_state *jaguar, UINT16 op)
void store_rn_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
UINT32 r1 = jaguar->r[(op >> 5) & 31];
WRITELONG(jaguar, r1, jaguar->r[op & 31]);
}
void store_rn_r14n(jaguar_state *jaguar, UINT16 op)
void store_rn_r14n(jaguar_cpu_state *jaguar, UINT16 op)
{
UINT32 r1 = convert_zero[(op >> 5) & 31];
WRITELONG(jaguar, jaguar->r[14] + r1 * 4, jaguar->r[op & 31]);
}
void store_rn_r15n(jaguar_state *jaguar, UINT16 op)
void store_rn_r15n(jaguar_cpu_state *jaguar, UINT16 op)
{
UINT32 r1 = convert_zero[(op >> 5) & 31];
WRITELONG(jaguar, jaguar->r[15] + r1 * 4, jaguar->r[op & 31]);
}
void store_rn_r14rn(jaguar_state *jaguar, UINT16 op)
void store_rn_r14rn(jaguar_cpu_state *jaguar, UINT16 op)
{
UINT32 r1 = jaguar->r[(op >> 5) & 31];
WRITELONG(jaguar, jaguar->r[14] + r1, jaguar->r[op & 31]);
}
void store_rn_r15rn(jaguar_state *jaguar, UINT16 op)
void store_rn_r15rn(jaguar_cpu_state *jaguar, UINT16 op)
{
UINT32 r1 = jaguar->r[(op >> 5) & 31];
WRITELONG(jaguar, jaguar->r[15] + r1, jaguar->r[op & 31]);
}
void storeb_rn_rn(jaguar_state *jaguar, UINT16 op)
void storeb_rn_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
UINT32 r1 = jaguar->r[(op >> 5) & 31];
WRITEBYTE(jaguar, r1, jaguar->r[op & 31]);
}
void storew_rn_rn(jaguar_state *jaguar, UINT16 op)
void storew_rn_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
UINT32 r1 = jaguar->r[(op >> 5) & 31];
WRITEWORD(jaguar, r1, jaguar->r[op & 31]);
}
void storep_rn_rn(jaguar_state *jaguar, UINT16 op) /* GPU only */
void storep_rn_rn(jaguar_cpu_state *jaguar, UINT16 op) /* GPU only */
{
UINT32 r1 = jaguar->r[(op >> 5) & 31];
WRITELONG(jaguar, r1, jaguar->ctrl[G_HIDATA]);
WRITELONG(jaguar, r1+4, jaguar->r[op & 31]);
}
void sub_rn_rn(jaguar_state *jaguar, UINT16 op)
void sub_rn_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
int dreg = op & 31;
UINT32 r1 = jaguar->r[(op >> 5) & 31];
@ -1178,7 +1177,7 @@ void sub_rn_rn(jaguar_state *jaguar, UINT16 op)
CLR_ZNC(jaguar); SET_ZNC_SUB(jaguar, r2, r1, res);
}
void subc_rn_rn(jaguar_state *jaguar, UINT16 op)
void subc_rn_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
int dreg = op & 31;
UINT32 r1 = jaguar->r[(op >> 5) & 31];
@ -1188,7 +1187,7 @@ void subc_rn_rn(jaguar_state *jaguar, UINT16 op)
CLR_ZNC(jaguar); SET_ZNC_SUB(jaguar, r2, r1, res);
}
void subq_n_rn(jaguar_state *jaguar, UINT16 op)
void subq_n_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
int dreg = op & 31;
UINT32 r1 = convert_zero[(op >> 5) & 31];
@ -1198,7 +1197,7 @@ void subq_n_rn(jaguar_state *jaguar, UINT16 op)
CLR_ZNC(jaguar); SET_ZNC_SUB(jaguar, r2, r1, res);
}
void subqmod_n_rn(jaguar_state *jaguar, UINT16 op) /* DSP only */
void subqmod_n_rn(jaguar_cpu_state *jaguar, UINT16 op) /* DSP only */
{
int dreg = op & 31;
UINT32 r1 = convert_zero[(op >> 5) & 31];
@ -1209,7 +1208,7 @@ void subqmod_n_rn(jaguar_state *jaguar, UINT16 op) /* DSP only */
CLR_ZNC(jaguar); SET_ZNC_SUB(jaguar, r2, r1, res);
}
void subqt_n_rn(jaguar_state *jaguar, UINT16 op)
void subqt_n_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
int dreg = op & 31;
UINT32 r1 = convert_zero[(op >> 5) & 31];
@ -1218,7 +1217,7 @@ void subqt_n_rn(jaguar_state *jaguar, UINT16 op)
jaguar->r[dreg] = res;
}
void xor_rn_rn(jaguar_state *jaguar, UINT16 op)
void xor_rn_rn(jaguar_cpu_state *jaguar, UINT16 op)
{
int dreg = op & 31;
UINT32 r1 = jaguar->r[(op >> 5) & 31];
@ -1236,7 +1235,7 @@ void xor_rn_rn(jaguar_state *jaguar, UINT16 op)
UINT32 jaguargpu_ctrl_r(device_t *device, offs_t offset)
{
jaguar_state *jaguar = get_safe_token(device);
jaguar_cpu_state *jaguar = get_safe_token(device);
if (LOG_GPU_IO) logerror("GPU read register @ F021%02X\n", offset * 4);
@ -1246,7 +1245,7 @@ UINT32 jaguargpu_ctrl_r(device_t *device, offs_t offset)
void jaguargpu_ctrl_w(device_t *device, offs_t offset, UINT32 data, UINT32 mem_mask)
{
jaguar_state *jaguar = get_safe_token(device);
jaguar_cpu_state *jaguar = get_safe_token(device);
UINT32 oldval, newval;
if (LOG_GPU_IO && offset != G_HIDATA)
@ -1332,7 +1331,7 @@ void jaguargpu_ctrl_w(device_t *device, offs_t offset, UINT32 data, UINT32 mem_m
UINT32 jaguardsp_ctrl_r(device_t *device, offs_t offset)
{
jaguar_state *jaguar = get_safe_token(device);
jaguar_cpu_state *jaguar = get_safe_token(device);
if (LOG_DSP_IO && offset != D_FLAGS)
logerror("DSP read register @ F1A1%02X\n", offset * 4);
@ -1344,7 +1343,7 @@ UINT32 jaguardsp_ctrl_r(device_t *device, offs_t offset)
void jaguardsp_ctrl_w(device_t *device, offs_t offset, UINT32 data, UINT32 mem_mask)
{
jaguar_state *jaguar = get_safe_token(device);
jaguar_cpu_state *jaguar = get_safe_token(device);
UINT32 oldval, newval;
if (LOG_DSP_IO && offset != D_FLAGS)
@ -1431,7 +1430,7 @@ void jaguardsp_ctrl_w(device_t *device, offs_t offset, UINT32 data, UINT32 mem_m
static CPU_SET_INFO( jaguargpu )
{
jaguar_state *jaguar = get_safe_token(device);
jaguar_cpu_state *jaguar = get_safe_token(device);
switch (state)
{
/* --- the following bits of info are set as 64-bit signed integers --- */
@ -1489,11 +1488,11 @@ static CPU_SET_INFO( jaguargpu )
CPU_GET_INFO( jaguargpu )
{
jaguar_state *jaguar = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
jaguar_cpu_state *jaguar = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
switch (state)
{
/* --- the following bits of info are returned as 64-bit signed integers --- */
case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(jaguar_state); break;
case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(jaguar_cpu_state); break;
case CPUINFO_INT_INPUT_LINES: info->i = 5; break;
case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break;
case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break;
@ -1628,7 +1627,7 @@ CPU_GET_INFO( jaguargpu )
static CPU_SET_INFO( jaguardsp )
{
jaguar_state *jaguar = get_safe_token(device);
jaguar_cpu_state *jaguar = get_safe_token(device);
switch (state)
{
/* --- the following bits of info are set as 64-bit signed integers --- */
@ -1642,7 +1641,7 @@ static CPU_SET_INFO( jaguardsp )
CPU_GET_INFO( jaguardsp )
{
jaguar_state *jaguar = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
jaguar_cpu_state *jaguar = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
switch (state)
{
/* --- the following bits of info are returned as 64-bit signed integers --- */

3
src/emu/cpu/jaguar/jaguar.h
View File

@ -74,8 +74,7 @@ enum
typedef void (*jaguar_int_func)(device_t *device);
typedef struct _jaguar_cpu_config jaguar_cpu_config;
struct _jaguar_cpu_config
struct jaguar_cpu_config
{
jaguar_int_func cpu_int_callback;
};

3
src/emu/cpu/konami/konami.c
View File

@ -43,8 +43,7 @@
#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
/* Konami Registers */
typedef struct _konami_state konami_state;
struct _konami_state
struct konami_state
{
PAIR pc; /* Program counter */
PAIR ppc; /* Previous program counter */

3
src/emu/cpu/lh5801/lh5801.c
View File

@ -54,8 +54,7 @@ enum
LH5801_IRQ_STATE
};
typedef struct _lh5801_state lh5801_state;
struct _lh5801_state
struct lh5801_state
{
const lh5801_cpu_core *config;
legacy_cpu_device *device;

3
src/emu/cpu/lh5801/lh5801.h
View File

@ -67,8 +67,7 @@ pc 8bit
typedef UINT8 (*lh5801_in_func)(device_t *device);
typedef struct _lh5801_cpu_core lh5801_cpu_core;
struct _lh5801_cpu_core
struct lh5801_cpu_core
{
lh5801_in_func in;
};

3
src/emu/cpu/m37710/m37710cm.h
View File

@ -72,8 +72,7 @@ INLINE int MAKE_INT_8(int A) {return (A & 0x80) ? A | ~0xff : A & 0xff;}
/* ======================================================================== */
/* CPU Structure */
typedef struct _m37710i_cpu_struct m37710i_cpu_struct;
struct _m37710i_cpu_struct
struct m37710i_cpu_struct
{
uint a; /* Accumulator */
uint b; /* holds high byte of accumulator */

3
src/emu/cpu/m6502/m6502.h
View File

@ -56,8 +56,7 @@ enum
#define M6510_INTERFACE(name) \
const m6502_interface (name) =
typedef struct _m6502_interface m6502_interface;
struct _m6502_interface
struct m6502_interface
{
devcb_read8 read_indexed_func;
devcb_write8 write_indexed_func;

3
src/emu/cpu/m6800/m6800.c
View File

@ -106,8 +106,7 @@ enum
#endif
/* 6800 Registers */
typedef struct _m6800_state m6800_state;
struct _m6800_state
struct m6800_state
{
// int subtype; /* CPU subtype */
PAIR ppc; /* Previous program counter */

3
src/emu/cpu/m6800/m6800.h
View File

@ -6,8 +6,7 @@
#define __M6800_H__
typedef struct _m6801_interface m6801_interface;
struct _m6801_interface
struct m6801_interface
{
devcb_write_line out_sc2_func;
};

3
src/emu/cpu/m6809/m6809.c
View File

@ -79,8 +79,7 @@
#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
/* 6809 Registers */
typedef struct _m68_state_t m68_state_t;
struct _m68_state_t
struct m68_state_t
{
PAIR pc; /* Program counter */
PAIR ppc; /* Previous program counter */

3
src/emu/cpu/m6809/m6809.h
View File

@ -23,8 +23,7 @@ DECLARE_LEGACY_CPU_DEVICE(M6809E, m6809e);
CPU_DISASSEMBLE( m6809 );
typedef struct _m6809_config m6809_config;
struct _m6809_config
struct m6809_config
{
UINT8 encrypt_only_first_byte; /* encrypt only the first byte in 10 xx and 11 xx opcodes */
};

3
src/emu/cpu/mb86233/mb86233.c
View File

@ -30,8 +30,7 @@ typedef union
float f;
} MB86233_REG;
typedef struct _mb86233_state mb86233_state;
struct _mb86233_state
struct mb86233_state
{
UINT16 pc;
MB86233_REG a;

3
src/emu/cpu/mb86233/mb86233.h
View File

@ -45,8 +45,7 @@ enum
typedef int (*mb86233_fifo_read_func)(device_t *device, UINT32 *data);
typedef void (*mb86233_fifo_write_func)(device_t *device, UINT32 data);
typedef struct _mb86233_cpu_core mb86233_cpu_core;
struct _mb86233_cpu_core
struct mb86233_cpu_core
{
mb86233_fifo_read_func fifo_read_cb;
mb86233_fifo_write_func fifo_write_cb;

3
src/emu/cpu/mb88xx/mb88xx.c
View File

@ -37,8 +37,7 @@
STRUCTURES & TYPEDEFS
***************************************************************************/
typedef struct _mb88_state mb88_state;
struct _mb88_state
struct mb88_state
{
UINT8 PC; /* Program Counter: 6 bits */
UINT8 PA; /* Page Address: 4 bits */

3
src/emu/cpu/mb88xx/mb88xx.h
View File

@ -54,8 +54,7 @@ enum
CONFIG STRUCTURE
***************************************************************************/
typedef struct _mb88_cpu_core mb88_cpu_core;
struct _mb88_cpu_core
struct mb88_cpu_core
{
UINT8 *PLA_config; /* PLA configuration (32 byte values), if NULL assume direct output */
};

3
src/emu/cpu/mc68hc11/hc11ops.h
View File

@ -1,5 +1,4 @@
typedef struct _hc11_opcode_list_struct hc11_opcode_list_struct;
struct _hc11_opcode_list_struct
struct hc11_opcode_list_struct
{
int page;
int opcode;

3
src/emu/cpu/mc68hc11/mc68hc11.c
View File

@ -36,8 +36,7 @@ enum
static const int div_tab[4] = { 1, 4, 8, 16 };
typedef struct _hc11_state hc11_state;
struct _hc11_state
struct hc11_state
{
union {
struct {

3
src/emu/cpu/mc68hc11/mc68hc11.h
View File

@ -31,8 +31,7 @@ DECLARE_LEGACY_CPU_DEVICE(MC68HC11, mc68hc11);
#define MC68HC11_IRQ_LINE 0
#define MC68HC11_TOC1_LINE 1
typedef struct _hc11_config hc11_config;
struct _hc11_config
struct hc11_config
{
int has_extended_io; // I/O enable flag
int internal_ram_size;

3
src/emu/cpu/mcs48/mcs48.c
View File

@ -118,8 +118,7 @@ T0 output clock
***************************************************************************/
/* live processor state */
typedef struct _mcs48_state mcs48_state;
struct _mcs48_state
struct mcs48_state
{
UINT16 prevpc; /* 16-bit previous program counter */
UINT16 pc; /* 16-bit program counter */

6
src/emu/cpu/mcs51/mcs51.c
View File

@ -234,8 +234,7 @@ enum
TYPE DEFINITIONS
***************************************************************************/
typedef struct _mcs51_uart mcs51_uart;
struct _mcs51_uart
struct mcs51_uart
{
UINT8 data_out; //Data to send out
UINT8 bits_to_send; //How many bits left to send when transmitting out the serial port
@ -246,8 +245,7 @@ struct _mcs51_uart
UINT8 delay_cycles; //Gross Hack;
};
typedef struct _mcs51_state_t mcs51_state_t;
struct _mcs51_state_t
struct mcs51_state_t
{
//Internal stuff
UINT16 ppc; //previous pc

3
src/emu/cpu/mcs51/mcs51.h
View File

@ -77,8 +77,7 @@ enum
***************************************************************************/
/* configuration of the DS5002FP */
typedef struct _ds5002fp_config ds5002fp_config;
struct _ds5002fp_config
struct ds5002fp_config
{
UINT8 mcon; /* bootstrap loader MCON register */
UINT8 rpctl; /* bootstrap loader RPCTL register */

3
src/emu/cpu/mips/mips3.h
View File

@ -210,8 +210,7 @@ enum
STRUCTURES
***************************************************************************/
typedef struct _mips3_config mips3_config;
struct _mips3_config
struct mips3_config
{
size_t icache; /* code cache size */
size_t dcache; /* data cache size */

6
src/emu/cpu/mips/mips3com.h
View File

@ -167,8 +167,7 @@ typedef enum _mips3_flavor mips3_flavor;
***************************************************************************/
/* MIPS3 TLB entry */
typedef struct _mips3_tlb_entry mips3_tlb_entry;
struct _mips3_tlb_entry
struct mips3_tlb_entry
{
UINT64 page_mask;
UINT64 entry_hi;
@ -181,8 +180,7 @@ typedef struct _mips3imp_state mips3imp_state;
/* MIPS3 state */
typedef struct _mips3_state mips3_state;
struct _mips3_state
struct mips3_state
{
/* core registers */
UINT32 pc;

9
src/emu/cpu/mips/mips3drc.c
View File

@ -150,8 +150,7 @@ using namespace uml;
***************************************************************************/
/* fast RAM info */
typedef struct _fast_ram_info fast_ram_info;
struct _fast_ram_info
struct fast_ram_info
{
offs_t start; /* start of the RAM block */
offs_t end; /* end of the RAM block */
@ -161,8 +160,7 @@ struct _fast_ram_info
/* hotspot info */
typedef struct _hotspot_info hotspot_info;
struct _hotspot_info
struct hotspot_info
{
offs_t pc; /* PC to consider */
UINT32 opcode; /* required opcode at that PC */
@ -171,8 +169,7 @@ struct _hotspot_info
/* internal compiler state */
typedef struct _compiler_state compiler_state;
struct _compiler_state
struct compiler_state
{
UINT32 cycles; /* accumulated cycles */
UINT8 checkints; /* need to check interrupts before next instruction */

3
src/emu/cpu/mips/r3000.c
View File

@ -116,8 +116,7 @@ CPU_DISASSEMBLE( r3000le );
***************************************************************************/
/* R3000 Registers */
typedef struct _r3000_state r3000_state;
struct _r3000_state
struct r3000_state
{
/* core registers */
UINT32 pc;

3
src/emu/cpu/mips/r3000.h
View File

@ -46,8 +46,7 @@ enum
STRUCTURES
***************************************************************************/
typedef struct _r3000_cpu_core r3000_cpu_core;
struct _r3000_cpu_core
struct r3000_cpu_core
{
UINT8 hasfpu; /* 1 if we have an FPU, 0 otherwise */
size_t icache; /* code cache size */

3
src/emu/cpu/mn10200/mn10200.c
View File

@ -22,8 +22,7 @@
extern int mn102_disassemble(char *buffer, UINT32 pc, const UINT8 *oprom);
typedef struct _mn102_info mn102_info;
struct _mn102_info
struct mn102_info
{
// The UINT32s are really UINT24
UINT32 pc;

73
src/emu/cpu/nec/nec.h
View File

@ -1,37 +1,36 @@
/* ASG 971222 -- rewrote this interface */
#ifndef __NEC_H_
#define __NEC_H_
typedef struct _nec_config nec_config;
struct _nec_config
{
const UINT8* v25v35_decryptiontable; // internal decryption table
};
#define NEC_INPUT_LINE_INTP0 10
#define NEC_INPUT_LINE_INTP1 11
#define NEC_INPUT_LINE_INTP2 12
#define NEC_INPUT_LINE_POLL 20
#define V25_PORT_P0 0x10000
#define V25_PORT_P1 0x10002
#define V25_PORT_P2 0x10004
#define V25_PORT_PT 0x10006
enum
{
NEC_PC=0,
NEC_IP, NEC_AW, NEC_CW, NEC_DW, NEC_BW, NEC_SP, NEC_BP, NEC_IX, NEC_IY,
NEC_FLAGS, NEC_ES, NEC_CS, NEC_SS, NEC_DS,
NEC_PENDING
};
/* Public functions */
DECLARE_LEGACY_CPU_DEVICE(V20, v20);
DECLARE_LEGACY_CPU_DEVICE(V25, v25);
DECLARE_LEGACY_CPU_DEVICE(V30, v30);
DECLARE_LEGACY_CPU_DEVICE(V33, v33);
DECLARE_LEGACY_CPU_DEVICE(V35, v35);
#endif
/* ASG 971222 -- rewrote this interface */
#ifndef __NEC_H_
#define __NEC_H_
struct nec_config
{
const UINT8* v25v35_decryptiontable; // internal decryption table
};
#define NEC_INPUT_LINE_INTP0 10
#define NEC_INPUT_LINE_INTP1 11
#define NEC_INPUT_LINE_INTP2 12
#define NEC_INPUT_LINE_POLL 20
#define V25_PORT_P0 0x10000
#define V25_PORT_P1 0x10002
#define V25_PORT_P2 0x10004
#define V25_PORT_PT 0x10006
enum
{
NEC_PC=0,
NEC_IP, NEC_AW, NEC_CW, NEC_DW, NEC_BW, NEC_SP, NEC_BP, NEC_IX, NEC_IY,
NEC_FLAGS, NEC_ES, NEC_CS, NEC_SS, NEC_DS,
NEC_PENDING
};
/* Public functions */
DECLARE_LEGACY_CPU_DEVICE(V20, v20);
DECLARE_LEGACY_CPU_DEVICE(V25, v25);
DECLARE_LEGACY_CPU_DEVICE(V30, v30);
DECLARE_LEGACY_CPU_DEVICE(V33, v33);
DECLARE_LEGACY_CPU_DEVICE(V35, v35);
#endif

3
src/emu/cpu/nec/necdasm.c
View File

@ -7,8 +7,7 @@
#include "emu.h"
typedef struct _nec_config nec_config;
struct _nec_config
struct nec_config
{
const UINT8* v25v35_decryptiontable; // internal decryption table
};

3
src/emu/cpu/nec/necpriv.h
View File

@ -33,8 +33,7 @@ typedef union
UINT8 b[16]; /* or as 8 bit registers */
} necbasicregs;
typedef struct _nec_state_t nec_state_t;
struct _nec_state_t
struct nec_state_t
{
necbasicregs regs;
offs_t fetch_xor;

3
src/emu/cpu/nec/v25priv.h
View File

@ -66,8 +66,7 @@ typedef union
UINT8 b[256];
} internalram;
typedef struct _v25_state_t v25_state_t;
struct _v25_state_t
struct v25_state_t
{
internalram ram;
offs_t fetch_xor;

3
src/emu/cpu/pdp1/pdp1.c
View File

@ -348,8 +348,7 @@
/* PDP1 Registers */
typedef struct _pdp1_state pdp1_state;
struct _pdp1_state
struct pdp1_state
{
/* processor registers */
UINT32 pc; /* program counter (12, 15 or 16 bits) */

3
src/emu/cpu/pdp1/pdp1.h
View File

@ -27,8 +27,7 @@ typedef void (*pdp1_read_binary_word_func)(device_t *device);
typedef void (*pdp1_io_sc_func)(device_t *device);
typedef struct _pdp1_reset_param_t pdp1_reset_param_t;
struct _pdp1_reset_param_t
struct pdp1_reset_param_t
{
/* callbacks for iot instructions (required for any I/O) */
pdp1_extern_iot_func extern_iot[64];

3
src/emu/cpu/pdp1/tx0.c
View File

@ -21,8 +21,7 @@ static void pulse_reset(device_t *device);
/* TX-0 Registers */
typedef struct _tx0_state tx0_state;
struct _tx0_state
struct tx0_state
{
const tx0_reset_param_t *iface;

3
src/emu/cpu/pdp1/tx0.h
View File

@ -23,8 +23,7 @@ enum
#define tx0_pulse_reset(cpudevice) (cpudevice)->state().set_state_int(TX0_RESET, 0)
#define tx0_pulse_io_complete(cpudevice) (cpudevice)->state().set_state_int(TX0_IO_COMPLETE, 0)
typedef struct _tx0_reset_param_t tx0_reset_param_t;
struct _tx0_reset_param_t
struct tx0_reset_param_t
{
/* 8 standard I/O handlers:
0: cpy (8kW only)

6
src/emu/cpu/pic16c5x/pic16c5x.c
View File

@ -67,8 +67,7 @@
typedef struct _pic16c5x_state pic16c5x_state;
struct _pic16c5x_state
struct pic16c5x_state
{
/******************** CPU Internal Registers *******************/
UINT16 PC;
@ -117,8 +116,7 @@ INLINE pic16c5x_state *get_safe_token(device_t *device)
/* opcode table entry */
typedef struct _pic16c5x_opcode pic16c5x_opcode;
struct _pic16c5x_opcode
struct pic16c5x_opcode
{
UINT8 cycles;
void (*function)(pic16c5x_state *);

9
src/emu/cpu/pic16c62x/pic16c62x.c
View File

@ -57,8 +57,7 @@
typedef struct _pic16c62x_state pic16c62x_state;
struct _pic16c62x_state
struct pic16c62x_state
{
/******************** CPU Internal Registers *******************/
UINT16 PC;
@ -109,15 +108,13 @@ INLINE pic16c62x_state *get_safe_token(device_t *device)
/* opcode table entry */
typedef struct _pic16c62x_opcode pic16c62x_opcode;
struct _pic16c62x_opcode
struct pic16c62x_opcode
{
UINT8 cycles;
void (*function)(pic16c62x_state *);
};
/* instruction list entry */
typedef struct _pic16c62x_instruction pic16c62x_instruction;
struct _pic16c62x_instruction
struct pic16c62x_instruction
{
char *format;
void (*function)(pic16c62x_state *);

3
src/emu/cpu/powerpc/ppc.h
View File

@ -164,8 +164,7 @@ enum
typedef void (*ppc4xx_spu_tx_handler)(device_t *device, UINT8 data);
typedef struct _powerpc_config powerpc_config;
struct _powerpc_config
struct powerpc_config
{
UINT32 bus_frequency;
read32_device_func dcr_read_func;

6
src/emu/cpu/powerpc/ppccom.h
View File

@ -491,8 +491,7 @@ enum
***************************************************************************/
/* PowerPC 4XX-specific serial port state */
typedef struct _ppc4xx_spu_state ppc4xx_spu_state;
struct _ppc4xx_spu_state
struct ppc4xx_spu_state
{
UINT8 regs[9];
UINT8 txbuf;
@ -509,8 +508,7 @@ typedef struct _ppcimp_state ppcimp_state;
/* PowerPC state */
typedef struct _powerpc_state powerpc_state;
struct _powerpc_state
struct powerpc_state
{
/* core registers */
UINT32 pc;

9
src/emu/cpu/powerpc/ppcdrc.c
View File

@ -129,8 +129,7 @@ extern offs_t ppc_dasm_one(char *buffer, UINT32 pc, UINT32 op);
***************************************************************************/
/* fast RAM info */
typedef struct _fast_ram_info fast_ram_info;
struct _fast_ram_info
struct fast_ram_info
{
offs_t start; /* start of the RAM block */
offs_t end; /* end of the RAM block */
@ -140,8 +139,7 @@ struct _fast_ram_info
/* hotspot info */
typedef struct _hotspot_info hotspot_info;
struct _hotspot_info
struct hotspot_info
{
offs_t pc; /* PC to consider */
UINT32 opcode; /* required opcode at that PC */
@ -150,8 +148,7 @@ struct _hotspot_info
/* internal compiler state */
typedef struct _compiler_state compiler_state;
struct _compiler_state
struct compiler_state
{
UINT32 cycles; /* accumulated cycles */
UINT8 checkints; /* need to check interrupts before next instruction */

3
src/emu/cpu/pps4/pps4.c
View File

@ -19,8 +19,7 @@
TYPE DEFINITIONS
***************************************************************************/
typedef struct _pps4_state pps4_state;
struct _pps4_state
struct pps4_state
{
UINT8 A; // Accumulator
UINT8 X;

3
src/emu/cpu/psx/dma.h
View File

@ -17,8 +17,7 @@ extern const device_type PSX_DMA;
typedef delegate<void (UINT32, INT32)> psx_dma_read_delegate;
typedef delegate<void (UINT32, INT32)> psx_dma_write_delegate;
typedef struct _psx_dma_channel psx_dma_channel;
struct _psx_dma_channel
struct psx_dma_channel
{
UINT32 n_base;
UINT32 n_blockcontrol;

3
src/emu/cpu/psx/rcnt.h
View File

@ -23,8 +23,7 @@ extern const device_type PSX_RCNT;
#define PSX_RC_CLC ( 0x100 )
#define PSX_RC_DIV ( 0x200 )
typedef struct _psx_root psx_root;
struct _psx_root
struct psx_root
{
emu_timer *timer;
UINT16 n_count;

3
src/emu/cpu/psx/sio.h
View File

@ -41,8 +41,7 @@ typedef void ( *psx_sio_handler )( running_machine &, int );
#define SIO_CONTROL_DSR_IENA ( 1 << 12 )
#define SIO_CONTROL_DTR ( 1 << 13 )
typedef struct _psx_sio psx_sio;
struct _psx_sio
struct psx_sio
{
UINT32 n_status;
UINT32 n_mode;

6
src/emu/cpu/rsp/rsp.h
View File

@ -70,8 +70,7 @@ enum
typedef void (*rsp_set_status_func)(device_t *device, UINT32 status);
typedef struct _rsp_config rsp_config;
struct _rsp_config
struct rsp_config
{
read32_device_func dp_reg_r;
write32_device_func dp_reg_w;
@ -155,8 +154,7 @@ typedef union
} ACCUMULATOR_REG;
typedef struct _rspimp_state rspimp_state;
typedef struct _rsp_state rsp_state;
struct _rsp_state
struct rsp_state
{
const rsp_config *config;
FILE *exec_output;

6
src/emu/cpu/rsp/rspdrc.c
View File

@ -82,8 +82,7 @@ extern offs_t rsp_dasm_one(char *buffer, offs_t pc, UINT32 op);
***************************************************************************/
/* fast RAM info */
typedef struct _fast_ram_info fast_ram_info;
struct _fast_ram_info
struct fast_ram_info
{
offs_t start; /* start of the RAM block */
offs_t end; /* end of the RAM block */
@ -93,8 +92,7 @@ struct _fast_ram_info
/* internal compiler state */
typedef struct _compiler_state compiler_state;
struct _compiler_state
struct compiler_state
{
UINT32 cycles; /* accumulated cycles */
UINT8 checkints; /* need to check interrupts before next instruction */

3
src/emu/cpu/s2650/s2650.c
View File

@ -25,8 +25,7 @@
/* define this to expand all EA calculations inline */
#define INLINE_EA 1
typedef struct _s2650_regs s2650_regs;
struct _s2650_regs {
struct s2650_regs {
UINT16 ppc; /* previous program counter (page + iar) */
UINT16 page; /* 8K page select register (A14..A13) */
UINT16 iar; /* instruction address register (A12..A0) */

3
src/emu/cpu/saturn/saturn.c
View File

@ -52,8 +52,7 @@ typedef SaturnNib Saturn64[16];
/****************************************************************************
* The SATURN registers.
****************************************************************************/
typedef struct _saturn_state saturn_state;
struct _saturn_state
struct saturn_state
{
saturn_cpu_core *config;

3
src/emu/cpu/saturn/saturn.h
View File

@ -50,8 +50,7 @@ HP38G 09/??/95 1LT8 Yorke
#define SATURN_INT_IRQ 1
#define SATURN_INT_NMI 2
typedef struct _saturn_cpu_core saturn_cpu_core;
struct _saturn_cpu_core
struct saturn_cpu_core
{
void (*out)(device_t*,int);
int (*in)(device_t*);

3
src/emu/cpu/sc61860/sc61860.c
View File

@ -40,8 +40,7 @@
/****************************************************************************
* The 61860 registers.
****************************************************************************/
typedef struct _sc61860_state sc61860_state;
struct _sc61860_state
struct sc61860_state
{
sc61860_cpu_core *config;
UINT8 p, q, r; //7 bits only?

3
src/emu/cpu/sc61860/sc61860.h
View File

@ -37,8 +37,7 @@
64 kb external ram (first 8kbyte not seen for program execution?) */
typedef struct _sc61860_cpu_core sc61860_cpu_core;
struct _sc61860_cpu_core
struct sc61860_cpu_core
{
int (*reset)(device_t *device);
int (*brk)(device_t *device);

3
src/emu/cpu/scmp/scmp.c
View File

@ -20,8 +20,7 @@
TYPE DEFINITIONS
***************************************************************************/
typedef struct _scmp_state scmp_state;
struct _scmp_state
struct scmp_state
{
scmp_config config;
PAIR PC;

3
src/emu/cpu/scmp/scmp.h
View File

@ -17,8 +17,7 @@ enum
/***************************************************************************
TYPE DEFINITIONS
***************************************************************************/
typedef struct _scmp_config scmp_config;
struct _scmp_config
struct scmp_config
{
devcb_write8 flag_out_func;
devcb_write_line sout_func;

3
src/emu/cpu/se3208/se3208.c
View File

@ -10,8 +10,7 @@
*/
typedef struct _se3208_state_t se3208_state_t;
struct _se3208_state_t
struct se3208_state_t
{
//GPR
UINT32 R[8];

3
src/emu/cpu/sh2/sh2.h
View File

@ -57,8 +57,7 @@ enum
SH2_R8, SH2_R9, SH2_R10, SH2_R11, SH2_R12, SH2_R13, SH2_R14, SH2_R15, SH2_EA
};
typedef struct _sh2_cpu_core sh2_cpu_core;
struct _sh2_cpu_core
struct sh2_cpu_core
{
int is_slave;
int (*dma_callback_kludge)(device_t *device, UINT32 src, UINT32 dst, UINT32 data, int size);

3
src/emu/cpu/sh2/sh2comn.h
View File

@ -26,8 +26,7 @@ class sh2_frontend;
#define SH2_CODE_XOR(a) ((a) ^ NATIVE_ENDIAN_VALUE_LE_BE(2,0))
typedef struct _irq_entry irq_entry;
struct _irq_entry
struct irq_entry
{
int irq_vector;
int irq_priority;

3
src/emu/cpu/sh2/sh2drc.c
View File

@ -89,8 +89,7 @@ extern int sh2_describe(void *param, opcode_desc *desc, const opcode_desc *prev)
***************************************************************************/
/* internal compiler state */
typedef struct _compiler_state compiler_state;
struct _compiler_state
struct compiler_state
{
UINT32 cycles; /* accumulated cycles */
UINT8 checkints; /* need to check interrupts before next instruction */

3
src/emu/cpu/sm8500/sm8500.c
View File

@ -30,8 +30,7 @@ they are internally.
#define FLAG_B 0x02
#define FLAG_I 0x01
typedef struct _sm8500_state sm8500_state;
struct _sm8500_state
struct sm8500_state
{
SM8500_CONFIG config;
UINT16 PC;

3
src/emu/cpu/ssem/ssem.c
View File

@ -14,8 +14,7 @@ CPU_DISASSEMBLE( ssem );
#define SSEM_DISASM_ON_UNIMPL 0
#define SSEM_DUMP_MEM_ON_UNIMPL 0
typedef struct _ssem_state ssem_state;
struct _ssem_state
struct ssem_state
{
UINT32 pc;
UINT32 a;

3
src/emu/cpu/ssp1601/ssp1601.c
View File

@ -29,8 +29,7 @@ CPU_DISASSEMBLE( ssp1601 );
typedef struct _ssp1601_state_t ssp1601_state_t;
struct _ssp1601_state_t
struct ssp1601_state_t
{
PAIR gr[8]; /* general regs, some are 16bit, some 32bit */
union {

3
src/emu/cpu/superfx/superfx.c
View File

@ -15,8 +15,7 @@ typedef struct
UINT8 valid[0x20];
} cache_t;
typedef struct _superfx_state superfx_state;
struct _superfx_state
struct superfx_state
{
superfx_config config;

3
src/emu/cpu/superfx/superfx.h
View File

@ -83,8 +83,7 @@ enum
#define SUPERFX_CFGR_IRQ 0x80 // IRQ
#define SUPERFX_CFGR_MS0 0x20 // MS0
typedef struct _superfx_config superfx_config;
struct _superfx_config
struct superfx_config
{
devcb_write_line out_irq_func; /* IRQ changed callback */
};

3
src/emu/cpu/t11/t11.c
View File

@ -22,8 +22,7 @@
*
*************************************/
typedef struct _t11_state t11_state;
struct _t11_state
struct t11_state
{
PAIR ppc; /* previous program counter */
PAIR reg[8];

3
src/emu/cpu/tlcs900/tlcs900.c
View File

@ -17,8 +17,7 @@ TODO:
#include "debugger.h"
#include "tlcs900.h"
typedef struct _tlcs900_state tlcs900_state;
struct _tlcs900_state
struct tlcs900_state
{
const tlcs900_interface *intf;

3
src/emu/cpu/tlcs900/tlcs900.h
View File

@ -37,8 +37,7 @@ enum
};
typedef struct _tlcs900_interface tlcs900_interface;
struct _tlcs900_interface
struct tlcs900_interface
{
devcb_write8 to1;
devcb_write8 to3;

3
src/emu/cpu/tms0980/tms0980.c
View File

@ -226,8 +226,7 @@ unknown cycle: CME, SSE, SSS
#define I_YNEC ( MICRO_MASK | M_YTP | M_CKN | M_NE )
typedef struct _tms0980_state tms0980_state;
struct _tms0980_state
struct tms0980_state
{
UINT8 prev_pc; /* previous program counter */
UINT8 prev_pa; /* previous page address register */

3
src/emu/cpu/tms0980/tms0980.h
View File

@ -9,8 +9,7 @@ enum {
};
typedef struct _tms0980_config tms0980_config;
struct _tms0980_config {
struct tms0980_config {
/* O-output PLA configuration */
struct {
UINT8 value;

3
src/emu/cpu/tms32010/tms32010.c
View File

@ -114,8 +114,7 @@ INLINE tms32010_state *get_safe_token(device_t *device)
}
/* opcode table entry */
typedef struct _tms32010_opcode tms32010_opcode;
struct _tms32010_opcode
struct tms32010_opcode
{
UINT8 cycles;
void (*function)(tms32010_state *);

3
src/emu/cpu/tms32025/tms32025.c
View File

@ -192,8 +192,7 @@ INLINE tms32025_state *get_safe_token(device_t *device)
}
/* opcode table entry */
typedef struct _tms32025_opcode tms32025_opcode;
struct _tms32025_opcode
struct tms32025_opcode
{
UINT8 cycles;
void (*function)(tms32025_state *);

3
src/emu/cpu/tms32051/tms32051.c
View File

@ -79,8 +79,7 @@ typedef struct
UINT16 pm;
} ST1;
typedef struct _tms32051_state tms32051_state;
struct _tms32051_state
struct tms32051_state
{
UINT16 pc;
UINT16 op;

3
src/emu/cpu/tms34010/tms34010.c
View File

@ -41,8 +41,7 @@ struct _XY
#endif
};
typedef struct _tms34010_state tms34010_state;
struct _tms34010_state
struct tms34010_state
{
UINT32 pc;
UINT32 ppc;

6
src/emu/cpu/tms34010/tms34010.h
View File

@ -177,8 +177,7 @@ enum
/* Configuration structure */
typedef struct _tms34010_display_params tms34010_display_params;
struct _tms34010_display_params
struct tms34010_display_params
{
UINT16 vcount; /* most recent VCOUNT */
UINT16 veblnk, vsblnk; /* start/end of VBLANK */
@ -189,8 +188,7 @@ struct _tms34010_display_params
};
typedef struct _tms34010_config tms34010_config;
struct _tms34010_config
struct tms34010_config
{
UINT8 halt_on_reset; /* /HCS pin, which determines HALT state after reset */
const char *screen_tag; /* the screen operated on */

3
src/emu/cpu/unsp/unsp.h
View File

@ -12,8 +12,7 @@
#define __UNSP_H__
typedef struct _unspimp_state unspimp_state;
typedef struct _unsp_state unsp_state;
struct _unsp_state
struct unsp_state
{
UINT16 r[16];
UINT8 irq;

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