-r4000: Report the correct sub-revision for the R4600, and allow specific R4x00 types to specify the FPU ID as well. [Ryan Holtz]

-indigo: Switched to using the new R4000 core. [Ryan Holtz]

-hal2: Corrected chip revision ID to match real hardware. [Ryan Holtz]

-sgi_mc: Correctly flag EISA bus present on both Indigo 2 and Indy, as VINO uses the EISA signals for GIO64 arbitration. [Ryan Holtz]

src/devices/cpu/mips/r4000.cpp

@@ -85,11 +85,11 @@ DEFINE_DEVICE_TYPE(R4000, r4000_device, "r4000", "MIPS R4000")
 DEFINE_DEVICE_TYPE(R4400, r4400_device, "r4400", "MIPS R4400")
 DEFINE_DEVICE_TYPE(R4600, r4600_device, "r4600", "QED R4600")
 
-r4000_base_device::r4000_base_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, u32 prid, cache_size_t icache_size, cache_size_t dcache_size)
+r4000_base_device::r4000_base_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, u32 prid, u32 fcr, cache_size_t icache_size, cache_size_t dcache_size)
 	: cpu_device(mconfig, type, tag, owner, clock)
 	, m_program_config_le("program", ENDIANNESS_LITTLE, 64, 32)
 	, m_program_config_be("program", ENDIANNESS_BIG, 64, 32)
-	, m_fcr0(0x00000500U)
+	, m_fcr0(fcr)
 {
 	m_cp0[CP0_PRId] = prid;
 

src/devices/cpu/mips/r4000.h

@@ -56,7 +56,7 @@ protected:
 		CACHE_256K = 6,
 		CACHE_512K = 7,
 	};
-	r4000_base_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, u32 prid, cache_size_t icache_size, cache_size_t dcache_size);
+	r4000_base_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, u32 prid, u32 fcr, cache_size_t icache_size, cache_size_t dcache_size);
 
 	enum cp0_reg : int
 	{
@@ -441,7 +441,7 @@ class r4000_device : public r4000_base_device
 public:
 	// NOTE: R4000 chips prior to 3.0 have an xtlb bug
 	r4000_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
-		: r4000_base_device(mconfig, R4000, tag, owner, clock, 0x0430, CACHE_8K, CACHE_8K)
+		: r4000_base_device(mconfig, R4000, tag, owner, clock, 0x0430, 0x0500, CACHE_8K, CACHE_8K)
 	{
 		// no secondary cache
 		m_cp0[CP0_Config] |= CONFIG_SC;
@@ -452,7 +452,7 @@ class r4400_device : public r4000_base_device
 {
 public:
 	r4400_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
-		: r4000_base_device(mconfig, R4400, tag, owner, clock, 0x0440, CACHE_16K, CACHE_16K)
+		: r4000_base_device(mconfig, R4400, tag, owner, clock, 0x0440, 0x0500, CACHE_16K, CACHE_16K)
 	{
 		// no secondary cache
 		m_cp0[CP0_Config] |= CONFIG_SC;
@@ -463,7 +463,7 @@ class r4600_device : public r4000_base_device
 {
 public:
 	r4600_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
-		: r4000_base_device(mconfig, R4600, tag, owner, clock, 0x2000, CACHE_16K, CACHE_16K)
+		: r4000_base_device(mconfig, R4600, tag, owner, clock, 0x2020, 0x2020, CACHE_16K, CACHE_16K)
 	{
 		// no secondary cache
 		m_cp0[CP0_Config] |= CONFIG_SC;

src/mame/drivers/indigo.cpp

@@ -18,7 +18,7 @@
 #include "emu.h"
 //#include "cpu/dsp56156/dsp56156.h"
 #include "cpu/mips/mips1.h"
-#include "cpu/mips/mips3.h"
+#include "cpu/mips/r4000.h"
 #include "machine/eepromser.h"
 #include "machine/hpc1.h"
 #include "machine/sgi.h"
@@ -100,7 +100,7 @@ protected:
 
 	DECLARE_WRITE64_MEMBER(write_ram);
 
-	required_device<r4000be_device> m_maincpu;
+	required_device<r4000_device> m_maincpu;
 	required_device<sgi_mc_device> m_mem_ctrl;
 	required_shared_ptr<uint64_t> m_share1;
 };
@@ -214,12 +214,13 @@ void indigo4k_state::indigo4k(machine_config &config)
 {
 	indigo_base(config);
 
-	mips3_device &cpu(R4000BE(config, m_maincpu, 50000000*2));
+	R4000(config, m_maincpu, 50000000*2);
-	cpu.set_icache_size(32768);
+	//m_maincpu->set_icache_size(32768);
-	cpu.set_dcache_size(32768);
+	//m_maincpu->set_dcache_size(32768);
-	cpu.set_addrmap(AS_PROGRAM, &indigo4k_state::mem_map);
+	m_maincpu->set_addrmap(AS_PROGRAM, &indigo4k_state::mem_map);
 
 	SGI_MC(config, m_mem_ctrl, m_maincpu, m_eeprom);
+	m_mem_ctrl->eisa_present().set_constant(0);
 	SGI_HPC1(config, m_hpc, m_maincpu, m_eeprom);
 }
 

src/mame/drivers/indy_indigo2.cpp

@@ -75,6 +75,8 @@
 #include "emupal.h"
 #include "screen.h"
 
+#include "logmacro.h"
+
 class ip24_state : public driver_device
 {
 public:
@@ -109,7 +111,8 @@ protected:
 	virtual void machine_reset() override;
 
 	DECLARE_WRITE64_MEMBER(write_ram);
-	DECLARE_READ32_MEMBER(bus_error);
+	template <uint32_t addr_base> DECLARE_READ64_MEMBER(bus_error_r);
+	template <uint32_t addr_base> DECLARE_WRITE64_MEMBER(bus_error_w);
 
 	uint8_t volume_r(offs_t offset);
 	void volume_w(offs_t offset, uint8_t data);
@@ -170,12 +173,23 @@ private:
 	required_device<wd33c93b_device> m_scsi_ctrl2;
 };
 
-READ32_MEMBER(ip24_state::bus_error)
+template <uint32_t addr_base>
+READ64_MEMBER(ip24_state::bus_error_r)
 {
+	logerror("Bus error (read)\n");
 	m_maincpu->bus_error();
+	m_mem_ctrl->set_cpu_buserr(addr_base + (offset << 3), mem_mask);
 	return 0;
 }
 
+template <uint32_t addr_base>
+WRITE64_MEMBER(ip24_state::bus_error_w)
+{
+	logerror("Bus error (write)\n");
+	m_maincpu->bus_error();
+	m_mem_ctrl->set_cpu_buserr(addr_base + (offset << 3), mem_mask);
+}
+
 READ32_MEMBER(ip22_state::eisa_io_r)
 {
 	return 0xffffffff;
@@ -228,7 +242,7 @@ void ip24_state::ip24_base_map(address_map &map)
 	map(0x08000000, 0x0fffffff).share("mainram").ram().w(FUNC(ip24_state::write_ram));     /* 128 MB of main RAM */
 	map(0x1f000000, 0x1f9fffff).rw(m_gio64, FUNC(gio64_device::read), FUNC(gio64_device::write));
 	map(0x1fa00000, 0x1fa1ffff).rw(m_mem_ctrl, FUNC(sgi_mc_device::read), FUNC(sgi_mc_device::write));
-	map(0x1fb00000, 0x1fb7ffff).r(FUNC(ip24_state::bus_error));
+	map(0x1fb00000, 0x1fb7ffff).rw(FUNC(ip24_state::bus_error_r<0x1fb00000>), FUNC(ip24_state::bus_error_w<0x1fb00000>));
 	map(0x1fb80000, 0x1fbfffff).m(m_hpc3, FUNC(hpc3_device::map));
 	map(0x1fc00000, 0x1fc7ffff).rom().region("user1", 0);
 	map(0x20000000, 0x27ffffff).share("mainram").ram().w(FUNC(ip24_state::write_ram));
@@ -312,6 +326,7 @@ void ip24_state::ip24_base(machine_config &config)
 {
 	SGI_MC(config, m_mem_ctrl, m_maincpu, m_eeprom);
 	m_mem_ctrl->int_dma_done_cb().set(m_ioc2, FUNC(ioc2_device::mc_dma_done_w));
+	m_mem_ctrl->eisa_present().set_constant(1);
 
 	NSCSI_BUS(config, "scsibus", 0);
 	NSCSI_CONNECTOR(config, "scsibus:0").option_set("wd33c93", WD33C93B)

src/mame/machine/hal2.cpp

@@ -78,8 +78,8 @@ uint16_t hal2_device::read(offs_t offset)
 		LOGMASKED(LOG_READS, "%s: HAL2 Status Read: %08x\n", machine().describe_context(), m_isr);
 		return m_isr;
 	case REVISION_REG:
-		LOGMASKED(LOG_READS, "%s: HAL2 Revision Read: 0x4011\n", machine().describe_context());
+		LOGMASKED(LOG_READS, "%s: HAL2 Revision Read: 0x4010\n", machine().describe_context());
-		return 0x4011;
+		return 0x4010;
 
 	case INDIRECT_DATA0_REG:
 		LOGMASKED(LOG_WRITES, "%s: HAL2 Indirect Data Register 0 Read: %04x\n", machine().describe_context(), m_idr[0]);

src/mame/machine/sgi.cpp

@@ -32,6 +32,7 @@ sgi_mc_device::sgi_mc_device(const machine_config &mconfig, const char *tag, dev
 	, m_maincpu(*this, finder_base::DUMMY_TAG)
 	, m_eeprom(*this, finder_base::DUMMY_TAG)
 	, m_int_dma_done_cb(*this)
+	, m_eisa_present(*this)
 	, m_rpss_timer(nullptr)
 	, m_dma_timer(nullptr)
 	, m_watchdog(0)
@@ -73,6 +74,7 @@ sgi_mc_device::sgi_mc_device(const machine_config &mconfig, const char *tag, dev
 void sgi_mc_device::device_resolve_objects()
 {
 	m_int_dma_done_cb.resolve_safe();
+	m_eisa_present.resolve_safe();
 }
 
 //-------------------------------------------------
@@ -81,15 +83,8 @@ void sgi_mc_device::device_resolve_objects()
 
 void sgi_mc_device::device_start()
 {
-	// if Indigo2, ID appropriately
+	m_sys_id = 0x03; // rev. C MC
-	if (!strcmp(machine().system().name, "ip244415"))
+	m_sys_id = m_eisa_present() << 4;
-	{
-		m_sys_id = 0x13; // rev. C MC, EISA bus present
-	}
-	else
-	{
-		m_sys_id = 0x03; // rev. C MC, no EISA bus
-	}
 
 	m_rpss_timer = timer_alloc(TIMER_RPSS);
 	m_rpss_timer->adjust(attotime::never);
@@ -186,14 +181,19 @@ void sgi_mc_device::device_reset()
 	m_space = &m_maincpu->space(AS_PROGRAM);
 }
 
-void sgi_mc_device::set_cpu_buserr(uint32_t address)
+void sgi_mc_device::set_cpu_buserr(uint32_t address, uint64_t mem_mask)
 {
 	m_cpu_error_addr = address;
 	m_cpu_error_status = 0x00000400;
-	if (address & 1)
+	uint64_t mask = 0x00000000000000ffULL;
-		m_cpu_error_status |= 0x000000f0;
+	for (uint32_t bit = 0; bit < 8; bit++)
-	else
+	{
-		m_cpu_error_status |= 0x0000000f;
+		if (mem_mask & mask)
+		{
+			m_cpu_error_status |= (1 << bit);
+		}
+		mask <<= 8;
+	}
 }
 
 uint32_t sgi_mc_device::dma_translate(uint32_t address)

src/mame/machine/sgi.h

@@ -28,11 +28,12 @@ public:
 	sgi_mc_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
 
 	auto int_dma_done_cb() { return m_int_dma_done_cb.bind(); }
+	auto eisa_present() { return m_eisa_present.bind(); }
 
 	DECLARE_READ32_MEMBER(read);
 	DECLARE_WRITE32_MEMBER(write);
 
-	void set_cpu_buserr(uint32_t address);
+	void set_cpu_buserr(uint32_t address, uint64_t mem_mask);
 	uint32_t get_mem_config(int channel) const { return m_mem_config[channel]; }
 
 protected:
@@ -69,6 +70,7 @@ private:
 	required_device<eeprom_serial_93cxx_device> m_eeprom;
 
 	devcb_write_line m_int_dma_done_cb;
+	devcb_write_line m_eisa_present;
 
 	address_space *m_space;