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(nw) Onyx c8002 : added devices
This commit is contained in:
Robbbert
parent
e7d2693098
commit
ac6c08eb74
@ -6,8 +6,6 @@ Onyx C8002
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2013-08-18 Skeleton Driver
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Copied from p8k.c
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The C8002 is one of the earliest minicomputers to use Unix as an operating system.
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The system consists of a main CPU (Z8002), and a slave CPU for Mass Storage control (Z80)
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@ -21,15 +19,29 @@ The Z8002 board contains a 16 MHz crystal; 3x Z80CTC; 5x Z80SIO/0; 3x Z80PIO; 2
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The system can handle 8 RS232 terminals, 7 hard drives, a tape cartridge drive, parallel i/o,
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and be connected to a RS422 network.
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Status:
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- Main screen prints an error with CTC (because there's no clock into it atm)
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- Subcpu screen (after a while) prints various statuses then waits for the fdc to respond
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To Do:
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- Hook up daisy chains (see p8k.cpp for how to hook up a 16-bit chain)
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(keyboard input depends on interrupts)
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- Remaining devices
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- Whatever hooks up to the devices
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- Eventually we'll need software
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- Manuals / schematics would be nice
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*************************************************************************************************/
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#include "emu.h"
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#include "cpu/z80/z80.h"
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#include "cpu/z8000/z8000.h"
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#include "machine/clock.h"
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#include "bus/rs232/rs232.h"
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//#include "cpu/z80/z80daisy.h"
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//#include "machine/z80ctc.h"
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//#include "machine/z80pio.h"
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//#include "machine/z80sio.h"
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#include "machine/z80ctc.h"
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#include "machine/z80pio.h"
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#include "machine/z80sio.h"
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//#include "machine/z80dma.h"
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#include "machine/terminal.h"
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@ -39,30 +51,106 @@ public:
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onyx_state(const machine_config &mconfig, device_type type, const char *tag)
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: driver_device(mconfig, type, tag)
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, m_maincpu(*this, "maincpu")
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, m_terminal(*this, "terminal")
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, m_ctc1(*this, "ctc1")
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, m_ctc2(*this, "ctc2")
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, m_ctc3(*this, "ctc3")
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, m_pio1(*this, "pio1")
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, m_pio2(*this, "pio2")
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, m_sio1(*this, "sio1")
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, m_sio2(*this, "sio2")
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, m_sio3(*this, "sio3")
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, m_sio4(*this, "sio4")
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, m_sio5(*this, "sio5")
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{ }
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DECLARE_MACHINE_RESET(c8002);
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void kbd_put(u8 data);
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DECLARE_READ8_MEMBER(portff05_r);
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DECLARE_READ8_MEMBER(io_r);
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DECLARE_WRITE8_MEMBER(io_w);
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private:
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uint8_t m_term_data;
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required_device<cpu_device> m_maincpu;
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required_device<generic_terminal_device> m_terminal;
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required_device<z80ctc_device> m_ctc1;
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required_device<z80ctc_device> m_ctc2;
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required_device<z80ctc_device> m_ctc3;
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required_device<z80pio_device> m_pio1;
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required_device<z80pio_device> m_pio2;
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required_device<z80sio_device> m_sio1;
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required_device<z80sio_device> m_sio2;
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required_device<z80sio_device> m_sio3;
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required_device<z80sio_device> m_sio4;
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required_device<z80sio_device> m_sio5;
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};
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READ8_MEMBER( onyx_state::portff05_r )
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READ8_MEMBER( onyx_state::io_r )
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{
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//return m_term_data;
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return 4;
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offset >>= 1;
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switch (offset >> 2)
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{
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case 0x00:
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return m_sio1->cd_ba_r(space, offset & 3);
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case 0x01:
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return m_sio2->cd_ba_r(space, offset & 3);
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case 0x02:
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return m_sio3->cd_ba_r(space, offset & 3);
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case 0x03:
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return m_sio4->cd_ba_r(space, offset & 3);
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case 0x04:
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return m_sio5->cd_ba_r(space, offset & 3);
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case 0x06:
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return m_ctc1->read(space, offset & 3);
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case 0x07:
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return m_ctc2->read(space, offset & 3);
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case 0x08:
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return m_ctc3->read(space, offset & 3);
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case 0x0a:
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return m_pio1->read(space, offset & 3);
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case 0x0b:
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return m_pio2->read(space, offset & 3);
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default:
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return 0;
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}
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}
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void onyx_state::kbd_put(u8 data)
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WRITE8_MEMBER( onyx_state::io_w )
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{
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m_term_data = data;
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offset >>= 1;
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switch (offset >> 2)
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{
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case 0x00: // ff00-ff07
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m_sio1->cd_ba_w(space, offset & 3, data);
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break;
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case 0x01: // ff08-ff0f
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m_sio2->cd_ba_w(space, offset & 3, data);
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break;
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case 0x02: // ff10-ff17
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m_sio3->cd_ba_w(space, offset & 3, data);
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break;
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case 0x03: // ff18-ff1f
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m_sio4->cd_ba_w(space, offset & 3, data);
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break;
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case 0x04: // ff20-ff27
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m_sio5->cd_ba_w(space, offset & 3, data);
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break;
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case 0x06: // ff30-ff37
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m_ctc1->write(space, offset & 3, data);
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break;
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case 0x07: // ff38-ff3f
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m_ctc2->write(space, offset & 3, data);
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break;
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case 0x08: // ff40-ff47
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m_ctc3->write(space, offset & 3, data);
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break;
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case 0x0a: // ff50-ff57
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m_pio1->write(space, offset & 3, data);
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break;
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case 0x0b: // ff58-ff5f
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m_pio2->write(space, offset & 3, data);
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break;
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default:
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break;
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}
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}
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@ -88,8 +176,7 @@ ADDRESS_MAP_END
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//ADDRESS_MAP_END
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static ADDRESS_MAP_START(c8002_io, AS_IO, 8, onyx_state)
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AM_RANGE(0xff00, 0xff01) AM_DEVWRITE("terminal", generic_terminal_device, write)
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AM_RANGE(0xff04, 0xff05) AM_READ(portff05_r)
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AM_RANGE(0xff00, 0xff5f) AM_READWRITE(io_r, io_w)
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ADDRESS_MAP_END
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static ADDRESS_MAP_START(submem, AS_PROGRAM, 8, onyx_state)
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@ -99,6 +186,9 @@ ADDRESS_MAP_END
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static ADDRESS_MAP_START(subio, AS_IO, 8, onyx_state)
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ADDRESS_MAP_GLOBAL_MASK(0xff)
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AM_RANGE(0x00, 0x03) AM_DEVREADWRITE("pio1s", z80pio_device, read, write)
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AM_RANGE(0x04, 0x04) AM_READNOP // disk status?
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AM_RANGE(0x0c, 0x0f) AM_DEVREADWRITE("sio1s", z80sio_device, cd_ba_r, cd_ba_w )
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ADDRESS_MAP_END
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@ -122,18 +212,48 @@ static MACHINE_CONFIG_START( c8002 )
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MCFG_CPU_IO_MAP(subio)
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MCFG_MACHINE_RESET_OVERRIDE(onyx_state, c8002)
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/* peripheral hardware */
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//MCFG_DEVICE_ADD("z80ctc_0", Z80CTC, XTAL_4MHz)
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//MCFG_DEVICE_ADD("z80ctc_1", Z80CTC, XTAL_4MHz)
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//MCFG_DEVICE_ADD("z80sio_0", Z80SIO, 9600)
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//MCFG_DEVICE_ADD("z80sio_1", Z80SIO, 9600)
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//MCFG_DEVICE_ADD("z80pio_0", Z80CTC, XTAL_4MHz)
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//MCFG_DEVICE_ADD("z80pio_1", Z80CTC, XTAL_4MHz)
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//MCFG_DEVICE_ADD("z80pio_2", Z80CTC, XTAL_4MHz)
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MCFG_DEVICE_ADD("sio1_clock", CLOCK, 307200)
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MCFG_CLOCK_SIGNAL_HANDLER(DEVWRITELINE("sio1", z80sio_device, rxca_w))
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MCFG_DEVCB_CHAIN_OUTPUT(DEVWRITELINE("sio1" ,z80sio_device, txca_w))
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/* video hardware */
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MCFG_DEVICE_ADD("terminal", GENERIC_TERMINAL, 0)
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MCFG_GENERIC_TERMINAL_KEYBOARD_CB(PUT(onyx_state, kbd_put))
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/* peripheral hardware */
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MCFG_DEVICE_ADD("pio1", Z80PIO, XTAL_16MHz/4)
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//MCFG_Z80PIO_OUT_INT_CB(INPUTLINE("maincpu", INPUT_LINE_IRQ0))
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MCFG_DEVICE_ADD("pio2", Z80PIO, XTAL_16MHz/4)
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//MCFG_Z80PIO_OUT_INT_CB(INPUTLINE("maincpu", INPUT_LINE_IRQ0))
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MCFG_DEVICE_ADD("ctc1", Z80CTC, XTAL_16MHz /4)
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MCFG_DEVICE_ADD("ctc2", Z80CTC, XTAL_16MHz /4)
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MCFG_DEVICE_ADD("ctc3", Z80CTC, XTAL_16MHz /4)
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MCFG_DEVICE_ADD("sio1", Z80SIO, XTAL_16MHz /4)
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MCFG_Z80SIO_OUT_TXDA_CB(DEVWRITELINE("rs232", rs232_port_device, write_txd))
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MCFG_Z80SIO_OUT_DTRA_CB(DEVWRITELINE("rs232", rs232_port_device, write_dtr))
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MCFG_Z80SIO_OUT_RTSA_CB(DEVWRITELINE("rs232", rs232_port_device, write_rts))
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MCFG_DEVICE_ADD("sio2", Z80SIO, XTAL_16MHz /4)
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MCFG_DEVICE_ADD("sio3", Z80SIO, XTAL_16MHz /4)
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MCFG_DEVICE_ADD("sio4", Z80SIO, XTAL_16MHz /4)
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MCFG_DEVICE_ADD("sio5", Z80SIO, XTAL_16MHz /4)
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MCFG_RS232_PORT_ADD("rs232", default_rs232_devices, "terminal")
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MCFG_RS232_RXD_HANDLER(DEVWRITELINE("sio1", z80sio_device, rxa_w))
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MCFG_RS232_DCD_HANDLER(DEVWRITELINE("sio1", z80sio_device, dcda_w))
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MCFG_RS232_CTS_HANDLER(DEVWRITELINE("sio1", z80sio_device, ctsa_w))
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MCFG_DEVICE_ADD("pio1s", Z80PIO, XTAL_16MHz/4)
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//MCFG_Z80PIO_OUT_INT_CB(INPUTLINE("subcpu", INPUT_LINE_IRQ0))
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MCFG_DEVICE_ADD("sio1s_clock", CLOCK, 614400)
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MCFG_CLOCK_SIGNAL_HANDLER(DEVWRITELINE("sio1s", z80sio_device, rxtxcb_w))
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//MCFG_DEVCB_CHAIN_OUTPUT(DEVWRITELINE("sio1s" ,z80sio_device, txca_w))
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MCFG_DEVICE_ADD("sio1s", Z80SIO, XTAL_16MHz /4)
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MCFG_Z80SIO_OUT_TXDB_CB(DEVWRITELINE("rs232s", rs232_port_device, write_txd))
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MCFG_Z80SIO_OUT_DTRB_CB(DEVWRITELINE("rs232s", rs232_port_device, write_dtr))
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MCFG_Z80SIO_OUT_RTSB_CB(DEVWRITELINE("rs232s", rs232_port_device, write_rts))
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MCFG_RS232_PORT_ADD("rs232s", default_rs232_devices, "terminal")
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MCFG_RS232_RXD_HANDLER(DEVWRITELINE("sio1s", z80sio_device, rxb_w))
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MCFG_RS232_DCD_HANDLER(DEVWRITELINE("sio1s", z80sio_device, dcdb_w))
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MCFG_RS232_CTS_HANDLER(DEVWRITELINE("sio1s", z80sio_device, ctsb_w))
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MACHINE_CONFIG_END
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/* ROM definition */
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