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namco54: longer irq to fix bosco shot sound regression (nw)

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This commit is contained in:
hap 2020-06-11 15:38:15 +02:00
parent d3a7b0ddc1
commit acf77a4374
7 changed files with 9 additions and 26 deletions
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4
src/devices/cpu/mb88xx/mb88xx.cpp
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@ -369,12 +369,12 @@ int mb88_cpu_device::pla( int inA, int inB )
void mb88_cpu_device::execute_set_input(int inputnum, int state)
{
/* on rising edge trigger interrupt */
if ( (m_pio & 0x04) && !m_nf && state == ASSERT_LINE )
if ( (m_pio & 0x04) && !m_nf && state != CLEAR_LINE )
{
m_pending_interrupt |= INT_CAUSE_EXTERNAL;
}
m_nf = state == ASSERT_LINE;
m_nf = state != CLEAR_LINE;
}
void mb88_cpu_device::update_pio_enable( uint8_t newpio )

12
src/mame/audio/namco52.cpp
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@ -114,17 +114,9 @@ void namco_52xx_device::write(uint8_t data)
{
machine().scheduler().synchronize(timer_expired_delegate(FUNC(namco_52xx_device::latch_callback),this), data);
// TODO: should use chip_select line for this
m_cpu->set_input_line(0, ASSERT_LINE);
// The execution time of one instruction is ~4us, so we must make sure to
// give the cpu time to poll the /IRQ input before we clear it.
// The input clock to the 06XX interface chip is 64H, that is
// 18432000/6/64 = 48kHz, so it makes sense for the irq line to be
// asserted for one clock cycle ~= 21us.
/* the 52xx uses TSTI to check for an interrupt; it also may be handling
a timer interrupt, so we need to ensure the IRQ line is held long enough */
machine().scheduler().timer_set(attotime::from_usec(5*21), timer_expired_delegate(FUNC(namco_52xx_device::irq_clear),this), 0);
machine().scheduler().timer_set(attotime::from_usec(100), timer_expired_delegate(FUNC(namco_52xx_device::irq_clear),this), 0);
}

9
src/mame/audio/namco54.cpp
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@ -99,14 +99,9 @@ void namco_54xx_device::write(uint8_t data)
{
machine().scheduler().synchronize(timer_expired_delegate(FUNC(namco_54xx_device::latch_callback),this), data);
// TODO: should use chip_select line for this
m_cpu->set_input_line(0, ASSERT_LINE);
// The execution time of one instruction is ~4us, so we must make sure to
// give the cpu time to poll the /IRQ input before we clear it.
// The input clock to the 06XX interface chip is 64H, that is
// 18432000/6/64 = 48kHz, so it makes sense for the irq line to be
// asserted for one clock cycle ~= 21us.
machine().scheduler().timer_set(attotime::from_usec(21), timer_expired_delegate(FUNC(namco_54xx_device::irq_clear),this), 0);
machine().scheduler().timer_set(attotime::from_usec(100), timer_expired_delegate(FUNC(namco_54xx_device::irq_clear),this), 0);
}

6
src/mame/drivers/galaga.cpp
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@ -1753,8 +1753,7 @@ void galaga_state::galagab(machine_config &config)
config.device_remove("06xx");
config.device_remove("54xx");
ls259_device* misclatch = reinterpret_cast<ls259_device*>(config.device("misclatch"));
// galaga has the custom chips on this line, so just set the resets this
// board has
// galaga has the custom chips on this line, so just set the resets this board has
misclatch->q_out_cb<3>().set_inputline("sub", INPUT_LINE_RESET).invert();
misclatch->q_out_cb<3>().append_inputline("sub2", INPUT_LINE_RESET).invert();
misclatch->q_out_cb<3>().append_inputline("sub3", INPUT_LINE_RESET).invert();
@ -1866,8 +1865,7 @@ void battles_state::battles(machine_config &config)
config.device_remove("54xx");
config.device_remove("06xx");
ls259_device* misclatch = reinterpret_cast<ls259_device*>(config.device("misclatch"));
// xevious has the custom chips on this line, so just set the resets
// this board has
// xevious has the custom chips on this line, so just set the resets this board has
misclatch->q_out_cb<3>().set_inputline("sub", INPUT_LINE_RESET).invert();
misclatch->q_out_cb<3>().append_inputline("sub2", INPUT_LINE_RESET).invert();

1
src/mame/drivers/polepos.cpp
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@ -860,7 +860,6 @@ void polepos_state::polepos(machine_config &config)
m_subcpu2->set_addrmap(AS_PROGRAM, &polepos_state::z8002_map_2);
namco_51xx_device &n51xx(NAMCO_51XX(config, "51xx", MASTER_CLOCK/8/2)); /* 1.536 MHz */
//n51xx.set_screen_tag(m_screen);
n51xx.input_callback<0>().set_ioport("DSWB").mask(0x0f);
n51xx.input_callback<1>().set_ioport("DSWB").rshift(4);
n51xx.input_callback<2>().set_ioport("IN0").mask(0x0f);

2
src/mame/machine/namco06.cpp
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@ -184,7 +184,7 @@ void namco_06xx_device::ctrl_w(uint8_t data)
m_control = data;
// The upper 3 control bits are the clock divider.
if ((m_control & 0xE0) == 0)
if ((m_control & 0xe0) == 0)
{
m_nmi_timer->adjust(attotime::never);
set_nmi(CLEAR_LINE);

1
src/mame/machine/namco06.h
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@ -42,7 +42,6 @@ private:
bool m_rw_stretch;
bool m_rw_change;
required_device<cpu_device> m_nmicpu;
devcb_write_line::array<4> m_chipsel;