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mips3: Cleanup TX4925 implementation. (nw)

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This commit is contained in:
Ted Green 2017-11-06 15:58:45 -07:00
parent fe74d5c47b
commit adb968a68a
2 changed files with 9 additions and 134 deletions
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80
src/devices/cpu/mips/mips3.cpp
View File

@ -192,7 +192,10 @@ mips3_device::mips3_device(const machine_config &mconfig, device_type type, cons
memset(m_hotspot, 0, sizeof(m_hotspot));
// configure the virtual TLB
set_vtlb_fixed_entries(2 * m_tlbentries + 2);
if (m_flavor == MIPS3_TYPE_TX4925)
set_vtlb_fixed_entries(2 * m_tlbentries + 3);
else
set_vtlb_fixed_entries(2 * m_tlbentries + 2);
}
device_memory_interface::space_config_vector mips3_device::memory_space_config() const
@ -940,11 +943,16 @@ void mips3_device::device_reset()
entry->entry_lo[1] = 0xfffffff8;
vtlb_load(2 * tlbindex + 0, 0, 0, 0);
vtlb_load(2 * tlbindex + 1, 0, 0, 0);
if (m_flavor == MIPS3_TYPE_TX4925)
vtlb_load(2 * tlbindex + 2, 0, 0, 0);
}
/* load the fixed TLB range */
vtlb_load(2 * m_tlbentries + 0, (0xa0000000 - 0x80000000) >> MIPS3_MIN_PAGE_SHIFT, 0x80000000, 0x00000000 | VTLB_READ_ALLOWED | VTLB_WRITE_ALLOWED | VTLB_FETCH_ALLOWED | VTLB_FLAG_VALID);
vtlb_load(2 * m_tlbentries + 1, (0xc0000000 - 0xa0000000) >> MIPS3_MIN_PAGE_SHIFT, 0xa0000000, 0x00000000 | VTLB_READ_ALLOWED | VTLB_WRITE_ALLOWED | VTLB_FETCH_ALLOWED | VTLB_FLAG_VALID);
// TX4925 on-board peripherals pass-through
if (m_flavor == MIPS3_TYPE_TX4925)
vtlb_load(2 * m_tlbentries + 2, (0xff200000 - 0xff1f0000) >> MIPS3_MIN_PAGE_SHIFT, 0xff1f0000, 0xff1f0000 | VTLB_READ_ALLOWED | VTLB_WRITE_ALLOWED | VTLB_FETCH_ALLOWED | VTLB_FLAG_VALID);
m_core->mode = (MODE_KERNEL << 1) | 0;
m_cache_dirty = true;
@ -985,12 +993,6 @@ offs_t mips3_device::disasm_disassemble(std::ostream &stream, offs_t pc, const u
inline bool mips3_device::RBYTE(offs_t address, uint32_t *result)
{
if ((m_flavor == MIPS3_TYPE_TX4925) && ((address & 0xffff0000) == 0xff1f0000))
{
*result = (*m_memory.read_byte)(*m_program, address);
return true;
}
const uint32_t tlbval = vtlb_table()[address >> 12];
if (tlbval & VTLB_READ_ALLOWED)
{
@ -1024,12 +1026,6 @@ inline bool mips3_device::RBYTE(offs_t address, uint32_t *result)
inline bool mips3_device::RHALF(offs_t address, uint32_t *result)
{
if ((m_flavor == MIPS3_TYPE_TX4925) && ((address & 0xffff0000) == 0xff1f0000))
{
*result = (*m_memory.read_word)(*m_program, address);
return true;
}
const uint32_t tlbval = vtlb_table()[address >> 12];
if (tlbval & VTLB_READ_ALLOWED)
{
@ -1063,12 +1059,6 @@ inline bool mips3_device::RHALF(offs_t address, uint32_t *result)
inline bool mips3_device::RWORD(offs_t address, uint32_t *result)
{
if ((m_flavor == MIPS3_TYPE_TX4925) && ((address & 0xffff0000) == 0xff1f0000))
{
*result = (*m_memory.read_dword)(*m_program, address);
return true;
}
const uint32_t tlbval = vtlb_table()[address >> 12];
if (tlbval & VTLB_READ_ALLOWED)
{
@ -1102,12 +1092,6 @@ inline bool mips3_device::RWORD(offs_t address, uint32_t *result)
inline bool mips3_device::RWORD_MASKED(offs_t address, uint32_t *result, uint32_t mem_mask)
{
if ((m_flavor == MIPS3_TYPE_TX4925) && ((address & 0xffff0000) == 0xff1f0000))
{
*result = (*m_memory.read_dword_masked)(*m_program, address, mem_mask);
return true;
}
const uint32_t tlbval = vtlb_table()[address >> 12];
if (tlbval & VTLB_READ_ALLOWED)
{
@ -1131,11 +1115,6 @@ inline bool mips3_device::RWORD_MASKED(offs_t address, uint32_t *result, uint32_
inline bool mips3_device::RDOUBLE(offs_t address, uint64_t *result)
{
if ((m_flavor == MIPS3_TYPE_TX4925) && ((address & 0xffff0000) == 0xff1f0000))
{
*result = (*m_memory.read_qword)(*m_program, address);
return true;
}
const uint32_t tlbval = vtlb_table()[address >> 12];
if (tlbval & VTLB_READ_ALLOWED)
{
@ -1159,12 +1138,6 @@ inline bool mips3_device::RDOUBLE(offs_t address, uint64_t *result)
inline bool mips3_device::RDOUBLE_MASKED(offs_t address, uint64_t *result, uint64_t mem_mask)
{
if ((m_flavor == MIPS3_TYPE_TX4925) && ((address & 0xffff0000) == 0xff1f0000))
{
*result = (*m_memory.read_qword_masked)(*m_program, address, mem_mask);
return true;
}
const uint32_t tlbval = vtlb_table()[address >> 12];
if (tlbval & VTLB_READ_ALLOWED)
{
@ -1188,12 +1161,6 @@ inline bool mips3_device::RDOUBLE_MASKED(offs_t address, uint64_t *result, uint6
inline void mips3_device::WBYTE(offs_t address, uint8_t data)
{
if ((m_flavor == MIPS3_TYPE_TX4925) && ((address & 0xffff0000) == 0xff1f0000))
{
(*m_memory.write_byte)(*m_program, address, data);
return;
}
const uint32_t tlbval = vtlb_table()[address >> 12];
if (tlbval & VTLB_WRITE_ALLOWED)
{
@ -1228,11 +1195,6 @@ inline void mips3_device::WBYTE(offs_t address, uint8_t data)
inline void mips3_device::WHALF(offs_t address, uint16_t data)
{
if ((m_flavor == MIPS3_TYPE_TX4925) && ((address & 0xffff0000) == 0xff1f0000))
{
(*m_memory.write_word)(*m_program, address, data);
return;
}
const uint32_t tlbval = vtlb_table()[address >> 12];
if (tlbval & VTLB_WRITE_ALLOWED)
{
@ -1267,12 +1229,6 @@ inline void mips3_device::WHALF(offs_t address, uint16_t data)
inline void mips3_device::WWORD(offs_t address, uint32_t data)
{
if ((m_flavor == MIPS3_TYPE_TX4925) && ((address & 0xffff0000) == 0xff1f0000))
{
(*m_memory.write_dword)(*m_program, address, data);
return;
}
const uint32_t tlbval = vtlb_table()[address >> 12];
if (tlbval & VTLB_WRITE_ALLOWED)
{
@ -1307,12 +1263,6 @@ inline void mips3_device::WWORD(offs_t address, uint32_t data)
inline void mips3_device::WWORD_MASKED(offs_t address, uint32_t data, uint32_t mem_mask)
{
if ((m_flavor == MIPS3_TYPE_TX4925) && ((address & 0xffff0000) == 0xff1f0000))
{
(*m_memory.write_dword_masked)(*m_program, address, data, mem_mask);
return;
}
const uint32_t tlbval = vtlb_table()[address >> 12];
if (tlbval & VTLB_WRITE_ALLOWED)
{
@ -1337,12 +1287,6 @@ inline void mips3_device::WWORD_MASKED(offs_t address, uint32_t data, uint32_t m
inline void mips3_device::WDOUBLE(offs_t address, uint64_t data)
{
if ((m_flavor == MIPS3_TYPE_TX4925) && ((address & 0xffff0000) == 0xff1f0000))
{
(*m_memory.write_qword)(*m_program, address, data);
return;
}
const uint32_t tlbval = vtlb_table()[address >> 12];
if (tlbval & VTLB_WRITE_ALLOWED)
{
@ -1367,12 +1311,6 @@ inline void mips3_device::WDOUBLE(offs_t address, uint64_t data)
inline void mips3_device::WDOUBLE_MASKED(offs_t address, uint64_t data, uint64_t mem_mask)
{
if ((m_flavor == MIPS3_TYPE_TX4925) && ((address & 0xffff0000) == 0xff1f0000))
{
(*m_memory.write_qword_masked)(*m_program, address, data, mem_mask);
return;
}
const uint32_t tlbval = vtlb_table()[address >> 12];
if (tlbval & VTLB_WRITE_ALLOWED)
{

63
src/devices/cpu/mips/mips3drc.cpp
View File

@ -836,69 +836,6 @@ void mips3_device::static_generate_memory_accessor(int mode, int size, int iswri
UML_LABEL(block, addrok); // addrok:
}
/* TX4925 on-board peripherals pass-through */
if (m_flavor == MIPS3_TYPE_TX4925)
{
int addrok;
UML_AND(block, I3, I0, 0xffff0000); // and i3, i0, 0xffff0000
UML_CMP(block, I3, 0xff1f0000); // cmp i3, 0xff1f0000
UML_JMPc(block, COND_NZ, addrok = label++);
switch (size)
{
case 1:
if (iswrite)
UML_WRITE(block, I0, I1, SIZE_BYTE, SPACE_PROGRAM); // write i0,i1,program_byte
else
UML_READ(block, I0, I0, SIZE_BYTE, SPACE_PROGRAM); // read i0,i0,program_byte
break;
case 2:
if (iswrite)
UML_WRITE(block, I0, I1, SIZE_WORD, SPACE_PROGRAM); // write i0,i1,program_word
else
UML_READ(block, I0, I0, SIZE_WORD, SPACE_PROGRAM); // read i0,i0,program_word
break;
case 4:
if (iswrite)
{
if (!ismasked)
UML_WRITE(block, I0, I1, SIZE_DWORD, SPACE_PROGRAM); // write i0,i1,program_dword
else
UML_WRITEM(block, I0, I1, I2, SIZE_DWORD, SPACE_PROGRAM); // writem i0,i1,i2,program_dword
}
else
{
if (!ismasked)
UML_READ(block, I0, I0, SIZE_DWORD, SPACE_PROGRAM); // read i0,i0,program_dword
else
UML_READM(block, I0, I0, I2, SIZE_DWORD, SPACE_PROGRAM); // readm i0,i0,i2,program_dword
}
break;
case 8:
if (iswrite)
{
if (!ismasked)
UML_DWRITE(block, I0, I1, SIZE_QWORD, SPACE_PROGRAM); // dwrite i0,i1,program_qword
else
UML_DWRITEM(block, I0, I1, I2, SIZE_QWORD, SPACE_PROGRAM); // dwritem i0,i1,i2,program_qword
}
else
{
if (!ismasked)
UML_DREAD(block, I0, I0, SIZE_QWORD, SPACE_PROGRAM); // dread i0,i0,program_qword
else
UML_DREADM(block, I0, I0, I2, SIZE_QWORD, SPACE_PROGRAM); // dreadm i0,i0,i2,program_qword
}
break;
}
UML_RET(block);
UML_LABEL(block, addrok);
}
/* general case: assume paging and perform a translation */
UML_SHR(block, I3, I0, 12); // shr i3,i0,12
UML_LOAD(block, I3, (void *)vtlb_table(), I3, SIZE_DWORD, SCALE_x4);// load i3,[vtlb_table],i3,dword