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misc/chance32.cpp: cleanups and QA
This commit is contained in:
angelosa
parent
829548f47a
commit
adeb48f06b
@ -1,12 +1,10 @@
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// license:BSD-3-Clause
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// copyright-holders:Angelo Salese
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// license: BSD-3-Clause
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// copyright-holders: Angelo Salese
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// thanks-to: Tomasz Slanina, Sarah Walker
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/***************************************************************************
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Acorn RiscPC line of computers
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preliminary driver by Angelo Salese,
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based on work by Tomasz Slanina and Sarah Walker
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TODO:
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- IOMD currently hardwired with ARM7500FE flavour for all machines, needs information about
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which uses what;
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@ -4,8 +4,6 @@
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ACT Apricot FP
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preliminary driver by Angelo Salese
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11/09/2011 - modernised. The portable doesn't seem to have
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scroll registers, and it sets the palette to black.
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@ -14,10 +14,10 @@ I/O: 2x 8255, 4x 8-dip banks, 1x single dip switch (at position 11m)
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OSC: 20MHz
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Notes:
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- Loosely based off rmhaihai.cpp.
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Changes needed for merging both implementations seems too trivial to warrant a
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- Loosely based off alba/rmhaihai.cpp.
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Changes needed for merging both implementations seems too non-trivial to warrant a
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driver merge, basically just the video HW, the CRTC (448x224 clocked at 20 MHz?)
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and a few I/O bits looks very similar, the odd screen size is also a thing in srmp2.cpp
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and a few I/O bits looks similar, the odd screen size is also a thing in srmp2.cpp
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and probably other Seta HWs.
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- CPU seems a bit too slow when deciding about what tile to discard,
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it also takes a bit too much to sync when a player takes a tile from the pond in
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@ -1,6 +1,6 @@
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// license:BSD-3-Clause
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// copyright-holders:Angelo Salese, Palindrome, FraSher, Roberto Fresca
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/***********************************************************************************************************************************************
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/**************************************************************************************************
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Driver: aristmk4
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@ -11,7 +11,7 @@
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original 86lions.c driver by Chris Hardy, Angelo Salese & Roberto Fresca
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***************** INITIALISATION *********************************************************************
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***************** INITIALISATION **************************************************************
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Method 1 :
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* Key in with the Jackpot Key followed by the Audit Key (F1 then F2 keys)
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@ -76,7 +76,7 @@
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Note: cgold2, fhunter and fhuntera must have DIP labeled "5201-5" switch to on at all times.
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This allows setup procedure to complete properly and game to play (if disabled, the games don't accept inputs).
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**********************************************************************************************************
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***************************************************************************************************
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Technical Notes:
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@ -103,7 +103,7 @@
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The AY8910 named ay2 has writes to lamps and the light tower on Port A and B. these are implemented via the layout
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**********************************************************************************************************
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***************************************************************************************************
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Updates....
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@ -216,7 +216,7 @@
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Renamed nodump program ROM in clkwise as it had the wrong EPROM number.
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*************************************************************************************************************
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***************************************************************************************************
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When the games first power on (or when reset), they will display a TILT message on the screen.
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This doesn't affect gameplay, and if there are no pending errors the game should coin up and/or play immediately.
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@ -295,7 +295,7 @@
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12. Hook up native/Jubilee MK4 games which have larger capacity ROMs (no native MK4 games dumped yet - all are MK2.5 format).
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***************** POKER GAMES ************************************************************************
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***************** POKER GAMES *****************************************************************
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Wild One & Golden Poker have a problem where the second branch condition is always true, see assembler below for
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example of Wild One.
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@ -318,7 +318,7 @@
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and SY6845E subvariants, so it all lies to those. -AS
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***********************************************************************************************************************************************/
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**************************************************************************************************/
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#define MAIN_CLOCK 12_MHz_XTAL
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@ -1,22 +1,27 @@
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// license:BSD-3-Clause
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// copyright-holders:David Haywood, Angelo Salese, Roberto Fresca
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/*********************************************************
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/**************************************************************************************************
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Chance 32
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Chance 32
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PAL System Co, Ltd.
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Osaka, Japan.
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PAL System Co, Ltd.
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Osaka, Japan.
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Driver by David Haywood, Angelo Salese & Roberto Fresca.
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TODO:
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- fill PCB details below;
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- some blanks in I/O section;
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- DIPs;
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- Need to flip everything in video/gfx code, is it possible to untangle?
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===================================================================================================
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1x HD46505SP / HD6845SP
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1x Z84C0008PEC
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XTAL: 12.000 Mhz
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*********************************************************/
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**************************************************************************************************/
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#include "emu.h"
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#include "cpu/z80/z80.h"
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@ -35,14 +40,13 @@ namespace {
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class chance32_state : public driver_device
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{
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public:
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chance32_state(const machine_config &mconfig, device_type type, const char *tag) :
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driver_device(mconfig, type, tag),
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m_fgram(*this, "fgram"),
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m_bgram(*this, "bgram"),
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m_maincpu(*this, "maincpu"),
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m_gfxdecode(*this, "gfxdecode"),
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m_lamps(*this, "lamp%u", 0U)
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{ }
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chance32_state(const machine_config &mconfig, device_type type, const char *tag)
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: driver_device(mconfig, type, tag)
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, m_maincpu(*this, "maincpu")
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, m_vram(*this, "vram%u", 0U)
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, m_gfxdecode(*this, "gfxdecode")
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, m_lamps(*this, "lamp%u", 0U)
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{ }
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void chance32(machine_config &config);
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@ -52,107 +56,88 @@ protected:
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virtual void video_start() override;
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private:
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void chance32_fgram_w(offs_t offset, uint8_t data)
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template <unsigned N> void vram_w(offs_t offset, uint8_t data)
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{
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m_fgram[offset] = data;
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m_fg_tilemap->mark_tile_dirty(offset / 2);
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m_vram[N][offset] = data;
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m_tilemap[N]->mark_tile_dirty(offset / 2);
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}
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void chance32_bgram_w(offs_t offset, uint8_t data)
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{
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m_bgram[offset] = data;
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m_bg_tilemap->mark_tile_dirty(offset / 2);
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}
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void key_matrix_w(uint8_t data);
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uint8_t key_matrix_r();
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void lamps_ff_w(uint8_t data);
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void mux_w(uint8_t data);
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void muxout_w(uint8_t data);
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uint8_t mux_r();
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template <unsigned N> TILE_GET_INFO_MEMBER(get_tile_info);
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uint32_t screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
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void main_map(address_map &map);
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void main_io(address_map &map);
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TILE_GET_INFO_MEMBER(get_fg_tile_info);
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TILE_GET_INFO_MEMBER(get_bg_tile_info);
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uint32_t screen_update_chance32(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
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void chance32_map(address_map &map);
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void chance32_portmap(address_map &map);
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tilemap_t *m_tilemap[2]{};
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tilemap_t *m_fg_tilemap = nullptr;
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tilemap_t *m_bg_tilemap = nullptr;
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uint8_t m_port_select = 0;
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required_shared_ptr<uint8_t> m_fgram;
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required_shared_ptr<uint8_t> m_bgram;
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uint8_t mux_data = 0;
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required_device<cpu_device> m_maincpu;
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required_shared_ptr_array<uint8_t, 2> m_vram;
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required_device<gfxdecode_device> m_gfxdecode;
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output_finder<13> m_lamps;
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};
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TILE_GET_INFO_MEMBER(chance32_state::get_fg_tile_info)
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template <unsigned N> TILE_GET_INFO_MEMBER(chance32_state::get_tile_info)
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{
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int code = (m_fgram[tile_index * 2 + 1] << 8) | m_fgram[tile_index * 2];
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int flip = (~code >> 12)&1;
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tileinfo.set(1,
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code & 0x0fff,
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code >> 13,
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TILE_FLIPYX(flip<<1)|flip);
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int code = (m_vram[N][tile_index * 2 + 1] << 8) | m_vram[N][tile_index * 2];
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int flip = (~code >> 12) & 1;
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tileinfo.set(
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N,
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code & 0x0fff,
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code >> 13,
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TILE_FLIPYX(flip << 1 | flip)
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);
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}
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TILE_GET_INFO_MEMBER(chance32_state::get_bg_tile_info)
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{
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int code = (m_bgram[tile_index * 2 +1] << 8) | m_bgram[tile_index * 2];
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int flip = (~code >> 12)&1;
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tileinfo.set(0,
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code & 0x0fff,
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code >> 13,
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TILE_FLIPYX(flip<<1|flip));
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}
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void chance32_state::video_start()
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{
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m_fg_tilemap = &machine().tilemap().create(*m_gfxdecode, tilemap_get_info_delegate(*this, FUNC(chance32_state::get_fg_tile_info)), TILEMAP_SCAN_ROWS, 16, 8, 35, 29);
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m_fg_tilemap->set_transparent_pen(0);
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m_tilemap[1] = &machine().tilemap().create(*m_gfxdecode, tilemap_get_info_delegate(*this, FUNC(chance32_state::get_tile_info<1>)), TILEMAP_SCAN_ROWS, 16, 8, 35, 29);
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m_tilemap[1]->set_transparent_pen(0);
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m_bg_tilemap = &machine().tilemap().create(*m_gfxdecode, tilemap_get_info_delegate(*this, FUNC(chance32_state::get_bg_tile_info)), TILEMAP_SCAN_ROWS, 16, 8, 35, 29);
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m_tilemap[0] = &machine().tilemap().create(*m_gfxdecode, tilemap_get_info_delegate(*this, FUNC(chance32_state::get_tile_info<0>)), TILEMAP_SCAN_ROWS, 16, 8, 35, 29);
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m_fg_tilemap->set_flip(TILE_FLIPX|TILE_FLIPY);
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m_bg_tilemap->set_flip(TILE_FLIPX|TILE_FLIPY);
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m_tilemap[0]->set_flip(TILE_FLIPX|TILE_FLIPY);
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m_tilemap[1]->set_flip(TILE_FLIPX|TILE_FLIPY);
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}
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uint32_t chance32_state::screen_update_chance32(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
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uint32_t chance32_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
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{
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m_bg_tilemap->draw(screen, bitmap, cliprect, 0, 0);
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m_fg_tilemap->draw(screen, bitmap, cliprect, 0, 0);
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m_tilemap[0]->draw(screen, bitmap, cliprect, 0, 0);
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m_tilemap[1]->draw(screen, bitmap, cliprect, 0, 0);
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return 0;
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}
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void chance32_state::mux_w(uint8_t data)
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void chance32_state::key_matrix_w(uint8_t data)
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{
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mux_data = data;
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m_port_select = data;
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}
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uint8_t chance32_state::mux_r()
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uint8_t chance32_state::key_matrix_r()
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{
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uint8_t res,i;
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const char *const muxnames[4] = { "IN0", "IN1", "IN2", "IN3" };
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const char *const portnames[4] = { "IN0", "IN1", "IN2", "IN3" };
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res = 0;
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for(i=0;i<4;i++)
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for(i = 0; i < 4; i++)
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{
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if(mux_data & 1 << i)
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res |= ioport(muxnames[i])->read();
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if(BIT(m_port_select, i))
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res |= ioport(portnames[i])->read();
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}
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return res;
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}
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void chance32_state::muxout_w(uint8_t data)
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{
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/* Muxed Lamps
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/* flip-flop lamps
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There are 2 groups of 7 output lines muxed in port 60h
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The first bit is the group/mux selector.
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@ -182,7 +167,10 @@ void chance32_state::muxout_w(uint8_t data)
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x--- ---- Bet lamp.
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*/
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if (data & 1) // bit 0 is the mux selector.
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void chance32_state::lamps_ff_w(uint8_t data)
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{
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// bit 0 selects between the two banks
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if (data & 1)
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{
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m_lamps[0] = BIT(data, 1); /* Lamp 0 - Small / Big */
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m_lamps[1] = BIT(data, 2); /* Lamp 1 - Big / Small */
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@ -197,7 +185,7 @@ void chance32_state::muxout_w(uint8_t data)
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else
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{
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// bit 1 is unknown...
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// TODO: what's bit 1 for?
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m_lamps[7] = BIT(data, 2); /* Lamp 7 - Fever! */
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m_lamps[8] = BIT(data, 3); /* Lamp 8 - Cancel */
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m_lamps[9] = BIT(data, 4); /* Lamp 9 - D-Up / Take */
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@ -210,89 +198,89 @@ void chance32_state::muxout_w(uint8_t data)
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}
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void chance32_state::chance32_map(address_map &map)
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void chance32_state::main_map(address_map &map)
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{
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map(0x0000, 0xcfff).rom();
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map(0xd800, 0xdfff).ram();
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map(0xe000, 0xefff).ram().w("palette", FUNC(palette_device::write8)).share("palette");
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map(0xf000, 0xf7ff).ram().w(FUNC(chance32_state::chance32_fgram_w)).share("fgram");
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map(0xf800, 0xffff).ram().w(FUNC(chance32_state::chance32_bgram_w)).share("bgram");
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map(0xf000, 0xf7ff).ram().w(FUNC(chance32_state::vram_w<1>)).share("vram1");
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map(0xf800, 0xffff).ram().w(FUNC(chance32_state::vram_w<0>)).share("vram0");
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}
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void chance32_state::chance32_portmap(address_map &map)
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void chance32_state::main_io(address_map &map)
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{
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map.global_mask(0xff);
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map(0x10, 0x10).nopw(); // writing bit3 constantly... watchdog?
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map(0x13, 0x13).w(FUNC(chance32_state::mux_w));
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map(0x13, 0x13).w(FUNC(chance32_state::key_matrix_w));
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map(0x20, 0x20).portr("DSW0");
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map(0x21, 0x21).portr("DSW1");
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map(0x22, 0x22).portr("DSW2");
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map(0x23, 0x23).portr("DSW3");
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map(0x24, 0x24).portr("DSW4");
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map(0x25, 0x25).r(FUNC(chance32_state::mux_r));
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map(0x25, 0x25).r(FUNC(chance32_state::key_matrix_r));
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map(0x26, 0x26).portr("UNK"); // vblank (other bits are checked for different reasons)
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map(0x30, 0x30).w("crtc", FUNC(mc6845_device::address_w));
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map(0x31, 0x31).w("crtc", FUNC(mc6845_device::register_w));
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map(0x50, 0x50).rw("oki", FUNC(okim6295_device::read), FUNC(okim6295_device::write));
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map(0x60, 0x60).w(FUNC(chance32_state::muxout_w));
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map(0x60, 0x60).w(FUNC(chance32_state::lamps_ff_w));
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}
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// TODO: diplocations are unconfirmed
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static INPUT_PORTS_START( chance32 )
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PORT_START("DSW0")
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PORT_DIPNAME( 0x01, 0x00, "DSW0" )
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PORT_DIPNAME( 0x01, 0x00, "DSW0" ) PORT_DIPLOCATION("SW0:1")
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PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x01, DEF_STR( On ) )
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PORT_DIPNAME( 0x02, 0x00, DEF_STR( Unknown ) )
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PORT_DIPNAME( 0x02, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW0:2")
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PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x02, DEF_STR( On ) )
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PORT_DIPNAME( 0x04, 0x00, "Auto Max Bet" )
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PORT_DIPNAME( 0x04, 0x00, "Auto Max Bet" ) PORT_DIPLOCATION("SW0:3")
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PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x04, DEF_STR( On ) )
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PORT_DIPNAME( 0x08, 0x00, DEF_STR( Flip_Screen ) )
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PORT_DIPNAME( 0x08, 0x00, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW0:4")
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PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x08, DEF_STR( On ) )
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PORT_DIPNAME( 0x10, 0x00, DEF_STR( Unknown ) )
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PORT_DIPNAME( 0x10, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW0:5")
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PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x10, DEF_STR( On ) )
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PORT_DIPNAME( 0x20, 0x00, DEF_STR( Unknown ) )
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PORT_DIPNAME( 0x20, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW0:6")
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PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x20, DEF_STR( On ) )
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PORT_DIPNAME( 0xc0, 0x00, "Maximum Bet" )
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PORT_DIPNAME( 0xc0, 0x00, "Maximum Bet" ) PORT_DIPLOCATION("SW0:7,8")
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PORT_DIPSETTING( 0x00, "10" )
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PORT_DIPSETTING( 0x40, "20" )
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PORT_DIPSETTING( 0x80, "30" )
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PORT_DIPSETTING( 0xc0, "50" )
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||||
PORT_START("DSW1")
|
||||
PORT_DIPNAME( 0x01, 0x00, "DSW1" )
|
||||
PORT_DIPNAME( 0x01, 0x00, "DSW1" ) PORT_DIPLOCATION("SW1:1")
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x01, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x02, 0x00, DEF_STR( Unknown ) )
|
||||
PORT_DIPNAME( 0x02, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW1:2")
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x02, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x04, 0x00, DEF_STR( Unknown ) )
|
||||
PORT_DIPNAME( 0x04, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW1:3")
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x04, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x08, 0x00, DEF_STR( Unknown ) )
|
||||
PORT_DIPNAME( 0x08, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW1:4")
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x08, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x10, 0x00, DEF_STR( Unknown ) )
|
||||
PORT_DIPNAME( 0x10, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW1:5")
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x10, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x20, 0x00, DEF_STR( Unknown ) )
|
||||
PORT_DIPNAME( 0x20, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW1:6")
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x20, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x40, 0x00, "Auto Hold" )
|
||||
PORT_DIPNAME( 0x40, 0x00, "Auto Hold" ) PORT_DIPLOCATION("SW1:7")
|
||||
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x80, 0x00, "Double-Up Type" )
|
||||
PORT_DIPNAME( 0x80, 0x00, "Double-Up Type" ) PORT_DIPLOCATION("SW1:8")
|
||||
PORT_DIPSETTING( 0x00, "Holds" )
|
||||
PORT_DIPSETTING( 0x80, "Big/Small" )
|
||||
|
||||
PORT_START("DSW2")
|
||||
PORT_DIPNAME( 0x07, 0x00, "Remote" )
|
||||
PORT_DIPNAME( 0x07, 0x00, "Remote" ) PORT_DIPLOCATION("SW2:1,2,3")
|
||||
PORT_DIPSETTING( 0x00, "5" )
|
||||
PORT_DIPSETTING( 0x01, "10" )
|
||||
PORT_DIPSETTING( 0x02, "20" )
|
||||
@ -301,7 +289,7 @@ static INPUT_PORTS_START( chance32 )
|
||||
PORT_DIPSETTING( 0x05, "50" )
|
||||
PORT_DIPSETTING( 0x06, "60" )
|
||||
PORT_DIPSETTING( 0x07, "100" )
|
||||
PORT_DIPNAME( 0x38, 0x00, "A-B Coinage Multiplier" )
|
||||
PORT_DIPNAME( 0x38, 0x00, "A-B Coinage Multiplier" ) PORT_DIPLOCATION("SW2:4,5,6")
|
||||
PORT_DIPSETTING( 0x00, "x1" )
|
||||
PORT_DIPSETTING( 0x08, "x2" )
|
||||
PORT_DIPSETTING( 0x10, "x4" )
|
||||
@ -310,66 +298,69 @@ static INPUT_PORTS_START( chance32 )
|
||||
PORT_DIPSETTING( 0x28, "x10" )
|
||||
PORT_DIPSETTING( 0x30, "x25" )
|
||||
PORT_DIPSETTING( 0x38, "x50" )
|
||||
PORT_DIPNAME( 0x40, 0x00, "DSW2" )
|
||||
PORT_DIPNAME( 0x40, 0x00, "DSW2" ) PORT_DIPLOCATION("SW2:7")
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x40, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x80, 0x00, DEF_STR( Unknown ) )
|
||||
PORT_DIPNAME( 0x80, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW2:8")
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x80, DEF_STR( On ) )
|
||||
|
||||
PORT_START("DSW3")
|
||||
PORT_DIPNAME( 0x01, 0x00, "DSW3" )
|
||||
PORT_DIPNAME( 0x01, 0x00, "DSW3" ) PORT_DIPLOCATION("SW3:1")
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x01, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x02, 0x00, DEF_STR( Unknown ) )
|
||||
PORT_DIPNAME( 0x02, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW3:2")
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x02, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x04, 0x00, DEF_STR( Unknown ) )
|
||||
PORT_DIPNAME( 0x04, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW3:3")
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x04, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x08, 0x00, DEF_STR( Unknown ) )
|
||||
PORT_DIPNAME( 0x08, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW3:4")
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x08, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x10, 0x00, DEF_STR( Unknown ) )
|
||||
PORT_DIPNAME( 0x10, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW3:5")
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x10, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x20, 0x00, DEF_STR( Unknown ) )
|
||||
PORT_DIPNAME( 0x20, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW3:6")
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x20, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x40, 0x00, DEF_STR( Unknown ) )
|
||||
PORT_DIPNAME( 0x40, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW3:7")
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x40, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x80, 0x00, DEF_STR( Unknown ) )
|
||||
PORT_DIPNAME( 0x80, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW3:8")
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x80, DEF_STR( On ) )
|
||||
|
||||
PORT_START("DSW4")
|
||||
PORT_DIPNAME( 0x01, 0x00, "DSW4" )
|
||||
PORT_DIPNAME( 0x01, 0x00, "DSW4" ) PORT_DIPLOCATION("SW4:1")
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x01, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x06, 0x00, "Bet Limit" )
|
||||
PORT_DIPNAME( 0x06, 0x00, "Bet Limit" ) PORT_DIPLOCATION("SW4:2,3")
|
||||
PORT_DIPSETTING( 0x00, "5000" )
|
||||
PORT_DIPSETTING( 0x02, "10000" )
|
||||
PORT_DIPSETTING( 0x04, "20000" )
|
||||
PORT_DIPSETTING( 0x06, "30000" )
|
||||
PORT_DIPNAME( 0x08, 0x00, DEF_STR( Unknown ) )
|
||||
PORT_DIPNAME( 0x08, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW4:4")
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x08, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x10, 0x00, DEF_STR( Unknown ) )
|
||||
PORT_DIPNAME( 0x10, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW4:5")
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x10, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x20, 0x00, DEF_STR( Unknown ) )
|
||||
PORT_DIPNAME( 0x20, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW4:6")
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x20, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x40, 0x00, DEF_STR( Unknown ) )
|
||||
PORT_DIPNAME( 0x40, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW4:7")
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x40, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x80, 0x00, DEF_STR( Unknown ) )
|
||||
PORT_DIPNAME( 0x80, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW4:8")
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x80, DEF_STR( On ) )
|
||||
|
||||
// TODO: sixth DIP bank?
|
||||
PORT_START("UNK")
|
||||
PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_CUSTOM ) PORT_VBLANK("screen") /* Otherwise is a 'Freeze' DIP switch */
|
||||
PORT_DIPNAME( 0x01, 0x00, "Freeze?" ) // checked at end of irq routine
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x01, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x02, 0x00, DEF_STR( Unknown ) )
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x02, DEF_STR( On ) )
|
||||
@ -428,8 +419,9 @@ static INPUT_PORTS_START( chance32 )
|
||||
PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_UNKNOWN )
|
||||
PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_MEMORY_RESET ) PORT_NAME("Reset")
|
||||
PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_COIN2 ) PORT_IMPULSE(3) PORT_NAME("Coin B")
|
||||
PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_SERVICE1 ) PORT_CODE(KEYCODE_8) PORT_NAME("Flip Screen 1") /* unknown purpose */
|
||||
PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_SERVICE1 ) PORT_CODE(KEYCODE_9) PORT_NAME("Flip Screen 2") /* unknown purpose */
|
||||
// both acts as a flip toggle, game intended for a cocktail cabinet?
|
||||
PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME("Flip Screen 1")
|
||||
PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME("Flip Screen 2")
|
||||
PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_GAMBLE_KEYIN)
|
||||
INPUT_PORTS_END
|
||||
|
||||
@ -439,9 +431,9 @@ static const gfx_layout tiles8x8_layout =
|
||||
16,8,
|
||||
RGN_FRAC(1,1),
|
||||
8,
|
||||
{ 0, 1, 2, 3,4,5,6,7 },
|
||||
{ 15*8, 14*8, 13*8, 12*8, 11*8, 10*8, 9*8, 8*8, 7*8, 6*8, 5*8, 4*8, 3*8, 2*8, 1*8, 0*8 },
|
||||
{ 7*128, 6*128, 5*128, 4*128, 3*128, 2*128, 1*128, 0*128 },
|
||||
{ STEP8(0, 1) },
|
||||
{ STEP16(15*8, -8) },
|
||||
{ STEP8(7*128, -128) },
|
||||
128*8
|
||||
};
|
||||
|
||||
@ -465,8 +457,8 @@ void chance32_state::chance32(machine_config &config)
|
||||
{
|
||||
/* basic machine hardware */
|
||||
Z80(config, m_maincpu, 12000000/2);
|
||||
m_maincpu->set_addrmap(AS_PROGRAM, &chance32_state::chance32_map);
|
||||
m_maincpu->set_addrmap(AS_IO, &chance32_state::chance32_portmap);
|
||||
m_maincpu->set_addrmap(AS_PROGRAM, &chance32_state::main_map);
|
||||
m_maincpu->set_addrmap(AS_IO, &chance32_state::main_io);
|
||||
m_maincpu->set_vblank_int("screen", FUNC(chance32_state::irq0_line_hold));
|
||||
|
||||
/* video hardware */
|
||||
@ -476,9 +468,10 @@ void chance32_state::chance32(machine_config &config)
|
||||
screen.set_vblank_time(ATTOSECONDS_IN_USEC(0));
|
||||
screen.set_size(40*16, 32*8);
|
||||
screen.set_visarea(0, 35*16-1, 0, 29*8-1);
|
||||
screen.set_screen_update(FUNC(chance32_state::screen_update_chance32));
|
||||
screen.set_screen_update(FUNC(chance32_state::screen_update));
|
||||
|
||||
hd6845s_device &crtc(HD6845S(config, "crtc", 12000000/16)); /* 52.786 Hz (similar to Major Poker) */
|
||||
/* 52.786 Hz (similar to Major Poker) */
|
||||
hd6845s_device &crtc(HD6845S(config, "crtc", 12000000/16));
|
||||
crtc.set_screen("screen");
|
||||
crtc.set_show_border_area(false);
|
||||
crtc.set_char_width(16);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user