mirror of
https://github.com/holub/mame
synced 2025-07-06 10:29:38 +03:00
tlcs870 - feature stubs (#3818)
* start adding stubs for various tlcs870 features (nw) * more logging (nw) * logging (nw) * moving forward (nw) * cpu flag fix (nw) * fake timer to push it along * fix some cpu bugs (nw)
This commit is contained in:
David Haywood
ajrhacker
parent
65ec00f211
commit
ae110ad5e6
@ -39,7 +39,6 @@ void tlcs870_device::tmp87ph40an_mem(address_map &map)
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map(0x000e, 0x000e).rw(FUNC(tlcs870_device::adccr_r), FUNC(tlcs870_device::adccr_w)); // A/D converter control
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map(0x000f, 0x000f).r(FUNC(tlcs870_device::adcdr_r)); // A/D converter result
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#if 0
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map(0x0010, 0x0010).w(FUNC(tlcs870_device::treg1a_l_w)); // Timer register 1A
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map(0x0011, 0x0011).w(FUNC(tlcs870_device::treg1a_h_w)); //
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@ -52,12 +51,11 @@ void tlcs870_device::tmp87ph40an_mem(address_map &map)
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map(0x0018, 0x0018).rw(FUNC(tlcs870_device::treg3a_r), FUNC(tlcs870_device::treg3a_w)); // Timer register 3A
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map(0x0019, 0x0019).r(FUNC(tlcs870_device::treg3b_r)); // Timer register 3B
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map(0x001a, 0x001a).w(FUNC(tlcs870_device::tc3cr_w)); // TC3 control
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map(0x001b, 0x001b).r(FUNC(tlcs870_device::treg4_r)); // Timer register 4
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map(0x001b, 0x001b).w(FUNC(tlcs870_device::treg4_w)); // Timer register 4
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map(0x001c, 0x001c).w(FUNC(tlcs870_device::tc4cr_w)); // TC4 control
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// 0x1d reserved
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// 0x1e reserved
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// 0x1f reserved
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map(0x0020, 0x0020).rw(FUNC(tlcs870_device::sio1sr_r), FUNC(tlcs870_device::sio1cr1_w)); // SIO1 status / SIO1 control
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map(0x0021, 0x0021).w(FUNC(tlcs870_device::sio1cr2_w)); // SIO1 control
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map(0x0022, 0x0022).rw(FUNC(tlcs870_device::sio2sr_r), FUNC(tlcs870_device::sio2cr1_w)); // SIO2 status / SIO2 control
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@ -83,24 +81,24 @@ void tlcs870_device::tmp87ph40an_mem(address_map &map)
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map(0x0035, 0x0035).w(FUNC(tlcs870_device::wdtcr2_w)); //
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map(0x0036, 0x0036).rw(FUNC(tlcs870_device::tbtcr_r), FUNC(tlcs870_device::tbtcr_w)); // TBT / TG / DVO control
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#endif
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map(0x0037, 0x0037).rw(FUNC(tlcs870_device::eintcr_r), FUNC(tlcs870_device::eintcr_w)); // External interrupt control
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#if 0
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map(0x0038, 0x0038).rw(FUNC(tlcs870_device::syscr1_r), FUNC(tlcs870_device::syscr1_w)); // System Control
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map(0x0039, 0x0039).rw(FUNC(tlcs870_device::syscr2_r), FUNC(tlcs870_device::syscr2_w)); //
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#endif
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map(0x003a, 0x003a).rw(FUNC(tlcs870_device::eir_l_r), FUNC(tlcs870_device::eir_l_w)); // Interrupt enable register
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map(0x003b, 0x003b).rw(FUNC(tlcs870_device::eir_h_r), FUNC(tlcs870_device::eir_h_w)); //
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map(0x003c, 0x003c).rw(FUNC(tlcs870_device::il_l_r), FUNC(tlcs870_device::il_l_w)); // Interrupt latch
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map(0x003d, 0x003d).rw(FUNC(tlcs870_device::il_h_r), FUNC(tlcs870_device::il_h_w)); //
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#if 0
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// 0x3e reserved
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map(0x003f, 0x003f).rw(FUNC(tlcs870_device::psw_r), FUNC(tlcs870_device::rbs_w)); // Program status word / Register bank selector
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#endif
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map(0x0040, 0x023f).ram().share("intram"); // register banks + internal RAM, not, code execution NOT allowed here
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map(0x0f80, 0x0fff).ram(); // DBR
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map(0x0040, 0x023f).ram().share("intram"); // register banks + internal RAM, not, code execution NOT allowed here (fetches FF and causes SWI)
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map(0x0f80, 0x0fef).ram(); // DBR (0f80 - 0fef = reserved)
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map(0x0ff0, 0x0fff).ram().share("dbr"); // DBR 0ff0-0ff7 = SIO1 buffer, 0ff8 - 0fff = SIO2 buffer)
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map(0xc000, 0xffff).rom();
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}
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@ -110,9 +108,11 @@ tlcs870_device::tlcs870_device(const machine_config &mconfig, device_type optype
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, m_program_config("program", ENDIANNESS_LITTLE, 8, 16, 0, program_map)
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, m_io_config("io", ENDIANNESS_LITTLE, 8, 16, 0)
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, m_intram(*this, "intram")
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, m_dbr(*this, "dbr")
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, m_port_in_cb{{*this}, {*this}, {*this}, {*this}, {*this}, {*this}, {*this}, {*this}}
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, m_port_out_cb{{*this}, {*this}, {*this}, {*this}, {*this}, {*this}, {*this}, {*this}}
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, m_port_analog_in_cb{{*this}, {*this}, {*this}, {*this}, {*this}, {*this}, {*this}, {*this}}
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, m_serial_out_cb{{*this}, {*this}}
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{
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}
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@ -276,12 +276,454 @@ WRITE8_MEMBER(tlcs870_device::p7cr_w)
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m_port7_cr = data;
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}
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// Timer emulation
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// 16-Bit Timer / Counter 2 (TC1)
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TIMER_CALLBACK_MEMBER(tlcs870_device::tc1_cb)
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{
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}
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WRITE8_MEMBER(tlcs870_device::tc1cr_w)
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{
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m_TC1CR = data;
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logerror("%s m_TC1CR (16-bit TC1 Timer Control Register) bits set to\n", machine().describe_context());
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logerror("%d: TFF1 (Timer F/F1 control for PPG mode)\n", (m_TC1CR & 0x80) ? 1 : 0);
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logerror("%d: SCAP1/MCAP1/METT1/MPPG1\n", (m_TC1CR & 0x40) ? 1 : 0);
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logerror("%d: TC1S-1 (TC1 Start Control)\n", (m_TC1CR & 0x20) ? 1 : 0);
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logerror("%d: TC1S-0 (TC1 Start Control)\n", (m_TC1CR & 0x10) ? 1 : 0);
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logerror("%d: TC1CK-1 (TC1 Source Clock select)\n", (m_TC1CR & 0x08) ? 1 : 0);
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logerror("%d: TC1CK-0 (TC1 Source Clock select)\n", (m_TC1CR & 0x04) ? 1 : 0);
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logerror("%d: TC1M-1 (TC1 Mode Select)\n", (m_TC1CR & 0x02) ? 1 : 0);
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logerror("%d: TC1M-0 (TC1 Mode Select)\n", (m_TC1CR & 0x01) ? 1 : 0);
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}
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WRITE8_MEMBER(tlcs870_device::treg1a_l_w)
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{
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m_TREG1A = (m_TREG1A & 0xff00) | data;
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}
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WRITE8_MEMBER(tlcs870_device::treg1a_h_w)
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{
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m_TREG1A = (m_TREG1A & 0x00ff) | (data << 8);
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}
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WRITE8_MEMBER(tlcs870_device::treg1b_l_w)
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{
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m_TREG1B = (m_TREG1B & 0xff00) | data;
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}
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WRITE8_MEMBER(tlcs870_device::treg1b_h_w)
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{
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m_TREG1B = (m_TREG1B & 0x00ff) | (data << 8);
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}
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READ8_MEMBER(tlcs870_device::treg1b_l_r)
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{
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return m_TREG1B & 0xff;
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}
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READ8_MEMBER(tlcs870_device::treg1b_h_r)
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{
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return (m_TREG1B >>8) & 0xff;
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}
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// 16-Bit Timer / Counter 2 (TC2)
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TIMER_CALLBACK_MEMBER(tlcs870_device::tc2_cb)
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{
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m_IL |= 1 << (15-TLCS870_IRQ_INTTC2);
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tc2_reload();
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}
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void tlcs870_device::tc2_reload()
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{
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m_tcx_timer[1]->adjust(cycles_to_attotime(5000)); // TODO: use real value
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}
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void tlcs870_device::tc2_cancel()
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{
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m_tcx_timer[1]->adjust(attotime::never);
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}
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WRITE8_MEMBER(tlcs870_device::tc2cr_w)
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{
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if (data & 0x20)
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{
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if (!(m_TC2CR & 0x20))
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{
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tc2_reload();
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}
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}
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else
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{
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tc2_cancel();
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}
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m_TC2CR = data;
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logerror("%s m_TC2CR (16-bit TC2 Timer Control Register) bits set to\n", machine().describe_context());
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logerror("%d: (invalid)\n", (m_TC2CR & 0x80) ? 1 : 0);
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logerror("%d: (invalid)\n", (m_TC2CR & 0x40) ? 1 : 0);
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logerror("%d: TC2S (TC2 Start Control)\n", (m_TC2CR & 0x20) ? 1 : 0);
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logerror("%d: TC2CK-2 (TC2 Source Clock select)\n", (m_TC2CR & 0x10) ? 1 : 0);
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logerror("%d: TC2CK-1 (TC2 Source Clock select)\n", (m_TC2CR & 0x08) ? 1 : 0);
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logerror("%d: TC2CK-0 (TC2 Source Clock select)\n", (m_TC2CR & 0x04) ? 1 : 0);
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logerror("%d: (invalid)\n", (m_TC2CR & 0x02) ? 1 : 0);
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logerror("%d: TC2M (TC2 Mode Select)\n", (m_TC2CR & 0x01) ? 1 : 0);
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}
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WRITE8_MEMBER(tlcs870_device::treg2_l_w)
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{
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m_TREG2 = (m_TREG2 & 0xff00) | data;
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}
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WRITE8_MEMBER(tlcs870_device::treg2_h_w)
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{
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m_TREG2 = (m_TREG2 & 0x00ff) | (data << 8);
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}
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// 8-Bit Timer / Counter 3 (TC3)
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TIMER_CALLBACK_MEMBER(tlcs870_device::tc3_cb)
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{
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}
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WRITE8_MEMBER(tlcs870_device::tc3cr_w)
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{
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m_TC3CR = data;
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logerror("%s m_TC3CR (8-bit TC3 Timer Control Register) bits set to\n", machine().describe_context());
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logerror("%d: (invalid)\n", (m_TC3CR & 0x80) ? 1 : 0);
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logerror("%d: SCAP (Software Capture Control)\n", (m_TC3CR & 0x40) ? 1 : 0);
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logerror("%d: (invalid)\n", (m_TC3CR & 0x20) ? 1 : 0);
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logerror("%d: TC3S (TC3 Start Control)\n", (m_TC3CR & 0x10) ? 1 : 0);
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logerror("%d: TC3CK-1 (TC3 Source Clock select)\n", (m_TC3CR & 0x08) ? 1 : 0);
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logerror("%d: TC3CK-0 (TC3 Source Clock select)\n", (m_TC3CR & 0x04) ? 1 : 0);
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logerror("%d: (invalid)\n", (m_TC3CR & 0x02) ? 1 : 0);
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logerror("%d: TC3M (TC3 Mode Select)\n", (m_TC3CR & 0x01) ? 1 : 0);
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}
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WRITE8_MEMBER(tlcs870_device::treg3a_w)
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{
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m_TREG3A = data;
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}
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READ8_MEMBER(tlcs870_device::treg3a_r)
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{
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return m_TREG3A;
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}
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READ8_MEMBER(tlcs870_device::treg3b_r)
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{
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return m_TREG3B;
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}
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// 8-Bit Timer / Counter 3 (TC4)
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TIMER_CALLBACK_MEMBER(tlcs870_device::tc4_cb)
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{
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}
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WRITE8_MEMBER(tlcs870_device::tc4cr_w)
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{
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m_TC4CR = data;
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logerror("%s m_TC4CR (8-bit TC4 Timer Control Register) bits set to\n", machine().describe_context());
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logerror("%d: TFF4-1 (Timer F/F 4 Control)\n", (m_TC4CR & 0x80) ? 1 : 0);
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logerror("%d: TFF4-0 (Timer F/F 4 Control)\n", (m_TC4CR & 0x40) ? 1 : 0);
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logerror("%d: (invalid)\n", (m_TC4CR & 0x20) ? 1 : 0);
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logerror("%d: TC4S (TC4 Start Control)\n", (m_TC4CR & 0x10) ? 1 : 0);
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logerror("%d: TC4CK-1 (TC4 Source Clock select)\n", (m_TC4CR & 0x08) ? 1 : 0);
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logerror("%d: TC4CK-0 (TC4 Source Clock select)\n", (m_TC4CR & 0x04) ? 1 : 0);
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logerror("%d: TC4M-1 (TC4 Mode Select)\n", (m_TC4CR & 0x02) ? 1 : 0);
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logerror("%d: TC4M-0 (TC4 Mode Select)\n", (m_TC4CR & 0x01) ? 1 : 0);
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}
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WRITE8_MEMBER(tlcs870_device::treg4_w)
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{
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m_TREG4 = data;
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}
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// Time Base Timer
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// this is used with TLCS870_IRQ_INTTBT (FFF2 INTTBT) (not used by hng64)
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// the divider output makes use of PORT1 bit 3, which must be properly configured
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WRITE8_MEMBER(tlcs870_device::tbtcr_w)
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{
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m_TBTCR = data;
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logerror("%s m_TBTCR (Time Base Timer) bits set to\n", machine().describe_context());
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logerror("%d: DV0EN (Divider Output Enable)\n", (m_TBTCR & 0x80) ? 1 : 0);
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logerror("%d: DVOCK-1 (Divide Output Frequency Selection)n", (m_TBTCR & 0x40) ? 1 : 0);
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logerror("%d: DVOCK-0 (Divide Output Frequency Selection)\n", (m_TBTCR & 0x20) ? 1 : 0);
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logerror("%d: DV7CK (?)\n", (m_TBTCR & 0x10) ? 1 : 0);
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logerror("%d: TBTEN (Time Base Timer Enable)\n", (m_TBTCR & 0x08) ? 1 : 0);
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logerror("%d: TBTCK-2 (Time Base Timer Interrupt Frequency)\n", (m_TBTCR & 0x04) ? 1 : 0);
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logerror("%d: TBTCK-1 (Time Base Timer Interrupt Frequency)\n", (m_TBTCR & 0x02) ? 1 : 0);
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logerror("%d: TBTCK-0 (Time Base Timer Interrupt Frequency)\n", (m_TBTCR & 0x01) ? 1 : 0);
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}
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READ8_MEMBER(tlcs870_device::tbtcr_r)
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{
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return m_TBTCR;
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}
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/* SIO emulation */
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// Serial Port 1
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WRITE8_MEMBER(tlcs870_device::sio1cr1_w)
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{
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m_SIOCR1[0] = data;
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logerror("%s m_SIOCR1[0] (Serial IO Port 1 Control Register 1) bits set to\n", machine().describe_context());
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logerror("%d: SIOS1 (Start/Stop transfer)\n", (m_SIOCR1[0] & 0x80) ? 1 : 0);
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logerror("%d: SIOINH1 (Abort/Continue transfer)\n", (m_SIOCR1[0] & 0x40) ? 1 : 0);
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logerror("%d: SIOM1-2 (Serial Mode)\n", (m_SIOCR1[0] & 0x20) ? 1 : 0);
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logerror("%d: SIOM1-1 (Serial Mode)\n", (m_SIOCR1[0] & 0x10) ? 1 : 0);
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logerror("%d: SIOM1-0 (Serial Mode)\n", (m_SIOCR1[0] & 0x08) ? 1 : 0);
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logerror("%d: SCK1-2 (Serial Clock)\n", (m_SIOCR1[0] & 0x04) ? 1 : 0);
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logerror("%d: SCK1-1 (Serial Clock)\n", (m_SIOCR1[0] & 0x02) ? 1 : 0);
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logerror("%d: SCK1-0 (Serial Clock)\n", (m_SIOCR1[0] & 0x01) ? 1 : 0);
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m_transfer_mode[0] = (m_SIOCR1[0] & 0x38) >> 3;
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switch (m_transfer_mode[0])
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{
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case 0x0: logerror("(Serial set to 8-bit transmit mode)\n"); break;
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case 0x1: logerror("(Serial set to invalid mode)\n"); break;
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case 0x2: logerror("(Serial set to 4-bit transmit mode)\n"); break;
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case 0x3: logerror("(Serial set to invalid mode)\n"); break;
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case 0x4: logerror("(Serial set to 8-bit transmit/receive mode)\n"); break;
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case 0x5: logerror("(Serial set to 8-bit receive mode)\n"); break;
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case 0x6: logerror("(Serial set to 4-bit receive mode)\n"); break;
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case 0x7: logerror("(Serial set to invalid mode)\n"); break;
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}
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if ((m_SIOCR1[0] & 0xc0) == 0x80)
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{
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// start transfer
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m_transfer_shiftpos[0] = 0;
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m_transfer_shiftreg[0] = 0;
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m_transfer_pos[0] = 0;
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m_serial_transmit_timer[0]->adjust(attotime::zero);
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}
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}
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WRITE8_MEMBER(tlcs870_device::sio1cr2_w)
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{
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m_SIOCR2[0] = data;
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logerror("%s m_SIOCR2[0] (Serial IO Port 1 Control Register 2) bits set to\n", machine().describe_context());
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logerror("%d: (invalid)\n", (m_SIOCR2[0] & 0x80) ? 1 : 0);
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logerror("%d: (invalid)\n", (m_SIOCR2[0] & 0x40) ? 1 : 0);
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logerror("%d: (invalid)\n", (m_SIOCR2[0] & 0x20) ? 1 : 0);
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logerror("%d: WAIT1-1 (Wait Control\n", (m_SIOCR2[0] & 0x10) ? 1 : 0);
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logerror("%d: WAIT1-0 (Wait Control)\n", (m_SIOCR2[0] & 0x08) ? 1 : 0);
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logerror("%d: BUF1-2 (Number of Transfer Bytes)\n", (m_SIOCR2[0] & 0x04) ? 1 : 0);
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logerror("%d: BUF1-1 (Number of Transfer Bytes)\n", (m_SIOCR2[0] & 0x02) ? 1 : 0);
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logerror("%d: BUF1-0 (Number of Transfer Bytes)\n", (m_SIOCR2[0] & 0x01) ? 1 : 0);
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m_transfer_numbytes[0] = (m_SIOCR2[0] & 0x7);
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logerror("(serial set to transfer %01x bytes)\n", m_transfer_numbytes[0]+1);
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}
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READ8_MEMBER(tlcs870_device::sio1sr_r)
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{
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/* TS-- ----
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T = Transfer in Progress
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S = Shift in Progress
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*/
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return 0x00;
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}
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TIMER_CALLBACK_MEMBER(tlcs870_device::sio0_transmit_cb)
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{
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int finish = 0;
|
||||
if (m_transfer_shiftpos[0] == 0)
|
||||
{
|
||||
m_transfer_shiftreg[0] = m_dbr[m_transfer_pos[0]];
|
||||
logerror("transmitting byte %02x\n", m_transfer_shiftreg[0]);
|
||||
}
|
||||
|
||||
int dataout = m_transfer_shiftreg[0] & 0x01;
|
||||
|
||||
m_serial_out_cb[0](dataout);
|
||||
|
||||
m_transfer_shiftreg[0] >>= 1;
|
||||
m_transfer_shiftpos[0]++;
|
||||
|
||||
if (m_transfer_shiftpos[0] == 8)
|
||||
{
|
||||
logerror("transmitted\n");
|
||||
|
||||
m_transfer_shiftpos[0] = 0;
|
||||
m_transfer_pos[0]++;
|
||||
|
||||
if (m_transfer_pos[0] > m_transfer_numbytes[0])
|
||||
{
|
||||
logerror("end of transmission\n");
|
||||
m_SIOCR1[0] &= ~0x80;
|
||||
// set interrupt latch
|
||||
m_IL |= 1 << (15-TLCS870_IRQ_INTSIO1);
|
||||
finish = 1;
|
||||
}
|
||||
}
|
||||
|
||||
if (!finish)
|
||||
m_serial_transmit_timer[0]->adjust(cycles_to_attotime(1000)); // TODO: use real speed
|
||||
}
|
||||
|
||||
// Serial Port 2
|
||||
WRITE8_MEMBER(tlcs870_device::sio2cr1_w)
|
||||
{
|
||||
m_SIOCR1[1] = data;
|
||||
|
||||
logerror("%s m_SIOCR1[1] (Serial IO Port 2 Control Register 1) bits set to\n", machine().describe_context());
|
||||
logerror("%d: SIOS2 (Start/Stop transfer)\n", (m_SIOCR1[1] & 0x80) ? 1 : 0);
|
||||
logerror("%d: SIOINH2 (Abort/Continue transfer)\n", (m_SIOCR1[1] & 0x40) ? 1 : 0);
|
||||
logerror("%d: SIOM2-2 (Serial Mode)\n", (m_SIOCR1[1] & 0x20) ? 1 : 0);
|
||||
logerror("%d: SIOM2-1 (Serial Mode)\n", (m_SIOCR1[1] & 0x10) ? 1 : 0);
|
||||
logerror("%d: SIOM2-0 (Serial Mode)\n", (m_SIOCR1[1] & 0x08) ? 1 : 0);
|
||||
logerror("%d: SCK2-2 (Serial Clock)\n", (m_SIOCR1[1] & 0x04) ? 1 : 0);
|
||||
logerror("%d: SCK2-1 (Serial Clock)\n", (m_SIOCR1[1] & 0x02) ? 1 : 0);
|
||||
logerror("%d: SCK2-0 (Serial Clock)\n", (m_SIOCR1[1] & 0x01) ? 1 : 0);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(tlcs870_device::sio2cr2_w)
|
||||
{
|
||||
m_SIOCR2[1] = data;
|
||||
|
||||
logerror("%s m_SIOCR2[1] (Serial IO Port 2 Control Register 2) bits set to\n", machine().describe_context());
|
||||
logerror("%d: (invalid)\n", (m_SIOCR2[1] & 0x80) ? 1 : 0);
|
||||
logerror("%d: (invalid)\n", (m_SIOCR2[1] & 0x40) ? 1 : 0);
|
||||
logerror("%d: (invalid)\n", (m_SIOCR2[1] & 0x20) ? 1 : 0);
|
||||
logerror("%d: WAIT2-1 (Wait Control\n", (m_SIOCR2[1] & 0x10) ? 1 : 0);
|
||||
logerror("%d: WAIT2-0 (Wait Control)\n", (m_SIOCR2[1] & 0x08) ? 1 : 0);
|
||||
logerror("%d: BUF2-2 (Number of Transfer Bytes)\n", (m_SIOCR2[1] & 0x04) ? 1 : 0);
|
||||
logerror("%d: BUF2-1 (Number of Transfer Bytes)\n", (m_SIOCR2[1] & 0x02) ? 1 : 0);
|
||||
logerror("%d: BUF2-0 (Number of Transfer Bytes)\n", (m_SIOCR2[1] & 0x01) ? 1 : 0);
|
||||
}
|
||||
|
||||
TIMER_CALLBACK_MEMBER(tlcs870_device::sio1_transmit_cb)
|
||||
{
|
||||
}
|
||||
|
||||
READ8_MEMBER(tlcs870_device::sio2sr_r)
|
||||
{
|
||||
/* TS-- ----
|
||||
|
||||
T = Transfer in Progress
|
||||
S = Shift in Progress
|
||||
|
||||
*/
|
||||
return 0x00;
|
||||
}
|
||||
|
||||
// WDT emulation (Watchdog Timer)
|
||||
|
||||
WRITE8_MEMBER(tlcs870_device::wdtcr1_w)
|
||||
{
|
||||
m_WDTCR1 = data;
|
||||
|
||||
logerror("%s m_WDTCR1 (Watchdog Timer Control 1) bits set to\n", machine().describe_context());
|
||||
logerror("%d: (invalid)\n", (m_WDTCR1 & 0x80) ? 1 : 0);
|
||||
logerror("%d: (invalid)\n", (m_WDTCR1 & 0x40) ? 1 : 0);
|
||||
logerror("%d: (invalid)\n", (m_WDTCR1 & 0x20) ? 1 : 0);
|
||||
logerror("%d: (invalid)\n", (m_WDTCR1 & 0x10) ? 1 : 0);
|
||||
logerror("%d: WDTEN (Watchdog Timer Enable, also req disable code to WDTCR2)\n", (m_WDTCR1 & 0x08) ? 1 : 0);
|
||||
logerror("%d: WDTT-1 (Watchdog Timer Detection Time)\n", (m_WDTCR1 & 0x04) ? 1 : 0);
|
||||
logerror("%d: WDTT-0 (Watchdog Timer Detection Time)\n", (m_WDTCR1 & 0x02) ? 1 : 0);
|
||||
logerror("%d: WDTOUT (Watchdog Timer Output select, 0 = interrupt, 1 = reset out)\n",(m_WDTCR1 & 0x01) ? 1 : 0);
|
||||
|
||||
// WDTOUT cannot be set to 1 by software
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(tlcs870_device::wdtcr2_w)
|
||||
{
|
||||
if (data == 0x4e)
|
||||
{
|
||||
// clear watchdog counter
|
||||
}
|
||||
else if (data == 0xb1)
|
||||
{
|
||||
// disable code
|
||||
if (!(m_WDTCR1 & 0x08))
|
||||
{
|
||||
logerror("%s wdtcr2_w - Watchdog disabled\n", machine().describe_context());
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Misc
|
||||
|
||||
// not used by hng64
|
||||
WRITE8_MEMBER(tlcs870_device::syscr1_w)
|
||||
{
|
||||
m_SYSCR1 = data;
|
||||
|
||||
logerror("%s m_SYSCR1 (System Control Register 1) bits set to\n", machine().describe_context());
|
||||
logerror("%d: STOP (STOP mode start)\n", (m_SYSCR1 & 0x80) ? 1 : 0);
|
||||
logerror("%d: RELM (release method for STOP, 0 edge, 1 level)\n", (m_SYSCR1 & 0x40) ? 1 : 0);
|
||||
logerror("%d: RETM (return mode after STOP, 0 normal, 1 slow)\n", (m_SYSCR1 & 0x20) ? 1 : 0);
|
||||
logerror("%d: OUTEN (port output control during STOP)\n", (m_SYSCR1 & 0x10) ? 1 : 0);
|
||||
logerror("%d: WUT-1 (warm up time at STOP release)\n", (m_SYSCR1 & 0x08) ? 1 : 0);
|
||||
logerror("%d: WUT-0 (warm up time at STOP release)\n", (m_SYSCR1 & 0x04) ? 1 : 0);
|
||||
logerror("%d: (invalid)\n", (m_SYSCR1 & 0x02) ? 1 : 0);
|
||||
logerror("%d: (invalid)\n", (m_SYSCR1 & 0x01) ? 1 : 0);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(tlcs870_device::syscr2_w)
|
||||
{
|
||||
m_SYSCR2 = data;
|
||||
|
||||
logerror("%s m_SYSCR2 (System Control Register 2) bits set to\n", machine().describe_context());
|
||||
logerror("%d: XEN (High Frequency Oscillator control)\n", (m_SYSCR2 & 0x80) ? 1 : 0);
|
||||
logerror("%d: XTEN (Low Frequency Oscillator control)\n", (m_SYSCR2 & 0x40) ? 1 : 0);
|
||||
logerror("%d: SYSCK (system clock select 0 high, 1 low)\n", (m_SYSCR2 & 0x20) ? 1 : 0);
|
||||
logerror("%d: IDLE (IDLE mode start)\n", (m_SYSCR2 & 0x10) ? 1 : 0); // hng64 sets this in case of ram test failures
|
||||
logerror("%d: (invalid)\n", (m_SYSCR2 & 0x08) ? 1 : 0);
|
||||
logerror("%d: (invalid)\n", (m_SYSCR2 & 0x04) ? 1 : 0);
|
||||
logerror("%d: (invalid)\n", (m_SYSCR2 & 0x02) ? 1 : 0);
|
||||
logerror("%d: (invalid)\n", (m_SYSCR2 & 0x01) ? 1 : 0);
|
||||
}
|
||||
|
||||
READ8_MEMBER(tlcs870_device::syscr1_r)
|
||||
{
|
||||
return m_SYSCR1; // low 2 bits are 'undefined'
|
||||
}
|
||||
|
||||
READ8_MEMBER(tlcs870_device::syscr2_r)
|
||||
{
|
||||
return m_SYSCR2 | 0x0f; // low bits always read as 1
|
||||
}
|
||||
|
||||
// RBS / PSW direct access
|
||||
|
||||
WRITE8_MEMBER(tlcs870_device::rbs_w)
|
||||
{
|
||||
// upper bits of PSW (status flags) cannot be written, only the register bank
|
||||
m_RBS = data & 0x0f;
|
||||
}
|
||||
|
||||
READ8_MEMBER(tlcs870_device::psw_r)
|
||||
{
|
||||
// outside of checking the results of opcodes that use it directly (DAA / DAS) this is the only way to read / check the 'half' flag
|
||||
return get_PSW();
|
||||
}
|
||||
|
||||
// ADC emulation
|
||||
|
||||
READ8_MEMBER(tlcs870_device::adcdr_r)
|
||||
{
|
||||
logerror("adcdr_r\n");
|
||||
return m_ADCDR;
|
||||
}
|
||||
|
||||
@ -330,7 +772,7 @@ WRITE8_MEMBER(tlcs870_device::eintcr_w)
|
||||
{
|
||||
m_EINTCR = data;
|
||||
|
||||
logerror("m_EINTCR (External Interrupt Control) bits set to\n");
|
||||
logerror("%s m_EINTCR (External Interrupt Control) bits set to\n", machine().describe_context());
|
||||
logerror("%d: INT1NC (Interrupt noise reject)\n", (m_EINTCR & 0x80) ? 1 : 0);
|
||||
logerror("%d: INT0EN (Interrupt 0 enable)\n", (m_EINTCR & 0x40) ? 1 : 0);
|
||||
logerror("%d: (invalid)\n", (m_EINTCR & 0x20) ? 1 : 0);
|
||||
@ -361,7 +803,7 @@ WRITE8_MEMBER(tlcs870_device::eir_l_w)
|
||||
{
|
||||
m_EIR = (m_EIR & 0xff00) | data;
|
||||
|
||||
logerror("m_EIR(LSB) (Interrupt Enable) bits set to\n");
|
||||
logerror("%s m_EIR(LSB) (Interrupt Enable) bits set to\n", machine().describe_context());
|
||||
logerror("%d: EF7 (External Interrupt 2)\n", (m_EIR & 0x0080) ? 1 : 0);
|
||||
logerror("%d: EF6 (Time Base Timer Interrupt)\n", (m_EIR & 0x0040) ? 1 : 0);
|
||||
logerror("%d: EF5 (External Interrupt 1)\n", (m_EIR & 0x0020) ? 1 : 0);
|
||||
@ -376,7 +818,7 @@ WRITE8_MEMBER(tlcs870_device::eir_h_w)
|
||||
{
|
||||
m_EIR = (m_EIR & 0x00ff) | (data << 8);
|
||||
|
||||
logerror("m_EIR(MSB) (Interrupt Enable) bits set to\n");
|
||||
logerror("%s m_EIR(MSB) (Interrupt Enable) bits set to\n", machine().describe_context());
|
||||
logerror("%d: EF15 (External Interrupt 5)\n", (m_EIR & 0x8000) ? 1 : 0);
|
||||
logerror("%d: EF14 (16-bit TC2 Interrupt)\n", (m_EIR & 0x4000) ? 1 : 0);
|
||||
logerror("%d: EF13 (Serial Interface 2 Interrupt)\n", (m_EIR & 0x2000) ? 1 : 0);
|
||||
@ -518,7 +960,7 @@ void tlcs870_device::take_interrupt(int priority)
|
||||
m_sp.d -= 3;
|
||||
|
||||
m_pc.d = vector;
|
||||
logerror("setting PC to %04x\n", m_addr);
|
||||
logerror("setting PC to %04x\n", m_pc.d);
|
||||
|
||||
}
|
||||
|
||||
@ -553,13 +995,51 @@ void tlcs870_device::execute_run()
|
||||
void tlcs870_device::device_reset()
|
||||
{
|
||||
m_pc.d = RM16(0xfffe);
|
||||
m_RBS = 0;
|
||||
m_EIR = 0;
|
||||
m_IL = 0;
|
||||
m_EINTCR = 0;
|
||||
m_ADCCR = 0;
|
||||
m_ADCDR = 0;
|
||||
|
||||
m_RBS = 0x00;
|
||||
m_EIR = 0x0000;
|
||||
m_IL = 0x0000;
|
||||
m_EINTCR = 0x00;
|
||||
m_ADCCR = 0x00;
|
||||
m_ADCDR = 0x00;
|
||||
m_SYSCR1 = 0x00;
|
||||
m_SYSCR2 = 0x80; // | 0x40, can order parts with low frequency oscillator enabled by default too (although default state is always to use high one?)
|
||||
m_TBTCR = 0x00;
|
||||
|
||||
m_TREG1A = 0x1234; // not initialized?
|
||||
m_TREG1B = 0x4321; // not initialized?
|
||||
m_TC1CR = 0x00;
|
||||
|
||||
m_TREG2 = 0x2301; // not initialized?
|
||||
m_TC2CR = 0x00;
|
||||
|
||||
m_TREG3A = 0x10; // not initialized?
|
||||
m_TREG3B = 0x32; // not initialized?
|
||||
m_TC3CR = 0x00;
|
||||
|
||||
m_TREG4 = 0x30; // not initialized?
|
||||
m_TC3CR = 0x00;
|
||||
|
||||
m_SIOCR1[0] = 0x00;
|
||||
m_SIOCR1[1] = 0x00;
|
||||
|
||||
m_SIOCR2[0] = 0x00;
|
||||
m_SIOCR2[1] = 0x00;
|
||||
|
||||
m_WDTCR1 = 0x09;
|
||||
|
||||
m_irqstate = 0;
|
||||
m_transfer_numbytes[0] = 0;
|
||||
m_transfer_numbytes[1] = 0;
|
||||
m_transfer_mode[0] = 0;
|
||||
m_transfer_mode[1] = 0;
|
||||
m_transfer_pos[0] = 0;
|
||||
m_transfer_pos[1] = 0;
|
||||
m_transfer_shiftreg[0] = 0;
|
||||
m_transfer_shiftreg[1] = 0;
|
||||
m_transfer_shiftpos[0] = 0;
|
||||
m_transfer_shiftpos[1] = 0;
|
||||
|
||||
|
||||
m_port_out_latch[0] = 0x00;
|
||||
m_port_out_latch[1] = 0x00;
|
||||
@ -724,9 +1204,20 @@ void tlcs870_device::device_start()
|
||||
cb.resolve_safe();
|
||||
for (auto &cb : m_port_analog_in_cb)
|
||||
cb.resolve_safe(0xff);
|
||||
for (auto &cb : m_serial_out_cb)
|
||||
cb.resolve_safe();
|
||||
|
||||
m_serial_transmit_timer[0] = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(tlcs870_device::sio0_transmit_cb), this));
|
||||
m_serial_transmit_timer[1] = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(tlcs870_device::sio1_transmit_cb), this));
|
||||
|
||||
m_tcx_timer[0] = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(tlcs870_device::tc1_cb), this));
|
||||
m_tcx_timer[1] = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(tlcs870_device::tc2_cb), this));
|
||||
m_tcx_timer[2] = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(tlcs870_device::tc3_cb), this));
|
||||
m_tcx_timer[3] = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(tlcs870_device::tc4_cb), this));
|
||||
}
|
||||
|
||||
|
||||
|
||||
void tlcs870_device::state_string_export(const device_state_entry &entry, std::string &str) const
|
||||
{
|
||||
int F = m_F;
|
||||
|
||||
@ -36,6 +36,10 @@ public:
|
||||
auto an6_in_cb() { return m_port_analog_in_cb[6].bind(); }
|
||||
auto an7_in_cb() { return m_port_analog_in_cb[7].bind(); }
|
||||
|
||||
auto serial0_out_cb() { return m_serial_out_cb[0].bind(); }
|
||||
auto serial1_out_cb() { return m_serial_out_cb[1].bind(); }
|
||||
|
||||
|
||||
protected:
|
||||
// construction/destruction
|
||||
tlcs870_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, address_map_constructor program_map);
|
||||
@ -152,6 +156,7 @@ private:
|
||||
address_space_config m_program_config;
|
||||
address_space_config m_io_config;
|
||||
required_shared_ptr<uint8_t> m_intram;
|
||||
required_shared_ptr<uint8_t> m_dbr;
|
||||
|
||||
PAIR m_prvpc, m_pc, m_sp;
|
||||
|
||||
@ -162,6 +167,8 @@ private:
|
||||
devcb_read8 m_port_in_cb[8];
|
||||
devcb_write8 m_port_out_cb[8];
|
||||
devcb_read8 m_port_analog_in_cb[8];
|
||||
devcb_write_line m_serial_out_cb[2];
|
||||
|
||||
|
||||
uint8_t m_port_out_latch[8];
|
||||
int m_read_input_port;
|
||||
@ -204,6 +211,46 @@ private:
|
||||
|
||||
DECLARE_WRITE8_MEMBER(eintcr_w);
|
||||
|
||||
DECLARE_WRITE8_MEMBER(treg1a_l_w);
|
||||
DECLARE_WRITE8_MEMBER(treg1a_h_w);
|
||||
DECLARE_WRITE8_MEMBER(treg1b_l_w);
|
||||
DECLARE_WRITE8_MEMBER(treg1b_h_w);
|
||||
DECLARE_WRITE8_MEMBER(tc1cr_w);
|
||||
DECLARE_WRITE8_MEMBER(tc2cr_w);
|
||||
DECLARE_WRITE8_MEMBER(treg2_l_w);
|
||||
DECLARE_WRITE8_MEMBER(treg2_h_w);
|
||||
DECLARE_WRITE8_MEMBER(treg3a_w);
|
||||
DECLARE_WRITE8_MEMBER(tc3cr_w);
|
||||
DECLARE_WRITE8_MEMBER(tc4cr_w);
|
||||
|
||||
DECLARE_READ8_MEMBER(treg1b_l_r);
|
||||
DECLARE_READ8_MEMBER(treg1b_h_r);
|
||||
DECLARE_READ8_MEMBER(treg3a_r);
|
||||
DECLARE_READ8_MEMBER(treg3b_r);
|
||||
DECLARE_WRITE8_MEMBER(treg4_w);
|
||||
|
||||
|
||||
DECLARE_WRITE8_MEMBER(sio1cr1_w);
|
||||
DECLARE_WRITE8_MEMBER(sio1cr2_w);
|
||||
DECLARE_WRITE8_MEMBER(sio2cr1_w);
|
||||
DECLARE_WRITE8_MEMBER(sio2cr2_w);
|
||||
DECLARE_READ8_MEMBER(sio2sr_r);
|
||||
DECLARE_READ8_MEMBER(sio1sr_r);
|
||||
|
||||
DECLARE_WRITE8_MEMBER(wdtcr1_w);
|
||||
DECLARE_WRITE8_MEMBER(wdtcr2_w);
|
||||
|
||||
DECLARE_WRITE8_MEMBER(tbtcr_w);
|
||||
|
||||
DECLARE_READ8_MEMBER(tbtcr_r);
|
||||
|
||||
DECLARE_WRITE8_MEMBER(syscr1_w);
|
||||
DECLARE_WRITE8_MEMBER(syscr2_w);
|
||||
DECLARE_READ8_MEMBER(syscr1_r);
|
||||
DECLARE_READ8_MEMBER(syscr2_r);
|
||||
DECLARE_WRITE8_MEMBER(rbs_w);
|
||||
DECLARE_READ8_MEMBER(psw_r);
|
||||
|
||||
DECLARE_READ8_MEMBER(adccr_r);
|
||||
DECLARE_READ8_MEMBER(adcdr_r);
|
||||
|
||||
@ -224,9 +271,47 @@ private:
|
||||
uint8_t m_EINTCR;
|
||||
uint8_t m_ADCCR;
|
||||
uint8_t m_ADCDR;
|
||||
uint8_t m_SYSCR1;
|
||||
uint8_t m_SYSCR2;
|
||||
uint8_t m_TBTCR;
|
||||
uint16_t m_TREG1A;
|
||||
uint16_t m_TREG1B;
|
||||
uint8_t m_TC1CR;
|
||||
uint16_t m_TREG2;
|
||||
uint8_t m_TC2CR;
|
||||
uint8_t m_TREG3A;
|
||||
uint8_t m_TREG3B;
|
||||
uint8_t m_TC3CR;
|
||||
uint8_t m_TREG4;
|
||||
uint8_t m_TC4CR;
|
||||
uint8_t m_SIOCR1[2];
|
||||
uint8_t m_SIOCR2[2];
|
||||
uint8_t m_WDTCR1;
|
||||
|
||||
uint16_t m_irqstate;
|
||||
|
||||
// serial stuff
|
||||
TIMER_CALLBACK_MEMBER(sio0_transmit_cb);
|
||||
TIMER_CALLBACK_MEMBER(sio1_transmit_cb);
|
||||
uint8_t m_transfer_numbytes[2];
|
||||
uint8_t m_transfer_pos[2];
|
||||
uint8_t m_transfer_shiftreg[2];
|
||||
uint8_t m_transfer_shiftpos[2];
|
||||
uint8_t m_transfer_mode[2];
|
||||
|
||||
emu_timer *m_serial_transmit_timer[2];
|
||||
|
||||
TIMER_CALLBACK_MEMBER(tc1_cb);
|
||||
TIMER_CALLBACK_MEMBER(tc2_cb);
|
||||
TIMER_CALLBACK_MEMBER(tc3_cb);
|
||||
TIMER_CALLBACK_MEMBER(tc4_cb);
|
||||
|
||||
void tc2_reload();
|
||||
void tc2_cancel();
|
||||
|
||||
emu_timer *m_tcx_timer[4];
|
||||
|
||||
|
||||
void set_irq_line(int irqline, int state);
|
||||
void check_interrupts();
|
||||
void take_interrupt(int priority);
|
||||
|
||||
@ -234,8 +234,8 @@ void tlcs870_device::do_POP_PSW(const uint8_t opbyte0)
|
||||
*/
|
||||
m_cycles = 3;
|
||||
|
||||
m_sp.d += 2;
|
||||
const uint16_t val = RM16(m_sp.d - 1);
|
||||
m_sp.d += 1;
|
||||
const uint8_t val = RM8(m_sp.d);
|
||||
set_PSW(val);
|
||||
}
|
||||
|
||||
@ -247,9 +247,9 @@ void tlcs870_device::do_PUSH_PSW(const uint8_t opbyte0)
|
||||
*/
|
||||
m_cycles = 2;
|
||||
|
||||
const uint16_t val = get_PSW();
|
||||
WM16(m_sp.d - 1, val);
|
||||
m_sp.d -= 2;
|
||||
const uint8_t val = get_PSW();
|
||||
WM8(m_sp.d, val);
|
||||
m_sp.d -= 1;
|
||||
}
|
||||
|
||||
void tlcs870_device::do_DAA_A(const uint8_t opbyte0)
|
||||
@ -410,7 +410,7 @@ void tlcs870_device::do_DEC_rr(const uint8_t opbyte0)
|
||||
}
|
||||
else
|
||||
{
|
||||
set_ZF();
|
||||
clear_ZF();
|
||||
}
|
||||
}
|
||||
|
||||
@ -619,7 +619,7 @@ void tlcs870_device::do_DEC_inx(const uint8_t opbyte0)
|
||||
}
|
||||
else
|
||||
{
|
||||
set_ZF();
|
||||
clear_ZF();
|
||||
}
|
||||
}
|
||||
|
||||
@ -653,7 +653,7 @@ void tlcs870_device::do_DEC_inHL(const uint8_t opbyte0)
|
||||
}
|
||||
else
|
||||
{
|
||||
set_ZF();
|
||||
clear_ZF();
|
||||
}
|
||||
}
|
||||
|
||||
@ -926,7 +926,7 @@ void tlcs870_device::do_DEC_r(const uint8_t opbyte0)
|
||||
}
|
||||
else
|
||||
{
|
||||
set_ZF();
|
||||
clear_ZF();
|
||||
}
|
||||
}
|
||||
|
||||
@ -1130,13 +1130,13 @@ void tlcs870_device::do_JP_mn(const uint8_t opbyte0)
|
||||
void tlcs870_device::do_ff_opcode(const uint8_t opbyte0)
|
||||
{
|
||||
/*
|
||||
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
|
||||
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
|
||||
SWI 1111 1111 - - - - 9 (1 if already in NMI)
|
||||
*/
|
||||
m_cycles = 9; // TODO: 1 if in NMI this acts as a NOP
|
||||
|
||||
// set interrupt latch
|
||||
m_IL |= 1<<TLCS870_IRQ_INTSW;
|
||||
m_IL |= 1 << (15 - TLCS870_IRQ_INTSW);
|
||||
}
|
||||
|
||||
/**********************************************************************************************************************/
|
||||
|
||||
@ -47,7 +47,7 @@ void tlcs870_device::set_PSW(uint8_t data)
|
||||
{
|
||||
// used by the push/pop opcodes, flags can't be written by memory access
|
||||
m_F = data & 0xf0;
|
||||
m_RBS = data & 0xf0;
|
||||
m_RBS = data & 0x0f;
|
||||
}
|
||||
|
||||
void tlcs870_device::handle_div(const int reg)
|
||||
|
||||
@ -1534,7 +1534,7 @@ void hng64_state::machine_reset()
|
||||
reset_sound();
|
||||
}
|
||||
|
||||
// used (shard ram access at least)
|
||||
// used (shared ram access at least)
|
||||
READ8_MEMBER(hng64_state::ioport0_r)
|
||||
{
|
||||
uint16_t addr = (m_ex_ramaddr | (m_ex_ramaddr_upper<<9)) & 0x7ff;
|
||||
@ -1551,7 +1551,7 @@ READ8_MEMBER(hng64_state::ioport1_r)
|
||||
return 0xff;
|
||||
}
|
||||
|
||||
// used (shard ram access at least)
|
||||
// used (shared ram access at least)
|
||||
WRITE8_MEMBER(hng64_state::ioport0_w)
|
||||
{
|
||||
uint16_t addr = (m_ex_ramaddr | (m_ex_ramaddr_upper<<9)) & 0x7ff;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user